Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	641010073	64649	0	0
DepthKnown_A	641010073	640883335	0	0
RvalidKnown_A	641010073	640883335	0	0
WreadyKnown_A	641010073	640883335	0	0
gen_passthru_fifo.paramCheckPass	1116	1116	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	64649	0	0
T2	1529	100	0	0
T3	359319	0	0	0
T4	456091	0	0	0
T5	1230	0	0	0
T6	8157	0	0	0
T7	621057	636	0	0
T8	24913	0	0	0
T9	1308	100	0	0
T10	3995	0	0	0
T11	0	256	0	0
T12	0	651	0	0
T18	146455	0	0	0
T26	0	128	0	0
T27	0	128	0	0
T28	0	933	0	0
T29	0	327	0	0
T30	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116	1116	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	641010073	162942	0	0
DepthKnown_A	641010073	640883335	0	0
RvalidKnown_A	641010073	640883335	0	0
WreadyKnown_A	641010073	640883335	0	0
gen_passthru_fifo.paramCheckPass	1116	1116	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	162942	0	0
T2	1529	100	0	0
T3	359319	0	0	0
T4	456091	0	0	0
T5	1230	0	0	0
T6	8157	0	0	0
T7	621057	636	0	0
T8	24913	0	0	0
T9	1308	100	0	0
T10	3995	0	0	0
T11	0	743	0	0
T12	0	3025	0	0
T18	146455	0	0	0
T26	0	587	0	0
T27	0	128	0	0
T28	0	4293	0	0
T29	0	1502	0	0
T30	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116	1116	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	641010073	14839971	0	0
DepthKnown_A	641010073	640883335	0	0
RvalidKnown_A	641010073	640883335	0	0
WreadyKnown_A	641010073	640883335	0	0
gen_passthru_fifo.paramCheckPass	1116	1116	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	14839971	0	0
T1	866	25	0	0
T2	1529	1	0	0
T3	359319	3283	0	0
T4	456091	4011	0	0
T5	1230	15	0	0
T6	8157	111	0	0
T7	621057	198116	0	0
T8	24913	57	0	0
T9	1308	1	0	0
T10	3995	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116	1116	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	641010073	34399176	0	0
DepthKnown_A	641010073	640883335	0	0
RvalidKnown_A	641010073	640883335	0	0
WreadyKnown_A	641010073	640883335	0	0
gen_passthru_fifo.paramCheckPass	1116	1116	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	34399176	0	0
T1	866	25	0	0
T2	1529	1	0	0
T3	359319	3283	0	0
T4	456091	17338	0	0
T5	1230	15	0	0
T6	8157	479	0	0
T7	621057	196808	0	0
T8	24913	288	0	0
T9	1308	1	0	0
T10	3995	107	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641010073	640883335	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116	1116	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0