| T366 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1450100270 |
|
|
Feb 04 12:41:22 PM PST 24 |
Feb 04 12:41:29 PM PST 24 |
36720197 ps |
| T110 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2198604939 |
|
|
Feb 04 12:41:32 PM PST 24 |
Feb 04 12:41:40 PM PST 24 |
30688715 ps |
| T367 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.898988500 |
|
|
Feb 04 12:41:23 PM PST 24 |
Feb 04 12:41:32 PM PST 24 |
77674846 ps |
| T368 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2716005620 |
|
|
Feb 04 12:41:20 PM PST 24 |
Feb 04 12:41:35 PM PST 24 |
1487354211 ps |
| T113 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.74825411 |
|
|
Feb 04 12:41:22 PM PST 24 |
Feb 04 12:41:30 PM PST 24 |
25631462 ps |
| T369 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.2074890953 |
|
|
Feb 04 12:41:40 PM PST 24 |
Feb 04 12:41:47 PM PST 24 |
17684130 ps |
| T370 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.1684225381 |
|
|
Feb 04 12:41:39 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
25147200 ps |
| T158 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3063071601 |
|
|
Feb 04 12:41:35 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
239373132 ps |
| T371 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1815208051 |
|
|
Feb 04 12:41:29 PM PST 24 |
Feb 04 12:41:38 PM PST 24 |
295267844 ps |
| T372 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.268696326 |
|
|
Feb 04 12:41:21 PM PST 24 |
Feb 04 12:41:30 PM PST 24 |
46456824 ps |
| T373 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.760529576 |
|
|
Feb 04 12:41:18 PM PST 24 |
Feb 04 12:41:27 PM PST 24 |
68614062 ps |
| T153 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2515289526 |
|
|
Feb 04 12:41:23 PM PST 24 |
Feb 04 12:41:36 PM PST 24 |
105657721 ps |
| T374 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1167930847 |
|
|
Feb 04 12:41:23 PM PST 24 |
Feb 04 12:41:31 PM PST 24 |
40819631 ps |
| T375 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3027537694 |
|
|
Feb 04 12:41:37 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
35332933 ps |
| T376 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2564635726 |
|
|
Feb 04 12:41:19 PM PST 24 |
Feb 04 12:42:01 PM PST 24 |
2493941132 ps |
| T377 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1927717553 |
|
|
Feb 04 12:41:37 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
106800405 ps |
| T378 |
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2278583429 |
|
|
Feb 04 12:41:23 PM PST 24 |
Feb 04 12:41:31 PM PST 24 |
265664752 ps |
| T156 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4046462009 |
|
|
Feb 04 12:41:42 PM PST 24 |
Feb 04 12:42:03 PM PST 24 |
556742500 ps |
| T379 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3530652583 |
|
|
Feb 04 12:41:43 PM PST 24 |
Feb 04 12:41:50 PM PST 24 |
146460592 ps |
| T380 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.852501363 |
|
|
Feb 04 12:41:30 PM PST 24 |
Feb 04 12:41:42 PM PST 24 |
241121125 ps |
| T381 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.1249376591 |
|
|
Feb 04 12:41:31 PM PST 24 |
Feb 04 12:41:39 PM PST 24 |
34586554 ps |
| T382 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2125007854 |
|
|
Feb 04 12:41:23 PM PST 24 |
Feb 04 12:41:31 PM PST 24 |
254087271 ps |
| T383 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2037824124 |
|
|
Feb 04 12:41:37 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
25087825 ps |
| T384 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.376272054 |
|
|
Feb 04 12:41:39 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
149290865 ps |
| T385 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.56481039 |
|
|
Feb 04 12:41:12 PM PST 24 |
Feb 04 12:41:31 PM PST 24 |
3665209137 ps |
| T386 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.21207138 |
|
|
Feb 04 12:41:44 PM PST 24 |
Feb 04 12:41:50 PM PST 24 |
61050310 ps |
| T154 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1159146407 |
|
|
Feb 04 12:41:34 PM PST 24 |
Feb 04 12:41:55 PM PST 24 |
738011282 ps |
| T387 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.1901361711 |
|
|
Feb 04 12:41:34 PM PST 24 |
Feb 04 12:41:40 PM PST 24 |
65871932 ps |
| T388 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1436406005 |
|
|
Feb 04 12:41:40 PM PST 24 |
Feb 04 12:41:48 PM PST 24 |
42724550 ps |
| T389 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.962847958 |
|
|
Feb 04 12:41:32 PM PST 24 |
Feb 04 12:41:41 PM PST 24 |
452760576 ps |
| T390 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.733029903 |
|
|
Feb 04 12:41:18 PM PST 24 |
Feb 04 12:41:26 PM PST 24 |
35256380 ps |
| T391 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.1566817104 |
|
|
Feb 04 12:41:34 PM PST 24 |
Feb 04 12:41:40 PM PST 24 |
43908540 ps |
| T392 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3311496123 |
|
|
Feb 04 12:41:32 PM PST 24 |
Feb 04 12:41:41 PM PST 24 |
116327543 ps |
| T393 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.893224161 |
|
|
Feb 04 12:41:34 PM PST 24 |
Feb 04 12:41:40 PM PST 24 |
62706028 ps |
| T394 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2669830440 |
|
|
Feb 04 12:41:33 PM PST 24 |
Feb 04 12:41:42 PM PST 24 |
433103433 ps |
| T395 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.2424897943 |
|
|
Feb 04 12:41:16 PM PST 24 |
Feb 04 12:41:22 PM PST 24 |
17679554 ps |
| T396 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3655533918 |
|
|
Feb 04 12:41:40 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
30103320 ps |
| T397 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2665125843 |
|
|
Feb 04 12:41:24 PM PST 24 |
Feb 04 12:42:03 PM PST 24 |
1936454073 ps |
| T398 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2162662606 |
|
|
Feb 04 12:41:14 PM PST 24 |
Feb 04 12:41:19 PM PST 24 |
61248634 ps |
| T399 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.646983124 |
|
|
Feb 04 12:41:20 PM PST 24 |
Feb 04 12:41:28 PM PST 24 |
12786063 ps |
| T400 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1668289293 |
|
|
Feb 04 12:41:33 PM PST 24 |
Feb 04 12:41:40 PM PST 24 |
47104298 ps |
| T67 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4213073843 |
|
|
Feb 04 12:41:14 PM PST 24 |
Feb 04 12:41:20 PM PST 24 |
61230222 ps |
| T401 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2723311733 |
|
|
Feb 04 12:41:32 PM PST 24 |
Feb 04 12:41:41 PM PST 24 |
2724025709 ps |
| T402 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1467961232 |
|
|
Feb 04 12:41:15 PM PST 24 |
Feb 04 12:41:20 PM PST 24 |
69861075 ps |
| T403 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.377846445 |
|
|
Feb 04 12:41:38 PM PST 24 |
Feb 04 12:41:47 PM PST 24 |
167861662 ps |
| T404 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.433774367 |
|
|
Feb 04 12:41:14 PM PST 24 |
Feb 04 12:41:19 PM PST 24 |
171373757 ps |
| T405 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3047477853 |
|
|
Feb 04 12:41:36 PM PST 24 |
Feb 04 12:41:44 PM PST 24 |
181392645 ps |
| T406 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2334225856 |
|
|
Feb 04 12:41:36 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
420102428 ps |
| T407 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2497041465 |
|
|
Feb 04 12:41:17 PM PST 24 |
Feb 04 12:41:28 PM PST 24 |
625562460 ps |
| T408 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1564487012 |
|
|
Feb 04 12:41:33 PM PST 24 |
Feb 04 12:41:41 PM PST 24 |
93863037 ps |
| T409 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.274706025 |
|
|
Feb 04 12:41:18 PM PST 24 |
Feb 04 12:41:26 PM PST 24 |
26289421 ps |
| T410 |
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.2185073781 |
|
|
Feb 04 12:41:20 PM PST 24 |
Feb 04 12:41:27 PM PST 24 |
26902794 ps |
| T150 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1094678573 |
|
|
Feb 04 12:41:33 PM PST 24 |
Feb 04 12:41:43 PM PST 24 |
176498776 ps |
| T411 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4217985018 |
|
|
Feb 04 12:41:38 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
77558456 ps |
| T412 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.4234021735 |
|
|
Feb 04 12:41:41 PM PST 24 |
Feb 04 12:41:47 PM PST 24 |
48510084 ps |
| T413 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.581167907 |
|
|
Feb 04 12:41:15 PM PST 24 |
Feb 04 12:41:21 PM PST 24 |
23821110 ps |
| T414 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2658176475 |
|
|
Feb 04 12:41:36 PM PST 24 |
Feb 04 12:41:45 PM PST 24 |
184503832 ps |
| T415 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3082874646 |
|
|
Feb 04 12:41:21 PM PST 24 |
Feb 04 12:41:42 PM PST 24 |
3860041757 ps |
| T416 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.166646999 |
|
|
Feb 04 12:41:33 PM PST 24 |
Feb 04 12:41:41 PM PST 24 |
126638544 ps |
| T417 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1264706902 |
|
|
Feb 04 12:41:18 PM PST 24 |
Feb 04 12:41:38 PM PST 24 |
2494537208 ps |
| T418 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.132184770 |
|
|
Feb 04 12:41:44 PM PST 24 |
Feb 04 12:41:51 PM PST 24 |
11942082 ps |
| T157 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2224332248 |
|
|
Feb 04 12:41:41 PM PST 24 |
Feb 04 12:42:04 PM PST 24 |
713670426 ps |
| T419 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.2465640044 |
|
|
Feb 04 12:41:38 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
15245844 ps |
| T420 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.3983850200 |
|
|
Feb 04 12:41:39 PM PST 24 |
Feb 04 12:41:46 PM PST 24 |
47242885 ps |
| T421 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3727667463 |
|
|
Feb 04 12:41:34 PM PST 24 |
Feb 04 12:41:45 PM PST 24 |
816285897 ps |
| T422 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2299560219 |
|
|
Feb 04 12:41:20 PM PST 24 |
Feb 04 12:41:27 PM PST 24 |
90794685 ps |
| T423 |
/workspace/coverage/default/43.spi_device_tpm_sts_read.137474045 |
|
|
Feb 04 02:37:47 PM PST 24 |
Feb 04 02:37:50 PM PST 24 |
72260334 ps |
| T223 |
/workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3507434463 |
|
|
Feb 04 02:36:34 PM PST 24 |
Feb 04 02:37:34 PM PST 24 |
18655925415 ps |
| T424 |
/workspace/coverage/default/10.spi_device_csb_read.1024435477 |
|
|
Feb 04 02:35:08 PM PST 24 |
Feb 04 02:35:15 PM PST 24 |
55483348 ps |
| T425 |
/workspace/coverage/default/9.spi_device_alert_test.180989559 |
|
|
Feb 04 02:35:01 PM PST 24 |
Feb 04 02:35:05 PM PST 24 |
24208085 ps |
| T215 |
/workspace/coverage/default/9.spi_device_mailbox.3501750937 |
|
|
Feb 04 02:34:53 PM PST 24 |
Feb 04 02:35:08 PM PST 24 |
9009623423 ps |
| T426 |
/workspace/coverage/default/7.spi_device_tpm_sts_read.1408893836 |
|
|
Feb 04 02:34:40 PM PST 24 |
Feb 04 02:34:43 PM PST 24 |
187686318 ps |
| T427 |
/workspace/coverage/default/35.spi_device_tpm_rw.1483133049 |
|
|
Feb 04 02:37:19 PM PST 24 |
Feb 04 02:37:21 PM PST 24 |
64974899 ps |
| T428 |
/workspace/coverage/default/7.spi_device_flash_and_tpm.3118140069 |
|
|
Feb 04 02:35:01 PM PST 24 |
Feb 04 02:35:58 PM PST 24 |
7683631142 ps |
| T118 |
/workspace/coverage/default/35.spi_device_stress_all.4286092187 |
|
|
Feb 04 02:37:19 PM PST 24 |
Feb 04 02:38:46 PM PST 24 |
5045189760 ps |
| T429 |
/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2339018956 |
|
|
Feb 04 02:34:09 PM PST 24 |
Feb 04 02:34:19 PM PST 24 |
456571451 ps |
| T147 |
/workspace/coverage/default/12.spi_device_flash_and_tpm.3044237869 |
|
|
Feb 04 02:35:26 PM PST 24 |
Feb 04 02:37:39 PM PST 24 |
29118052201 ps |
| T430 |
/workspace/coverage/default/41.spi_device_read_buffer_direct.2729945025 |
|
|
Feb 04 02:37:37 PM PST 24 |
Feb 04 02:37:44 PM PST 24 |
93820344 ps |
| T431 |
/workspace/coverage/default/39.spi_device_tpm_sts_read.3055307429 |
|
|
Feb 04 02:37:29 PM PST 24 |
Feb 04 02:37:35 PM PST 24 |
406047326 ps |
| T432 |
/workspace/coverage/default/29.spi_device_tpm_all.3110406656 |
|
|
Feb 04 02:36:51 PM PST 24 |
Feb 04 02:37:17 PM PST 24 |
1233466005 ps |
| T176 |
/workspace/coverage/default/25.spi_device_pass_cmd_filtering.3889815021 |
|
|
Feb 04 02:36:34 PM PST 24 |
Feb 04 02:36:49 PM PST 24 |
1689021597 ps |
| T433 |
/workspace/coverage/default/25.spi_device_tpm_sts_read.1337362084 |
|
|
Feb 04 02:36:27 PM PST 24 |
Feb 04 02:36:29 PM PST 24 |
280486526 ps |
| T228 |
/workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1528620907 |
|
|
Feb 04 02:37:25 PM PST 24 |
Feb 04 02:37:38 PM PST 24 |
948344075 ps |
| T221 |
/workspace/coverage/default/44.spi_device_pass_cmd_filtering.1842441983 |
|
|
Feb 04 02:37:42 PM PST 24 |
Feb 04 02:37:59 PM PST 24 |
3111383045 ps |
| T434 |
/workspace/coverage/default/33.spi_device_pass_cmd_filtering.3045463008 |
|
|
Feb 04 02:37:04 PM PST 24 |
Feb 04 02:37:57 PM PST 24 |
18497075787 ps |
| T435 |
/workspace/coverage/default/32.spi_device_stress_all.503856583 |
|
|
Feb 04 02:36:49 PM PST 24 |
Feb 04 02:36:56 PM PST 24 |
56126553 ps |
| T436 |
/workspace/coverage/default/17.spi_device_mailbox.1638785534 |
|
|
Feb 04 02:35:45 PM PST 24 |
Feb 04 02:36:06 PM PST 24 |
1960433727 ps |
| T437 |
/workspace/coverage/default/0.spi_device_read_buffer_direct.2401202952 |
|
|
Feb 04 02:33:41 PM PST 24 |
Feb 04 02:33:47 PM PST 24 |
637946178 ps |
| T438 |
/workspace/coverage/default/20.spi_device_csb_read.1790838219 |
|
|
Feb 04 02:35:57 PM PST 24 |
Feb 04 02:36:02 PM PST 24 |
22337540 ps |
| T439 |
/workspace/coverage/default/37.spi_device_pass_cmd_filtering.188805654 |
|
|
Feb 04 02:37:27 PM PST 24 |
Feb 04 02:37:49 PM PST 24 |
10092311192 ps |
| T274 |
/workspace/coverage/default/21.spi_device_flash_mode.3942678249 |
|
|
Feb 04 02:36:05 PM PST 24 |
Feb 04 02:36:23 PM PST 24 |
1203467121 ps |
| T146 |
/workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3298269902 |
|
|
Feb 04 02:36:29 PM PST 24 |
Feb 04 02:40:46 PM PST 24 |
130700465942 ps |
| T440 |
/workspace/coverage/default/31.spi_device_cfg_cmd.1416997155 |
|
|
Feb 04 02:37:02 PM PST 24 |
Feb 04 02:37:06 PM PST 24 |
337342506 ps |
| T212 |
/workspace/coverage/default/12.spi_device_intercept.3412914984 |
|
|
Feb 04 02:35:12 PM PST 24 |
Feb 04 02:35:19 PM PST 24 |
1340005493 ps |
| T441 |
/workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1555629231 |
|
|
Feb 04 02:36:12 PM PST 24 |
Feb 04 02:36:29 PM PST 24 |
24543616248 ps |
| T162 |
/workspace/coverage/default/3.spi_device_stress_all.2944826858 |
|
|
Feb 04 02:34:18 PM PST 24 |
Feb 04 02:43:16 PM PST 24 |
202063290718 ps |
| T442 |
/workspace/coverage/default/24.spi_device_read_buffer_direct.1293126292 |
|
|
Feb 04 02:36:31 PM PST 24 |
Feb 04 02:36:38 PM PST 24 |
2111872945 ps |
| T443 |
/workspace/coverage/default/47.spi_device_tpm_sts_read.2694819235 |
|
|
Feb 04 02:38:13 PM PST 24 |
Feb 04 02:38:15 PM PST 24 |
31171233 ps |
| T145 |
/workspace/coverage/default/23.spi_device_flash_all.1074170962 |
|
|
Feb 04 02:36:27 PM PST 24 |
Feb 04 02:37:31 PM PST 24 |
17135628369 ps |
| T444 |
/workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1374284196 |
|
|
Feb 04 02:38:06 PM PST 24 |
Feb 04 02:38:12 PM PST 24 |
123975409 ps |
| T173 |
/workspace/coverage/default/5.spi_device_upload.2188700632 |
|
|
Feb 04 02:34:28 PM PST 24 |
Feb 04 02:34:42 PM PST 24 |
455319166 ps |
| T445 |
/workspace/coverage/default/36.spi_device_mailbox.1489399008 |
|
|
Feb 04 02:37:29 PM PST 24 |
Feb 04 02:37:39 PM PST 24 |
2470855293 ps |
| T167 |
/workspace/coverage/default/48.spi_device_flash_all.4089096767 |
|
|
Feb 04 02:38:20 PM PST 24 |
Feb 04 02:43:55 PM PST 24 |
375152199060 ps |
| T446 |
/workspace/coverage/default/8.spi_device_csb_read.1449202580 |
|
|
Feb 04 02:34:55 PM PST 24 |
Feb 04 02:34:59 PM PST 24 |
16080504 ps |
| T447 |
/workspace/coverage/default/48.spi_device_read_buffer_direct.1024277667 |
|
|
Feb 04 02:38:13 PM PST 24 |
Feb 04 02:38:17 PM PST 24 |
676271519 ps |
| T448 |
/workspace/coverage/default/19.spi_device_alert_test.1090476687 |
|
|
Feb 04 02:35:53 PM PST 24 |
Feb 04 02:35:59 PM PST 24 |
34540338 ps |
| T449 |
/workspace/coverage/default/6.spi_device_stress_all.4153080446 |
|
|
Feb 04 02:34:33 PM PST 24 |
Feb 04 02:35:44 PM PST 24 |
19740894319 ps |
| T450 |
/workspace/coverage/default/16.spi_device_tpm_rw.3578009515 |
|
|
Feb 04 02:35:37 PM PST 24 |
Feb 04 02:35:52 PM PST 24 |
698149022 ps |
| T451 |
/workspace/coverage/default/22.spi_device_read_buffer_direct.3901979583 |
|
|
Feb 04 02:36:24 PM PST 24 |
Feb 04 02:36:29 PM PST 24 |
362227640 ps |
| T452 |
/workspace/coverage/default/30.spi_device_tpm_rw.1136678940 |
|
|
Feb 04 02:36:41 PM PST 24 |
Feb 04 02:36:53 PM PST 24 |
320834008 ps |
| T453 |
/workspace/coverage/default/4.spi_device_read_buffer_direct.4132919850 |
|
|
Feb 04 02:34:18 PM PST 24 |
Feb 04 02:34:26 PM PST 24 |
75746631 ps |
| T454 |
/workspace/coverage/default/8.spi_device_ram_cfg.174460984 |
|
|
Feb 04 02:34:55 PM PST 24 |
Feb 04 02:34:59 PM PST 24 |
18042880 ps |
| T148 |
/workspace/coverage/default/37.spi_device_stress_all.3009822075 |
|
|
Feb 04 02:37:29 PM PST 24 |
Feb 04 02:40:44 PM PST 24 |
60530660717 ps |
| T455 |
/workspace/coverage/default/38.spi_device_tpm_sts_read.2485047576 |
|
|
Feb 04 02:37:30 PM PST 24 |
Feb 04 02:37:35 PM PST 24 |
501791463 ps |
| T456 |
/workspace/coverage/default/48.spi_device_tpm_rw.803375765 |
|
|
Feb 04 02:38:10 PM PST 24 |
Feb 04 02:38:13 PM PST 24 |
255400944 ps |
| T230 |
/workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1454177191 |
|
|
Feb 04 02:37:28 PM PST 24 |
Feb 04 02:38:09 PM PST 24 |
16810951800 ps |
| T457 |
/workspace/coverage/default/9.spi_device_read_buffer_direct.3717510570 |
|
|
Feb 04 02:35:02 PM PST 24 |
Feb 04 02:35:11 PM PST 24 |
4773835322 ps |
| T458 |
/workspace/coverage/default/12.spi_device_upload.2771222977 |
|
|
Feb 04 02:35:35 PM PST 24 |
Feb 04 02:35:48 PM PST 24 |
272155913 ps |
| T55 |
/workspace/coverage/default/4.spi_device_sec_cm.1374874720 |
|
|
Feb 04 02:34:18 PM PST 24 |
Feb 04 02:34:24 PM PST 24 |
339629322 ps |
| T59 |
/workspace/coverage/default/39.spi_device_upload.1979872693 |
|
|
Feb 04 02:37:29 PM PST 24 |
Feb 04 02:37:47 PM PST 24 |
6420931364 ps |
| T60 |
/workspace/coverage/default/45.spi_device_tpm_all.785546851 |
|
|
Feb 04 02:38:08 PM PST 24 |
Feb 04 02:38:33 PM PST 24 |
6684102851 ps |
| T61 |
/workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2217691808 |
|
|
Feb 04 02:34:08 PM PST 24 |
Feb 04 02:39:47 PM PST 24 |
147692064619 ps |
| T62 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.1307025247 |
|
|
Feb 04 02:34:14 PM PST 24 |
Feb 04 02:34:38 PM PST 24 |
17444848477 ps |
| T63 |
/workspace/coverage/default/9.spi_device_tpm_sts_read.2128829099 |
|
|
Feb 04 02:35:07 PM PST 24 |
Feb 04 02:35:13 PM PST 24 |
53252533 ps |
| T64 |
/workspace/coverage/default/1.spi_device_flash_all.3570523386 |
|
|
Feb 04 02:34:08 PM PST 24 |
Feb 04 02:42:26 PM PST 24 |
100614037710 ps |
| T277 |
/workspace/coverage/default/26.spi_device_tpm_all.3540833999 |
|
|
Feb 04 02:36:34 PM PST 24 |
Feb 04 02:37:08 PM PST 24 |
1945798217 ps |
| T459 |
/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3137204602 |
|
|
Feb 04 02:35:30 PM PST 24 |
Feb 04 02:35:53 PM PST 24 |
3549039175 ps |
| T460 |
/workspace/coverage/default/23.spi_device_read_buffer_direct.2255843965 |
|
|
Feb 04 02:36:31 PM PST 24 |
Feb 04 02:36:37 PM PST 24 |
898649349 ps |
| T461 |
/workspace/coverage/default/37.spi_device_tpm_all.3983254140 |
|
|
Feb 04 02:37:29 PM PST 24 |
Feb 04 02:38:37 PM PST 24 |
40427800922 ps |
| T462 |
/workspace/coverage/default/11.spi_device_mailbox.4148902959 |
|
|
Feb 04 02:35:08 PM PST 24 |
Feb 04 02:35:23 PM PST 24 |
4972949033 ps |
| T235 |
/workspace/coverage/default/3.spi_device_cfg_cmd.2225964731 |
|
|
Feb 04 02:34:18 PM PST 24 |
Feb 04 02:34:26 PM PST 24 |
226126124 ps |
| T463 |
/workspace/coverage/default/23.spi_device_pass_cmd_filtering.3532454317 |
|
|
Feb 04 02:36:16 PM PST 24 |
Feb 04 02:36:46 PM PST 24 |
13859966777 ps |
| T273 |
/workspace/coverage/default/7.spi_device_flash_mode.371942968 |
|
|
Feb 04 02:34:44 PM PST 24 |
Feb 04 02:35:12 PM PST 24 |
14703231833 ps |
| T464 |
/workspace/coverage/default/40.spi_device_csb_read.1598525413 |
|
|
Feb 04 02:37:34 PM PST 24 |
Feb 04 02:37:40 PM PST 24 |
70380723 ps |
| T181 |
/workspace/coverage/default/32.spi_device_flash_all.3411019522 |
|
|
Feb 04 02:37:02 PM PST 24 |
Feb 04 02:37:30 PM PST 24 |
5240062098 ps |
| T465 |
/workspace/coverage/default/8.spi_device_read_buffer_direct.3964357526 |
|
|
Feb 04 02:35:03 PM PST 24 |
Feb 04 02:35:11 PM PST 24 |
881410986 ps |
| T275 |
/workspace/coverage/default/27.spi_device_flash_mode.609569127 |
|
|
Feb 04 02:36:41 PM PST 24 |
Feb 04 02:37:09 PM PST 24 |
10036443177 ps |
| T203 |
/workspace/coverage/default/10.spi_device_mailbox.829521898 |
|
|
Feb 04 02:35:12 PM PST 24 |
Feb 04 02:35:24 PM PST 24 |
1704630450 ps |
| T466 |
/workspace/coverage/default/20.spi_device_tpm_sts_read.1606480610 |
|
|
Feb 04 02:35:55 PM PST 24 |
Feb 04 02:36:01 PM PST 24 |
141086824 ps |
| T467 |
/workspace/coverage/default/34.spi_device_stress_all.1267401130 |
|
|
Feb 04 02:36:53 PM PST 24 |
Feb 04 02:37:00 PM PST 24 |
33402092 ps |
| T468 |
/workspace/coverage/default/5.spi_device_pass_cmd_filtering.2222573373 |
|
|
Feb 04 02:34:27 PM PST 24 |
Feb 04 02:34:41 PM PST 24 |
105252654 ps |
| T219 |
/workspace/coverage/default/43.spi_device_upload.3399770862 |
|
|
Feb 04 02:37:45 PM PST 24 |
Feb 04 02:38:00 PM PST 24 |
10096617655 ps |
| T149 |
/workspace/coverage/default/18.spi_device_stress_all.3501150588 |
|
|
Feb 04 02:35:46 PM PST 24 |
Feb 04 02:38:34 PM PST 24 |
18353740449 ps |
| T469 |
/workspace/coverage/default/9.spi_device_ram_cfg.3108363587 |
|
|
Feb 04 02:34:55 PM PST 24 |
Feb 04 02:34:58 PM PST 24 |
48784766 ps |
| T470 |
/workspace/coverage/default/45.spi_device_read_buffer_direct.1909892402 |
|
|
Feb 04 02:38:06 PM PST 24 |
Feb 04 02:38:16 PM PST 24 |
1797610932 ps |
| T56 |
/workspace/coverage/default/0.spi_device_sec_cm.1490806669 |
|
|
Feb 04 02:33:40 PM PST 24 |
Feb 04 02:33:42 PM PST 24 |
66150660 ps |
| T231 |
/workspace/coverage/default/36.spi_device_flash_all.21908940 |
|
|
Feb 04 02:37:18 PM PST 24 |
Feb 04 02:37:50 PM PST 24 |
26442116780 ps |
| T240 |
/workspace/coverage/default/1.spi_device_pass_cmd_filtering.3793287631 |
|
|
Feb 04 02:34:05 PM PST 24 |
Feb 04 02:34:16 PM PST 24 |
3307287202 ps |
| T198 |
/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4005738364 |
|
|
Feb 04 02:35:43 PM PST 24 |
Feb 04 02:37:35 PM PST 24 |
8536986314 ps |
| T471 |
/workspace/coverage/default/39.spi_device_csb_read.2588491107 |
|
|
Feb 04 02:37:26 PM PST 24 |
Feb 04 02:37:34 PM PST 24 |
60777675 ps |
| T472 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3683861298 |
|
|
Feb 04 02:35:54 PM PST 24 |
Feb 04 02:36:17 PM PST 24 |
5666432755 ps |
| T164 |
/workspace/coverage/default/24.spi_device_mailbox.3133501766 |
|
|
Feb 04 02:36:34 PM PST 24 |
Feb 04 02:36:53 PM PST 24 |
3266549770 ps |
| T473 |
/workspace/coverage/default/19.spi_device_tpm_rw.1398896818 |
|
|
Feb 04 02:35:47 PM PST 24 |
Feb 04 02:35:59 PM PST 24 |
708134699 ps |
| T474 |
/workspace/coverage/default/2.spi_device_alert_test.4200500580 |
|
|
Feb 04 02:34:10 PM PST 24 |
Feb 04 02:34:17 PM PST 24 |
15576148 ps |
| T475 |
/workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3042419798 |
|
|
Feb 04 02:37:33 PM PST 24 |
Feb 04 02:37:49 PM PST 24 |
7606454788 ps |
| T185 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.2021059246 |
|
|
Feb 04 02:34:03 PM PST 24 |
Feb 04 02:34:19 PM PST 24 |
6012741567 ps |
| T476 |
/workspace/coverage/default/41.spi_device_flash_and_tpm.1072854804 |
|
|
Feb 04 02:37:42 PM PST 24 |
Feb 04 02:40:37 PM PST 24 |
102443517250 ps |
| T477 |
/workspace/coverage/default/43.spi_device_cfg_cmd.1020921995 |
|
|
Feb 04 02:37:44 PM PST 24 |
Feb 04 02:37:53 PM PST 24 |
1445918195 ps |
| T184 |
/workspace/coverage/default/9.spi_device_flash_and_tpm.1177142197 |
|
|
Feb 04 02:35:05 PM PST 24 |
Feb 04 02:42:49 PM PST 24 |
260930976808 ps |
| T478 |
/workspace/coverage/default/5.spi_device_alert_test.1738303616 |
|
|
Feb 04 02:34:24 PM PST 24 |
Feb 04 02:34:37 PM PST 24 |
14970680 ps |
| T183 |
/workspace/coverage/default/7.spi_device_stress_all.3737789995 |
|
|
Feb 04 02:34:48 PM PST 24 |
Feb 04 02:46:12 PM PST 24 |
166002264335 ps |
| T241 |
/workspace/coverage/default/28.spi_device_intercept.2085732077 |
|
|
Feb 04 02:36:37 PM PST 24 |
Feb 04 02:36:45 PM PST 24 |
752376563 ps |
| T195 |
/workspace/coverage/default/20.spi_device_flash_all.1788397796 |
|
|
Feb 04 02:36:07 PM PST 24 |
Feb 04 02:37:24 PM PST 24 |
7364601688 ps |
| T165 |
/workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3396094724 |
|
|
Feb 04 02:34:09 PM PST 24 |
Feb 04 02:34:26 PM PST 24 |
2350242066 ps |
| T479 |
/workspace/coverage/default/49.spi_device_upload.2463458821 |
|
|
Feb 04 02:38:22 PM PST 24 |
Feb 04 02:38:35 PM PST 24 |
4406953014 ps |
| T237 |
/workspace/coverage/default/43.spi_device_mailbox.4208989614 |
|
|
Feb 04 02:37:48 PM PST 24 |
Feb 04 02:38:31 PM PST 24 |
44471372135 ps |
| T480 |
/workspace/coverage/default/18.spi_device_csb_read.2668001951 |
|
|
Feb 04 02:35:47 PM PST 24 |
Feb 04 02:35:57 PM PST 24 |
13620042 ps |
| T481 |
/workspace/coverage/default/1.spi_device_cfg_cmd.185019790 |
|
|
Feb 04 02:34:06 PM PST 24 |
Feb 04 02:34:18 PM PST 24 |
2690624583 ps |
| T482 |
/workspace/coverage/default/47.spi_device_alert_test.4082091730 |
|
|
Feb 04 02:38:15 PM PST 24 |
Feb 04 02:38:18 PM PST 24 |
13398108 ps |
| T483 |
/workspace/coverage/default/28.spi_device_cfg_cmd.764112518 |
|
|
Feb 04 02:36:42 PM PST 24 |
Feb 04 02:36:54 PM PST 24 |
514949967 ps |
| T484 |
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3864496595 |
|
|
Feb 04 02:34:41 PM PST 24 |
Feb 04 02:34:47 PM PST 24 |
2493203417 ps |
| T160 |
/workspace/coverage/default/31.spi_device_flash_all.3820885850 |
|
|
Feb 04 02:36:49 PM PST 24 |
Feb 04 02:42:16 PM PST 24 |
284419675748 ps |
| T485 |
/workspace/coverage/default/13.spi_device_pass_cmd_filtering.1113260838 |
|
|
Feb 04 02:35:30 PM PST 24 |
Feb 04 02:35:45 PM PST 24 |
10997818080 ps |
| T486 |
/workspace/coverage/default/45.spi_device_csb_read.195717119 |
|
|
Feb 04 02:38:16 PM PST 24 |
Feb 04 02:38:19 PM PST 24 |
45412572 ps |
| T68 |
/workspace/coverage/default/42.spi_device_flash_and_tpm.2506905559 |
|
|
Feb 04 02:37:53 PM PST 24 |
Feb 04 02:38:34 PM PST 24 |
4829732072 ps |
| T487 |
/workspace/coverage/default/45.spi_device_upload.2901936602 |
|
|
Feb 04 02:38:05 PM PST 24 |
Feb 04 02:38:16 PM PST 24 |
1254038344 ps |
| T488 |
/workspace/coverage/default/16.spi_device_tpm_read_hw_reg.43512357 |
|
|
Feb 04 02:35:44 PM PST 24 |
Feb 04 02:36:05 PM PST 24 |
5074864511 ps |
| T243 |
/workspace/coverage/default/13.spi_device_flash_and_tpm.2868416404 |
|
|
Feb 04 02:35:30 PM PST 24 |
Feb 04 02:37:12 PM PST 24 |
12208931035 ps |
| T489 |
/workspace/coverage/default/7.spi_device_alert_test.4155895218 |
|
|
Feb 04 02:34:54 PM PST 24 |
Feb 04 02:34:56 PM PST 24 |
16494486 ps |
| T490 |
/workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2669578940 |
|
|
Feb 04 02:38:16 PM PST 24 |
Feb 04 02:38:32 PM PST 24 |
8200047025 ps |
| T234 |
/workspace/coverage/default/45.spi_device_intercept.3465184007 |
|
|
Feb 04 02:38:04 PM PST 24 |
Feb 04 02:38:10 PM PST 24 |
2375633490 ps |
| T491 |
/workspace/coverage/default/31.spi_device_tpm_rw.422575117 |
|
|
Feb 04 02:36:47 PM PST 24 |
Feb 04 02:36:56 PM PST 24 |
26683795 ps |
| T196 |
/workspace/coverage/default/7.spi_device_intercept.3585842250 |
|
|
Feb 04 02:34:36 PM PST 24 |
Feb 04 02:34:43 PM PST 24 |
1035299724 ps |
| T492 |
/workspace/coverage/default/38.spi_device_csb_read.3613878485 |
|
|
Feb 04 02:37:26 PM PST 24 |
Feb 04 02:37:34 PM PST 24 |
15397647 ps |
| T493 |
/workspace/coverage/default/44.spi_device_alert_test.3619802448 |
|
|
Feb 04 02:38:05 PM PST 24 |
Feb 04 02:38:08 PM PST 24 |
30054418 ps |
| T494 |
/workspace/coverage/default/8.spi_device_tpm_sts_read.145056973 |
|
|
Feb 04 02:34:54 PM PST 24 |
Feb 04 02:34:58 PM PST 24 |
958884550 ps |
| T201 |
/workspace/coverage/default/37.spi_device_intercept.590744818 |
|
|
Feb 04 02:37:30 PM PST 24 |
Feb 04 02:37:37 PM PST 24 |
730729722 ps |
| T495 |
/workspace/coverage/default/20.spi_device_tpm_rw.1499656706 |
|
|
Feb 04 02:35:52 PM PST 24 |
Feb 04 02:36:00 PM PST 24 |
30352963 ps |
| T276 |
/workspace/coverage/default/28.spi_device_flash_mode.1494867442 |
|
|
Feb 04 02:36:44 PM PST 24 |
Feb 04 02:37:09 PM PST 24 |
1569150596 ps |
| T496 |
/workspace/coverage/default/0.spi_device_tpm_rw.3980566241 |
|
|
Feb 04 02:33:44 PM PST 24 |
Feb 04 02:33:46 PM PST 24 |
25259716 ps |
| T497 |
/workspace/coverage/default/18.spi_device_ram_cfg.3348588852 |
|
|
Feb 04 02:35:51 PM PST 24 |
Feb 04 02:35:59 PM PST 24 |
17430875 ps |
| T498 |
/workspace/coverage/default/44.spi_device_flash_all.679667954 |
|
|
Feb 04 02:37:48 PM PST 24 |
Feb 04 02:42:20 PM PST 24 |
56457131121 ps |
| T499 |
/workspace/coverage/default/31.spi_device_alert_test.4085318857 |
|
|
Feb 04 02:37:02 PM PST 24 |
Feb 04 02:37:05 PM PST 24 |
30251361 ps |
| T500 |
/workspace/coverage/default/19.spi_device_flash_mode.3831524360 |
|
|
Feb 04 02:35:58 PM PST 24 |
Feb 04 02:36:26 PM PST 24 |
17689087587 ps |
| T272 |
/workspace/coverage/default/43.spi_device_flash_mode.3354453360 |
|
|
Feb 04 02:37:52 PM PST 24 |
Feb 04 02:38:11 PM PST 24 |
4275191445 ps |
| T501 |
/workspace/coverage/default/6.spi_device_flash_mode.304092696 |
|
|
Feb 04 02:34:37 PM PST 24 |
Feb 04 02:35:17 PM PST 24 |
23178943859 ps |
| T502 |
/workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3590202020 |
|
|
Feb 04 02:37:36 PM PST 24 |
Feb 04 02:41:46 PM PST 24 |
34243163430 ps |
| T503 |
/workspace/coverage/default/29.spi_device_mailbox.2993351998 |
|
|
Feb 04 02:36:44 PM PST 24 |
Feb 04 02:36:57 PM PST 24 |
79914067 ps |
| T504 |
/workspace/coverage/default/11.spi_device_flash_mode.3399077481 |
|
|
Feb 04 02:35:13 PM PST 24 |
Feb 04 02:35:30 PM PST 24 |
1655023564 ps |
| T505 |
/workspace/coverage/default/24.spi_device_alert_test.442604312 |
|
|
Feb 04 02:36:33 PM PST 24 |
Feb 04 02:36:41 PM PST 24 |
50672064 ps |
| T506 |
/workspace/coverage/default/7.spi_device_ram_cfg.3087221008 |
|
|
Feb 04 02:34:34 PM PST 24 |
Feb 04 02:34:40 PM PST 24 |
34646281 ps |
| T202 |
/workspace/coverage/default/13.spi_device_mailbox.1802016408 |
|
|
Feb 04 02:35:30 PM PST 24 |
Feb 04 02:35:58 PM PST 24 |
10190803983 ps |
| T507 |
/workspace/coverage/default/17.spi_device_intercept.2418923377 |
|
|
Feb 04 02:35:44 PM PST 24 |
Feb 04 02:35:59 PM PST 24 |
127180180 ps |
| T210 |
/workspace/coverage/default/48.spi_device_stress_all.1297500542 |
|
|
Feb 04 02:38:12 PM PST 24 |
Feb 04 02:45:50 PM PST 24 |
279364439866 ps |
| T206 |
/workspace/coverage/default/15.spi_device_mailbox.3246515 |
|
|
Feb 04 02:35:39 PM PST 24 |
Feb 04 02:35:53 PM PST 24 |
246476220 ps |
| T508 |
/workspace/coverage/default/8.spi_device_flash_and_tpm.2182770568 |
|
|
Feb 04 02:35:09 PM PST 24 |
Feb 04 02:38:27 PM PST 24 |
90162461551 ps |
| T509 |
/workspace/coverage/default/13.spi_device_read_buffer_direct.2323877887 |
|
|
Feb 04 02:35:26 PM PST 24 |
Feb 04 02:35:39 PM PST 24 |
723602062 ps |
| T510 |
/workspace/coverage/default/21.spi_device_tpm_rw.1048372227 |
|
|
Feb 04 02:36:13 PM PST 24 |
Feb 04 02:36:21 PM PST 24 |
25808635 ps |
| T511 |
/workspace/coverage/default/16.spi_device_mem_parity.183582611 |
|
|
Feb 04 02:35:39 PM PST 24 |
Feb 04 02:35:51 PM PST 24 |
78308614 ps |
| T512 |
/workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2352800922 |
|
|
Feb 04 02:35:27 PM PST 24 |
Feb 04 02:35:44 PM PST 24 |
1398103654 ps |
| T166 |
/workspace/coverage/default/37.spi_device_flash_and_tpm.2979495216 |
|
|
Feb 04 02:37:25 PM PST 24 |
Feb 04 02:39:51 PM PST 24 |
16765838356 ps |
| T513 |
/workspace/coverage/default/14.spi_device_ram_cfg.3200041622 |
|
|
Feb 04 02:35:27 PM PST 24 |
Feb 04 02:35:36 PM PST 24 |
35930611 ps |
| T514 |
/workspace/coverage/default/16.spi_device_flash_mode.4048427030 |
|
|
Feb 04 02:35:43 PM PST 24 |
Feb 04 02:36:03 PM PST 24 |
1596787369 ps |
| T515 |
/workspace/coverage/default/27.spi_device_tpm_rw.1413458839 |
|
|
Feb 04 02:36:39 PM PST 24 |
Feb 04 02:36:44 PM PST 24 |
15974298 ps |
| T516 |
/workspace/coverage/default/31.spi_device_csb_read.698779284 |
|
|
Feb 04 02:36:43 PM PST 24 |
Feb 04 02:36:55 PM PST 24 |
53680658 ps |
| T517 |
/workspace/coverage/default/29.spi_device_flash_and_tpm.3380022414 |
|
|
Feb 04 02:36:50 PM PST 24 |
Feb 04 02:37:54 PM PST 24 |
4721731304 ps |
| T518 |
/workspace/coverage/default/18.spi_device_flash_and_tpm.793788078 |
|
|
Feb 04 02:35:52 PM PST 24 |
Feb 04 02:39:07 PM PST 24 |
26116022154 ps |
| T519 |
/workspace/coverage/default/39.spi_device_stress_all.3531264127 |
|
|
Feb 04 02:37:29 PM PST 24 |
Feb 04 02:40:16 PM PST 24 |
95502634229 ps |
| T520 |
/workspace/coverage/default/47.spi_device_csb_read.331974721 |
|
|
Feb 04 02:38:08 PM PST 24 |
Feb 04 02:38:11 PM PST 24 |
199269653 ps |
| T521 |
/workspace/coverage/default/34.spi_device_flash_all.2234030584 |
|
|
Feb 04 02:36:58 PM PST 24 |
Feb 04 02:38:03 PM PST 24 |
31872395314 ps |
| T522 |
/workspace/coverage/default/13.spi_device_ram_cfg.2920064499 |
|
|
Feb 04 02:35:29 PM PST 24 |
Feb 04 02:35:37 PM PST 24 |
40516703 ps |
| T523 |
/workspace/coverage/default/41.spi_device_csb_read.2083799805 |
|
|
Feb 04 02:37:38 PM PST 24 |
Feb 04 02:37:41 PM PST 24 |
16191491 ps |
| T524 |
/workspace/coverage/default/49.spi_device_csb_read.95296382 |
|
|
Feb 04 02:38:21 PM PST 24 |
Feb 04 02:38:23 PM PST 24 |
20351618 ps |
| T525 |
/workspace/coverage/default/2.spi_device_csb_read.3242826671 |
|
|
Feb 04 02:34:05 PM PST 24 |
Feb 04 02:34:10 PM PST 24 |
14834685 ps |
| T526 |
/workspace/coverage/default/8.spi_device_mailbox.2445860809 |
|
|
Feb 04 02:34:57 PM PST 24 |
Feb 04 02:35:14 PM PST 24 |
11208439642 ps |
| T527 |
/workspace/coverage/default/39.spi_device_tpm_rw.2344714090 |
|
|
Feb 04 02:37:40 PM PST 24 |
Feb 04 02:37:42 PM PST 24 |
54080680 ps |
| T189 |
/workspace/coverage/default/47.spi_device_flash_and_tpm.536601483 |
|
|
Feb 04 02:38:15 PM PST 24 |
Feb 04 02:40:38 PM PST 24 |
129041590872 ps |
| T528 |
/workspace/coverage/default/35.spi_device_pass_cmd_filtering.1250869293 |
|
|
Feb 04 02:37:23 PM PST 24 |
Feb 04 02:37:33 PM PST 24 |
4825356346 ps |
| T227 |
/workspace/coverage/default/13.spi_device_pass_addr_payload_swap.911293369 |
|
|
Feb 04 02:35:29 PM PST 24 |
Feb 04 02:35:49 PM PST 24 |
11260724417 ps |
| T529 |
/workspace/coverage/default/13.spi_device_tpm_rw.1225735392 |
|
|
Feb 04 02:35:32 PM PST 24 |
Feb 04 02:35:44 PM PST 24 |
200420020 ps |
| T530 |
/workspace/coverage/default/24.spi_device_flash_mode.2371932701 |
|
|
Feb 04 02:36:22 PM PST 24 |
Feb 04 02:36:35 PM PST 24 |
6077279917 ps |
| T531 |
/workspace/coverage/default/30.spi_device_csb_read.3402434545 |
|
|
Feb 04 02:36:52 PM PST 24 |
Feb 04 02:36:59 PM PST 24 |
40687955 ps |
| T532 |
/workspace/coverage/default/47.spi_device_tpm_rw.970124833 |
|
|
Feb 04 02:38:07 PM PST 24 |
Feb 04 02:38:09 PM PST 24 |
28367459 ps |
| T533 |
/workspace/coverage/default/5.spi_device_flash_mode.3825295963 |
|
|
Feb 04 02:34:31 PM PST 24 |
Feb 04 02:34:51 PM PST 24 |
7845433683 ps |
| T534 |
/workspace/coverage/default/6.spi_device_alert_test.1905952990 |
|
|
Feb 04 02:34:37 PM PST 24 |
Feb 04 02:34:41 PM PST 24 |
15226047 ps |
| T194 |
/workspace/coverage/default/3.spi_device_flash_all.1988389330 |
|
|
Feb 04 02:34:17 PM PST 24 |
Feb 04 02:35:27 PM PST 24 |
26337664456 ps |
| T535 |
/workspace/coverage/default/44.spi_device_flash_and_tpm.2676181883 |
|
|
Feb 04 02:37:51 PM PST 24 |
Feb 04 02:41:01 PM PST 24 |
22455210962 ps |
| T536 |
/workspace/coverage/default/13.spi_device_flash_all.2416406014 |
|
|
Feb 04 02:35:26 PM PST 24 |
Feb 04 02:39:30 PM PST 24 |
86553749572 ps |
| T537 |
/workspace/coverage/default/6.spi_device_mem_parity.3302490898 |
|
|
Feb 04 02:34:29 PM PST 24 |
Feb 04 02:34:39 PM PST 24 |
14282562 ps |
| T538 |
/workspace/coverage/default/40.spi_device_read_buffer_direct.777855587 |
|
|
Feb 04 02:37:38 PM PST 24 |
Feb 04 02:37:44 PM PST 24 |
1077163093 ps |
| T539 |
/workspace/coverage/default/3.spi_device_csb_read.787168770 |
|
|
Feb 04 02:34:08 PM PST 24 |
Feb 04 02:34:17 PM PST 24 |
62681102 ps |
| T540 |
/workspace/coverage/default/27.spi_device_read_buffer_direct.1964159834 |
|
|
Feb 04 02:36:31 PM PST 24 |
Feb 04 02:36:40 PM PST 24 |
498873496 ps |
| T541 |
/workspace/coverage/default/42.spi_device_upload.1392742885 |
|
|
Feb 04 02:37:45 PM PST 24 |
Feb 04 02:37:52 PM PST 24 |
221677545 ps |
| T542 |
/workspace/coverage/default/15.spi_device_pass_cmd_filtering.2887672723 |
|
|
Feb 04 02:35:37 PM PST 24 |
Feb 04 02:35:53 PM PST 24 |
251420688 ps |
| T543 |
/workspace/coverage/default/46.spi_device_mailbox.706998877 |
|
|
Feb 04 02:38:07 PM PST 24 |
Feb 04 02:38:11 PM PST 24 |
159771564 ps |
| T544 |
/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2899883286 |
|
|
Feb 04 02:36:40 PM PST 24 |
Feb 04 02:36:51 PM PST 24 |
94241319 ps |
| T545 |
/workspace/coverage/default/23.spi_device_tpm_all.4194620546 |
|
|
Feb 04 02:36:07 PM PST 24 |
Feb 04 02:36:53 PM PST 24 |
18194063952 ps |
| T546 |
/workspace/coverage/default/18.spi_device_alert_test.4083604937 |
|
|
Feb 04 02:35:54 PM PST 24 |
Feb 04 02:36:00 PM PST 24 |
47442407 ps |
| T547 |
/workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1431217078 |
|
|
Feb 04 02:35:54 PM PST 24 |
Feb 04 02:36:14 PM PST 24 |
5251366239 ps |
| T548 |
/workspace/coverage/default/21.spi_device_mailbox.742790393 |
|
|
Feb 04 02:36:14 PM PST 24 |
Feb 04 02:36:27 PM PST 24 |
3248327146 ps |