Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.18 98.51 94.87 98.60 89.36 97.29 96.40 98.24


Total test records in report: 1116
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T1001 /workspace/coverage/default/25.spi_device_stress_all.3437116553 Feb 04 02:36:30 PM PST 24 Feb 04 02:37:37 PM PST 24 23362697360 ps
T1002 /workspace/coverage/default/7.spi_device_mailbox.2211954349 Feb 04 02:34:38 PM PST 24 Feb 04 02:34:58 PM PST 24 24742940769 ps
T1003 /workspace/coverage/default/5.spi_device_mem_parity.1432240824 Feb 04 02:34:20 PM PST 24 Feb 04 02:34:25 PM PST 24 20991814 ps
T1004 /workspace/coverage/default/5.spi_device_csb_read.1490838906 Feb 04 02:34:20 PM PST 24 Feb 04 02:34:24 PM PST 24 61181602 ps
T1005 /workspace/coverage/default/17.spi_device_read_buffer_direct.3496955636 Feb 04 02:35:41 PM PST 24 Feb 04 02:35:57 PM PST 24 1026346766 ps
T1006 /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2896174584 Feb 04 02:35:05 PM PST 24 Feb 04 02:36:00 PM PST 24 2790862443 ps
T1007 /workspace/coverage/default/8.spi_device_cfg_cmd.2486652977 Feb 04 02:34:54 PM PST 24 Feb 04 02:34:58 PM PST 24 500646386 ps
T1008 /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3394454659 Feb 04 02:37:43 PM PST 24 Feb 04 02:38:03 PM PST 24 6990987332 ps
T1009 /workspace/coverage/default/20.spi_device_intercept.4136001377 Feb 04 02:35:54 PM PST 24 Feb 04 02:36:02 PM PST 24 100036387 ps
T1010 /workspace/coverage/default/35.spi_device_upload.2505970605 Feb 04 02:37:26 PM PST 24 Feb 04 02:37:48 PM PST 24 59820738464 ps
T1011 /workspace/coverage/default/0.spi_device_upload.1645940191 Feb 04 02:33:41 PM PST 24 Feb 04 02:33:48 PM PST 24 530990520 ps
T1012 /workspace/coverage/default/25.spi_device_flash_mode.1499531195 Feb 04 02:36:45 PM PST 24 Feb 04 02:37:15 PM PST 24 658930506 ps
T1013 /workspace/coverage/default/35.spi_device_flash_and_tpm.456549719 Feb 04 02:37:18 PM PST 24 Feb 04 02:44:51 PM PST 24 60557893814 ps
T1014 /workspace/coverage/default/12.spi_device_flash_mode.2408165207 Feb 04 02:35:28 PM PST 24 Feb 04 02:36:12 PM PST 24 21475567046 ps
T1015 /workspace/coverage/default/48.spi_device_csb_read.498693891 Feb 04 02:38:14 PM PST 24 Feb 04 02:38:16 PM PST 24 44374741 ps
T1016 /workspace/coverage/default/1.spi_device_csb_read.4030953422 Feb 04 02:33:47 PM PST 24 Feb 04 02:34:01 PM PST 24 83791854 ps
T1017 /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1217705140 Feb 04 02:36:27 PM PST 24 Feb 04 02:36:55 PM PST 24 36560112817 ps
T1018 /workspace/coverage/default/23.spi_device_flash_mode.1931542035 Feb 04 02:36:28 PM PST 24 Feb 04 02:36:37 PM PST 24 340567072 ps
T1019 /workspace/coverage/default/11.spi_device_ram_cfg.1424159272 Feb 04 02:35:04 PM PST 24 Feb 04 02:35:09 PM PST 24 16944495 ps
T1020 /workspace/coverage/default/30.spi_device_stress_all.4187020173 Feb 04 02:36:50 PM PST 24 Feb 04 02:44:46 PM PST 24 76771198512 ps
T1021 /workspace/coverage/default/24.spi_device_flash_all.469927570 Feb 04 02:36:28 PM PST 24 Feb 04 02:37:49 PM PST 24 28543540363 ps
T1022 /workspace/coverage/default/36.spi_device_read_buffer_direct.14562654 Feb 04 02:37:27 PM PST 24 Feb 04 02:37:40 PM PST 24 1796736243 ps
T1023 /workspace/coverage/default/24.spi_device_tpm_sts_read.3687639745 Feb 04 02:36:36 PM PST 24 Feb 04 02:36:42 PM PST 24 54118355 ps
T1024 /workspace/coverage/default/20.spi_device_cfg_cmd.4258725691 Feb 04 02:35:53 PM PST 24 Feb 04 02:36:04 PM PST 24 4374309556 ps
T1025 /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2961373231 Feb 04 02:36:32 PM PST 24 Feb 04 02:36:40 PM PST 24 184569337 ps
T1026 /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3229175205 Feb 04 02:34:38 PM PST 24 Feb 04 02:35:00 PM PST 24 14539665673 ps
T1027 /workspace/coverage/default/26.spi_device_flash_and_tpm.3587918338 Feb 04 02:36:34 PM PST 24 Feb 04 02:39:04 PM PST 24 16634137506 ps
T1028 /workspace/coverage/default/3.spi_device_tpm_sts_read.2140666218 Feb 04 02:34:06 PM PST 24 Feb 04 02:34:17 PM PST 24 118842391 ps
T1029 /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3325835614 Feb 04 02:34:09 PM PST 24 Feb 04 02:34:26 PM PST 24 1868597295 ps
T1030 /workspace/coverage/default/40.spi_device_mailbox.2157160912 Feb 04 02:37:42 PM PST 24 Feb 04 02:38:00 PM PST 24 3269807543 ps
T1031 /workspace/coverage/default/42.spi_device_csb_read.2241094718 Feb 04 02:37:40 PM PST 24 Feb 04 02:37:42 PM PST 24 25389223 ps
T1032 /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3783545227 Feb 04 02:37:04 PM PST 24 Feb 04 02:37:37 PM PST 24 10260847767 ps
T1033 /workspace/coverage/default/33.spi_device_mailbox.3961969312 Feb 04 02:36:51 PM PST 24 Feb 04 02:37:55 PM PST 24 78482092466 ps
T1034 /workspace/coverage/default/17.spi_device_pass_cmd_filtering.733997060 Feb 04 02:35:46 PM PST 24 Feb 04 02:36:18 PM PST 24 30072004395 ps
T1035 /workspace/coverage/default/49.spi_device_tpm_rw.388811856 Feb 04 02:38:16 PM PST 24 Feb 04 02:38:20 PM PST 24 49804378 ps
T1036 /workspace/coverage/default/25.spi_device_tpm_all.2827930698 Feb 04 02:36:45 PM PST 24 Feb 04 02:37:30 PM PST 24 13876183016 ps
T1037 /workspace/coverage/default/14.spi_device_tpm_sts_read.4006902241 Feb 04 02:35:31 PM PST 24 Feb 04 02:35:40 PM PST 24 64465973 ps
T1038 /workspace/coverage/default/20.spi_device_read_buffer_direct.2764438921 Feb 04 02:36:15 PM PST 24 Feb 04 02:36:27 PM PST 24 1431086632 ps
T1039 /workspace/coverage/default/3.spi_device_alert_test.2527707236 Feb 04 02:34:23 PM PST 24 Feb 04 02:34:36 PM PST 24 72946727 ps
T1040 /workspace/coverage/default/5.spi_device_mailbox.1752004927 Feb 04 02:34:46 PM PST 24 Feb 04 02:35:00 PM PST 24 4108520131 ps
T1041 /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1324831092 Feb 04 02:36:11 PM PST 24 Feb 04 02:36:17 PM PST 24 4387490925 ps
T1042 /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.489837953 Feb 04 02:36:42 PM PST 24 Feb 04 02:37:09 PM PST 24 23167257273 ps
T1043 /workspace/coverage/default/49.spi_device_read_buffer_direct.3284516741 Feb 04 02:38:10 PM PST 24 Feb 04 02:38:17 PM PST 24 4781838868 ps
T1044 /workspace/coverage/default/6.spi_device_read_buffer_direct.1151989042 Feb 04 02:34:40 PM PST 24 Feb 04 02:34:46 PM PST 24 619948545 ps
T1045 /workspace/coverage/default/11.spi_device_alert_test.2662693475 Feb 04 02:35:14 PM PST 24 Feb 04 02:35:17 PM PST 24 108619383 ps
T1046 /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.773173202 Feb 04 02:34:36 PM PST 24 Feb 04 02:35:45 PM PST 24 8820848505 ps
T1047 /workspace/coverage/default/46.spi_device_tpm_rw.476083191 Feb 04 02:38:04 PM PST 24 Feb 04 02:38:10 PM PST 24 487380306 ps
T1048 /workspace/coverage/default/0.spi_device_alert_test.2797210896 Feb 04 02:33:50 PM PST 24 Feb 04 02:34:01 PM PST 24 21942712 ps
T1049 /workspace/coverage/default/3.spi_device_mem_parity.1591293073 Feb 04 02:34:15 PM PST 24 Feb 04 02:34:22 PM PST 24 58976164 ps
T1050 /workspace/coverage/default/19.spi_device_stress_all.2295939640 Feb 04 02:35:53 PM PST 24 Feb 04 02:41:21 PM PST 24 79127528577 ps
T1051 /workspace/coverage/default/9.spi_device_csb_read.1621389991 Feb 04 02:35:04 PM PST 24 Feb 04 02:35:11 PM PST 24 34323101 ps
T1052 /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3047840344 Feb 04 02:36:50 PM PST 24 Feb 04 02:37:11 PM PST 24 16495169659 ps
T1053 /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.93230128 Feb 04 02:38:21 PM PST 24 Feb 04 02:41:29 PM PST 24 48169197214 ps
T1054 /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.527702915 Feb 04 02:38:16 PM PST 24 Feb 04 02:45:37 PM PST 24 107027159262 ps
T1055 /workspace/coverage/default/31.spi_device_pass_cmd_filtering.236276120 Feb 04 02:36:51 PM PST 24 Feb 04 02:37:01 PM PST 24 351274742 ps
T1056 /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2935792273 Feb 04 02:37:23 PM PST 24 Feb 04 02:37:30 PM PST 24 1831844459 ps
T1057 /workspace/coverage/default/3.spi_device_upload.2406900904 Feb 04 02:34:18 PM PST 24 Feb 04 02:34:29 PM PST 24 1837618877 ps
T1058 /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1467553501 Feb 04 02:38:01 PM PST 24 Feb 04 02:38:06 PM PST 24 263145796 ps
T1059 /workspace/coverage/default/44.spi_device_flash_mode.642823583 Feb 04 02:37:49 PM PST 24 Feb 04 02:38:01 PM PST 24 450902136 ps
T1060 /workspace/coverage/default/19.spi_device_flash_all.1265613605 Feb 04 02:35:55 PM PST 24 Feb 04 02:39:42 PM PST 24 78868435578 ps
T1061 /workspace/coverage/default/14.spi_device_flash_mode.3827498162 Feb 04 02:35:36 PM PST 24 Feb 04 02:36:16 PM PST 24 14138669739 ps
T1062 /workspace/coverage/default/1.spi_device_tpm_all.2279632723 Feb 04 02:34:06 PM PST 24 Feb 04 02:34:55 PM PST 24 33808466784 ps
T1063 /workspace/coverage/default/38.spi_device_read_buffer_direct.1188925774 Feb 04 02:37:33 PM PST 24 Feb 04 02:37:42 PM PST 24 246114714 ps
T1064 /workspace/coverage/default/44.spi_device_upload.3026082055 Feb 04 02:37:52 PM PST 24 Feb 04 02:37:57 PM PST 24 1667718403 ps
T1065 /workspace/coverage/default/28.spi_device_tpm_sts_read.2841890371 Feb 04 02:36:41 PM PST 24 Feb 04 02:36:50 PM PST 24 20161813 ps
T1066 /workspace/coverage/default/32.spi_device_read_buffer_direct.328881849 Feb 04 02:36:54 PM PST 24 Feb 04 02:37:05 PM PST 24 1608771305 ps
T1067 /workspace/coverage/default/41.spi_device_intercept.4049806393 Feb 04 02:37:38 PM PST 24 Feb 04 02:37:47 PM PST 24 3704927162 ps
T1068 /workspace/coverage/default/23.spi_device_tpm_rw.173156227 Feb 04 02:36:13 PM PST 24 Feb 04 02:36:23 PM PST 24 288751688 ps
T1069 /workspace/coverage/default/15.spi_device_csb_read.3442707095 Feb 04 02:35:39 PM PST 24 Feb 04 02:35:51 PM PST 24 37940491 ps
T1070 /workspace/coverage/default/35.spi_device_flash_mode.1536993727 Feb 04 02:37:16 PM PST 24 Feb 04 02:38:17 PM PST 24 25741337199 ps
T1071 /workspace/coverage/default/49.spi_device_mailbox.32802009 Feb 04 02:38:20 PM PST 24 Feb 04 02:38:27 PM PST 24 780425729 ps
T1072 /workspace/coverage/default/38.spi_device_flash_mode.751128271 Feb 04 02:37:27 PM PST 24 Feb 04 02:38:04 PM PST 24 11937404114 ps
T1073 /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2218496080 Feb 04 02:33:41 PM PST 24 Feb 04 02:34:19 PM PST 24 25487525410 ps
T1074 /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.23863117 Feb 04 02:35:06 PM PST 24 Feb 04 02:35:27 PM PST 24 2434024315 ps
T1075 /workspace/coverage/default/35.spi_device_alert_test.506294547 Feb 04 02:37:09 PM PST 24 Feb 04 02:37:11 PM PST 24 130076487 ps
T1076 /workspace/coverage/default/33.spi_device_stress_all.3599968519 Feb 04 02:36:54 PM PST 24 Feb 04 02:37:00 PM PST 24 165578852 ps
T1077 /workspace/coverage/default/25.spi_device_intercept.2783391528 Feb 04 02:36:33 PM PST 24 Feb 04 02:36:45 PM PST 24 205706512 ps
T1078 /workspace/coverage/default/10.spi_device_cfg_cmd.1794676843 Feb 04 02:35:12 PM PST 24 Feb 04 02:35:28 PM PST 24 26599946876 ps
T1079 /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3135508930 Feb 04 02:37:37 PM PST 24 Feb 04 02:37:43 PM PST 24 829918960 ps
T1080 /workspace/coverage/default/45.spi_device_alert_test.2775756051 Feb 04 02:38:06 PM PST 24 Feb 04 02:38:08 PM PST 24 22888527 ps
T1081 /workspace/coverage/default/27.spi_device_upload.1027858854 Feb 04 02:36:37 PM PST 24 Feb 04 02:36:45 PM PST 24 609903421 ps
T1082 /workspace/coverage/default/33.spi_device_tpm_all.3792009493 Feb 04 02:36:49 PM PST 24 Feb 04 02:37:28 PM PST 24 30223115194 ps
T1083 /workspace/coverage/default/0.spi_device_flash_and_tpm.1499487331 Feb 04 02:33:41 PM PST 24 Feb 04 02:35:05 PM PST 24 12597783230 ps
T1084 /workspace/coverage/default/1.spi_device_intercept.3498088994 Feb 04 02:34:05 PM PST 24 Feb 04 02:34:14 PM PST 24 373372375 ps
T1085 /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1014437553 Feb 04 02:35:08 PM PST 24 Feb 04 02:35:17 PM PST 24 177549751 ps
T1086 /workspace/coverage/default/12.spi_device_mailbox.775465619 Feb 04 02:35:30 PM PST 24 Feb 04 02:35:54 PM PST 24 8201989400 ps
T1087 /workspace/coverage/default/21.spi_device_read_buffer_direct.4189195569 Feb 04 02:36:20 PM PST 24 Feb 04 02:36:29 PM PST 24 1187782748 ps
T1088 /workspace/coverage/default/18.spi_device_tpm_sts_read.1820328017 Feb 04 02:35:46 PM PST 24 Feb 04 02:35:57 PM PST 24 116198312 ps
T1089 /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2711482703 Feb 04 02:34:17 PM PST 24 Feb 04 02:34:49 PM PST 24 1616240999 ps
T1090 /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3613987157 Feb 04 02:37:31 PM PST 24 Feb 04 02:40:19 PM PST 24 14062338130 ps
T1091 /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3389329290 Feb 04 02:34:29 PM PST 24 Feb 04 02:34:47 PM PST 24 4802595207 ps
T1092 /workspace/coverage/default/29.spi_device_stress_all.328833932 Feb 04 02:36:49 PM PST 24 Feb 04 02:40:02 PM PST 24 22651860980 ps
T1093 /workspace/coverage/default/45.spi_device_cfg_cmd.1006763155 Feb 04 02:38:06 PM PST 24 Feb 04 02:38:13 PM PST 24 1605273831 ps
T1094 /workspace/coverage/default/9.spi_device_upload.3336132947 Feb 04 02:34:57 PM PST 24 Feb 04 02:35:07 PM PST 24 14207067581 ps
T1095 /workspace/coverage/default/2.spi_device_tpm_all.3362670796 Feb 04 02:34:04 PM PST 24 Feb 04 02:34:34 PM PST 24 9065917822 ps
T1096 /workspace/coverage/default/18.spi_device_mem_parity.884366018 Feb 04 02:35:46 PM PST 24 Feb 04 02:35:57 PM PST 24 25594258 ps
T1097 /workspace/coverage/default/20.spi_device_mailbox.4262719930 Feb 04 02:35:54 PM PST 24 Feb 04 02:36:23 PM PST 24 28971709584 ps
T1098 /workspace/coverage/default/40.spi_device_alert_test.3598825759 Feb 04 02:37:38 PM PST 24 Feb 04 02:37:41 PM PST 24 14208511 ps
T1099 /workspace/coverage/default/0.spi_device_csb_read.94379215 Feb 04 02:33:42 PM PST 24 Feb 04 02:33:44 PM PST 24 59394267 ps
T1100 /workspace/coverage/default/44.spi_device_csb_read.2468339038 Feb 04 02:37:46 PM PST 24 Feb 04 02:37:50 PM PST 24 41992760 ps
T1101 /workspace/coverage/default/30.spi_device_alert_test.895749924 Feb 04 02:36:48 PM PST 24 Feb 04 02:36:56 PM PST 24 144952692 ps
T1102 /workspace/coverage/default/11.spi_device_mem_parity.2626931398 Feb 04 02:35:08 PM PST 24 Feb 04 02:35:14 PM PST 24 48891962 ps
T1103 /workspace/coverage/default/36.spi_device_intercept.2336852056 Feb 04 02:37:25 PM PST 24 Feb 04 02:37:37 PM PST 24 450556212 ps
T1104 /workspace/coverage/default/8.spi_device_tpm_all.2764867107 Feb 04 02:35:00 PM PST 24 Feb 04 02:35:42 PM PST 24 2856000313 ps
T1105 /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3783489393 Feb 04 02:37:09 PM PST 24 Feb 04 02:37:13 PM PST 24 202304981 ps
T1106 /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3546644887 Feb 04 02:36:50 PM PST 24 Feb 04 02:39:32 PM PST 24 65596024788 ps
T1107 /workspace/coverage/default/12.spi_device_read_buffer_direct.944386990 Feb 04 02:35:28 PM PST 24 Feb 04 02:35:40 PM PST 24 515553062 ps
T1108 /workspace/coverage/default/19.spi_device_read_buffer_direct.1822278722 Feb 04 02:35:56 PM PST 24 Feb 04 02:36:07 PM PST 24 1135394743 ps
T1109 /workspace/coverage/default/37.spi_device_cfg_cmd.2572855343 Feb 04 02:37:27 PM PST 24 Feb 04 02:37:36 PM PST 24 1167377960 ps
T1110 /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3917091240 Feb 04 02:36:15 PM PST 24 Feb 04 02:36:25 PM PST 24 520172600 ps
T1111 /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3722509750 Feb 04 02:35:53 PM PST 24 Feb 04 02:36:03 PM PST 24 4476424191 ps
T1112 /workspace/coverage/default/9.spi_device_pass_cmd_filtering.314049238 Feb 04 02:35:07 PM PST 24 Feb 04 02:35:19 PM PST 24 7503544863 ps
T1113 /workspace/coverage/default/18.spi_device_pass_cmd_filtering.830017319 Feb 04 02:35:47 PM PST 24 Feb 04 02:36:16 PM PST 24 7866406898 ps
T1114 /workspace/coverage/default/25.spi_device_tpm_rw.2724625624 Feb 04 02:36:27 PM PST 24 Feb 04 02:36:30 PM PST 24 76809398 ps
T1115 /workspace/coverage/default/15.spi_device_read_buffer_direct.3017931444 Feb 04 02:35:38 PM PST 24 Feb 04 02:35:57 PM PST 24 4955244233 ps
T1116 /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2459934161 Feb 04 02:35:04 PM PST 24 Feb 04 02:35:29 PM PST 24 12765376803 ps

Test location /workspace/coverage/default/42.spi_device_stress_all.3498445404
Short name T7
Test name
Test status
Simulation time 258776221714 ps
CPU time 523.97 seconds
Started Feb 04 02:37:48 PM PST 24
Finished Feb 04 02:46:34 PM PST 24
Peak memory 269472 kb
Host smart-f5708a6d-8212-4d9a-9e4b-625720b45e98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498445404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3498445404
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1514486428
Short name T11
Test name
Test status
Simulation time 17659129785 ps
CPU time 46.51 seconds
Started Feb 04 02:38:05 PM PST 24
Finished Feb 04 02:38:54 PM PST 24
Peak memory 256924 kb
Host smart-3e57408e-e444-4d10-90c3-8531fc7d5b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514486428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1514486428
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1841527583
Short name T12
Test name
Test status
Simulation time 316053865745 ps
CPU time 2287.98 seconds
Started Feb 04 02:38:08 PM PST 24
Finished Feb 04 03:16:17 PM PST 24
Peak memory 300324 kb
Host smart-1916e8c0-0444-472c-9de3-50dea71ee9d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841527583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1841527583
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1560199100
Short name T73
Test name
Test status
Simulation time 328391242 ps
CPU time 7.13 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:50 PM PST 24
Peak memory 215016 kb
Host smart-bc574036-3550-40ec-bca7-4cacefa3cc4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560199100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1560199100
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.691760485
Short name T50
Test name
Test status
Simulation time 12642858400 ps
CPU time 146.86 seconds
Started Feb 04 02:35:35 PM PST 24
Finished Feb 04 02:38:10 PM PST 24
Peak memory 256476 kb
Host smart-f58f8b4d-0542-4d01-a499-1da5dcb000d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691760485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.691760485
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1126568339
Short name T65
Test name
Test status
Simulation time 87277265097 ps
CPU time 545.52 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:45:55 PM PST 24
Peak memory 286164 kb
Host smart-656283d6-d2ad-430a-bc88-60f8cd642999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126568339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1126568339
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.3296465318
Short name T53
Test name
Test status
Simulation time 20509303 ps
CPU time 0.71 seconds
Started Feb 04 02:35:06 PM PST 24
Finished Feb 04 02:35:12 PM PST 24
Peak memory 216220 kb
Host smart-d2a124c2-eadd-47fc-b72d-fe4e042c5aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296465318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.3296465318
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1928448116
Short name T80
Test name
Test status
Simulation time 158778198 ps
CPU time 4.79 seconds
Started Feb 04 12:41:16 PM PST 24
Finished Feb 04 12:41:25 PM PST 24
Peak memory 215220 kb
Host smart-411ce08b-8b79-4672-9328-3fff9e8531a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928448116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
928448116
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.539947103
Short name T28
Test name
Test status
Simulation time 555930813203 ps
CPU time 816 seconds
Started Feb 04 02:38:17 PM PST 24
Finished Feb 04 02:51:55 PM PST 24
Peak memory 283820 kb
Host smart-1d9539c5-d380-42c3-bbbe-f8aa22ef1d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539947103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.539947103
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.918947484
Short name T4
Test name
Test status
Simulation time 19829970281 ps
CPU time 30.52 seconds
Started Feb 04 02:37:15 PM PST 24
Finished Feb 04 02:37:48 PM PST 24
Peak memory 246360 kb
Host smart-d7b96a74-2e47-46c4-a130-1f8b970c9b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918947484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.918947484
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3570523386
Short name T64
Test name
Test status
Simulation time 100614037710 ps
CPU time 489.6 seconds
Started Feb 04 02:34:08 PM PST 24
Finished Feb 04 02:42:26 PM PST 24
Peak memory 268488 kb
Host smart-b621163c-f27e-467d-a6fc-63e019b4cbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570523386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3570523386
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4129674274
Short name T97
Test name
Test status
Simulation time 3354932848 ps
CPU time 8.84 seconds
Started Feb 04 12:41:20 PM PST 24
Finished Feb 04 12:41:36 PM PST 24
Peak memory 207112 kb
Host smart-65a6fd1d-e31d-48ae-b36e-05e981c5e8f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129674274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4129674274
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2944826858
Short name T162
Test name
Test status
Simulation time 202063290718 ps
CPU time 532.59 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:43:16 PM PST 24
Peak memory 273856 kb
Host smart-a494659d-e142-40b0-8af7-5fc7d032ce55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944826858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2944826858
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2825290541
Short name T47
Test name
Test status
Simulation time 71916377 ps
CPU time 0.95 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:34:17 PM PST 24
Peak memory 235372 kb
Host smart-d016b143-2ffa-4e3b-b879-274e0c091270
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825290541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2825290541
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2197976939
Short name T248
Test name
Test status
Simulation time 14060748893 ps
CPU time 194.14 seconds
Started Feb 04 02:36:39 PM PST 24
Finished Feb 04 02:39:57 PM PST 24
Peak memory 286936 kb
Host smart-b7078a64-71bb-4e13-9518-d0dac9e1952f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197976939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2197976939
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3641589047
Short name T79
Test name
Test status
Simulation time 15505342300 ps
CPU time 19.77 seconds
Started Feb 04 12:41:18 PM PST 24
Finished Feb 04 12:41:44 PM PST 24
Peak memory 215156 kb
Host smart-4083b047-3c3d-4b1d-8c97-86b677e2bc54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641589047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3641589047
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1714509688
Short name T34
Test name
Test status
Simulation time 83118733326 ps
CPU time 556.29 seconds
Started Feb 04 02:36:12 PM PST 24
Finished Feb 04 02:45:36 PM PST 24
Peak memory 270312 kb
Host smart-628d0087-e8e1-4171-8664-7aaa1663245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714509688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1714509688
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3820885850
Short name T160
Test name
Test status
Simulation time 284419675748 ps
CPU time 320.91 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:42:16 PM PST 24
Peak memory 257440 kb
Host smart-1549415e-d51f-47ff-870e-70892894536e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820885850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3820885850
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3737789995
Short name T183
Test name
Test status
Simulation time 166002264335 ps
CPU time 677.38 seconds
Started Feb 04 02:34:48 PM PST 24
Finished Feb 04 02:46:12 PM PST 24
Peak memory 282144 kb
Host smart-bc0ff0b8-6327-4288-87c0-943b8df21a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737789995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3737789995
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2316495389
Short name T267
Test name
Test status
Simulation time 120578807207 ps
CPU time 478.49 seconds
Started Feb 04 02:36:11 PM PST 24
Finished Feb 04 02:44:11 PM PST 24
Peak memory 264036 kb
Host smart-db64076b-21c7-4641-9062-9ae6c67ccc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316495389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2316495389
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1017594437
Short name T114
Test name
Test status
Simulation time 11202277367 ps
CPU time 71.78 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:37:03 PM PST 24
Peak memory 252716 kb
Host smart-416a9858-1204-46c4-96cd-11dcea2e9362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017594437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1017594437
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3107481335
Short name T88
Test name
Test status
Simulation time 896228134 ps
CPU time 6.12 seconds
Started Feb 04 12:41:31 PM PST 24
Finished Feb 04 12:41:44 PM PST 24
Peak memory 219340 kb
Host smart-792e1ab3-0b0c-43f2-9718-f2ee94ad2b93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107481335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
107481335
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3099978252
Short name T270
Test name
Test status
Simulation time 163347203790 ps
CPU time 388.49 seconds
Started Feb 04 02:33:40 PM PST 24
Finished Feb 04 02:40:11 PM PST 24
Peak memory 271616 kb
Host smart-d4a37262-dfac-451e-ab7e-ecad3dfe7f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099978252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3099978252
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.673002758
Short name T298
Test name
Test status
Simulation time 107154456 ps
CPU time 0.99 seconds
Started Feb 04 02:33:38 PM PST 24
Finished Feb 04 02:33:42 PM PST 24
Peak memory 217900 kb
Host smart-76bd476f-bec6-4b39-97dc-527fead0455f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673002758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.673002758
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2767324753
Short name T254
Test name
Test status
Simulation time 42633951235 ps
CPU time 94.12 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:38:30 PM PST 24
Peak memory 252200 kb
Host smart-abfd204f-0c8e-4e77-b396-7eb8dc752dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767324753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2767324753
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2722005760
Short name T632
Test name
Test status
Simulation time 2894823278 ps
CPU time 24.95 seconds
Started Feb 04 02:37:36 PM PST 24
Finished Feb 04 02:38:05 PM PST 24
Peak memory 233624 kb
Host smart-516940f1-1087-4f48-9b4c-76f9fb9ff220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722005760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2722005760
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.91548898
Short name T95
Test name
Test status
Simulation time 1315635159 ps
CPU time 13.38 seconds
Started Feb 04 12:41:23 PM PST 24
Finished Feb 04 12:41:42 PM PST 24
Peak memory 215100 kb
Host smart-dd0abf15-724d-462c-9728-9596439abaa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91548898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_t
l_intg_err.91548898
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.960638581
Short name T252
Test name
Test status
Simulation time 6386494494 ps
CPU time 32.83 seconds
Started Feb 04 02:35:36 PM PST 24
Finished Feb 04 02:36:20 PM PST 24
Peak memory 249244 kb
Host smart-8490eeae-8d43-4dc0-b387-55b5ffa9dfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960638581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.960638581
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.453059144
Short name T827
Test name
Test status
Simulation time 23322116116 ps
CPU time 284.52 seconds
Started Feb 04 02:35:25 PM PST 24
Finished Feb 04 02:40:19 PM PST 24
Peak memory 285224 kb
Host smart-6dc7ba94-7ef1-44db-b01e-d889670f076a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453059144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.453059144
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2931604921
Short name T192
Test name
Test status
Simulation time 8776033405 ps
CPU time 84.75 seconds
Started Feb 04 02:35:43 PM PST 24
Finished Feb 04 02:37:20 PM PST 24
Peak memory 264676 kb
Host smart-ca1a4a32-aab5-4cef-876f-f00d71cf84c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931604921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2931604921
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2121749440
Short name T668
Test name
Test status
Simulation time 35909413905 ps
CPU time 49.28 seconds
Started Feb 04 02:34:17 PM PST 24
Finished Feb 04 02:35:12 PM PST 24
Peak memory 238792 kb
Host smart-9c8f8a22-6d68-4d60-9a39-053d3c7eb39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121749440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2121749440
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.678400479
Short name T69
Test name
Test status
Simulation time 49934501503 ps
CPU time 135.13 seconds
Started Feb 04 02:34:17 PM PST 24
Finished Feb 04 02:36:38 PM PST 24
Peak memory 266928 kb
Host smart-b40d59c2-2872-426d-a2bb-dd196f1b578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678400479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.678400479
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4101367722
Short name T42
Test name
Test status
Simulation time 37341171007 ps
CPU time 27.93 seconds
Started Feb 04 02:36:46 PM PST 24
Finished Feb 04 02:37:23 PM PST 24
Peak memory 237016 kb
Host smart-0d388efd-e6c3-460c-90f6-0146e9a8ff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101367722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4101367722
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1980423251
Short name T351
Test name
Test status
Simulation time 56316393 ps
CPU time 2.43 seconds
Started Feb 04 12:41:19 PM PST 24
Finished Feb 04 12:41:27 PM PST 24
Peak memory 216108 kb
Host smart-fcd1a263-d91d-4d09-bff0-256dc85ae863
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980423251 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1980423251
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3388306038
Short name T361
Test name
Test status
Simulation time 1519322739 ps
CPU time 8.32 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:51 PM PST 24
Peak memory 214948 kb
Host smart-84f00232-e28a-4636-af7d-a63ac27dc540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388306038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3388306038
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2709865919
Short name T318
Test name
Test status
Simulation time 38993255 ps
CPU time 0.77 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 202552 kb
Host smart-f86ab9ce-7604-4de6-a0a4-bd6687cd253b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709865919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2709865919
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2002739063
Short name T264
Test name
Test status
Simulation time 204619756229 ps
CPU time 450.2 seconds
Started Feb 04 02:34:06 PM PST 24
Finished Feb 04 02:41:46 PM PST 24
Peak memory 265316 kb
Host smart-87d50c42-6531-40b2-a58f-fbfc7922209e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002739063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2002739063
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2466021443
Short name T269
Test name
Test status
Simulation time 18636162820 ps
CPU time 232.37 seconds
Started Feb 04 02:35:45 PM PST 24
Finished Feb 04 02:39:49 PM PST 24
Peak memory 271816 kb
Host smart-2f441f69-edc5-42c0-9114-359f9a7a7cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466021443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2466021443
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2262165703
Short name T823
Test name
Test status
Simulation time 295114206578 ps
CPU time 435.27 seconds
Started Feb 04 02:35:56 PM PST 24
Finished Feb 04 02:43:16 PM PST 24
Peak memory 255804 kb
Host smart-890e8798-6934-4e22-9237-8a95eef489e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262165703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2262165703
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1882714501
Short name T257
Test name
Test status
Simulation time 122636367490 ps
CPU time 553.18 seconds
Started Feb 04 02:37:01 PM PST 24
Finished Feb 04 02:46:15 PM PST 24
Peak memory 266848 kb
Host smart-1dc1635a-c59f-4891-abc1-d9723ac64784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882714501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1882714501
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.368795724
Short name T312
Test name
Test status
Simulation time 13508878 ps
CPU time 0.72 seconds
Started Feb 04 02:35:44 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 204384 kb
Host smart-40795a93-6250-4270-85e7-e2368ccd7e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368795724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.368795724
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4213073843
Short name T67
Test name
Test status
Simulation time 61230222 ps
CPU time 1.22 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:20 PM PST 24
Peak memory 206824 kb
Host smart-90d859c0-da00-488f-b779-d3a5a77063a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213073843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4213073843
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.752550147
Short name T74
Test name
Test status
Simulation time 203660610 ps
CPU time 2.69 seconds
Started Feb 04 12:41:29 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 215320 kb
Host smart-fc0093f4-0371-4945-a892-80d0890447a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752550147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.752550147
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.56481039
Short name T385
Test name
Test status
Simulation time 3665209137 ps
CPU time 17.39 seconds
Started Feb 04 12:41:12 PM PST 24
Finished Feb 04 12:41:31 PM PST 24
Peak memory 206968 kb
Host smart-de545303-4433-471f-872e-a7b305956990
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56481039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
aliasing.56481039
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2564635726
Short name T376
Test name
Test status
Simulation time 2493941132 ps
CPU time 36.23 seconds
Started Feb 04 12:41:19 PM PST 24
Finished Feb 04 12:42:01 PM PST 24
Peak memory 206644 kb
Host smart-ae7020c1-f394-4c13-9b39-97ba576ff55d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564635726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2564635726
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.274706025
Short name T409
Test name
Test status
Simulation time 26289421 ps
CPU time 1.96 seconds
Started Feb 04 12:41:18 PM PST 24
Finished Feb 04 12:41:26 PM PST 24
Peak memory 215108 kb
Host smart-a83d78cd-3a99-4cca-bf87-6043b093c27f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274706025 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.274706025
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1948316473
Short name T92
Test name
Test status
Simulation time 99329042 ps
CPU time 1.91 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:21 PM PST 24
Peak memory 215012 kb
Host smart-4361135e-8077-4147-b514-1aec302612c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948316473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
948316473
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.581167907
Short name T413
Test name
Test status
Simulation time 23821110 ps
CPU time 0.73 seconds
Started Feb 04 12:41:15 PM PST 24
Finished Feb 04 12:41:21 PM PST 24
Peak memory 202772 kb
Host smart-8dea4996-8356-4aa8-9614-9989d7e2506e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581167907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.581167907
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2421606329
Short name T106
Test name
Test status
Simulation time 220426172 ps
CPU time 2.19 seconds
Started Feb 04 12:41:13 PM PST 24
Finished Feb 04 12:41:17 PM PST 24
Peak memory 215016 kb
Host smart-48caa62a-63a9-4c43-9271-543b0e07b3cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421606329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2421606329
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4101717487
Short name T335
Test name
Test status
Simulation time 37085740 ps
CPU time 0.68 seconds
Started Feb 04 12:41:18 PM PST 24
Finished Feb 04 12:41:25 PM PST 24
Peak memory 202784 kb
Host smart-1fd7ccf8-93bc-4950-b0a5-1d6189a3be75
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101717487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4101717487
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2497041465
Short name T407
Test name
Test status
Simulation time 625562460 ps
CPU time 4.36 seconds
Started Feb 04 12:41:17 PM PST 24
Finished Feb 04 12:41:28 PM PST 24
Peak memory 215016 kb
Host smart-79fed8e4-0e12-4947-aefa-f6b0a45634e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497041465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2497041465
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1167453187
Short name T82
Test name
Test status
Simulation time 3170849332 ps
CPU time 4.96 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:22 PM PST 24
Peak memory 216276 kb
Host smart-b0843e0c-4e3f-40f6-a464-9b82aec97359
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167453187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
167453187
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2515289526
Short name T153
Test name
Test status
Simulation time 105657721 ps
CPU time 6.58 seconds
Started Feb 04 12:41:23 PM PST 24
Finished Feb 04 12:41:36 PM PST 24
Peak memory 215008 kb
Host smart-337cffb8-2262-484a-b313-02780fd5ad43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515289526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2515289526
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2943804671
Short name T99
Test name
Test status
Simulation time 664582491 ps
CPU time 8.78 seconds
Started Feb 04 12:41:20 PM PST 24
Finished Feb 04 12:41:36 PM PST 24
Peak memory 215048 kb
Host smart-fb20bc0a-fcbb-4b5f-a7ea-8954721162cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943804671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2943804671
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2665125843
Short name T397
Test name
Test status
Simulation time 1936454073 ps
CPU time 34.24 seconds
Started Feb 04 12:41:24 PM PST 24
Finished Feb 04 12:42:03 PM PST 24
Peak memory 206824 kb
Host smart-76eaaef4-0b7c-493f-a044-24996bc175f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665125843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2665125843
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3292258385
Short name T109
Test name
Test status
Simulation time 35415753 ps
CPU time 1.17 seconds
Started Feb 04 12:41:19 PM PST 24
Finished Feb 04 12:41:26 PM PST 24
Peak memory 214992 kb
Host smart-de353116-4613-44cc-9322-5ab32c0fa781
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292258385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3292258385
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2162662606
Short name T398
Test name
Test status
Simulation time 61248634 ps
CPU time 1.25 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:19 PM PST 24
Peak memory 206872 kb
Host smart-128ebe5e-6429-4aa6-ac2b-a243d6a765da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162662606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
162662606
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.311990517
Short name T317
Test name
Test status
Simulation time 13289790 ps
CPU time 0.76 seconds
Started Feb 04 12:41:19 PM PST 24
Finished Feb 04 12:41:26 PM PST 24
Peak memory 202772 kb
Host smart-5355e2c2-952b-4374-990c-6ecdfc3e1836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311990517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.311990517
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.433774367
Short name T404
Test name
Test status
Simulation time 171373757 ps
CPU time 1.7 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:19 PM PST 24
Peak memory 214988 kb
Host smart-ad6e5a3d-5106-42e7-a1c8-8205c8b70f4c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433774367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.433774367
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1467961232
Short name T402
Test name
Test status
Simulation time 69861075 ps
CPU time 0.66 seconds
Started Feb 04 12:41:15 PM PST 24
Finished Feb 04 12:41:20 PM PST 24
Peak memory 203008 kb
Host smart-7705437c-ff26-4da3-ad7a-2640e3a272c7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467961232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1467961232
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2278583429
Short name T378
Test name
Test status
Simulation time 265664752 ps
CPU time 1.77 seconds
Started Feb 04 12:41:23 PM PST 24
Finished Feb 04 12:41:31 PM PST 24
Peak memory 206816 kb
Host smart-862f94e8-fb47-4d6d-a365-1e2387223390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278583429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2278583429
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1123236553
Short name T89
Test name
Test status
Simulation time 368559736 ps
CPU time 4.59 seconds
Started Feb 04 12:41:19 PM PST 24
Finished Feb 04 12:41:30 PM PST 24
Peak memory 215200 kb
Host smart-43cbcb9f-9a9d-470e-8e61-7c1533687526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123236553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
123236553
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.166646999
Short name T416
Test name
Test status
Simulation time 126638544 ps
CPU time 2.29 seconds
Started Feb 04 12:41:33 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 216432 kb
Host smart-c45b063b-08a4-4653-8a80-e6379bf60a17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166646999 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.166646999
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2198604939
Short name T110
Test name
Test status
Simulation time 30688715 ps
CPU time 1.87 seconds
Started Feb 04 12:41:32 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 214980 kb
Host smart-7a1834e0-2560-4987-8e70-8836d95c585e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198604939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2198604939
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3302408122
Short name T343
Test name
Test status
Simulation time 51850188 ps
CPU time 0.71 seconds
Started Feb 04 12:41:33 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 202784 kb
Host smart-65e4fa1d-d6c7-495d-ae8b-6a9117d3842d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302408122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3302408122
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2764171453
Short name T322
Test name
Test status
Simulation time 159699975 ps
CPU time 2.97 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 214904 kb
Host smart-d8c4d97d-21e2-4ef7-9103-fd63dcfc60ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764171453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2764171453
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1393518912
Short name T126
Test name
Test status
Simulation time 588164400 ps
CPU time 2.53 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 216412 kb
Host smart-f5054a84-b02a-4b08-8906-9731248eb7d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393518912 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1393518912
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3600279290
Short name T111
Test name
Test status
Simulation time 92948923 ps
CPU time 1.36 seconds
Started Feb 04 12:41:31 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 206796 kb
Host smart-80b8c820-3638-4c59-81ae-49c6ac32efc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600279290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3600279290
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4184126355
Short name T326
Test name
Test status
Simulation time 119284113 ps
CPU time 2.91 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:42 PM PST 24
Peak memory 214660 kb
Host smart-c7f1e431-34f1-4e81-ad6e-f1b22c00e616
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184126355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4184126355
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3873833937
Short name T84
Test name
Test status
Simulation time 45040629 ps
CPU time 3.2 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:41:49 PM PST 24
Peak memory 215052 kb
Host smart-57a14e5d-e887-4d7f-8045-03e8216e9c06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873833937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3873833937
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.551808941
Short name T78
Test name
Test status
Simulation time 743035774 ps
CPU time 12.09 seconds
Started Feb 04 12:41:31 PM PST 24
Finished Feb 04 12:41:50 PM PST 24
Peak memory 215100 kb
Host smart-682d00da-ed38-442b-bf94-8a67061814b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551808941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.551808941
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3840983267
Short name T340
Test name
Test status
Simulation time 69827254 ps
CPU time 2.14 seconds
Started Feb 04 12:41:32 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 215204 kb
Host smart-6d6730bb-30d0-4a41-a459-bbc0a9eb422d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840983267 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3840983267
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3616156930
Short name T98
Test name
Test status
Simulation time 42857218 ps
CPU time 2.51 seconds
Started Feb 04 12:41:37 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 214892 kb
Host smart-2e753dbf-738f-47ff-9d93-a1ee90cdb906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616156930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3616156930
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.114176672
Short name T337
Test name
Test status
Simulation time 41533682 ps
CPU time 0.7 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 202744 kb
Host smart-50a3788a-0c2a-420a-96cb-918832411241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114176672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.114176672
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.962847958
Short name T389
Test name
Test status
Simulation time 452760576 ps
CPU time 2.9 seconds
Started Feb 04 12:41:32 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 206872 kb
Host smart-c09be9b6-5d6c-4c9b-8eff-127d7dcc5bd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962847958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.962847958
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1094678573
Short name T150
Test name
Test status
Simulation time 176498776 ps
CPU time 4.18 seconds
Started Feb 04 12:41:33 PM PST 24
Finished Feb 04 12:41:43 PM PST 24
Peak memory 215164 kb
Host smart-f7293d26-f560-445d-8322-cd0f43890297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094678573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1094678573
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3474149545
Short name T364
Test name
Test status
Simulation time 576480458 ps
CPU time 18.48 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:42:03 PM PST 24
Peak memory 214788 kb
Host smart-bebbff5a-a4ed-4a66-837d-fec208f440fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474149545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3474149545
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2541821074
Short name T142
Test name
Test status
Simulation time 39087932 ps
CPU time 1.8 seconds
Started Feb 04 12:41:37 PM PST 24
Finished Feb 04 12:41:45 PM PST 24
Peak memory 216156 kb
Host smart-d7f3ee88-0a01-4d95-a588-4a7bccad00cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541821074 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2541821074
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3077674904
Short name T108
Test name
Test status
Simulation time 182360627 ps
CPU time 2.37 seconds
Started Feb 04 12:41:37 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 206716 kb
Host smart-6d7506df-d7b8-4fad-a443-81ad655be78d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077674904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3077674904
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2019005311
Short name T332
Test name
Test status
Simulation time 11270315 ps
CPU time 0.74 seconds
Started Feb 04 12:41:31 PM PST 24
Finished Feb 04 12:41:39 PM PST 24
Peak memory 203080 kb
Host smart-380635b5-78a5-4890-87be-4809b6ae51a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019005311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2019005311
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2334225856
Short name T406
Test name
Test status
Simulation time 420102428 ps
CPU time 2.82 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 206784 kb
Host smart-6c0b95ef-963d-4ace-9e61-a8f6c117f01b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334225856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2334225856
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3727667463
Short name T421
Test name
Test status
Simulation time 816285897 ps
CPU time 5.43 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:45 PM PST 24
Peak memory 215064 kb
Host smart-895dc55f-8a60-48f0-ab23-79eb13dfbacb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727667463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3727667463
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1159146407
Short name T154
Test name
Test status
Simulation time 738011282 ps
CPU time 15.4 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:55 PM PST 24
Peak memory 215080 kb
Host smart-5f3b6741-fea9-4cf4-adfd-2b7de6f2c1a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159146407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1159146407
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2181685682
Short name T76
Test name
Test status
Simulation time 177785303 ps
CPU time 1.29 seconds
Started Feb 04 12:41:33 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 215204 kb
Host smart-016417a6-3255-4277-b5ad-c7b5ccc0058d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181685682 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2181685682
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3027537694
Short name T375
Test name
Test status
Simulation time 35332933 ps
CPU time 2.22 seconds
Started Feb 04 12:41:37 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 219204 kb
Host smart-8c55fbf0-90c3-4008-b059-00aeb1e3dda4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027537694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3027537694
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1321933446
Short name T356
Test name
Test status
Simulation time 40749674 ps
CPU time 0.67 seconds
Started Feb 04 12:41:28 PM PST 24
Finished Feb 04 12:41:37 PM PST 24
Peak memory 202812 kb
Host smart-09d77213-2129-453f-a00a-e8162976620c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321933446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1321933446
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2669830440
Short name T394
Test name
Test status
Simulation time 433103433 ps
CPU time 3.02 seconds
Started Feb 04 12:41:33 PM PST 24
Finished Feb 04 12:41:42 PM PST 24
Peak memory 206600 kb
Host smart-12998932-9f9a-4e41-976c-81c6c0515d11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669830440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2669830440
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.626109237
Short name T354
Test name
Test status
Simulation time 72683720 ps
CPU time 2.38 seconds
Started Feb 04 12:41:37 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 215136 kb
Host smart-34fe316f-ac46-435a-bd41-b918fa0a4276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626109237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.626109237
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.870318337
Short name T358
Test name
Test status
Simulation time 2848711150 ps
CPU time 7.62 seconds
Started Feb 04 12:41:38 PM PST 24
Finished Feb 04 12:41:52 PM PST 24
Peak memory 215060 kb
Host smart-6bc692f5-ecc6-4f7b-a0e8-9b88eec0aaea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870318337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.870318337
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.876491594
Short name T350
Test name
Test status
Simulation time 24762938 ps
CPU time 1.81 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:41:47 PM PST 24
Peak memory 216068 kb
Host smart-5d1da56f-7b90-40c6-8c60-ca7be4d358b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876491594 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.876491594
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3856365360
Short name T344
Test name
Test status
Simulation time 19380074 ps
CPU time 1.26 seconds
Started Feb 04 12:41:40 PM PST 24
Finished Feb 04 12:41:47 PM PST 24
Peak memory 206776 kb
Host smart-37f111e6-9270-44f3-af75-d7620c4feaf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856365360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3856365360
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1094778342
Short name T334
Test name
Test status
Simulation time 10272626 ps
CPU time 0.69 seconds
Started Feb 04 12:41:42 PM PST 24
Finished Feb 04 12:41:49 PM PST 24
Peak memory 202900 kb
Host smart-06c4ffaa-c0b3-403f-94a3-cb12f3254282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094778342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1094778342
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.519107827
Short name T345
Test name
Test status
Simulation time 612950113 ps
CPU time 4.14 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 206752 kb
Host smart-704020d3-653e-4bb0-bebd-3a73bacb3678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519107827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.519107827
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.828222300
Short name T85
Test name
Test status
Simulation time 49856392 ps
CPU time 1.84 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 215264 kb
Host smart-c4f302ee-1c75-475b-bada-283861eddf77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828222300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.828222300
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.543406207
Short name T155
Test name
Test status
Simulation time 1692882030 ps
CPU time 21.57 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:42:06 PM PST 24
Peak memory 215024 kb
Host smart-9e03b071-06ca-4289-af7a-fa34b627dc87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543406207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.543406207
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2658176475
Short name T414
Test name
Test status
Simulation time 184503832 ps
CPU time 1.84 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:45 PM PST 24
Peak memory 215108 kb
Host smart-60c8a389-8128-4f75-815b-9dd845b6a76c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658176475 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2658176475
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4217985018
Short name T411
Test name
Test status
Simulation time 77558456 ps
CPU time 1.25 seconds
Started Feb 04 12:41:38 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 206800 kb
Host smart-5c30f360-7313-4d8f-94f5-cd6fc8e74d15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217985018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4217985018
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.436728297
Short name T313
Test name
Test status
Simulation time 11380837 ps
CPU time 0.68 seconds
Started Feb 04 12:41:43 PM PST 24
Finished Feb 04 12:41:50 PM PST 24
Peak memory 202772 kb
Host smart-3dde2b8c-050c-4a66-9670-8bc869004ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436728297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.436728297
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3729006056
Short name T347
Test name
Test status
Simulation time 97606473 ps
CPU time 1.73 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 206792 kb
Host smart-9c84be09-a226-4018-ac22-2027b5069f0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729006056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3729006056
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3047477853
Short name T405
Test name
Test status
Simulation time 181392645 ps
CPU time 2.54 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:44 PM PST 24
Peak memory 215204 kb
Host smart-5f87ee3e-df1a-4459-9af4-7889e394119a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047477853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3047477853
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1436406005
Short name T388
Test name
Test status
Simulation time 42724550 ps
CPU time 2.19 seconds
Started Feb 04 12:41:40 PM PST 24
Finished Feb 04 12:41:48 PM PST 24
Peak memory 215628 kb
Host smart-69d891fc-98d0-4ac1-a2dd-597e3e2541c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436406005 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1436406005
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2064031339
Short name T101
Test name
Test status
Simulation time 36360732 ps
CPU time 1.25 seconds
Started Feb 04 12:41:43 PM PST 24
Finished Feb 04 12:41:50 PM PST 24
Peak memory 206748 kb
Host smart-9fcb771c-88f1-4d40-a14e-efcc0a6056ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064031339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2064031339
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3559124508
Short name T133
Test name
Test status
Simulation time 60144194 ps
CPU time 0.72 seconds
Started Feb 04 12:41:43 PM PST 24
Finished Feb 04 12:41:50 PM PST 24
Peak memory 202764 kb
Host smart-7588e547-3fd8-4804-9b68-71387c39807e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559124508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3559124508
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.377846445
Short name T403
Test name
Test status
Simulation time 167861662 ps
CPU time 2.78 seconds
Started Feb 04 12:41:38 PM PST 24
Finished Feb 04 12:41:47 PM PST 24
Peak memory 215156 kb
Host smart-d33fba79-3994-41ae-81ab-a8d81023c3b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377846445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.377846445
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4121550513
Short name T83
Test name
Test status
Simulation time 83259046 ps
CPU time 3.28 seconds
Started Feb 04 12:41:38 PM PST 24
Finished Feb 04 12:41:48 PM PST 24
Peak memory 215340 kb
Host smart-673a4ea9-3416-43ee-b64b-c3d108e30716
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121550513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4121550513
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.955075825
Short name T152
Test name
Test status
Simulation time 1146948457 ps
CPU time 18.26 seconds
Started Feb 04 12:41:42 PM PST 24
Finished Feb 04 12:42:06 PM PST 24
Peak memory 215252 kb
Host smart-33db9b15-ea6f-46d9-9177-4d68a281de6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955075825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.955075825
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2037824124
Short name T383
Test name
Test status
Simulation time 25087825 ps
CPU time 1.48 seconds
Started Feb 04 12:41:37 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 215148 kb
Host smart-9dfddb24-0837-40f1-9529-556d9b2dd1d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037824124 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2037824124
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1668289293
Short name T400
Test name
Test status
Simulation time 47104298 ps
CPU time 1.39 seconds
Started Feb 04 12:41:33 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 206780 kb
Host smart-2d2cb84d-01fc-4993-9733-3ca1990c5dbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668289293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1668289293
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.132184770
Short name T418
Test name
Test status
Simulation time 11942082 ps
CPU time 0.68 seconds
Started Feb 04 12:41:44 PM PST 24
Finished Feb 04 12:41:51 PM PST 24
Peak memory 202748 kb
Host smart-483a3482-1247-4141-a8e9-92d30c5aeeed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132184770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.132184770
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2723311733
Short name T401
Test name
Test status
Simulation time 2724025709 ps
CPU time 3.06 seconds
Started Feb 04 12:41:32 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 215120 kb
Host smart-4069a818-8f56-47e8-8678-d83193d5b9a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723311733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2723311733
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1524868491
Short name T349
Test name
Test status
Simulation time 148601274 ps
CPU time 2.56 seconds
Started Feb 04 12:41:42 PM PST 24
Finished Feb 04 12:41:51 PM PST 24
Peak memory 215260 kb
Host smart-3b9337b7-9145-4e5f-a6a7-05ff0bdeacde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524868491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1524868491
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4046462009
Short name T156
Test name
Test status
Simulation time 556742500 ps
CPU time 14.82 seconds
Started Feb 04 12:41:42 PM PST 24
Finished Feb 04 12:42:03 PM PST 24
Peak memory 215136 kb
Host smart-9433eb20-39bb-49ba-b945-3eec89308452
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046462009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4046462009
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1954909695
Short name T75
Test name
Test status
Simulation time 25413041 ps
CPU time 1.23 seconds
Started Feb 04 12:41:45 PM PST 24
Finished Feb 04 12:41:51 PM PST 24
Peak memory 215060 kb
Host smart-aefa71f5-0ea9-43a9-ad76-ecadb635aaa8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954909695 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1954909695
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3530652583
Short name T379
Test name
Test status
Simulation time 146460592 ps
CPU time 1.34 seconds
Started Feb 04 12:41:43 PM PST 24
Finished Feb 04 12:41:50 PM PST 24
Peak memory 215048 kb
Host smart-ba8acb5d-8190-4442-8dba-91c34d1ba76f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530652583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3530652583
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3655533918
Short name T396
Test name
Test status
Simulation time 30103320 ps
CPU time 0.74 seconds
Started Feb 04 12:41:40 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 202748 kb
Host smart-021a0139-ec58-4fb5-9f6e-28a5ca0ed3c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655533918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3655533918
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1673074532
Short name T355
Test name
Test status
Simulation time 153880347 ps
CPU time 3.14 seconds
Started Feb 04 12:41:29 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 214920 kb
Host smart-27fe529a-4804-43aa-897f-0570ce8590fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673074532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1673074532
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.991216486
Short name T338
Test name
Test status
Simulation time 799309865 ps
CPU time 2.93 seconds
Started Feb 04 12:41:45 PM PST 24
Finished Feb 04 12:41:53 PM PST 24
Peak memory 215132 kb
Host smart-7e40c718-775e-4235-8c64-33fa6cf848ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991216486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.991216486
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3143939139
Short name T128
Test name
Test status
Simulation time 1072240515 ps
CPU time 21.92 seconds
Started Feb 04 12:41:44 PM PST 24
Finished Feb 04 12:42:11 PM PST 24
Peak memory 215012 kb
Host smart-043c2685-25cf-4526-87a7-1c2de1eeb0cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143939139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3143939139
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4150017507
Short name T105
Test name
Test status
Simulation time 1242867136 ps
CPU time 20.88 seconds
Started Feb 04 12:41:16 PM PST 24
Finished Feb 04 12:41:42 PM PST 24
Peak memory 214928 kb
Host smart-a251597e-99c5-4b23-a535-4786f8041055
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150017507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4150017507
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.364801505
Short name T353
Test name
Test status
Simulation time 20648113058 ps
CPU time 37.06 seconds
Started Feb 04 12:41:15 PM PST 24
Finished Feb 04 12:41:57 PM PST 24
Peak memory 206812 kb
Host smart-7787b860-ee48-4a36-bd5c-f1a033cb3903
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364801505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.364801505
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2769178611
Short name T339
Test name
Test status
Simulation time 26082915 ps
CPU time 0.97 seconds
Started Feb 04 12:41:16 PM PST 24
Finished Feb 04 12:41:22 PM PST 24
Peak memory 206308 kb
Host smart-55c11c38-fd83-44d7-b3af-4558f006af4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769178611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2769178611
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.268696326
Short name T372
Test name
Test status
Simulation time 46456824 ps
CPU time 2.61 seconds
Started Feb 04 12:41:21 PM PST 24
Finished Feb 04 12:41:30 PM PST 24
Peak memory 216348 kb
Host smart-ecf095df-d433-47ef-b973-a318b7338f7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268696326 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.268696326
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.733029903
Short name T390
Test name
Test status
Simulation time 35256380 ps
CPU time 1.27 seconds
Started Feb 04 12:41:18 PM PST 24
Finished Feb 04 12:41:26 PM PST 24
Peak memory 215000 kb
Host smart-f8851f22-9dba-4e4b-b66d-6b9c5730f963
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733029903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.733029903
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2404167534
Short name T341
Test name
Test status
Simulation time 57625882 ps
CPU time 0.74 seconds
Started Feb 04 12:41:12 PM PST 24
Finished Feb 04 12:41:14 PM PST 24
Peak memory 202752 kb
Host smart-1c652ea5-ac8a-43ae-aa77-ce20bba4841e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404167534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
404167534
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2299560219
Short name T422
Test name
Test status
Simulation time 90794685 ps
CPU time 1.45 seconds
Started Feb 04 12:41:20 PM PST 24
Finished Feb 04 12:41:27 PM PST 24
Peak memory 215072 kb
Host smart-87c6fa6f-60c6-4c1b-8f55-f7ed1d4e33a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299560219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2299560219
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.950054405
Short name T331
Test name
Test status
Simulation time 35666630 ps
CPU time 0.67 seconds
Started Feb 04 12:41:24 PM PST 24
Finished Feb 04 12:41:30 PM PST 24
Peak memory 203068 kb
Host smart-346a41aa-c1ab-49b0-988e-2dad400132ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950054405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.950054405
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3064090858
Short name T129
Test name
Test status
Simulation time 124800748 ps
CPU time 3.88 seconds
Started Feb 04 12:41:16 PM PST 24
Finished Feb 04 12:41:25 PM PST 24
Peak memory 215052 kb
Host smart-e8aae534-591a-4d90-a783-6bb132b2cf73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064090858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3064090858
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1182456895
Short name T77
Test name
Test status
Simulation time 224612093 ps
CPU time 4.19 seconds
Started Feb 04 12:41:16 PM PST 24
Finished Feb 04 12:41:26 PM PST 24
Peak memory 215324 kb
Host smart-4d1d6ce2-d2e9-4bd9-8613-743970b00d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182456895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
182456895
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.376272054
Short name T384
Test name
Test status
Simulation time 149290865 ps
CPU time 0.77 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 202760 kb
Host smart-1722d57c-6bb8-4900-9111-c567abea9aff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376272054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.376272054
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4234021735
Short name T412
Test name
Test status
Simulation time 48510084 ps
CPU time 0.74 seconds
Started Feb 04 12:41:41 PM PST 24
Finished Feb 04 12:41:47 PM PST 24
Peak memory 202652 kb
Host smart-3e54ca3d-f9bf-4f83-8578-bccf7b21ed5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234021735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4234021735
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2074890953
Short name T369
Test name
Test status
Simulation time 17684130 ps
CPU time 0.73 seconds
Started Feb 04 12:41:40 PM PST 24
Finished Feb 04 12:41:47 PM PST 24
Peak memory 202740 kb
Host smart-3ad83218-8377-4355-a25a-b5eb771ef931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074890953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2074890953
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.21207138
Short name T386
Test name
Test status
Simulation time 61050310 ps
CPU time 0.68 seconds
Started Feb 04 12:41:44 PM PST 24
Finished Feb 04 12:41:50 PM PST 24
Peak memory 203104 kb
Host smart-d96889d2-8431-4545-aac4-dbc4ebf50702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21207138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.21207138
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.784957037
Short name T143
Test name
Test status
Simulation time 15653460 ps
CPU time 0.7 seconds
Started Feb 04 12:41:46 PM PST 24
Finished Feb 04 12:41:52 PM PST 24
Peak memory 202836 kb
Host smart-7d5a8e9c-a396-4b97-8a7c-51d53d8871cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784957037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.784957037
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1091010451
Short name T324
Test name
Test status
Simulation time 62097020 ps
CPU time 0.74 seconds
Started Feb 04 12:41:43 PM PST 24
Finished Feb 04 12:41:49 PM PST 24
Peak memory 202792 kb
Host smart-9516f0df-97f1-4043-8583-15381d317fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091010451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1091010451
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3378522163
Short name T359
Test name
Test status
Simulation time 24305683 ps
CPU time 0.76 seconds
Started Feb 04 12:41:41 PM PST 24
Finished Feb 04 12:41:49 PM PST 24
Peak memory 202640 kb
Host smart-4ea96cb2-c8d7-4064-aa7c-8c7130dd6e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378522163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3378522163
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.454096563
Short name T93
Test name
Test status
Simulation time 24429548 ps
CPU time 0.79 seconds
Started Feb 04 12:41:46 PM PST 24
Finished Feb 04 12:41:52 PM PST 24
Peak memory 202828 kb
Host smart-04128b7c-5154-47fa-b600-1cfda8dc5379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454096563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.454096563
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.824637954
Short name T365
Test name
Test status
Simulation time 22693807 ps
CPU time 0.73 seconds
Started Feb 04 12:41:41 PM PST 24
Finished Feb 04 12:41:49 PM PST 24
Peak memory 202984 kb
Host smart-2355c80f-04ea-435c-8439-dd7a554e10d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824637954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.824637954
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3810334289
Short name T315
Test name
Test status
Simulation time 13574865 ps
CPU time 0.69 seconds
Started Feb 04 12:41:46 PM PST 24
Finished Feb 04 12:41:52 PM PST 24
Peak memory 203132 kb
Host smart-819c3a59-c901-497a-8cc7-4d5124d77f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810334289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3810334289
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1815540365
Short name T103
Test name
Test status
Simulation time 484743267 ps
CPU time 22.38 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 206324 kb
Host smart-afc1b0bb-8589-4f0e-91f2-c2cc889f471e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815540365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1815540365
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3977804009
Short name T66
Test name
Test status
Simulation time 45870149 ps
CPU time 0.96 seconds
Started Feb 04 12:41:22 PM PST 24
Finished Feb 04 12:41:30 PM PST 24
Peak memory 206192 kb
Host smart-118c7365-3ede-445e-b537-43fb0a5d6cc8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977804009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3977804009
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3160869831
Short name T323
Test name
Test status
Simulation time 93513136 ps
CPU time 1.35 seconds
Started Feb 04 12:41:20 PM PST 24
Finished Feb 04 12:41:29 PM PST 24
Peak memory 215340 kb
Host smart-11ff95da-0b72-46bf-a487-8a13860db8d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160869831 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3160869831
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1346069518
Short name T117
Test name
Test status
Simulation time 338813265 ps
CPU time 2.68 seconds
Started Feb 04 12:41:19 PM PST 24
Finished Feb 04 12:41:28 PM PST 24
Peak memory 215036 kb
Host smart-6f16ca46-447e-4397-9e08-2f34eafcdff0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346069518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
346069518
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2424897943
Short name T395
Test name
Test status
Simulation time 17679554 ps
CPU time 0.71 seconds
Started Feb 04 12:41:16 PM PST 24
Finished Feb 04 12:41:22 PM PST 24
Peak memory 203124 kb
Host smart-7d55f8ef-6523-4025-a4b7-aee3d87251fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424897943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
424897943
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2433309971
Short name T107
Test name
Test status
Simulation time 68556211 ps
CPU time 1.33 seconds
Started Feb 04 12:41:17 PM PST 24
Finished Feb 04 12:41:25 PM PST 24
Peak memory 215060 kb
Host smart-1ba957f8-7fcb-427d-a7fc-7e043954665f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433309971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2433309971
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.159684398
Short name T320
Test name
Test status
Simulation time 11574849 ps
CPU time 0.76 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:18 PM PST 24
Peak memory 202724 kb
Host smart-b9e549c6-b965-4674-bd23-80e3c82d6efe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159684398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.159684398
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2125007854
Short name T382
Test name
Test status
Simulation time 254087271 ps
CPU time 1.73 seconds
Started Feb 04 12:41:23 PM PST 24
Finished Feb 04 12:41:31 PM PST 24
Peak memory 206888 kb
Host smart-088ba8e7-3c16-448f-9923-c999a571f408
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125007854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2125007854
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3082874646
Short name T415
Test name
Test status
Simulation time 3860041757 ps
CPU time 13.99 seconds
Started Feb 04 12:41:21 PM PST 24
Finished Feb 04 12:41:42 PM PST 24
Peak memory 215136 kb
Host smart-8000fc26-5634-4b78-8cda-30a6d3de7745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082874646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3082874646
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2864581659
Short name T132
Test name
Test status
Simulation time 51112253 ps
CPU time 0.71 seconds
Started Feb 04 12:41:47 PM PST 24
Finished Feb 04 12:41:52 PM PST 24
Peak memory 202816 kb
Host smart-dbd7cc39-6377-4b17-b0e3-767d8f8c7b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864581659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2864581659
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.999064819
Short name T327
Test name
Test status
Simulation time 156182293 ps
CPU time 0.77 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 202876 kb
Host smart-3229432d-9423-49c0-984b-dd378e746b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999064819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.999064819
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3488684015
Short name T94
Test name
Test status
Simulation time 14648199 ps
CPU time 0.72 seconds
Started Feb 04 12:41:46 PM PST 24
Finished Feb 04 12:41:52 PM PST 24
Peak memory 203104 kb
Host smart-e2097c3f-a5f4-4fb5-9a64-0b470693cdf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488684015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3488684015
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.752488279
Short name T342
Test name
Test status
Simulation time 10848058 ps
CPU time 0.66 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:44 PM PST 24
Peak memory 203084 kb
Host smart-ad1f5b11-ae5c-4b6c-a8c1-280e1b425403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752488279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.752488279
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2804231130
Short name T316
Test name
Test status
Simulation time 62756825 ps
CPU time 0.73 seconds
Started Feb 04 12:41:47 PM PST 24
Finished Feb 04 12:41:52 PM PST 24
Peak memory 202812 kb
Host smart-d7508ef6-faf9-4f7a-9020-630d7ac09a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804231130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2804231130
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1879595915
Short name T336
Test name
Test status
Simulation time 14094623 ps
CPU time 0.76 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 203032 kb
Host smart-6edde49b-4f12-4c6f-8b21-2220194a2139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879595915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1879595915
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1901361711
Short name T387
Test name
Test status
Simulation time 65871932 ps
CPU time 0.74 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 202756 kb
Host smart-e255bd2c-4830-4395-973b-493926823392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901361711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1901361711
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1824624720
Short name T112
Test name
Test status
Simulation time 11602359 ps
CPU time 0.78 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 202724 kb
Host smart-96677432-760c-489f-944b-3f2cb5fd08db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824624720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1824624720
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.893224161
Short name T393
Test name
Test status
Simulation time 62706028 ps
CPU time 0.75 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 202868 kb
Host smart-6292dc88-18b8-4779-8a39-c4443de55fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893224161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.893224161
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1684225381
Short name T370
Test name
Test status
Simulation time 25147200 ps
CPU time 0.75 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 202772 kb
Host smart-94cf904d-b83c-46bc-8203-964434802eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684225381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1684225381
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.797380756
Short name T319
Test name
Test status
Simulation time 336949667 ps
CPU time 8.43 seconds
Started Feb 04 12:41:19 PM PST 24
Finished Feb 04 12:41:33 PM PST 24
Peak memory 206768 kb
Host smart-c5a02193-525f-4f35-b137-03716e0dd156
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797380756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.797380756
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1264706902
Short name T417
Test name
Test status
Simulation time 2494537208 ps
CPU time 13.4 seconds
Started Feb 04 12:41:18 PM PST 24
Finished Feb 04 12:41:38 PM PST 24
Peak memory 206840 kb
Host smart-b5910d2d-ab3b-49af-91bd-7fc001ac29fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264706902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1264706902
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.74825411
Short name T113
Test name
Test status
Simulation time 25631462 ps
CPU time 1.38 seconds
Started Feb 04 12:41:22 PM PST 24
Finished Feb 04 12:41:30 PM PST 24
Peak memory 215072 kb
Host smart-916c491a-2d30-4f81-a15f-9d29d7c21d75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74825411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
hw_reset.74825411
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1801696771
Short name T360
Test name
Test status
Simulation time 144197484 ps
CPU time 2.21 seconds
Started Feb 04 12:41:21 PM PST 24
Finished Feb 04 12:41:29 PM PST 24
Peak memory 216264 kb
Host smart-49ddca31-e817-4274-819e-35007f1fc3e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801696771 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1801696771
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.760529576
Short name T373
Test name
Test status
Simulation time 68614062 ps
CPU time 2.55 seconds
Started Feb 04 12:41:18 PM PST 24
Finished Feb 04 12:41:27 PM PST 24
Peak memory 206700 kb
Host smart-7401da89-fbf8-4052-9a77-b27bde0a90d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760529576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.760529576
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.646983124
Short name T399
Test name
Test status
Simulation time 12786063 ps
CPU time 0.72 seconds
Started Feb 04 12:41:20 PM PST 24
Finished Feb 04 12:41:28 PM PST 24
Peak memory 203004 kb
Host smart-3f925456-ce40-49db-b89c-67c30802acd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646983124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.646983124
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2356377129
Short name T102
Test name
Test status
Simulation time 77468384 ps
CPU time 1.69 seconds
Started Feb 04 12:41:16 PM PST 24
Finished Feb 04 12:41:25 PM PST 24
Peak memory 215024 kb
Host smart-805edb02-f6a4-433f-a736-84fe15f50d7d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356377129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2356377129
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1450100270
Short name T366
Test name
Test status
Simulation time 36720197 ps
CPU time 0.68 seconds
Started Feb 04 12:41:22 PM PST 24
Finished Feb 04 12:41:29 PM PST 24
Peak memory 202656 kb
Host smart-55e63a64-6d45-4ee3-a8b1-5a6daa653668
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450100270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1450100270
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.639232733
Short name T325
Test name
Test status
Simulation time 599279478 ps
CPU time 3.95 seconds
Started Feb 04 12:41:17 PM PST 24
Finished Feb 04 12:41:27 PM PST 24
Peak memory 206872 kb
Host smart-59058c60-9b5e-46e5-b98f-aa17fb472017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639232733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.639232733
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.898988500
Short name T367
Test name
Test status
Simulation time 77674846 ps
CPU time 3.05 seconds
Started Feb 04 12:41:23 PM PST 24
Finished Feb 04 12:41:32 PM PST 24
Peak memory 215244 kb
Host smart-e6e645c7-dd58-4d7c-921c-f5f634e2da75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898988500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.898988500
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2248928996
Short name T127
Test name
Test status
Simulation time 322557676 ps
CPU time 7.27 seconds
Started Feb 04 12:41:20 PM PST 24
Finished Feb 04 12:41:35 PM PST 24
Peak memory 215184 kb
Host smart-0f59ed1a-72a0-4556-ab27-f9f7e4724581
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248928996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2248928996
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3983850200
Short name T420
Test name
Test status
Simulation time 47242885 ps
CPU time 0.73 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 203128 kb
Host smart-dd1da157-c8f8-47ed-9a14-d554d7107bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983850200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3983850200
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2521549026
Short name T328
Test name
Test status
Simulation time 24347405 ps
CPU time 0.71 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:44 PM PST 24
Peak memory 202804 kb
Host smart-34a8c31a-ea29-46b9-b23e-68ad91cdabf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521549026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2521549026
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3477552922
Short name T91
Test name
Test status
Simulation time 20725299 ps
CPU time 0.73 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 202820 kb
Host smart-4447f97a-d6f2-4b42-9d4d-995c2119123b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477552922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3477552922
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1566817104
Short name T391
Test name
Test status
Simulation time 43908540 ps
CPU time 0.7 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 202812 kb
Host smart-00748314-0e2e-4c3b-bd64-addd001796e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566817104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1566817104
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1249376591
Short name T381
Test name
Test status
Simulation time 34586554 ps
CPU time 0.76 seconds
Started Feb 04 12:41:31 PM PST 24
Finished Feb 04 12:41:39 PM PST 24
Peak memory 202804 kb
Host smart-d6fac8b3-82ac-416e-b679-f0f8ed6b03a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249376591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1249376591
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2465640044
Short name T419
Test name
Test status
Simulation time 15245844 ps
CPU time 0.71 seconds
Started Feb 04 12:41:38 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 202800 kb
Host smart-a849e68b-2ebf-43fb-96de-40a29855e0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465640044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2465640044
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2968560878
Short name T363
Test name
Test status
Simulation time 59474875 ps
CPU time 0.73 seconds
Started Feb 04 12:41:31 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 202840 kb
Host smart-5b03c54e-2cee-44f4-b3ef-63e7fa200f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968560878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2968560878
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3231740245
Short name T51
Test name
Test status
Simulation time 53753504 ps
CPU time 0.8 seconds
Started Feb 04 12:41:38 PM PST 24
Finished Feb 04 12:41:45 PM PST 24
Peak memory 203212 kb
Host smart-f689a7bc-f385-498d-b307-8f69fcb4c874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231740245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3231740245
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3239827688
Short name T100
Test name
Test status
Simulation time 26971521 ps
CPU time 0.79 seconds
Started Feb 04 12:41:37 PM PST 24
Finished Feb 04 12:41:44 PM PST 24
Peak memory 202896 kb
Host smart-a6e3629c-259f-4d73-a035-544b9c9a465d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239827688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3239827688
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2481237931
Short name T131
Test name
Test status
Simulation time 31993939 ps
CPU time 0.73 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 202772 kb
Host smart-ad006a24-5746-476d-9861-ab7d6dca0cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481237931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2481237931
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1167930847
Short name T374
Test name
Test status
Simulation time 40819631 ps
CPU time 1.81 seconds
Started Feb 04 12:41:23 PM PST 24
Finished Feb 04 12:41:31 PM PST 24
Peak memory 216168 kb
Host smart-be986751-72b0-4f74-bd9d-c7e6bcbbc788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167930847 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1167930847
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3273579450
Short name T330
Test name
Test status
Simulation time 66657857 ps
CPU time 1.25 seconds
Started Feb 04 12:41:17 PM PST 24
Finished Feb 04 12:41:25 PM PST 24
Peak memory 214996 kb
Host smart-e02483ad-da7d-441b-9646-62daebf1988b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273579450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
273579450
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2185073781
Short name T410
Test name
Test status
Simulation time 26902794 ps
CPU time 0.84 seconds
Started Feb 04 12:41:20 PM PST 24
Finished Feb 04 12:41:27 PM PST 24
Peak memory 202832 kb
Host smart-10f42c30-ea09-4fc4-a0f8-ee3de49872df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185073781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
185073781
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.579588700
Short name T116
Test name
Test status
Simulation time 213912902 ps
CPU time 2.96 seconds
Started Feb 04 12:41:18 PM PST 24
Finished Feb 04 12:41:27 PM PST 24
Peak memory 214960 kb
Host smart-3fc046ec-e48c-4949-a26f-ce7e9ab47473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579588700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.579588700
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1265607665
Short name T333
Test name
Test status
Simulation time 77658587 ps
CPU time 4.02 seconds
Started Feb 04 12:41:17 PM PST 24
Finished Feb 04 12:41:27 PM PST 24
Peak memory 215320 kb
Host smart-41b0e59e-6711-44d8-aaea-c681949a55aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265607665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
265607665
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2716005620
Short name T368
Test name
Test status
Simulation time 1487354211 ps
CPU time 8.41 seconds
Started Feb 04 12:41:20 PM PST 24
Finished Feb 04 12:41:35 PM PST 24
Peak memory 215068 kb
Host smart-f8514343-df48-4cc1-93ba-69be22c48ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716005620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2716005620
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.619271404
Short name T283
Test name
Test status
Simulation time 179861553 ps
CPU time 2.39 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:42 PM PST 24
Peak memory 216448 kb
Host smart-e6e6d8d9-67bb-47dd-9970-efd44245372c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619271404 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.619271404
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3964434744
Short name T104
Test name
Test status
Simulation time 78724468 ps
CPU time 1.22 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 206684 kb
Host smart-325b91b7-2d11-428a-9957-df5c86db7a59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964434744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
964434744
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.324553603
Short name T329
Test name
Test status
Simulation time 23420235 ps
CPU time 0.78 seconds
Started Feb 04 12:41:31 PM PST 24
Finished Feb 04 12:41:39 PM PST 24
Peak memory 202772 kb
Host smart-01426589-75d8-4ef2-b9e6-9747709e51d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324553603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.324553603
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.198356802
Short name T357
Test name
Test status
Simulation time 388504479 ps
CPU time 1.72 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 206632 kb
Host smart-45d513b1-fc28-4fd9-b839-8f2156df83de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198356802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.198356802
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4292623087
Short name T362
Test name
Test status
Simulation time 26985056 ps
CPU time 1.81 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:41:47 PM PST 24
Peak memory 215188 kb
Host smart-1e80e7f4-12ec-4ec2-aa11-51e032c437bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292623087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
292623087
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3063071601
Short name T158
Test name
Test status
Simulation time 239373132 ps
CPU time 7.08 seconds
Started Feb 04 12:41:35 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 214968 kb
Host smart-dca86c5c-ed0c-4c57-aab9-d6fd344a499e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063071601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3063071601
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2599127207
Short name T96
Test name
Test status
Simulation time 28504932 ps
CPU time 1.38 seconds
Started Feb 04 12:41:32 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 215172 kb
Host smart-907e14b2-6734-45a6-9c0a-61ae738cc9b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599127207 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2599127207
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1564487012
Short name T408
Test name
Test status
Simulation time 93863037 ps
CPU time 2.64 seconds
Started Feb 04 12:41:33 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 215032 kb
Host smart-6618b24a-5d54-4a29-bb51-3fac958f5c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564487012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
564487012
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.463432056
Short name T314
Test name
Test status
Simulation time 27366298 ps
CPU time 0.76 seconds
Started Feb 04 12:41:37 PM PST 24
Finished Feb 04 12:41:45 PM PST 24
Peak memory 202704 kb
Host smart-1118932d-5df0-4400-ade5-9b2bba2a0441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463432056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.463432056
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.852501363
Short name T380
Test name
Test status
Simulation time 241121125 ps
CPU time 3.63 seconds
Started Feb 04 12:41:30 PM PST 24
Finished Feb 04 12:41:42 PM PST 24
Peak memory 206632 kb
Host smart-31f0b7d0-1381-4ef7-93c0-5a3bfaa34751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852501363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.852501363
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1644437424
Short name T87
Test name
Test status
Simulation time 552315333 ps
CPU time 3.85 seconds
Started Feb 04 12:41:31 PM PST 24
Finished Feb 04 12:41:42 PM PST 24
Peak memory 216352 kb
Host smart-1f434a23-ef02-411c-9340-6a4ddcde1b76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644437424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
644437424
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3053053844
Short name T151
Test name
Test status
Simulation time 538202523 ps
CPU time 14.66 seconds
Started Feb 04 12:41:32 PM PST 24
Finished Feb 04 12:41:54 PM PST 24
Peak memory 214992 kb
Host smart-7306ce77-78f4-4ccb-a1d2-f9a202ed1504
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053053844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3053053844
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4199887677
Short name T321
Test name
Test status
Simulation time 21987228 ps
CPU time 1.14 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:44 PM PST 24
Peak memory 215104 kb
Host smart-a73b0ecc-b37d-4e9e-89c9-21762f6267b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199887677 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4199887677
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1927717553
Short name T377
Test name
Test status
Simulation time 106800405 ps
CPU time 1.53 seconds
Started Feb 04 12:41:37 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 206740 kb
Host smart-f3861213-3104-4652-9ee2-667b2229d059
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927717553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
927717553
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3111673965
Short name T348
Test name
Test status
Simulation time 39714256 ps
CPU time 0.73 seconds
Started Feb 04 12:41:39 PM PST 24
Finished Feb 04 12:41:46 PM PST 24
Peak memory 202836 kb
Host smart-cbd534be-ed5c-44ca-92fc-3fd00783858d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111673965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
111673965
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.883979395
Short name T352
Test name
Test status
Simulation time 27064930 ps
CPU time 1.72 seconds
Started Feb 04 12:41:33 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 206660 kb
Host smart-7c3bbf7e-79ee-4731-a005-02b7db577582
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883979395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.883979395
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.848936375
Short name T130
Test name
Test status
Simulation time 1625029821 ps
CPU time 9.42 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:49 PM PST 24
Peak memory 214920 kb
Host smart-4db6149e-a52d-4d6d-b579-a024b8782e03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848936375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.848936375
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1768229676
Short name T90
Test name
Test status
Simulation time 87784061 ps
CPU time 1.82 seconds
Started Feb 04 12:41:34 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 216156 kb
Host smart-e07d302d-b54e-43b1-aded-a9fd67a3dddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768229676 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1768229676
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3311496123
Short name T392
Test name
Test status
Simulation time 116327543 ps
CPU time 2.79 seconds
Started Feb 04 12:41:32 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 207016 kb
Host smart-a608de6d-b013-47de-9309-6b400ec52b14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311496123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
311496123
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2919665403
Short name T346
Test name
Test status
Simulation time 13408293 ps
CPU time 0.79 seconds
Started Feb 04 12:41:36 PM PST 24
Finished Feb 04 12:41:44 PM PST 24
Peak memory 203136 kb
Host smart-df732048-2e34-4ef9-8f13-7b1a0351af25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919665403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
919665403
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1815208051
Short name T371
Test name
Test status
Simulation time 295267844 ps
CPU time 1.81 seconds
Started Feb 04 12:41:29 PM PST 24
Finished Feb 04 12:41:38 PM PST 24
Peak memory 207024 kb
Host smart-26629593-a539-4755-aae3-191eeb935bc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815208051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1815208051
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1272123993
Short name T86
Test name
Test status
Simulation time 55562765 ps
CPU time 1.98 seconds
Started Feb 04 12:41:35 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 215212 kb
Host smart-4fbc01c5-fb94-46c0-8b77-30330a6730bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272123993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
272123993
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2224332248
Short name T157
Test name
Test status
Simulation time 713670426 ps
CPU time 15.87 seconds
Started Feb 04 12:41:41 PM PST 24
Finished Feb 04 12:42:04 PM PST 24
Peak memory 215236 kb
Host smart-0abc84cd-22dd-45b8-a371-6a535d4241b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224332248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2224332248
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2797210896
Short name T1048
Test name
Test status
Simulation time 21942712 ps
CPU time 0.7 seconds
Started Feb 04 02:33:50 PM PST 24
Finished Feb 04 02:34:01 PM PST 24
Peak memory 204928 kb
Host smart-55c6da06-3230-444f-8e84-5140a1a0b39e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797210896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
797210896
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3537492553
Short name T793
Test name
Test status
Simulation time 77515652 ps
CPU time 2.67 seconds
Started Feb 04 02:33:40 PM PST 24
Finished Feb 04 02:33:44 PM PST 24
Peak memory 233580 kb
Host smart-6dcc26b2-f15c-4253-824d-5a74c551d2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537492553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3537492553
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.94379215
Short name T1099
Test name
Test status
Simulation time 59394267 ps
CPU time 0.75 seconds
Started Feb 04 02:33:42 PM PST 24
Finished Feb 04 02:33:44 PM PST 24
Peak memory 205116 kb
Host smart-be632c97-5887-4820-a077-201cee921d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94379215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.94379215
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4047443503
Short name T758
Test name
Test status
Simulation time 385771914 ps
CPU time 6.88 seconds
Started Feb 04 02:33:40 PM PST 24
Finished Feb 04 02:33:49 PM PST 24
Peak memory 234484 kb
Host smart-970ff81e-2337-43df-b4da-bb3c1c803a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047443503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4047443503
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1499487331
Short name T1083
Test name
Test status
Simulation time 12597783230 ps
CPU time 82.6 seconds
Started Feb 04 02:33:41 PM PST 24
Finished Feb 04 02:35:05 PM PST 24
Peak memory 253136 kb
Host smart-cd1eeea1-fe2b-45d9-9ad7-153759d2101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499487331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1499487331
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.574971658
Short name T224
Test name
Test status
Simulation time 7577603411 ps
CPU time 71.71 seconds
Started Feb 04 02:33:42 PM PST 24
Finished Feb 04 02:34:55 PM PST 24
Peak memory 256636 kb
Host smart-997f71f9-d355-4738-b9e3-b07c5b671596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574971658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
574971658
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4135599581
Short name T795
Test name
Test status
Simulation time 1722443444 ps
CPU time 11.51 seconds
Started Feb 04 02:33:43 PM PST 24
Finished Feb 04 02:33:56 PM PST 24
Peak memory 233712 kb
Host smart-3ccc08cb-8e16-49bd-820e-a6f053cb826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135599581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4135599581
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3587183340
Short name T551
Test name
Test status
Simulation time 1102567501 ps
CPU time 2.98 seconds
Started Feb 04 02:33:40 PM PST 24
Finished Feb 04 02:33:44 PM PST 24
Peak memory 217040 kb
Host smart-118d6b1f-acfc-4cec-8b40-3bb45acb1a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587183340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3587183340
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2902374939
Short name T580
Test name
Test status
Simulation time 2971897658 ps
CPU time 10.19 seconds
Started Feb 04 02:33:43 PM PST 24
Finished Feb 04 02:33:54 PM PST 24
Peak memory 236648 kb
Host smart-5d814bba-ade3-4aa9-bcf2-c2521ae5193a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902374939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2902374939
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4153034590
Short name T742
Test name
Test status
Simulation time 7733344866 ps
CPU time 22.65 seconds
Started Feb 04 02:33:39 PM PST 24
Finished Feb 04 02:34:03 PM PST 24
Peak memory 229548 kb
Host smart-89896645-d711-4ba8-96ab-08eb0d6ade74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153034590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4153034590
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2616406722
Short name T675
Test name
Test status
Simulation time 3919817241 ps
CPU time 5.09 seconds
Started Feb 04 02:33:40 PM PST 24
Finished Feb 04 02:33:47 PM PST 24
Peak memory 217676 kb
Host smart-52e129fe-2aa5-4b1c-ac00-d0e2d2d1a2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616406722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2616406722
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2852666818
Short name T655
Test name
Test status
Simulation time 34553523 ps
CPU time 0.71 seconds
Started Feb 04 02:33:40 PM PST 24
Finished Feb 04 02:33:42 PM PST 24
Peak memory 216236 kb
Host smart-6b8f6a65-b6b9-4fef-9e46-8caa0cb6d6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852666818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2852666818
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2401202952
Short name T437
Test name
Test status
Simulation time 637946178 ps
CPU time 3.88 seconds
Started Feb 04 02:33:41 PM PST 24
Finished Feb 04 02:33:47 PM PST 24
Peak memory 221528 kb
Host smart-dbd830f4-4cc7-4968-999f-812d7a84bdf3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2401202952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2401202952
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1490806669
Short name T56
Test name
Test status
Simulation time 66150660 ps
CPU time 1.08 seconds
Started Feb 04 02:33:40 PM PST 24
Finished Feb 04 02:33:42 PM PST 24
Peak memory 235440 kb
Host smart-383be3ae-7e0c-433f-aa7b-74aaa97ac43e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490806669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1490806669
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4009245790
Short name T564
Test name
Test status
Simulation time 1103516362 ps
CPU time 13.93 seconds
Started Feb 04 02:33:40 PM PST 24
Finished Feb 04 02:33:55 PM PST 24
Peak memory 216380 kb
Host smart-56fd9069-1b5b-4953-b195-1c74e820ad38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009245790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4009245790
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2218496080
Short name T1073
Test name
Test status
Simulation time 25487525410 ps
CPU time 36.42 seconds
Started Feb 04 02:33:41 PM PST 24
Finished Feb 04 02:34:19 PM PST 24
Peak memory 216452 kb
Host smart-7a8c0857-14f6-422f-994c-2622516bf3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218496080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2218496080
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3980566241
Short name T496
Test name
Test status
Simulation time 25259716 ps
CPU time 1.34 seconds
Started Feb 04 02:33:44 PM PST 24
Finished Feb 04 02:33:46 PM PST 24
Peak memory 216340 kb
Host smart-45dcb444-bf8d-4864-99d6-e55473906ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980566241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3980566241
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1594137350
Short name T956
Test name
Test status
Simulation time 21795064 ps
CPU time 0.72 seconds
Started Feb 04 02:33:40 PM PST 24
Finished Feb 04 02:33:42 PM PST 24
Peak memory 205448 kb
Host smart-d9422d05-f9bd-44e5-b98b-3be74d2a3e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594137350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1594137350
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1645940191
Short name T1011
Test name
Test status
Simulation time 530990520 ps
CPU time 5.52 seconds
Started Feb 04 02:33:41 PM PST 24
Finished Feb 04 02:33:48 PM PST 24
Peak memory 217812 kb
Host smart-fd9187da-a91b-434e-8209-60fc0f1b0782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645940191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1645940191
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4112145940
Short name T715
Test name
Test status
Simulation time 22631142 ps
CPU time 0.77 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:34:17 PM PST 24
Peak memory 204936 kb
Host smart-3c1ae44f-3442-441c-8679-4b0bd211a74f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112145940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
112145940
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.185019790
Short name T481
Test name
Test status
Simulation time 2690624583 ps
CPU time 6.27 seconds
Started Feb 04 02:34:06 PM PST 24
Finished Feb 04 02:34:18 PM PST 24
Peak memory 233728 kb
Host smart-b8cf864d-f94e-454f-a68d-31e735f4d8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185019790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.185019790
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4030953422
Short name T1016
Test name
Test status
Simulation time 83791854 ps
CPU time 0.79 seconds
Started Feb 04 02:33:47 PM PST 24
Finished Feb 04 02:34:01 PM PST 24
Peak memory 206152 kb
Host smart-dd8876c0-6443-4663-a0ab-bca20f5c3dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030953422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4030953422
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2217691808
Short name T61
Test name
Test status
Simulation time 147692064619 ps
CPU time 330.22 seconds
Started Feb 04 02:34:08 PM PST 24
Finished Feb 04 02:39:47 PM PST 24
Peak memory 241040 kb
Host smart-4b739404-2003-44b2-bdfa-1f52bc6c1030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217691808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2217691808
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3517067983
Short name T957
Test name
Test status
Simulation time 337941774 ps
CPU time 5.73 seconds
Started Feb 04 02:34:06 PM PST 24
Finished Feb 04 02:34:22 PM PST 24
Peak memory 224584 kb
Host smart-169a9fc6-2e6a-45d7-930c-8956da3fdd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517067983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3517067983
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3498088994
Short name T1084
Test name
Test status
Simulation time 373372375 ps
CPU time 2.14 seconds
Started Feb 04 02:34:05 PM PST 24
Finished Feb 04 02:34:14 PM PST 24
Peak memory 218472 kb
Host smart-6fa0dbdf-8aba-45b6-beda-7fadfd505a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498088994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3498088994
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2467780000
Short name T775
Test name
Test status
Simulation time 2904292698 ps
CPU time 10.1 seconds
Started Feb 04 02:34:04 PM PST 24
Finished Feb 04 02:34:19 PM PST 24
Peak memory 216972 kb
Host smart-6d862e85-5b30-4149-9d2a-25deccde42b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467780000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2467780000
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1311550184
Short name T2
Test name
Test status
Simulation time 15460586 ps
CPU time 1.01 seconds
Started Feb 04 02:33:50 PM PST 24
Finished Feb 04 02:34:01 PM PST 24
Peak memory 217880 kb
Host smart-b2738c44-b078-4405-bf1e-153adfb6ac91
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311550184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1311550184
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.131104503
Short name T285
Test name
Test status
Simulation time 148779784 ps
CPU time 2.42 seconds
Started Feb 04 02:34:05 PM PST 24
Finished Feb 04 02:34:12 PM PST 24
Peak memory 232816 kb
Host smart-98cf631d-c7ad-4d70-a015-25161f01566d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131104503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
131104503
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3793287631
Short name T240
Test name
Test status
Simulation time 3307287202 ps
CPU time 6.53 seconds
Started Feb 04 02:34:05 PM PST 24
Finished Feb 04 02:34:16 PM PST 24
Peak memory 220460 kb
Host smart-dfb3f2cc-3005-41ec-869c-4381eb8f321a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793287631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3793287631
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.826985836
Short name T588
Test name
Test status
Simulation time 17651197 ps
CPU time 0.74 seconds
Started Feb 04 02:33:59 PM PST 24
Finished Feb 04 02:34:02 PM PST 24
Peak memory 216276 kb
Host smart-e425319a-ed99-467b-a830-3292906f875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826985836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.826985836
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.692994757
Short name T567
Test name
Test status
Simulation time 1500853614 ps
CPU time 3.19 seconds
Started Feb 04 02:34:06 PM PST 24
Finished Feb 04 02:34:20 PM PST 24
Peak memory 219784 kb
Host smart-fde94518-dd28-4630-93a4-4bf5f553befe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=692994757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.692994757
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.574514475
Short name T57
Test name
Test status
Simulation time 88574256 ps
CPU time 1.17 seconds
Started Feb 04 02:34:10 PM PST 24
Finished Feb 04 02:34:18 PM PST 24
Peak memory 235420 kb
Host smart-9f80ddb8-2ac1-423e-8b19-a2ad818e7192
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574514475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.574514475
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2270552482
Short name T697
Test name
Test status
Simulation time 164721322 ps
CPU time 1 seconds
Started Feb 04 02:33:58 PM PST 24
Finished Feb 04 02:34:02 PM PST 24
Peak memory 206192 kb
Host smart-f26a7cd8-77c8-48e9-9002-7fb490260f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270552482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2270552482
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2279632723
Short name T1062
Test name
Test status
Simulation time 33808466784 ps
CPU time 43.17 seconds
Started Feb 04 02:34:06 PM PST 24
Finished Feb 04 02:34:55 PM PST 24
Peak memory 216428 kb
Host smart-0659596f-30b8-4ac2-906f-5759d1d08293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279632723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2279632723
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2339018956
Short name T429
Test name
Test status
Simulation time 456571451 ps
CPU time 2.59 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:34:19 PM PST 24
Peak memory 208008 kb
Host smart-cb706f11-5f9e-468a-af01-091b7b4c399c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339018956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2339018956
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3430388509
Short name T822
Test name
Test status
Simulation time 128190674 ps
CPU time 1.87 seconds
Started Feb 04 02:34:04 PM PST 24
Finished Feb 04 02:34:11 PM PST 24
Peak memory 216312 kb
Host smart-78918c09-887e-46f1-958f-e024a4c8c528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430388509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3430388509
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3810979082
Short name T825
Test name
Test status
Simulation time 163364885 ps
CPU time 1.19 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:34:18 PM PST 24
Peak memory 206004 kb
Host smart-08cdbec9-f690-4a50-aea1-de6dfcc63ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810979082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3810979082
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3539413233
Short name T803
Test name
Test status
Simulation time 1060070143 ps
CPU time 8.94 seconds
Started Feb 04 02:34:07 PM PST 24
Finished Feb 04 02:34:25 PM PST 24
Peak memory 226136 kb
Host smart-59c54c27-528b-449e-b6b9-cf0231e45054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539413233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3539413233
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1955337047
Short name T999
Test name
Test status
Simulation time 13494851 ps
CPU time 0.7 seconds
Started Feb 04 02:35:04 PM PST 24
Finished Feb 04 02:35:09 PM PST 24
Peak memory 204924 kb
Host smart-414dcc60-79fc-4c61-85f1-c1a97d901013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955337047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1955337047
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1794676843
Short name T1078
Test name
Test status
Simulation time 26599946876 ps
CPU time 12.94 seconds
Started Feb 04 02:35:12 PM PST 24
Finished Feb 04 02:35:28 PM PST 24
Peak memory 220956 kb
Host smart-5dcf469f-f33e-4967-a753-05c2cbbac301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794676843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1794676843
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1024435477
Short name T424
Test name
Test status
Simulation time 55483348 ps
CPU time 0.74 seconds
Started Feb 04 02:35:08 PM PST 24
Finished Feb 04 02:35:15 PM PST 24
Peak memory 205484 kb
Host smart-3f8c6340-bf38-4c2c-9dea-506108a1da75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024435477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1024435477
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1303670493
Short name T656
Test name
Test status
Simulation time 2367087280 ps
CPU time 16.23 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:35:27 PM PST 24
Peak memory 235344 kb
Host smart-3c650b2e-148c-4036-890b-ed450b718d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303670493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1303670493
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.395549928
Short name T255
Test name
Test status
Simulation time 29340728109 ps
CPU time 172.43 seconds
Started Feb 04 02:35:06 PM PST 24
Finished Feb 04 02:38:05 PM PST 24
Peak memory 260216 kb
Host smart-352e7b6b-86e3-4a43-87f2-fa68872215b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395549928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.395549928
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1992791656
Short name T982
Test name
Test status
Simulation time 11637438205 ps
CPU time 139.51 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:37:31 PM PST 24
Peak memory 254256 kb
Host smart-372e4324-a541-43c1-a3ec-2854dbfa2418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992791656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1992791656
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1024217308
Short name T3
Test name
Test status
Simulation time 7811248615 ps
CPU time 23.68 seconds
Started Feb 04 02:35:06 PM PST 24
Finished Feb 04 02:35:36 PM PST 24
Peak memory 223880 kb
Host smart-1f4ecf1b-0444-4898-b20c-bf0cafa28c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024217308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1024217308
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2627396002
Short name T137
Test name
Test status
Simulation time 797674934 ps
CPU time 5.56 seconds
Started Feb 04 02:35:02 PM PST 24
Finished Feb 04 02:35:11 PM PST 24
Peak memory 224540 kb
Host smart-7441d7c0-3a10-4aed-bb8d-2f0b939ff166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627396002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2627396002
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.829521898
Short name T203
Test name
Test status
Simulation time 1704630450 ps
CPU time 8.75 seconds
Started Feb 04 02:35:12 PM PST 24
Finished Feb 04 02:35:24 PM PST 24
Peak memory 230272 kb
Host smart-ee0e4a66-34df-4a34-a84b-25990f037818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829521898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.829521898
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2090756788
Short name T703
Test name
Test status
Simulation time 29099468 ps
CPU time 1.07 seconds
Started Feb 04 02:35:06 PM PST 24
Finished Feb 04 02:35:13 PM PST 24
Peak memory 217852 kb
Host smart-d1fe025f-8423-4ca0-816c-1005b93b4f5f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090756788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2090756788
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3269592805
Short name T869
Test name
Test status
Simulation time 6609799690 ps
CPU time 19.2 seconds
Started Feb 04 02:34:56 PM PST 24
Finished Feb 04 02:35:17 PM PST 24
Peak memory 237980 kb
Host smart-8eec2e80-5a6a-4346-bbde-802c0919edd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269592805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3269592805
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1014437553
Short name T1085
Test name
Test status
Simulation time 177549751 ps
CPU time 3.25 seconds
Started Feb 04 02:35:08 PM PST 24
Finished Feb 04 02:35:17 PM PST 24
Peak memory 217268 kb
Host smart-5916eb4b-9d01-4d04-a8fa-9172021ccffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014437553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1014437553
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4051525676
Short name T796
Test name
Test status
Simulation time 532828768 ps
CPU time 3.55 seconds
Started Feb 04 02:35:13 PM PST 24
Finished Feb 04 02:35:20 PM PST 24
Peak memory 220180 kb
Host smart-74536049-a220-4caf-aad1-51a5a8418824
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4051525676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4051525676
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4245945849
Short name T245
Test name
Test status
Simulation time 377832415309 ps
CPU time 505.15 seconds
Started Feb 04 02:35:09 PM PST 24
Finished Feb 04 02:43:39 PM PST 24
Peak memory 266356 kb
Host smart-e5475ade-f64f-4c1b-b3ae-f6f6a2225cb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245945849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4245945849
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1817095548
Short name T798
Test name
Test status
Simulation time 14289257290 ps
CPU time 40.59 seconds
Started Feb 04 02:35:06 PM PST 24
Finished Feb 04 02:35:52 PM PST 24
Peak memory 216456 kb
Host smart-bb262361-b979-4bce-b818-f48793fd375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817095548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1817095548
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2459934161
Short name T1116
Test name
Test status
Simulation time 12765376803 ps
CPU time 18.95 seconds
Started Feb 04 02:35:04 PM PST 24
Finished Feb 04 02:35:29 PM PST 24
Peak memory 216444 kb
Host smart-433b21e4-e81e-4f21-ab09-4ac2efcf7dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459934161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2459934161
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.944070018
Short name T746
Test name
Test status
Simulation time 343310286 ps
CPU time 1.76 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:35:13 PM PST 24
Peak memory 216660 kb
Host smart-f118b115-92e6-48a9-9f4d-ce09ba28e142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944070018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.944070018
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2797465260
Short name T10
Test name
Test status
Simulation time 235138421 ps
CPU time 0.87 seconds
Started Feb 04 02:35:09 PM PST 24
Finished Feb 04 02:35:15 PM PST 24
Peak memory 205400 kb
Host smart-598b5f5a-5bb1-445a-9b33-848e2de371d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797465260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2797465260
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2261491827
Short name T731
Test name
Test status
Simulation time 28108625009 ps
CPU time 24.67 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:35:36 PM PST 24
Peak memory 224704 kb
Host smart-ed2bd61a-5bee-4446-a6d5-24261e81099f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261491827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2261491827
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2662693475
Short name T1045
Test name
Test status
Simulation time 108619383 ps
CPU time 0.69 seconds
Started Feb 04 02:35:14 PM PST 24
Finished Feb 04 02:35:17 PM PST 24
Peak memory 204840 kb
Host smart-bc2a79a5-5d77-4015-8390-ca520728d5d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662693475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2662693475
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.372967754
Short name T973
Test name
Test status
Simulation time 16307213630 ps
CPU time 14.23 seconds
Started Feb 04 02:35:13 PM PST 24
Finished Feb 04 02:35:30 PM PST 24
Peak memory 234292 kb
Host smart-7a44042d-cbfb-46ba-920d-2254cb2f5f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372967754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.372967754
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.788163619
Short name T600
Test name
Test status
Simulation time 16439469 ps
CPU time 0.78 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:35:12 PM PST 24
Peak memory 206148 kb
Host smart-7ced0390-b129-4d28-ac90-0f7bfad659ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788163619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.788163619
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1623191068
Short name T168
Test name
Test status
Simulation time 6395342926 ps
CPU time 64.33 seconds
Started Feb 04 02:35:14 PM PST 24
Finished Feb 04 02:36:21 PM PST 24
Peak memory 244536 kb
Host smart-4036065e-cdcf-4f3a-84a1-1693f018a760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623191068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1623191068
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.20307640
Short name T570
Test name
Test status
Simulation time 40250833215 ps
CPU time 131.86 seconds
Started Feb 04 02:35:04 PM PST 24
Finished Feb 04 02:37:22 PM PST 24
Peak memory 237736 kb
Host smart-0f2cd24e-97b9-4098-b13a-d9a637d33202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20307640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.20307640
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3641615319
Short name T583
Test name
Test status
Simulation time 2511070521 ps
CPU time 34.85 seconds
Started Feb 04 02:35:17 PM PST 24
Finished Feb 04 02:35:53 PM PST 24
Peak memory 236060 kb
Host smart-dde1fda0-257a-4cfe-ac50-f69bfd6d5bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641615319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3641615319
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3399077481
Short name T504
Test name
Test status
Simulation time 1655023564 ps
CPU time 13.54 seconds
Started Feb 04 02:35:13 PM PST 24
Finished Feb 04 02:35:30 PM PST 24
Peak memory 237256 kb
Host smart-905deb2e-809c-46af-ae67-b02bebd94743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399077481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3399077481
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.642316103
Short name T959
Test name
Test status
Simulation time 2344617007 ps
CPU time 3.9 seconds
Started Feb 04 02:35:14 PM PST 24
Finished Feb 04 02:35:20 PM PST 24
Peak memory 218092 kb
Host smart-b7f29ffd-5d85-45c5-b31a-b9712c3b43ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642316103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.642316103
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4148902959
Short name T462
Test name
Test status
Simulation time 4972949033 ps
CPU time 9.83 seconds
Started Feb 04 02:35:08 PM PST 24
Finished Feb 04 02:35:23 PM PST 24
Peak memory 251008 kb
Host smart-dc9c6a70-0ff0-4dce-91a6-48288a6814ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148902959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4148902959
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2626931398
Short name T1102
Test name
Test status
Simulation time 48891962 ps
CPU time 1.04 seconds
Started Feb 04 02:35:08 PM PST 24
Finished Feb 04 02:35:14 PM PST 24
Peak memory 217840 kb
Host smart-69b2022c-65b4-46bb-ba7a-97d64dbb6820
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626931398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2626931398
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.23863117
Short name T1074
Test name
Test status
Simulation time 2434024315 ps
CPU time 15.18 seconds
Started Feb 04 02:35:06 PM PST 24
Finished Feb 04 02:35:27 PM PST 24
Peak memory 232808 kb
Host smart-6e134cfd-a528-4964-a594-d45243adb2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23863117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.23863117
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3853727168
Short name T565
Test name
Test status
Simulation time 45181534 ps
CPU time 2.62 seconds
Started Feb 04 02:35:07 PM PST 24
Finished Feb 04 02:35:15 PM PST 24
Peak memory 232708 kb
Host smart-90b5f293-93bb-4587-be0a-72e6355b7cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853727168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3853727168
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.1424159272
Short name T1019
Test name
Test status
Simulation time 16944495 ps
CPU time 0.72 seconds
Started Feb 04 02:35:04 PM PST 24
Finished Feb 04 02:35:09 PM PST 24
Peak memory 216232 kb
Host smart-6c46cb11-9052-4b0f-a210-03b5088dab74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424159272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.1424159272
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1987606103
Short name T965
Test name
Test status
Simulation time 2199579758 ps
CPU time 6.32 seconds
Started Feb 04 02:35:04 PM PST 24
Finished Feb 04 02:35:14 PM PST 24
Peak memory 222500 kb
Host smart-abecd4bd-063f-49f2-8368-0c0086cc5867
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1987606103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1987606103
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3676768206
Short name T49
Test name
Test status
Simulation time 51401739 ps
CPU time 0.96 seconds
Started Feb 04 02:35:12 PM PST 24
Finished Feb 04 02:35:16 PM PST 24
Peak memory 206328 kb
Host smart-3ef406c8-8038-492a-ad7d-ff426dade091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676768206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3676768206
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.531855765
Short name T562
Test name
Test status
Simulation time 7897010436 ps
CPU time 29.65 seconds
Started Feb 04 02:35:08 PM PST 24
Finished Feb 04 02:35:43 PM PST 24
Peak memory 216796 kb
Host smart-2fff83e4-2f62-4d02-b903-638f1f925150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531855765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.531855765
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1827189330
Short name T917
Test name
Test status
Simulation time 1357650726 ps
CPU time 7.94 seconds
Started Feb 04 02:35:12 PM PST 24
Finished Feb 04 02:35:23 PM PST 24
Peak memory 216428 kb
Host smart-81a4b259-a312-4a1c-af03-61b171ba1261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827189330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1827189330
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1372672227
Short name T579
Test name
Test status
Simulation time 664207327 ps
CPU time 3.56 seconds
Started Feb 04 02:35:13 PM PST 24
Finished Feb 04 02:35:19 PM PST 24
Peak memory 216572 kb
Host smart-3f3cfe0a-466e-4f05-af48-d9e002294530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372672227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1372672227
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.572112110
Short name T963
Test name
Test status
Simulation time 417946462 ps
CPU time 1.09 seconds
Started Feb 04 02:35:17 PM PST 24
Finished Feb 04 02:35:19 PM PST 24
Peak memory 206372 kb
Host smart-c13331a8-fcce-4c9a-8bfa-a509835fec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572112110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.572112110
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3623910089
Short name T998
Test name
Test status
Simulation time 533185958 ps
CPU time 6.88 seconds
Started Feb 04 02:35:08 PM PST 24
Finished Feb 04 02:35:21 PM PST 24
Peak memory 217448 kb
Host smart-2018830d-aa0d-4cc2-916f-9ad068894cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623910089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3623910089
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1752360716
Short name T762
Test name
Test status
Simulation time 21216640 ps
CPU time 0.72 seconds
Started Feb 04 02:35:27 PM PST 24
Finished Feb 04 02:35:36 PM PST 24
Peak memory 204360 kb
Host smart-6662d582-0a9f-431f-978f-5d8eb793728b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752360716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1752360716
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3358893816
Short name T871
Test name
Test status
Simulation time 304035870 ps
CPU time 2.37 seconds
Started Feb 04 02:35:31 PM PST 24
Finished Feb 04 02:35:42 PM PST 24
Peak memory 218456 kb
Host smart-412d97f8-2cfd-4d30-b3a6-34a550d4734b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358893816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3358893816
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3997281688
Short name T291
Test name
Test status
Simulation time 49034818 ps
CPU time 0.77 seconds
Started Feb 04 02:35:04 PM PST 24
Finished Feb 04 02:35:11 PM PST 24
Peak memory 206532 kb
Host smart-f8e2c7c3-f8cf-48b1-bfe1-5a888fa4e448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997281688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3997281688
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3261391243
Short name T780
Test name
Test status
Simulation time 55876491607 ps
CPU time 67.17 seconds
Started Feb 04 02:35:27 PM PST 24
Finished Feb 04 02:36:43 PM PST 24
Peak memory 249484 kb
Host smart-272600fe-bb04-4d17-83f9-16fa2a6a83b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261391243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3261391243
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3044237869
Short name T147
Test name
Test status
Simulation time 29118052201 ps
CPU time 124.56 seconds
Started Feb 04 02:35:26 PM PST 24
Finished Feb 04 02:37:39 PM PST 24
Peak memory 240648 kb
Host smart-a412b968-1217-474a-a6fb-9c98958e05cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044237869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3044237869
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.186953676
Short name T256
Test name
Test status
Simulation time 5940453524 ps
CPU time 51.97 seconds
Started Feb 04 02:35:31 PM PST 24
Finished Feb 04 02:36:32 PM PST 24
Peak memory 240172 kb
Host smart-7db695c8-451f-4326-b1af-8b0c48db29fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186953676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.186953676
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2408165207
Short name T1014
Test name
Test status
Simulation time 21475567046 ps
CPU time 35.55 seconds
Started Feb 04 02:35:28 PM PST 24
Finished Feb 04 02:36:12 PM PST 24
Peak memory 248932 kb
Host smart-3119ea45-9557-4081-bced-2908451e4da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408165207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2408165207
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3412914984
Short name T212
Test name
Test status
Simulation time 1340005493 ps
CPU time 4.35 seconds
Started Feb 04 02:35:12 PM PST 24
Finished Feb 04 02:35:19 PM PST 24
Peak memory 233312 kb
Host smart-24c84ce3-b4b8-48b5-9a6c-1b710c5b3bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412914984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3412914984
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.775465619
Short name T1086
Test name
Test status
Simulation time 8201989400 ps
CPU time 15.11 seconds
Started Feb 04 02:35:30 PM PST 24
Finished Feb 04 02:35:54 PM PST 24
Peak memory 224160 kb
Host smart-ee186e9c-b58f-467a-81cf-c0933d19ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775465619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.775465619
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2305336269
Short name T25
Test name
Test status
Simulation time 49711220 ps
CPU time 0.99 seconds
Started Feb 04 02:35:14 PM PST 24
Finished Feb 04 02:35:17 PM PST 24
Peak memory 217880 kb
Host smart-799c84c3-16e8-4dfc-bf54-9d4fc32b9426
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305336269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2305336269
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.833231166
Short name T910
Test name
Test status
Simulation time 19292732727 ps
CPU time 50.49 seconds
Started Feb 04 02:35:12 PM PST 24
Finished Feb 04 02:36:05 PM PST 24
Peak memory 241000 kb
Host smart-774578cf-9828-48cd-9752-a30196ea5bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833231166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.833231166
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1720242289
Short name T659
Test name
Test status
Simulation time 657064893 ps
CPU time 7.96 seconds
Started Feb 04 02:35:15 PM PST 24
Finished Feb 04 02:35:25 PM PST 24
Peak memory 218064 kb
Host smart-2ce79d41-86fd-4b5a-bfe9-853838269a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720242289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1720242289
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3286344155
Short name T962
Test name
Test status
Simulation time 21130891 ps
CPU time 0.74 seconds
Started Feb 04 02:35:13 PM PST 24
Finished Feb 04 02:35:16 PM PST 24
Peak memory 216280 kb
Host smart-6deea2f0-680d-49db-bfbf-50cd9e244ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286344155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3286344155
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.944386990
Short name T1107
Test name
Test status
Simulation time 515553062 ps
CPU time 3.61 seconds
Started Feb 04 02:35:28 PM PST 24
Finished Feb 04 02:35:40 PM PST 24
Peak memory 222032 kb
Host smart-bbe5cc3f-57f0-4828-869c-28b77a31f85c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=944386990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.944386990
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2052471760
Short name T712
Test name
Test status
Simulation time 518840112 ps
CPU time 2.78 seconds
Started Feb 04 02:35:13 PM PST 24
Finished Feb 04 02:35:18 PM PST 24
Peak memory 216384 kb
Host smart-fabff85a-19b2-4fa7-aab9-115c25becb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052471760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2052471760
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2053328949
Short name T136
Test name
Test status
Simulation time 687735836 ps
CPU time 2.04 seconds
Started Feb 04 02:35:15 PM PST 24
Finished Feb 04 02:35:19 PM PST 24
Peak memory 206956 kb
Host smart-77383209-f830-4035-aab5-1a35b99b279f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053328949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2053328949
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1139265483
Short name T928
Test name
Test status
Simulation time 517650070 ps
CPU time 4.22 seconds
Started Feb 04 02:35:21 PM PST 24
Finished Feb 04 02:35:26 PM PST 24
Peak memory 216392 kb
Host smart-cbe7b462-49b2-4c02-abc7-5a54f1eb908e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139265483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1139265483
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1522973482
Short name T881
Test name
Test status
Simulation time 255697646 ps
CPU time 0.93 seconds
Started Feb 04 02:35:11 PM PST 24
Finished Feb 04 02:35:16 PM PST 24
Peak memory 205396 kb
Host smart-b5c16ac1-ddd6-498c-8a9e-897373247b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522973482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1522973482
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2771222977
Short name T458
Test name
Test status
Simulation time 272155913 ps
CPU time 5.58 seconds
Started Feb 04 02:35:35 PM PST 24
Finished Feb 04 02:35:48 PM PST 24
Peak memory 233488 kb
Host smart-6bfb90b2-d5fc-41be-a6fd-e08530ef4be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771222977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2771222977
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1442719800
Short name T831
Test name
Test status
Simulation time 32026346 ps
CPU time 0.72 seconds
Started Feb 04 02:35:28 PM PST 24
Finished Feb 04 02:35:37 PM PST 24
Peak memory 204444 kb
Host smart-2cda87ee-a3b5-496b-8292-090e23d8417d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442719800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1442719800
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4061070039
Short name T927
Test name
Test status
Simulation time 182819078 ps
CPU time 2.9 seconds
Started Feb 04 02:35:25 PM PST 24
Finished Feb 04 02:35:35 PM PST 24
Peak memory 233272 kb
Host smart-87096cd7-4d0c-45ed-a2a4-34e731cf8b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061070039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4061070039
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3500721649
Short name T860
Test name
Test status
Simulation time 23134315 ps
CPU time 0.82 seconds
Started Feb 04 02:35:27 PM PST 24
Finished Feb 04 02:35:37 PM PST 24
Peak memory 206156 kb
Host smart-f839d0d9-4184-42c9-a74c-afdba6fc0c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500721649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3500721649
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2416406014
Short name T536
Test name
Test status
Simulation time 86553749572 ps
CPU time 234 seconds
Started Feb 04 02:35:26 PM PST 24
Finished Feb 04 02:39:30 PM PST 24
Peak memory 257436 kb
Host smart-0d60fed8-3e8b-45b5-8062-185ace841fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416406014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2416406014
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2868416404
Short name T243
Test name
Test status
Simulation time 12208931035 ps
CPU time 92.97 seconds
Started Feb 04 02:35:30 PM PST 24
Finished Feb 04 02:37:12 PM PST 24
Peak memory 234472 kb
Host smart-ea9f3f5a-c85b-4436-9afc-c1b46cbcdf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868416404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2868416404
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3784982106
Short name T163
Test name
Test status
Simulation time 89472674395 ps
CPU time 263.32 seconds
Started Feb 04 02:35:34 PM PST 24
Finished Feb 04 02:40:05 PM PST 24
Peak memory 252828 kb
Host smart-6cebe456-124a-4fd1-ac91-d9b717b9f35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784982106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3784982106
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3112231747
Short name T873
Test name
Test status
Simulation time 1136290810 ps
CPU time 11.3 seconds
Started Feb 04 02:35:29 PM PST 24
Finished Feb 04 02:35:48 PM PST 24
Peak memory 240184 kb
Host smart-fcfc5a1b-a7fc-4568-bf7b-381b6e176760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112231747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3112231747
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.533346108
Short name T947
Test name
Test status
Simulation time 2108615166 ps
CPU time 5.1 seconds
Started Feb 04 02:35:34 PM PST 24
Finished Feb 04 02:35:47 PM PST 24
Peak memory 220716 kb
Host smart-6f5fbf33-ded7-4a4b-9b68-8453d10c37f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533346108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.533346108
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1802016408
Short name T202
Test name
Test status
Simulation time 10190803983 ps
CPU time 18.9 seconds
Started Feb 04 02:35:30 PM PST 24
Finished Feb 04 02:35:58 PM PST 24
Peak memory 233624 kb
Host smart-5a6fce8f-aa8a-449c-9d51-f01e1b7fff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802016408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1802016408
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.440991145
Short name T716
Test name
Test status
Simulation time 17387197 ps
CPU time 0.98 seconds
Started Feb 04 02:35:30 PM PST 24
Finished Feb 04 02:35:40 PM PST 24
Peak memory 217856 kb
Host smart-0140f072-de98-4c77-8eaa-82bad574bb8d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440991145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.440991145
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.911293369
Short name T227
Test name
Test status
Simulation time 11260724417 ps
CPU time 12.9 seconds
Started Feb 04 02:35:29 PM PST 24
Finished Feb 04 02:35:49 PM PST 24
Peak memory 244928 kb
Host smart-c2734bdf-ebf8-4bae-ac54-4967c17d90e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911293369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.911293369
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1113260838
Short name T485
Test name
Test status
Simulation time 10997818080 ps
CPU time 5.42 seconds
Started Feb 04 02:35:30 PM PST 24
Finished Feb 04 02:35:45 PM PST 24
Peak memory 233636 kb
Host smart-e45a42c8-9038-412b-b272-ba7b4f236846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113260838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1113260838
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.2920064499
Short name T522
Test name
Test status
Simulation time 40516703 ps
CPU time 0.71 seconds
Started Feb 04 02:35:29 PM PST 24
Finished Feb 04 02:35:37 PM PST 24
Peak memory 216268 kb
Host smart-5381ac89-826f-4de8-b4e7-d588e12c437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920064499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2920064499
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2323877887
Short name T509
Test name
Test status
Simulation time 723602062 ps
CPU time 3.21 seconds
Started Feb 04 02:35:26 PM PST 24
Finished Feb 04 02:35:39 PM PST 24
Peak memory 217396 kb
Host smart-629388c9-720e-43a5-bfe5-de6621c6426e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2323877887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2323877887
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3738830722
Short name T691
Test name
Test status
Simulation time 2429366511 ps
CPU time 38.92 seconds
Started Feb 04 02:35:25 PM PST 24
Finished Feb 04 02:36:12 PM PST 24
Peak memory 252052 kb
Host smart-ccad559f-2360-423c-80e3-b344146da18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738830722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3738830722
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2539743767
Short name T279
Test name
Test status
Simulation time 2919198532 ps
CPU time 40.66 seconds
Started Feb 04 02:35:29 PM PST 24
Finished Feb 04 02:36:17 PM PST 24
Peak memory 216604 kb
Host smart-feeb56d7-47ef-4d5d-93b9-2d9233557301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539743767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2539743767
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2352800922
Short name T512
Test name
Test status
Simulation time 1398103654 ps
CPU time 8.45 seconds
Started Feb 04 02:35:27 PM PST 24
Finished Feb 04 02:35:44 PM PST 24
Peak memory 216336 kb
Host smart-e64cd29a-ba23-45b5-8d4e-163d023ed8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352800922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2352800922
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1225735392
Short name T529
Test name
Test status
Simulation time 200420020 ps
CPU time 2.73 seconds
Started Feb 04 02:35:32 PM PST 24
Finished Feb 04 02:35:44 PM PST 24
Peak memory 217600 kb
Host smart-f31abca2-cffa-4c93-9807-d3712a0485c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225735392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1225735392
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2482922564
Short name T39
Test name
Test status
Simulation time 221747376 ps
CPU time 0.94 seconds
Started Feb 04 02:35:27 PM PST 24
Finished Feb 04 02:35:37 PM PST 24
Peak memory 205460 kb
Host smart-ad214275-57cc-4f36-97d3-6c9cfba4e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482922564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2482922564
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1174469979
Short name T296
Test name
Test status
Simulation time 5930419312 ps
CPU time 6.41 seconds
Started Feb 04 02:35:32 PM PST 24
Finished Feb 04 02:35:46 PM PST 24
Peak memory 236352 kb
Host smart-9b916599-c63c-4543-a334-c6fb223a27b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174469979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1174469979
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3849649788
Short name T916
Test name
Test status
Simulation time 45670214 ps
CPU time 0.68 seconds
Started Feb 04 02:35:38 PM PST 24
Finished Feb 04 02:35:50 PM PST 24
Peak memory 204936 kb
Host smart-383dc285-893b-4427-aac4-3c196bee1cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849649788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3849649788
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2055574322
Short name T623
Test name
Test status
Simulation time 2465981169 ps
CPU time 8.04 seconds
Started Feb 04 02:35:27 PM PST 24
Finished Feb 04 02:35:44 PM PST 24
Peak memory 219000 kb
Host smart-20528b48-861c-47c9-83c6-846f95826b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055574322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2055574322
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2513937718
Short name T301
Test name
Test status
Simulation time 46399474 ps
CPU time 0.76 seconds
Started Feb 04 02:35:31 PM PST 24
Finished Feb 04 02:35:40 PM PST 24
Peak memory 206520 kb
Host smart-1b8c04b4-2768-4891-b732-16f1308a560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513937718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2513937718
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2679517613
Short name T634
Test name
Test status
Simulation time 14781614329 ps
CPU time 37.73 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:36:34 PM PST 24
Peak memory 252652 kb
Host smart-ec3a90d8-c140-4e32-b8f8-bdc64f22d120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679517613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2679517613
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.934424497
Short name T837
Test name
Test status
Simulation time 63031701636 ps
CPU time 455.18 seconds
Started Feb 04 02:35:33 PM PST 24
Finished Feb 04 02:43:17 PM PST 24
Peak memory 253024 kb
Host smart-db1e3c3b-d5ac-4aac-9d96-e4f53b90eed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934424497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.934424497
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.951019885
Short name T978
Test name
Test status
Simulation time 29434444995 ps
CPU time 234.7 seconds
Started Feb 04 02:35:36 PM PST 24
Finished Feb 04 02:39:42 PM PST 24
Peak memory 268368 kb
Host smart-dedf620b-75b4-4eac-bfd7-a3766b575705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951019885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.951019885
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3827498162
Short name T1061
Test name
Test status
Simulation time 14138669739 ps
CPU time 33.41 seconds
Started Feb 04 02:35:36 PM PST 24
Finished Feb 04 02:36:16 PM PST 24
Peak memory 240096 kb
Host smart-16218477-15d7-44cc-8dc5-bc769e5250e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827498162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3827498162
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4133521945
Short name T41
Test name
Test status
Simulation time 11696730096 ps
CPU time 9.37 seconds
Started Feb 04 02:35:31 PM PST 24
Finished Feb 04 02:35:49 PM PST 24
Peak memory 218948 kb
Host smart-490b9b2b-1c69-4110-8c36-1536a906c802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133521945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4133521945
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3371959604
Short name T773
Test name
Test status
Simulation time 5719468670 ps
CPU time 21.72 seconds
Started Feb 04 02:35:35 PM PST 24
Finished Feb 04 02:36:04 PM PST 24
Peak memory 230432 kb
Host smart-cf2d44c4-789a-4e1f-8ce5-50ea23aaac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371959604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3371959604
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.969856213
Short name T920
Test name
Test status
Simulation time 149440125 ps
CPU time 1.02 seconds
Started Feb 04 02:35:31 PM PST 24
Finished Feb 04 02:35:41 PM PST 24
Peak memory 216628 kb
Host smart-498b873e-9966-48e7-8745-a0c4833c123f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969856213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.969856213
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3137204602
Short name T459
Test name
Test status
Simulation time 3549039175 ps
CPU time 13.59 seconds
Started Feb 04 02:35:30 PM PST 24
Finished Feb 04 02:35:53 PM PST 24
Peak memory 229180 kb
Host smart-83ffd1be-70d6-4d2b-82e8-45e9dfa10d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137204602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3137204602
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.167067710
Short name T614
Test name
Test status
Simulation time 713861112 ps
CPU time 6.39 seconds
Started Feb 04 02:35:25 PM PST 24
Finished Feb 04 02:35:40 PM PST 24
Peak memory 233380 kb
Host smart-5bea22cb-dcea-4c76-a942-8c5e700913da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167067710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.167067710
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.3200041622
Short name T513
Test name
Test status
Simulation time 35930611 ps
CPU time 0.73 seconds
Started Feb 04 02:35:27 PM PST 24
Finished Feb 04 02:35:36 PM PST 24
Peak memory 216264 kb
Host smart-2d57f355-d101-4eeb-9747-3a836469a582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200041622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.3200041622
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2786927778
Short name T816
Test name
Test status
Simulation time 646411049 ps
CPU time 3.4 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:35:54 PM PST 24
Peak memory 218736 kb
Host smart-dd3c971c-c8d9-409f-a358-0ff9a17a5f84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2786927778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2786927778
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3492236193
Short name T851
Test name
Test status
Simulation time 10622471653 ps
CPU time 45.05 seconds
Started Feb 04 02:35:27 PM PST 24
Finished Feb 04 02:36:21 PM PST 24
Peak memory 216432 kb
Host smart-db0dcfbf-2bf7-416d-a594-083d47ae4d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492236193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3492236193
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1731515212
Short name T686
Test name
Test status
Simulation time 154833958 ps
CPU time 1.54 seconds
Started Feb 04 02:35:26 PM PST 24
Finished Feb 04 02:35:36 PM PST 24
Peak memory 206900 kb
Host smart-6306a3c8-17ed-4ef3-a066-99c2675f9f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731515212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1731515212
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3787378181
Short name T841
Test name
Test status
Simulation time 226359638 ps
CPU time 1.44 seconds
Started Feb 04 02:35:28 PM PST 24
Finished Feb 04 02:35:38 PM PST 24
Peak memory 208560 kb
Host smart-fba6a20e-12f5-487d-9cf3-68e2fb705707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787378181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3787378181
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4006902241
Short name T1037
Test name
Test status
Simulation time 64465973 ps
CPU time 0.79 seconds
Started Feb 04 02:35:31 PM PST 24
Finished Feb 04 02:35:40 PM PST 24
Peak memory 205336 kb
Host smart-cdc48d4e-8859-450a-927b-a820fbc09c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006902241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4006902241
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3272838036
Short name T863
Test name
Test status
Simulation time 1458090688 ps
CPU time 10.31 seconds
Started Feb 04 02:35:28 PM PST 24
Finished Feb 04 02:35:47 PM PST 24
Peak memory 220184 kb
Host smart-85cbb7a8-4c6b-4a49-9b5b-af7f5de2a9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272838036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3272838036
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2201295365
Short name T673
Test name
Test status
Simulation time 174868706 ps
CPU time 0.74 seconds
Started Feb 04 02:35:35 PM PST 24
Finished Feb 04 02:35:44 PM PST 24
Peak memory 204964 kb
Host smart-f0e88c5c-6850-4e28-9645-19a37823dd26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201295365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2201295365
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.398817876
Short name T814
Test name
Test status
Simulation time 74774538 ps
CPU time 2.51 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:35:53 PM PST 24
Peak memory 233552 kb
Host smart-9a4ec611-ee8c-461f-ac8e-9d911ce4e203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398817876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.398817876
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3442707095
Short name T1069
Test name
Test status
Simulation time 37940491 ps
CPU time 0.78 seconds
Started Feb 04 02:35:39 PM PST 24
Finished Feb 04 02:35:51 PM PST 24
Peak memory 206248 kb
Host smart-f8812807-af19-4960-8df1-6a296bd51d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442707095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3442707095
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3391529719
Short name T599
Test name
Test status
Simulation time 251266850772 ps
CPU time 180.41 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:38:57 PM PST 24
Peak memory 261376 kb
Host smart-92fdfa93-a804-4fe7-aa2d-555cbd8eac8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391529719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3391529719
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2812619016
Short name T573
Test name
Test status
Simulation time 6199260450 ps
CPU time 84.59 seconds
Started Feb 04 02:35:39 PM PST 24
Finished Feb 04 02:37:15 PM PST 24
Peak memory 249312 kb
Host smart-43085035-49e5-4e7d-9e3f-ea2ff893dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812619016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2812619016
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2557184931
Short name T553
Test name
Test status
Simulation time 29157659941 ps
CPU time 37.38 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:36:28 PM PST 24
Peak memory 246268 kb
Host smart-8fc3349b-7a89-470e-93c6-68cd949b064b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557184931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2557184931
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2076628979
Short name T628
Test name
Test status
Simulation time 1697683676 ps
CPU time 7.89 seconds
Started Feb 04 02:35:43 PM PST 24
Finished Feb 04 02:36:04 PM PST 24
Peak memory 234356 kb
Host smart-30c2281a-0b4f-4d0c-9e1b-e47f35924e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076628979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2076628979
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3246515
Short name T206
Test name
Test status
Simulation time 246476220 ps
CPU time 3.47 seconds
Started Feb 04 02:35:39 PM PST 24
Finished Feb 04 02:35:53 PM PST 24
Peak memory 224504 kb
Host smart-fca2bf12-f5ff-4679-b4a7-535314235dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3246515
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2562171883
Short name T769
Test name
Test status
Simulation time 44526392 ps
CPU time 1.13 seconds
Started Feb 04 02:35:45 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 216660 kb
Host smart-bbd38bb1-7cb1-4ac6-a75e-f60c7314b919
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562171883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2562171883
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3961330959
Short name T226
Test name
Test status
Simulation time 5592281634 ps
CPU time 15.84 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:36:12 PM PST 24
Peak memory 216596 kb
Host smart-6c366023-beed-41d6-be09-e76bcfac7b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961330959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3961330959
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2887672723
Short name T542
Test name
Test status
Simulation time 251420688 ps
CPU time 4.07 seconds
Started Feb 04 02:35:37 PM PST 24
Finished Feb 04 02:35:53 PM PST 24
Peak memory 233384 kb
Host smart-a8dd8c5c-2e7e-44ea-9d50-c603bc940c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887672723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2887672723
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.537665975
Short name T556
Test name
Test status
Simulation time 17176440 ps
CPU time 0.73 seconds
Started Feb 04 02:35:34 PM PST 24
Finished Feb 04 02:35:43 PM PST 24
Peak memory 216276 kb
Host smart-911d18e6-3b8d-4407-8f02-86e46ab7813a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537665975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.537665975
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3017931444
Short name T1115
Test name
Test status
Simulation time 4955244233 ps
CPU time 7.12 seconds
Started Feb 04 02:35:38 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 218984 kb
Host smart-03dfaf7e-1962-41cb-be33-e9b40ce710ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3017931444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3017931444
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1263862564
Short name T781
Test name
Test status
Simulation time 148244454669 ps
CPU time 560.27 seconds
Started Feb 04 02:35:36 PM PST 24
Finished Feb 04 02:45:03 PM PST 24
Peak memory 265700 kb
Host smart-99fd7f20-3983-41ab-b530-6bcfcb4cf455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263862564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1263862564
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3703503563
Short name T22
Test name
Test status
Simulation time 23005977153 ps
CPU time 27.43 seconds
Started Feb 04 02:35:35 PM PST 24
Finished Feb 04 02:36:10 PM PST 24
Peak memory 216396 kb
Host smart-7499f977-6a63-41ca-9d6a-341a16a51bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703503563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3703503563
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.548999567
Short name T665
Test name
Test status
Simulation time 8989700714 ps
CPU time 24.66 seconds
Started Feb 04 02:35:48 PM PST 24
Finished Feb 04 02:36:21 PM PST 24
Peak memory 216388 kb
Host smart-7ebb5db5-981f-43ba-a0d7-5fbf1052df85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548999567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.548999567
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2063763859
Short name T654
Test name
Test status
Simulation time 236168321 ps
CPU time 1.78 seconds
Started Feb 04 02:35:42 PM PST 24
Finished Feb 04 02:35:56 PM PST 24
Peak memory 216384 kb
Host smart-7b9b7e34-37db-4139-b196-689484f132cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063763859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2063763859
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3615871895
Short name T946
Test name
Test status
Simulation time 393530629 ps
CPU time 0.88 seconds
Started Feb 04 02:35:36 PM PST 24
Finished Feb 04 02:35:48 PM PST 24
Peak memory 205480 kb
Host smart-e9613174-7360-45b3-b318-9d1b25ce2d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615871895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3615871895
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4172345491
Short name T925
Test name
Test status
Simulation time 165028579 ps
CPU time 4.08 seconds
Started Feb 04 02:35:37 PM PST 24
Finished Feb 04 02:35:52 PM PST 24
Peak memory 232816 kb
Host smart-f1a7aed1-3e30-447d-9552-e358e153cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172345491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4172345491
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1759251734
Short name T38
Test name
Test status
Simulation time 124844721 ps
CPU time 2.75 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:35:59 PM PST 24
Peak memory 233684 kb
Host smart-d2c8ab96-eeba-4564-afc8-20d4fc027598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759251734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1759251734
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3200656697
Short name T882
Test name
Test status
Simulation time 60179211 ps
CPU time 0.76 seconds
Started Feb 04 02:35:45 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 205176 kb
Host smart-9df74aad-b6f5-489c-a080-54fee98f143a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200656697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3200656697
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4005738364
Short name T198
Test name
Test status
Simulation time 8536986314 ps
CPU time 99.97 seconds
Started Feb 04 02:35:43 PM PST 24
Finished Feb 04 02:37:35 PM PST 24
Peak memory 255660 kb
Host smart-64bca3d8-d047-4beb-8fbe-8b2a29fbf23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005738364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4005738364
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4048427030
Short name T514
Test name
Test status
Simulation time 1596787369 ps
CPU time 6.85 seconds
Started Feb 04 02:35:43 PM PST 24
Finished Feb 04 02:36:03 PM PST 24
Peak memory 240472 kb
Host smart-369f765a-acc2-48e4-a92e-cd28dbefc336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048427030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4048427030
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4185145979
Short name T694
Test name
Test status
Simulation time 678198513 ps
CPU time 4.48 seconds
Started Feb 04 02:35:41 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 224488 kb
Host smart-a84d968d-0f51-4791-a30a-633c0fb0e6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185145979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4185145979
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1614273784
Short name T135
Test name
Test status
Simulation time 45880366488 ps
CPU time 26.16 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:36:17 PM PST 24
Peak memory 240692 kb
Host smart-bfee88c2-abff-4db8-bacf-3d1929b580ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614273784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1614273784
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.183582611
Short name T511
Test name
Test status
Simulation time 78308614 ps
CPU time 1 seconds
Started Feb 04 02:35:39 PM PST 24
Finished Feb 04 02:35:51 PM PST 24
Peak memory 217880 kb
Host smart-6abf76ac-b090-49e9-8b75-a9a760cb7edf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183582611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.183582611
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3951741774
Short name T622
Test name
Test status
Simulation time 37718429770 ps
CPU time 15.56 seconds
Started Feb 04 02:35:36 PM PST 24
Finished Feb 04 02:35:59 PM PST 24
Peak memory 229600 kb
Host smart-0827d74d-3573-43f7-b222-a306827be057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951741774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3951741774
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2075244926
Short name T676
Test name
Test status
Simulation time 6259640847 ps
CPU time 22.38 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:36:13 PM PST 24
Peak memory 237388 kb
Host smart-dbb1b52f-da40-4685-a10e-7247ffa1fcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075244926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2075244926
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.1478884788
Short name T290
Test name
Test status
Simulation time 39657511 ps
CPU time 0.74 seconds
Started Feb 04 02:35:37 PM PST 24
Finished Feb 04 02:35:50 PM PST 24
Peak memory 216236 kb
Host smart-04f43efd-245e-4b59-93a9-605a98b07063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478884788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.1478884788
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3943665995
Short name T304
Test name
Test status
Simulation time 590853644 ps
CPU time 3.48 seconds
Started Feb 04 02:35:45 PM PST 24
Finished Feb 04 02:36:00 PM PST 24
Peak memory 222092 kb
Host smart-766a2c63-8e27-4890-a25f-41f1ef7b962e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3943665995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3943665995
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.368234411
Short name T700
Test name
Test status
Simulation time 200089602 ps
CPU time 1 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:35:52 PM PST 24
Peak memory 206256 kb
Host smart-3c460ba1-0f95-41ca-8740-f9931937255a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368234411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.368234411
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1827354198
Short name T805
Test name
Test status
Simulation time 2992461793 ps
CPU time 42.39 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:36:34 PM PST 24
Peak memory 220496 kb
Host smart-2ed3fd45-6faa-4e92-a223-4037dd1eebc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827354198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1827354198
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.43512357
Short name T488
Test name
Test status
Simulation time 5074864511 ps
CPU time 8.75 seconds
Started Feb 04 02:35:44 PM PST 24
Finished Feb 04 02:36:05 PM PST 24
Peak memory 217132 kb
Host smart-b7f02668-535d-4ea6-84d7-d5c28f824190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43512357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.43512357
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3578009515
Short name T450
Test name
Test status
Simulation time 698149022 ps
CPU time 3.31 seconds
Started Feb 04 02:35:37 PM PST 24
Finished Feb 04 02:35:52 PM PST 24
Peak memory 208764 kb
Host smart-1ffcdd2b-7ee0-4532-9b91-90e89b0f8e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578009515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3578009515
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.406991856
Short name T849
Test name
Test status
Simulation time 140492036 ps
CPU time 1.07 seconds
Started Feb 04 02:35:38 PM PST 24
Finished Feb 04 02:35:50 PM PST 24
Peak memory 206460 kb
Host smart-05556f5c-f429-4119-8924-1c456622a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406991856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.406991856
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2859375289
Short name T650
Test name
Test status
Simulation time 433378000 ps
CPU time 3.62 seconds
Started Feb 04 02:35:41 PM PST 24
Finished Feb 04 02:35:56 PM PST 24
Peak memory 233760 kb
Host smart-19e7cf49-149c-452b-ad1d-63c6fb9c4cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859375289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2859375289
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3030309272
Short name T706
Test name
Test status
Simulation time 21687162 ps
CPU time 0.7 seconds
Started Feb 04 02:35:43 PM PST 24
Finished Feb 04 02:35:56 PM PST 24
Peak memory 205256 kb
Host smart-4708ad95-6af3-41c3-bbde-ae8eb914100c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030309272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3030309272
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.119204220
Short name T971
Test name
Test status
Simulation time 4064891539 ps
CPU time 6.88 seconds
Started Feb 04 02:35:45 PM PST 24
Finished Feb 04 02:36:03 PM PST 24
Peak memory 219572 kb
Host smart-7b669be8-c9da-465c-8a27-b3861a009490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119204220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.119204220
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2237473514
Short name T639
Test name
Test status
Simulation time 21722143 ps
CPU time 0.78 seconds
Started Feb 04 02:35:41 PM PST 24
Finished Feb 04 02:35:54 PM PST 24
Peak memory 205116 kb
Host smart-b7de6114-08db-4bd9-9e4f-f3a2b57fd487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237473514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2237473514
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.4128171503
Short name T785
Test name
Test status
Simulation time 102706931348 ps
CPU time 127.29 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:38:04 PM PST 24
Peak memory 240516 kb
Host smart-b5a4c184-c1b4-4a00-a8ba-9606bcadb9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128171503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.4128171503
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.914125596
Short name T915
Test name
Test status
Simulation time 4825703955 ps
CPU time 91.07 seconds
Started Feb 04 02:35:37 PM PST 24
Finished Feb 04 02:37:20 PM PST 24
Peak memory 254432 kb
Host smart-47ffa460-00b1-441f-9460-82034a9332ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914125596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.914125596
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.37122630
Short name T911
Test name
Test status
Simulation time 1134611282 ps
CPU time 13.18 seconds
Started Feb 04 02:35:45 PM PST 24
Finished Feb 04 02:36:10 PM PST 24
Peak memory 229256 kb
Host smart-01c88d69-1f02-49da-bec1-465821ba2add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37122630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.37122630
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2418923377
Short name T507
Test name
Test status
Simulation time 127180180 ps
CPU time 3.01 seconds
Started Feb 04 02:35:44 PM PST 24
Finished Feb 04 02:35:59 PM PST 24
Peak memory 218548 kb
Host smart-54c36944-0a4b-42f5-98dc-f4aadaff5ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418923377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2418923377
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1638785534
Short name T436
Test name
Test status
Simulation time 1960433727 ps
CPU time 10.01 seconds
Started Feb 04 02:35:45 PM PST 24
Finished Feb 04 02:36:06 PM PST 24
Peak memory 224420 kb
Host smart-36082874-ed53-43e2-b821-319cf88fd677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638785534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1638785534
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.24591187
Short name T995
Test name
Test status
Simulation time 52371648 ps
CPU time 1.05 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:35:52 PM PST 24
Peak memory 217972 kb
Host smart-bf91bf7c-15e6-487d-bcf1-eb8b5a5f7313
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24591187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.24591187
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3117185380
Short name T610
Test name
Test status
Simulation time 8818165752 ps
CPU time 26.64 seconds
Started Feb 04 02:35:41 PM PST 24
Finished Feb 04 02:36:20 PM PST 24
Peak memory 233884 kb
Host smart-4d51861d-e547-42a0-8f6e-c95be38e5713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117185380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3117185380
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.733997060
Short name T1034
Test name
Test status
Simulation time 30072004395 ps
CPU time 21.46 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:36:18 PM PST 24
Peak memory 228684 kb
Host smart-828616a6-dfb3-4979-a715-df3bd315f307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733997060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.733997060
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.2826124552
Short name T966
Test name
Test status
Simulation time 18948846 ps
CPU time 0.81 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 216232 kb
Host smart-74af5659-544c-4de0-9979-0a52dd4f67f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826124552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.2826124552
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3496955636
Short name T1005
Test name
Test status
Simulation time 1026346766 ps
CPU time 5.18 seconds
Started Feb 04 02:35:41 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 222212 kb
Host smart-232f0da3-dd30-443a-bc41-20e269060c05
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3496955636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3496955636
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3371678970
Short name T658
Test name
Test status
Simulation time 65676338456 ps
CPU time 167.24 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:38:38 PM PST 24
Peak memory 272704 kb
Host smart-0e0283e9-0348-4ad6-ab9b-f608a66e61fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371678970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3371678970
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3184692242
Short name T843
Test name
Test status
Simulation time 4860668977 ps
CPU time 62.33 seconds
Started Feb 04 02:35:48 PM PST 24
Finished Feb 04 02:36:59 PM PST 24
Peak memory 216448 kb
Host smart-b3a38456-6578-4b73-8162-76303b7b8d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184692242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3184692242
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1003838144
Short name T689
Test name
Test status
Simulation time 5099636467 ps
CPU time 18.34 seconds
Started Feb 04 02:35:38 PM PST 24
Finished Feb 04 02:36:08 PM PST 24
Peak memory 216500 kb
Host smart-82b587fb-3b6e-4a88-81e3-ca2e8d435efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003838144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1003838144
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4112964548
Short name T902
Test name
Test status
Simulation time 455010639 ps
CPU time 5.48 seconds
Started Feb 04 02:35:40 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 216300 kb
Host smart-0c6d7346-c7d2-43b1-ad19-fb159acc562e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112964548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4112964548
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2673271167
Short name T19
Test name
Test status
Simulation time 338365088 ps
CPU time 0.9 seconds
Started Feb 04 02:35:36 PM PST 24
Finished Feb 04 02:35:48 PM PST 24
Peak memory 206456 kb
Host smart-c5255f03-8a15-41e4-a8ec-77a3188c43f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673271167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2673271167
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1669376325
Short name T630
Test name
Test status
Simulation time 2323199164 ps
CPU time 6.87 seconds
Started Feb 04 02:35:44 PM PST 24
Finished Feb 04 02:36:03 PM PST 24
Peak memory 226636 kb
Host smart-f946fe75-0e6f-47c5-b5ee-a3cf331781e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669376325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1669376325
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4083604937
Short name T546
Test name
Test status
Simulation time 47442407 ps
CPU time 0.71 seconds
Started Feb 04 02:35:54 PM PST 24
Finished Feb 04 02:36:00 PM PST 24
Peak memory 204900 kb
Host smart-6c2b5ac7-9327-4a99-a3b5-40d2ccb4bd5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083604937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4083604937
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1509242846
Short name T14
Test name
Test status
Simulation time 79803657 ps
CPU time 2.75 seconds
Started Feb 04 02:35:56 PM PST 24
Finished Feb 04 02:36:04 PM PST 24
Peak memory 231944 kb
Host smart-8791fee4-24bc-4ba7-be1d-e13839790e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509242846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1509242846
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2668001951
Short name T480
Test name
Test status
Simulation time 13620042 ps
CPU time 0.77 seconds
Started Feb 04 02:35:47 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 205160 kb
Host smart-3ceeab65-f837-458d-8d46-6b3ee1c53daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668001951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2668001951
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.533400221
Short name T612
Test name
Test status
Simulation time 12340808078 ps
CPU time 60.36 seconds
Started Feb 04 02:35:44 PM PST 24
Finished Feb 04 02:36:57 PM PST 24
Peak memory 257424 kb
Host smart-7da3b753-0c52-4c21-9fb8-da8331b55f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533400221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.533400221
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.793788078
Short name T518
Test name
Test status
Simulation time 26116022154 ps
CPU time 188.1 seconds
Started Feb 04 02:35:52 PM PST 24
Finished Feb 04 02:39:07 PM PST 24
Peak memory 249516 kb
Host smart-60581de1-48bc-4e39-b4d6-765cb600e01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793788078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.793788078
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2808993190
Short name T958
Test name
Test status
Simulation time 1822974291 ps
CPU time 19.1 seconds
Started Feb 04 02:35:43 PM PST 24
Finished Feb 04 02:36:15 PM PST 24
Peak memory 239104 kb
Host smart-2135ecb3-ea8e-45d7-86f4-fe6c1921ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808993190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2808993190
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2298511700
Short name T578
Test name
Test status
Simulation time 3735830078 ps
CPU time 19.98 seconds
Started Feb 04 02:35:55 PM PST 24
Finished Feb 04 02:36:20 PM PST 24
Peak memory 232800 kb
Host smart-244e0913-3875-49af-b239-f6305607042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298511700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2298511700
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2801912663
Short name T604
Test name
Test status
Simulation time 8394675666 ps
CPU time 12.9 seconds
Started Feb 04 02:35:55 PM PST 24
Finished Feb 04 02:36:13 PM PST 24
Peak memory 219952 kb
Host smart-1add838b-c22a-4572-a00c-3a622a594495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801912663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2801912663
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.897959530
Short name T937
Test name
Test status
Simulation time 2547108414 ps
CPU time 10.26 seconds
Started Feb 04 02:35:54 PM PST 24
Finished Feb 04 02:36:10 PM PST 24
Peak memory 236408 kb
Host smart-2a2c94c4-578f-4eef-ae58-6e15e323ea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897959530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.897959530
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.884366018
Short name T1096
Test name
Test status
Simulation time 25594258 ps
CPU time 1.11 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 216592 kb
Host smart-40f54b25-3b81-492e-856d-6bf10eaa3795
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884366018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.884366018
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1173754833
Short name T824
Test name
Test status
Simulation time 1486544160 ps
CPU time 4.02 seconds
Started Feb 04 02:35:56 PM PST 24
Finished Feb 04 02:36:05 PM PST 24
Peak memory 216888 kb
Host smart-2e86560a-f081-4d8d-988d-3cfcf71a992c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173754833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1173754833
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.830017319
Short name T1113
Test name
Test status
Simulation time 7866406898 ps
CPU time 19.43 seconds
Started Feb 04 02:35:47 PM PST 24
Finished Feb 04 02:36:16 PM PST 24
Peak memory 234252 kb
Host smart-7ae62e9e-9db8-4350-96fa-e945974c57d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830017319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.830017319
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.3348588852
Short name T497
Test name
Test status
Simulation time 17430875 ps
CPU time 0.74 seconds
Started Feb 04 02:35:51 PM PST 24
Finished Feb 04 02:35:59 PM PST 24
Peak memory 216288 kb
Host smart-414c9c5b-35fa-4957-ab9b-327037b2ee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348588852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.3348588852
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1697117973
Short name T308
Test name
Test status
Simulation time 1216725149 ps
CPU time 6.66 seconds
Started Feb 04 02:35:47 PM PST 24
Finished Feb 04 02:36:03 PM PST 24
Peak memory 222476 kb
Host smart-8d79b0ea-6e3a-449b-8d7f-e0d538a2563b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1697117973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1697117973
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3501150588
Short name T149
Test name
Test status
Simulation time 18353740449 ps
CPU time 157.42 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:38:34 PM PST 24
Peak memory 250092 kb
Host smart-8605b46b-1b59-4709-b9f3-30ee13582189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501150588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3501150588
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1826009544
Short name T850
Test name
Test status
Simulation time 10201782151 ps
CPU time 42.66 seconds
Started Feb 04 02:35:48 PM PST 24
Finished Feb 04 02:36:39 PM PST 24
Peak memory 216436 kb
Host smart-6340a7d1-30f8-4042-8db4-8288078790db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826009544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1826009544
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2092148112
Short name T698
Test name
Test status
Simulation time 4636750359 ps
CPU time 4.61 seconds
Started Feb 04 02:35:47 PM PST 24
Finished Feb 04 02:36:01 PM PST 24
Peak memory 216272 kb
Host smart-3c1ea8c7-0fb8-4bdf-a7cb-a8ef16057b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092148112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2092148112
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3627226704
Short name T939
Test name
Test status
Simulation time 209735148 ps
CPU time 3.09 seconds
Started Feb 04 02:35:56 PM PST 24
Finished Feb 04 02:36:04 PM PST 24
Peak memory 216340 kb
Host smart-7d0e06b1-43a6-4f19-a871-327dccd5aac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627226704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3627226704
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1820328017
Short name T1088
Test name
Test status
Simulation time 116198312 ps
CPU time 1.05 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 206460 kb
Host smart-deb437e9-c042-4480-b96a-345528c1a89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820328017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1820328017
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.696824848
Short name T549
Test name
Test status
Simulation time 467282913 ps
CPU time 6.13 seconds
Started Feb 04 02:35:52 PM PST 24
Finished Feb 04 02:36:05 PM PST 24
Peak memory 233568 kb
Host smart-a71922eb-1c22-472b-91dc-ec415d73e8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696824848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.696824848
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1090476687
Short name T448
Test name
Test status
Simulation time 34540338 ps
CPU time 0.73 seconds
Started Feb 04 02:35:53 PM PST 24
Finished Feb 04 02:35:59 PM PST 24
Peak memory 205280 kb
Host smart-9841cb4d-2980-4d7c-a102-d017032ec85a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090476687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1090476687
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3020620566
Short name T626
Test name
Test status
Simulation time 4509303233 ps
CPU time 6.17 seconds
Started Feb 04 02:35:52 PM PST 24
Finished Feb 04 02:36:05 PM PST 24
Peak memory 233764 kb
Host smart-3574d75c-e1a3-49ce-a1fa-ac6ed3b9f05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020620566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3020620566
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1735933976
Short name T645
Test name
Test status
Simulation time 44812663 ps
CPU time 0.76 seconds
Started Feb 04 02:35:46 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 205084 kb
Host smart-d4aefc27-242b-424c-bc54-a9a2b903f672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735933976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1735933976
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1265613605
Short name T1060
Test name
Test status
Simulation time 78868435578 ps
CPU time 221.19 seconds
Started Feb 04 02:35:55 PM PST 24
Finished Feb 04 02:39:42 PM PST 24
Peak memory 249172 kb
Host smart-50c9f9af-5eaa-416c-9076-e7203e36fa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265613605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1265613605
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.522080263
Short name T876
Test name
Test status
Simulation time 1212875778 ps
CPU time 12.48 seconds
Started Feb 04 02:35:56 PM PST 24
Finished Feb 04 02:36:13 PM PST 24
Peak memory 221720 kb
Host smart-c230baf0-586c-44e3-9658-6356c580e0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522080263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.522080263
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3831524360
Short name T500
Test name
Test status
Simulation time 17689087587 ps
CPU time 24.1 seconds
Started Feb 04 02:35:58 PM PST 24
Finished Feb 04 02:36:26 PM PST 24
Peak memory 251788 kb
Host smart-a6909169-ed54-471a-9157-ef338ee1337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831524360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3831524360
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.265346344
Short name T718
Test name
Test status
Simulation time 356273088 ps
CPU time 3.7 seconds
Started Feb 04 02:35:56 PM PST 24
Finished Feb 04 02:36:05 PM PST 24
Peak memory 233020 kb
Host smart-e1f94706-29be-47f5-8285-cd0649b54bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265346344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.265346344
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3582704886
Short name T904
Test name
Test status
Simulation time 1293493584 ps
CPU time 4.86 seconds
Started Feb 04 02:35:54 PM PST 24
Finished Feb 04 02:36:04 PM PST 24
Peak memory 233260 kb
Host smart-3b4b67f7-321e-431a-99e7-c06879039773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582704886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3582704886
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2583773612
Short name T725
Test name
Test status
Simulation time 95797715 ps
CPU time 0.98 seconds
Started Feb 04 02:35:56 PM PST 24
Finished Feb 04 02:36:02 PM PST 24
Peak memory 215740 kb
Host smart-e84c43ab-c626-44b8-9c1a-eef1049b6ca2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583773612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2583773612
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1431217078
Short name T547
Test name
Test status
Simulation time 5251366239 ps
CPU time 14.94 seconds
Started Feb 04 02:35:54 PM PST 24
Finished Feb 04 02:36:14 PM PST 24
Peak memory 218068 kb
Host smart-2bcb9ca9-41a9-464f-bbdb-eff55513038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431217078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1431217078
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1209759068
Short name T856
Test name
Test status
Simulation time 588217259 ps
CPU time 2.67 seconds
Started Feb 04 02:35:52 PM PST 24
Finished Feb 04 02:36:01 PM PST 24
Peak memory 216892 kb
Host smart-a2844533-8cf6-4bf0-babd-06ed424a0446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209759068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1209759068
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.4226820558
Short name T635
Test name
Test status
Simulation time 30051334 ps
CPU time 0.71 seconds
Started Feb 04 02:35:47 PM PST 24
Finished Feb 04 02:35:57 PM PST 24
Peak memory 216284 kb
Host smart-22ea9098-1c1f-42f7-9ec6-a1d7a9acc6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226820558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.4226820558
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1822278722
Short name T1108
Test name
Test status
Simulation time 1135394743 ps
CPU time 5.83 seconds
Started Feb 04 02:35:56 PM PST 24
Finished Feb 04 02:36:07 PM PST 24
Peak memory 218928 kb
Host smart-afe81bc2-7e42-44c3-81d9-e9a311950392
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1822278722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1822278722
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2295939640
Short name T1050
Test name
Test status
Simulation time 79127528577 ps
CPU time 322.46 seconds
Started Feb 04 02:35:53 PM PST 24
Finished Feb 04 02:41:21 PM PST 24
Peak memory 282068 kb
Host smart-79412898-ab62-4c27-8920-ea5b4683036d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295939640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2295939640
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2258549785
Short name T719
Test name
Test status
Simulation time 17725162791 ps
CPU time 40.84 seconds
Started Feb 04 02:35:52 PM PST 24
Finished Feb 04 02:36:40 PM PST 24
Peak memory 216472 kb
Host smart-e7dee4f2-2ab0-4c87-8393-8ee75a333e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258549785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2258549785
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3683861298
Short name T472
Test name
Test status
Simulation time 5666432755 ps
CPU time 18.17 seconds
Started Feb 04 02:35:54 PM PST 24
Finished Feb 04 02:36:17 PM PST 24
Peak memory 216448 kb
Host smart-eac18b1c-aeb8-43f2-a7e0-a2f1eae1c7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683861298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3683861298
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1398896818
Short name T473
Test name
Test status
Simulation time 708134699 ps
CPU time 3.08 seconds
Started Feb 04 02:35:47 PM PST 24
Finished Feb 04 02:35:59 PM PST 24
Peak memory 216468 kb
Host smart-27238827-133e-4b0b-a570-0938da2e1393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398896818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1398896818
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.463146749
Short name T704
Test name
Test status
Simulation time 88703381 ps
CPU time 0.94 seconds
Started Feb 04 02:35:56 PM PST 24
Finished Feb 04 02:36:02 PM PST 24
Peak memory 206472 kb
Host smart-388a9eaa-c742-4f49-a4f0-cf5be376d3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463146749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.463146749
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.604699979
Short name T615
Test name
Test status
Simulation time 7527169031 ps
CPU time 22.37 seconds
Started Feb 04 02:35:55 PM PST 24
Finished Feb 04 02:36:22 PM PST 24
Peak memory 240924 kb
Host smart-51100172-fbf0-45c9-a617-7dbca0bc2aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604699979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.604699979
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4200500580
Short name T474
Test name
Test status
Simulation time 15576148 ps
CPU time 0.73 seconds
Started Feb 04 02:34:10 PM PST 24
Finished Feb 04 02:34:17 PM PST 24
Peak memory 204968 kb
Host smart-dcfc4633-f1cd-45a0-b9a0-ecddc54feee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200500580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
200500580
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1447782166
Short name T199
Test name
Test status
Simulation time 294578096 ps
CPU time 3.43 seconds
Started Feb 04 02:34:07 PM PST 24
Finished Feb 04 02:34:20 PM PST 24
Peak memory 233784 kb
Host smart-97d8ce02-4799-415c-b0a9-a22ef4f2d397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447782166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1447782166
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3242826671
Short name T525
Test name
Test status
Simulation time 14834685 ps
CPU time 0.79 seconds
Started Feb 04 02:34:05 PM PST 24
Finished Feb 04 02:34:10 PM PST 24
Peak memory 205188 kb
Host smart-5ea6155e-2758-4832-89a9-7e2366281e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242826671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3242826671
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2683633351
Short name T246
Test name
Test status
Simulation time 40383612806 ps
CPU time 257.39 seconds
Started Feb 04 02:34:06 PM PST 24
Finished Feb 04 02:38:34 PM PST 24
Peak memory 265588 kb
Host smart-a7c30e20-bb9e-48a3-ad29-656fd675e0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683633351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2683633351
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3286537110
Short name T177
Test name
Test status
Simulation time 25520526043 ps
CPU time 67.05 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:35:24 PM PST 24
Peak memory 256568 kb
Host smart-7fca9d5c-9029-420e-9708-13b1bd583ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286537110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3286537110
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.151703378
Short name T261
Test name
Test status
Simulation time 420114956906 ps
CPU time 688.9 seconds
Started Feb 04 02:34:10 PM PST 24
Finished Feb 04 02:45:46 PM PST 24
Peak memory 267852 kb
Host smart-9ec8a3e6-c5e3-4119-af1f-b87f60e358d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151703378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
151703378
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3065511779
Short name T755
Test name
Test status
Simulation time 19564609835 ps
CPU time 46.36 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:35:03 PM PST 24
Peak memory 233836 kb
Host smart-ae7ea6a9-ea79-46f6-82e5-9523b78b183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065511779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3065511779
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1499397196
Short name T872
Test name
Test status
Simulation time 11719412200 ps
CPU time 9.58 seconds
Started Feb 04 02:34:05 PM PST 24
Finished Feb 04 02:34:19 PM PST 24
Peak memory 224548 kb
Host smart-53d8e6a1-9bb9-40ab-9936-5f59480b7c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499397196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1499397196
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2248210773
Short name T8
Test name
Test status
Simulation time 249160489 ps
CPU time 4.32 seconds
Started Feb 04 02:34:01 PM PST 24
Finished Feb 04 02:34:07 PM PST 24
Peak memory 224452 kb
Host smart-fd3a32dd-4224-42ec-ac0b-21deaa30b071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248210773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2248210773
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3971403012
Short name T944
Test name
Test status
Simulation time 32344230 ps
CPU time 1.02 seconds
Started Feb 04 02:34:07 PM PST 24
Finished Feb 04 02:34:17 PM PST 24
Peak memory 216720 kb
Host smart-bb1dbe09-79a2-4935-a425-084325d97e49
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971403012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3971403012
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3396094724
Short name T165
Test name
Test status
Simulation time 2350242066 ps
CPU time 9.15 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:34:26 PM PST 24
Peak memory 240140 kb
Host smart-8e6f52d8-44d4-4b65-b50e-5d6c386865cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396094724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3396094724
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2021059246
Short name T185
Test name
Test status
Simulation time 6012741567 ps
CPU time 10.24 seconds
Started Feb 04 02:34:03 PM PST 24
Finished Feb 04 02:34:19 PM PST 24
Peak memory 218092 kb
Host smart-3d213858-5ee9-4300-bc4d-f3fec0d8fc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021059246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2021059246
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.3311043271
Short name T54
Test name
Test status
Simulation time 85937016 ps
CPU time 0.72 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:34:17 PM PST 24
Peak memory 216336 kb
Host smart-dab57122-05e2-4bf8-9f8e-aced854c17a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311043271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.3311043271
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1156199658
Short name T638
Test name
Test status
Simulation time 647264134 ps
CPU time 4.06 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:34:21 PM PST 24
Peak memory 222148 kb
Host smart-e54d6092-d78e-497f-b331-a39609c8439d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1156199658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1156199658
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1909285776
Short name T253
Test name
Test status
Simulation time 3606217399 ps
CPU time 56.81 seconds
Started Feb 04 02:34:07 PM PST 24
Finished Feb 04 02:35:13 PM PST 24
Peak memory 256100 kb
Host smart-e23b33f4-a60d-4b8e-8af9-9d4d680448e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909285776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1909285776
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3362670796
Short name T1095
Test name
Test status
Simulation time 9065917822 ps
CPU time 25.27 seconds
Started Feb 04 02:34:04 PM PST 24
Finished Feb 04 02:34:34 PM PST 24
Peak memory 216480 kb
Host smart-58cb9235-3710-49a7-872c-ea25e68c3595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362670796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3362670796
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3922177393
Short name T709
Test name
Test status
Simulation time 20757539991 ps
CPU time 17.53 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:34:34 PM PST 24
Peak memory 216448 kb
Host smart-7c138625-d7c1-4691-b26d-ff939ae7f1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922177393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3922177393
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1156113077
Short name T23
Test name
Test status
Simulation time 581472652 ps
CPU time 1.47 seconds
Started Feb 04 02:34:06 PM PST 24
Finished Feb 04 02:34:17 PM PST 24
Peak memory 207996 kb
Host smart-2e7af6dd-9cc4-4197-bc9a-00cd75582eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156113077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1156113077
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1694541711
Short name T764
Test name
Test status
Simulation time 155224671 ps
CPU time 1.16 seconds
Started Feb 04 02:34:10 PM PST 24
Finished Feb 04 02:34:21 PM PST 24
Peak memory 206448 kb
Host smart-3ec09f85-a829-4791-b89c-0e05ade455c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694541711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1694541711
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.4180136136
Short name T190
Test name
Test status
Simulation time 3480544079 ps
CPU time 9 seconds
Started Feb 04 02:34:05 PM PST 24
Finished Feb 04 02:34:19 PM PST 24
Peak memory 217640 kb
Host smart-ada58a78-b7b3-4a25-862b-a1e6f3c44db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180136136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4180136136
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2492789756
Short name T46
Test name
Test status
Simulation time 14308292 ps
CPU time 0.72 seconds
Started Feb 04 02:36:19 PM PST 24
Finished Feb 04 02:36:22 PM PST 24
Peak memory 204936 kb
Host smart-52cbe78e-bfd5-4e3d-9fdf-73a62e710f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492789756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2492789756
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4258725691
Short name T1024
Test name
Test status
Simulation time 4374309556 ps
CPU time 4.86 seconds
Started Feb 04 02:35:53 PM PST 24
Finished Feb 04 02:36:04 PM PST 24
Peak memory 218400 kb
Host smart-f0598fc1-0dad-4e10-b968-642322d85888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258725691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4258725691
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1790838219
Short name T438
Test name
Test status
Simulation time 22337540 ps
CPU time 0.79 seconds
Started Feb 04 02:35:57 PM PST 24
Finished Feb 04 02:36:02 PM PST 24
Peak memory 205120 kb
Host smart-8194b6ed-dfe3-4272-9762-5fa120a96380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790838219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1790838219
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1788397796
Short name T195
Test name
Test status
Simulation time 7364601688 ps
CPU time 73.58 seconds
Started Feb 04 02:36:07 PM PST 24
Finished Feb 04 02:37:24 PM PST 24
Peak memory 253588 kb
Host smart-72e4fa99-a013-4653-a8ad-f030ac7fab5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788397796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1788397796
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3188269272
Short name T182
Test name
Test status
Simulation time 136308291705 ps
CPU time 254.43 seconds
Started Feb 04 02:36:23 PM PST 24
Finished Feb 04 02:40:39 PM PST 24
Peak memory 251232 kb
Host smart-a3d03ca1-18ad-4a91-acfb-9746f0dcc13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188269272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3188269272
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2807293925
Short name T271
Test name
Test status
Simulation time 80709244531 ps
CPU time 284.9 seconds
Started Feb 04 02:36:15 PM PST 24
Finished Feb 04 02:41:06 PM PST 24
Peak memory 250616 kb
Host smart-78beecee-81e1-4756-87ea-9dc01cf5efeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807293925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2807293925
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1701035042
Short name T123
Test name
Test status
Simulation time 6978470429 ps
CPU time 22.38 seconds
Started Feb 04 02:36:14 PM PST 24
Finished Feb 04 02:36:44 PM PST 24
Peak memory 232124 kb
Host smart-7772c99f-bd9c-48eb-afb3-b040c89fb1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701035042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1701035042
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4136001377
Short name T1009
Test name
Test status
Simulation time 100036387 ps
CPU time 2.64 seconds
Started Feb 04 02:35:54 PM PST 24
Finished Feb 04 02:36:02 PM PST 24
Peak memory 233456 kb
Host smart-51537ce9-9a64-4dac-9087-14d552962fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136001377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4136001377
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4262719930
Short name T1097
Test name
Test status
Simulation time 28971709584 ps
CPU time 23.27 seconds
Started Feb 04 02:35:54 PM PST 24
Finished Feb 04 02:36:23 PM PST 24
Peak memory 232556 kb
Host smart-db6ef4c0-71dc-4f75-9739-20930ff03f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262719930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4262719930
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.4256476275
Short name T32
Test name
Test status
Simulation time 3999606664 ps
CPU time 11.97 seconds
Started Feb 04 02:35:58 PM PST 24
Finished Feb 04 02:36:14 PM PST 24
Peak memory 224640 kb
Host smart-cdd46dac-a6fe-4f8e-a948-aaa3d5fd502a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256476275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.4256476275
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2358019050
Short name T909
Test name
Test status
Simulation time 1148005634 ps
CPU time 3.08 seconds
Started Feb 04 02:35:59 PM PST 24
Finished Feb 04 02:36:06 PM PST 24
Peak memory 224544 kb
Host smart-67dcc476-d49d-47ca-be2d-0da381ff89ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358019050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2358019050
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2764438921
Short name T1038
Test name
Test status
Simulation time 1431086632 ps
CPU time 5.31 seconds
Started Feb 04 02:36:15 PM PST 24
Finished Feb 04 02:36:27 PM PST 24
Peak memory 222576 kb
Host smart-ba015162-92ab-467a-915f-03318307d177
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2764438921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2764438921
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.524370669
Short name T766
Test name
Test status
Simulation time 26090383693 ps
CPU time 245.78 seconds
Started Feb 04 02:36:19 PM PST 24
Finished Feb 04 02:40:27 PM PST 24
Peak memory 255096 kb
Host smart-009f3d39-8c86-4b9b-ae85-935b858387ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524370669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.524370669
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3315114369
Short name T611
Test name
Test status
Simulation time 1350911469 ps
CPU time 20.23 seconds
Started Feb 04 02:35:55 PM PST 24
Finished Feb 04 02:36:21 PM PST 24
Peak memory 216436 kb
Host smart-2acaf0e7-df27-4795-ba92-a4f2417491d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315114369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3315114369
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3722509750
Short name T1111
Test name
Test status
Simulation time 4476424191 ps
CPU time 4.37 seconds
Started Feb 04 02:35:53 PM PST 24
Finished Feb 04 02:36:03 PM PST 24
Peak memory 216464 kb
Host smart-d96b0804-d7a9-480c-b252-3493c22ffa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722509750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3722509750
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1499656706
Short name T495
Test name
Test status
Simulation time 30352963 ps
CPU time 1.18 seconds
Started Feb 04 02:35:52 PM PST 24
Finished Feb 04 02:36:00 PM PST 24
Peak memory 207728 kb
Host smart-87ecfc8a-5839-49f5-8733-73e276a11b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499656706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1499656706
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1606480610
Short name T466
Test name
Test status
Simulation time 141086824 ps
CPU time 0.88 seconds
Started Feb 04 02:35:55 PM PST 24
Finished Feb 04 02:36:01 PM PST 24
Peak memory 205732 kb
Host smart-ca536ee5-471f-4dfc-8b54-5f8e0062c084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606480610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1606480610
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1307878036
Short name T717
Test name
Test status
Simulation time 1557150936 ps
CPU time 7.54 seconds
Started Feb 04 02:35:55 PM PST 24
Finished Feb 04 02:36:08 PM PST 24
Peak memory 217396 kb
Host smart-723c47bf-7b41-42a0-94e8-8c29fa1c52fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307878036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1307878036
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2368371350
Short name T307
Test name
Test status
Simulation time 38284512 ps
CPU time 0.72 seconds
Started Feb 04 02:36:07 PM PST 24
Finished Feb 04 02:36:11 PM PST 24
Peak memory 204400 kb
Host smart-4d9a01b8-fe7e-43cc-9d75-a335f4e3d5f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368371350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2368371350
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2909195972
Short name T836
Test name
Test status
Simulation time 297762127 ps
CPU time 3.31 seconds
Started Feb 04 02:36:20 PM PST 24
Finished Feb 04 02:36:26 PM PST 24
Peak memory 233596 kb
Host smart-a1991cd2-95c6-4b27-86e5-6112b1f3ea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909195972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2909195972
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.288964491
Short name T791
Test name
Test status
Simulation time 20291125 ps
CPU time 0.79 seconds
Started Feb 04 02:36:13 PM PST 24
Finished Feb 04 02:36:22 PM PST 24
Peak memory 206184 kb
Host smart-e876f942-8e14-4f59-97a4-dd77693ae263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288964491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.288964491
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1042124343
Short name T577
Test name
Test status
Simulation time 116655132379 ps
CPU time 65.18 seconds
Started Feb 04 02:36:15 PM PST 24
Finished Feb 04 02:37:27 PM PST 24
Peak memory 240956 kb
Host smart-69028de2-a6aa-4a3b-a73d-fbb58ff01f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042124343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1042124343
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3401093098
Short name T693
Test name
Test status
Simulation time 64468127400 ps
CPU time 102.16 seconds
Started Feb 04 02:36:15 PM PST 24
Finished Feb 04 02:38:03 PM PST 24
Peak memory 249216 kb
Host smart-50965b17-903a-4b62-aa75-bc9e1a40e456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401093098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3401093098
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3942678249
Short name T274
Test name
Test status
Simulation time 1203467121 ps
CPU time 15.65 seconds
Started Feb 04 02:36:05 PM PST 24
Finished Feb 04 02:36:23 PM PST 24
Peak memory 252324 kb
Host smart-0fc12eda-165f-4f01-b528-4438c381550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942678249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3942678249
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1435603192
Short name T681
Test name
Test status
Simulation time 1119547048 ps
CPU time 7.86 seconds
Started Feb 04 02:36:14 PM PST 24
Finished Feb 04 02:36:29 PM PST 24
Peak memory 237116 kb
Host smart-4a108e64-a95c-4b43-9c92-aa161d816c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435603192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1435603192
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.742790393
Short name T548
Test name
Test status
Simulation time 3248327146 ps
CPU time 6.09 seconds
Started Feb 04 02:36:14 PM PST 24
Finished Feb 04 02:36:27 PM PST 24
Peak memory 235188 kb
Host smart-ae6fe6a9-702a-4d62-92de-5d9b488dc386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742790393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.742790393
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3917091240
Short name T1110
Test name
Test status
Simulation time 520172600 ps
CPU time 3.59 seconds
Started Feb 04 02:36:15 PM PST 24
Finished Feb 04 02:36:25 PM PST 24
Peak memory 216848 kb
Host smart-063497f1-a6eb-4221-b7ea-d61cda8d1b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917091240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3917091240
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.333400762
Short name T690
Test name
Test status
Simulation time 1873830902 ps
CPU time 7.13 seconds
Started Feb 04 02:36:22 PM PST 24
Finished Feb 04 02:36:30 PM PST 24
Peak memory 232772 kb
Host smart-9bff24ec-3482-4a43-9868-135583707adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333400762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.333400762
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.4189195569
Short name T1087
Test name
Test status
Simulation time 1187782748 ps
CPU time 6.36 seconds
Started Feb 04 02:36:20 PM PST 24
Finished Feb 04 02:36:29 PM PST 24
Peak memory 222708 kb
Host smart-5a661550-457f-4bd9-9ada-498892c0a130
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4189195569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.4189195569
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1056823885
Short name T738
Test name
Test status
Simulation time 11802241903 ps
CPU time 137.19 seconds
Started Feb 04 02:36:23 PM PST 24
Finished Feb 04 02:38:42 PM PST 24
Peak memory 271964 kb
Host smart-11ded608-4344-49b7-b7dc-dbde3433b19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056823885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1056823885
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1804847237
Short name T278
Test name
Test status
Simulation time 1103584374 ps
CPU time 22.56 seconds
Started Feb 04 02:36:15 PM PST 24
Finished Feb 04 02:36:44 PM PST 24
Peak memory 216400 kb
Host smart-5748dcf4-6dca-4ab2-bce8-4c343ca74c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804847237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1804847237
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1324831092
Short name T1041
Test name
Test status
Simulation time 4387490925 ps
CPU time 4.47 seconds
Started Feb 04 02:36:11 PM PST 24
Finished Feb 04 02:36:17 PM PST 24
Peak memory 216424 kb
Host smart-90aebb71-b7ca-4f5a-aed2-90ca4a56562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324831092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1324831092
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1048372227
Short name T510
Test name
Test status
Simulation time 25808635 ps
CPU time 0.99 seconds
Started Feb 04 02:36:13 PM PST 24
Finished Feb 04 02:36:21 PM PST 24
Peak memory 206628 kb
Host smart-4b245616-4d94-4fd4-a7c7-8e67f7cc6070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048372227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1048372227
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1625154478
Short name T679
Test name
Test status
Simulation time 52005406 ps
CPU time 0.75 seconds
Started Feb 04 02:36:16 PM PST 24
Finished Feb 04 02:36:22 PM PST 24
Peak memory 205424 kb
Host smart-21b853aa-7647-44fa-9168-516cd26452a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625154478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1625154478
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2502443608
Short name T728
Test name
Test status
Simulation time 2608111044 ps
CPU time 9.81 seconds
Started Feb 04 02:36:14 PM PST 24
Finished Feb 04 02:36:31 PM PST 24
Peak memory 236680 kb
Host smart-20253e3a-f465-481e-9ade-2f51ec7b9d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502443608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2502443608
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3064462846
Short name T779
Test name
Test status
Simulation time 12103243 ps
CPU time 0.69 seconds
Started Feb 04 02:36:11 PM PST 24
Finished Feb 04 02:36:14 PM PST 24
Peak memory 204888 kb
Host smart-b1835465-5038-459e-8392-9bc2c66042d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064462846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3064462846
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1551611995
Short name T606
Test name
Test status
Simulation time 891283192 ps
CPU time 3.54 seconds
Started Feb 04 02:36:14 PM PST 24
Finished Feb 04 02:36:25 PM PST 24
Peak memory 218996 kb
Host smart-36b69cf6-aad6-4236-a057-4caec1bfbe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551611995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1551611995
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2240461743
Short name T853
Test name
Test status
Simulation time 62497661 ps
CPU time 0.75 seconds
Started Feb 04 02:36:14 PM PST 24
Finished Feb 04 02:36:22 PM PST 24
Peak memory 205104 kb
Host smart-bca6f023-8b53-403a-ad69-1cb2f470520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240461743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2240461743
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.78113811
Short name T260
Test name
Test status
Simulation time 672313815278 ps
CPU time 255.77 seconds
Started Feb 04 02:36:15 PM PST 24
Finished Feb 04 02:40:37 PM PST 24
Peak memory 257384 kb
Host smart-09d8e6f5-8cf4-46a2-8c60-c7bee72a8ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78113811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.78113811
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.688950818
Short name T730
Test name
Test status
Simulation time 7773904046 ps
CPU time 90 seconds
Started Feb 04 02:36:14 PM PST 24
Finished Feb 04 02:37:51 PM PST 24
Peak memory 249572 kb
Host smart-7a40b6be-2da2-4ebd-83e2-b7a7402f7778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688950818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.688950818
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3968354522
Short name T993
Test name
Test status
Simulation time 2543569831 ps
CPU time 15.45 seconds
Started Feb 04 02:36:13 PM PST 24
Finished Feb 04 02:36:35 PM PST 24
Peak memory 250840 kb
Host smart-7bcd00aa-c035-4de8-854e-1bbc091e224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968354522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3968354522
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1053169518
Short name T787
Test name
Test status
Simulation time 13458851489 ps
CPU time 8.4 seconds
Started Feb 04 02:36:10 PM PST 24
Finished Feb 04 02:36:21 PM PST 24
Peak memory 219224 kb
Host smart-a9de249b-b17a-4036-b829-e127bd5ef3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053169518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1053169518
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4031812896
Short name T883
Test name
Test status
Simulation time 7065656412 ps
CPU time 7.84 seconds
Started Feb 04 02:36:07 PM PST 24
Finished Feb 04 02:36:18 PM PST 24
Peak memory 233844 kb
Host smart-f9d8a84e-756e-491f-9895-9340f671df47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031812896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4031812896
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3395756107
Short name T636
Test name
Test status
Simulation time 1440740671 ps
CPU time 7.16 seconds
Started Feb 04 02:36:13 PM PST 24
Finished Feb 04 02:36:27 PM PST 24
Peak memory 233456 kb
Host smart-71871742-8756-460f-9c42-ca999b392ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395756107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3395756107
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4038177037
Short name T967
Test name
Test status
Simulation time 31507939752 ps
CPU time 25.71 seconds
Started Feb 04 02:36:14 PM PST 24
Finished Feb 04 02:36:47 PM PST 24
Peak memory 235804 kb
Host smart-2fcdb10b-b422-44d6-adde-8472e539fd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038177037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4038177037
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3901979583
Short name T451
Test name
Test status
Simulation time 362227640 ps
CPU time 3.74 seconds
Started Feb 04 02:36:24 PM PST 24
Finished Feb 04 02:36:29 PM PST 24
Peak memory 217336 kb
Host smart-e7e9da63-a53c-4e0a-a776-8998370f73f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3901979583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3901979583
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3342315565
Short name T187
Test name
Test status
Simulation time 37781104186 ps
CPU time 209.14 seconds
Started Feb 04 02:36:14 PM PST 24
Finished Feb 04 02:39:50 PM PST 24
Peak memory 282000 kb
Host smart-d05f0f0d-64ff-4e8d-8ef0-adc6bcc0bb17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342315565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3342315565
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.503175889
Short name T602
Test name
Test status
Simulation time 4725730453 ps
CPU time 61.87 seconds
Started Feb 04 02:36:17 PM PST 24
Finished Feb 04 02:37:23 PM PST 24
Peak memory 216416 kb
Host smart-f6a3fe56-4ed9-4a71-8596-9846d27e123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503175889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.503175889
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3845679580
Short name T754
Test name
Test status
Simulation time 3517033458 ps
CPU time 10.2 seconds
Started Feb 04 02:36:23 PM PST 24
Finished Feb 04 02:36:35 PM PST 24
Peak memory 217172 kb
Host smart-f08f0de7-a2bf-4a63-a41a-854ba185a903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845679580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3845679580
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1488588969
Short name T669
Test name
Test status
Simulation time 96507985 ps
CPU time 0.99 seconds
Started Feb 04 02:36:12 PM PST 24
Finished Feb 04 02:36:20 PM PST 24
Peak memory 207940 kb
Host smart-d2c111c7-9e2f-46d6-bc2a-e23452f953ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488588969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1488588969
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2447023674
Short name T601
Test name
Test status
Simulation time 74968333 ps
CPU time 0.89 seconds
Started Feb 04 02:36:13 PM PST 24
Finished Feb 04 02:36:21 PM PST 24
Peak memory 205408 kb
Host smart-65714b15-bf58-4b4a-8016-226adb17c28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447023674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2447023674
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.242244646
Short name T942
Test name
Test status
Simulation time 12737706924 ps
CPU time 14.67 seconds
Started Feb 04 02:36:11 PM PST 24
Finished Feb 04 02:36:27 PM PST 24
Peak memory 234336 kb
Host smart-150f1e3a-2587-4596-b969-f38c2dcb81de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242244646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.242244646
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2885796983
Short name T761
Test name
Test status
Simulation time 12856726 ps
CPU time 0.74 seconds
Started Feb 04 02:36:24 PM PST 24
Finished Feb 04 02:36:26 PM PST 24
Peak memory 204396 kb
Host smart-3207b326-ca5c-40f9-8dd6-50b26a6e9736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885796983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2885796983
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1842974771
Short name T776
Test name
Test status
Simulation time 232143065 ps
CPU time 2.67 seconds
Started Feb 04 02:36:28 PM PST 24
Finished Feb 04 02:36:32 PM PST 24
Peak memory 233556 kb
Host smart-c999a318-40b6-4dd1-89c2-156b42f5b35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842974771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1842974771
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4181088994
Short name T777
Test name
Test status
Simulation time 22850587 ps
CPU time 0.8 seconds
Started Feb 04 02:36:12 PM PST 24
Finished Feb 04 02:36:14 PM PST 24
Peak memory 206152 kb
Host smart-952d6a7f-eba6-4173-b7fc-2a390291d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181088994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4181088994
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1074170962
Short name T145
Test name
Test status
Simulation time 17135628369 ps
CPU time 62.92 seconds
Started Feb 04 02:36:27 PM PST 24
Finished Feb 04 02:37:31 PM PST 24
Peak memory 253440 kb
Host smart-0f088b41-09cf-4cc1-8b6f-e042aa7e0c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074170962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1074170962
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2927475104
Short name T908
Test name
Test status
Simulation time 100068914123 ps
CPU time 181.78 seconds
Started Feb 04 02:36:23 PM PST 24
Finished Feb 04 02:39:27 PM PST 24
Peak memory 236380 kb
Host smart-f99da3ad-7fe3-4922-af54-14031186b16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927475104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2927475104
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2205677897
Short name T251
Test name
Test status
Simulation time 13258032400 ps
CPU time 155.99 seconds
Started Feb 04 02:36:31 PM PST 24
Finished Feb 04 02:39:11 PM PST 24
Peak memory 252456 kb
Host smart-34ad5cd7-ef4e-4821-b56e-83910a506b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205677897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2205677897
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1931542035
Short name T1018
Test name
Test status
Simulation time 340567072 ps
CPU time 7.55 seconds
Started Feb 04 02:36:28 PM PST 24
Finished Feb 04 02:36:37 PM PST 24
Peak memory 233484 kb
Host smart-c42b8705-0112-4131-a15c-268f166fdda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931542035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1931542035
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1389239543
Short name T571
Test name
Test status
Simulation time 6196956005 ps
CPU time 7.98 seconds
Started Feb 04 02:36:28 PM PST 24
Finished Feb 04 02:36:37 PM PST 24
Peak memory 233096 kb
Host smart-6e4019bc-662c-4210-90e2-9a636b92ce3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389239543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1389239543
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.711853457
Short name T984
Test name
Test status
Simulation time 21577857421 ps
CPU time 65.02 seconds
Started Feb 04 02:36:39 PM PST 24
Finished Feb 04 02:37:48 PM PST 24
Peak memory 232812 kb
Host smart-11bcb63c-2d47-416b-addd-18e5c0c2ae5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711853457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.711853457
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2585376442
Short name T865
Test name
Test status
Simulation time 1699969177 ps
CPU time 6.05 seconds
Started Feb 04 02:36:27 PM PST 24
Finished Feb 04 02:36:35 PM PST 24
Peak memory 232764 kb
Host smart-2a3c554e-632f-4ebc-be88-4ad5d8dcdbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585376442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2585376442
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3532454317
Short name T463
Test name
Test status
Simulation time 13859966777 ps
CPU time 24.27 seconds
Started Feb 04 02:36:16 PM PST 24
Finished Feb 04 02:36:46 PM PST 24
Peak memory 232772 kb
Host smart-a72bcd42-f3ee-4838-aa43-f8302ff04b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532454317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3532454317
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2255843965
Short name T460
Test name
Test status
Simulation time 898649349 ps
CPU time 3.74 seconds
Started Feb 04 02:36:31 PM PST 24
Finished Feb 04 02:36:37 PM PST 24
Peak memory 218952 kb
Host smart-6196912e-55d9-468c-a0ee-34c8d8bf18ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2255843965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2255843965
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1407981616
Short name T929
Test name
Test status
Simulation time 43941951594 ps
CPU time 285.38 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:41:26 PM PST 24
Peak memory 249376 kb
Host smart-51c76837-9cfe-4856-ac15-eb69f4acd312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407981616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1407981616
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4194620546
Short name T545
Test name
Test status
Simulation time 18194063952 ps
CPU time 44.04 seconds
Started Feb 04 02:36:07 PM PST 24
Finished Feb 04 02:36:53 PM PST 24
Peak memory 216444 kb
Host smart-a1bc13aa-1136-48ee-a520-bf99d3515030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194620546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4194620546
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1555629231
Short name T441
Test name
Test status
Simulation time 24543616248 ps
CPU time 15.66 seconds
Started Feb 04 02:36:12 PM PST 24
Finished Feb 04 02:36:29 PM PST 24
Peak memory 216428 kb
Host smart-450290c2-772b-4319-89de-735ec12e4680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555629231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1555629231
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.173156227
Short name T1068
Test name
Test status
Simulation time 288751688 ps
CPU time 1.34 seconds
Started Feb 04 02:36:13 PM PST 24
Finished Feb 04 02:36:23 PM PST 24
Peak memory 207948 kb
Host smart-cbf2c681-910b-4530-8935-78a4023e6444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173156227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.173156227
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1258208042
Short name T839
Test name
Test status
Simulation time 60895347 ps
CPU time 0.82 seconds
Started Feb 04 02:36:06 PM PST 24
Finished Feb 04 02:36:10 PM PST 24
Peak memory 205440 kb
Host smart-c637dd9d-41c8-4c1a-ac05-eb9806e1d08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258208042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1258208042
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4288523030
Short name T953
Test name
Test status
Simulation time 14321787328 ps
CPU time 12.07 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:36:53 PM PST 24
Peak memory 237108 kb
Host smart-3213ab96-d900-4a43-b0bf-be54ee46a9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288523030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4288523030
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.442604312
Short name T505
Test name
Test status
Simulation time 50672064 ps
CPU time 0.71 seconds
Started Feb 04 02:36:33 PM PST 24
Finished Feb 04 02:36:41 PM PST 24
Peak memory 204432 kb
Host smart-df29d238-4d83-4e6c-b6eb-2351a0c4789f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442604312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.442604312
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1690748077
Short name T829
Test name
Test status
Simulation time 11190817826 ps
CPU time 11.4 seconds
Started Feb 04 02:36:30 PM PST 24
Finished Feb 04 02:36:44 PM PST 24
Peak memory 233944 kb
Host smart-448ee7d4-6531-4913-b647-5d4ccd0cd9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690748077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1690748077
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.291339012
Short name T20
Test name
Test status
Simulation time 42604240 ps
CPU time 0.76 seconds
Started Feb 04 02:36:31 PM PST 24
Finished Feb 04 02:36:36 PM PST 24
Peak memory 206212 kb
Host smart-960e0aec-e1ac-477e-b8a5-1d2e7923dde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291339012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.291339012
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.469927570
Short name T1021
Test name
Test status
Simulation time 28543540363 ps
CPU time 79.83 seconds
Started Feb 04 02:36:28 PM PST 24
Finished Feb 04 02:37:49 PM PST 24
Peak memory 265640 kb
Host smart-6e82c948-6fce-46cc-a74a-347812540342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469927570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.469927570
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.912401307
Short name T855
Test name
Test status
Simulation time 6754396669 ps
CPU time 84.91 seconds
Started Feb 04 02:36:40 PM PST 24
Finished Feb 04 02:38:13 PM PST 24
Peak memory 251320 kb
Host smart-780a9f76-1f95-4fd3-81a0-47713dfeccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912401307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.912401307
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3298269902
Short name T146
Test name
Test status
Simulation time 130700465942 ps
CPU time 255.26 seconds
Started Feb 04 02:36:29 PM PST 24
Finished Feb 04 02:40:46 PM PST 24
Peak memory 241080 kb
Host smart-6068a96a-139f-414c-b094-cdaff759d74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298269902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3298269902
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2371932701
Short name T530
Test name
Test status
Simulation time 6077279917 ps
CPU time 11.08 seconds
Started Feb 04 02:36:22 PM PST 24
Finished Feb 04 02:36:35 PM PST 24
Peak memory 232780 kb
Host smart-8dff21a6-57c4-485d-8212-28aad67f7b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371932701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2371932701
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3965650551
Short name T170
Test name
Test status
Simulation time 9028333286 ps
CPU time 10.61 seconds
Started Feb 04 02:36:26 PM PST 24
Finished Feb 04 02:36:39 PM PST 24
Peak memory 217784 kb
Host smart-aefc45b8-5680-4787-a61a-4e044e6c12ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965650551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3965650551
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3133501766
Short name T164
Test name
Test status
Simulation time 3266549770 ps
CPU time 11.92 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:36:53 PM PST 24
Peak memory 239076 kb
Host smart-61266927-7eaf-494b-a940-88968ff79b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133501766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3133501766
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3507434463
Short name T223
Test name
Test status
Simulation time 18655925415 ps
CPU time 53.33 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:37:34 PM PST 24
Peak memory 249800 kb
Host smart-ebb85a20-b186-485b-85b1-71641ee6709c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507434463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3507434463
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2397152693
Short name T671
Test name
Test status
Simulation time 1299207726 ps
CPU time 4.81 seconds
Started Feb 04 02:36:31 PM PST 24
Finished Feb 04 02:36:38 PM PST 24
Peak memory 233296 kb
Host smart-5cb0981c-3d9f-4d6d-ac79-ef991bb51c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397152693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2397152693
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1293126292
Short name T442
Test name
Test status
Simulation time 2111872945 ps
CPU time 3.88 seconds
Started Feb 04 02:36:31 PM PST 24
Finished Feb 04 02:36:38 PM PST 24
Peak memory 219880 kb
Host smart-74520424-6885-46d2-b3af-150ea307a7e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1293126292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1293126292
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1327291185
Short name T736
Test name
Test status
Simulation time 3278849885 ps
CPU time 31.76 seconds
Started Feb 04 02:36:35 PM PST 24
Finished Feb 04 02:37:13 PM PST 24
Peak memory 216424 kb
Host smart-f8f9f50d-2b27-45eb-b3e5-fe9849ee9d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327291185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1327291185
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.489837953
Short name T1042
Test name
Test status
Simulation time 23167257273 ps
CPU time 17.18 seconds
Started Feb 04 02:36:42 PM PST 24
Finished Feb 04 02:37:09 PM PST 24
Peak memory 216432 kb
Host smart-6f2440d4-f1fc-4f41-a2e5-849f16f053f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489837953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.489837953
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.107297437
Short name T6
Test name
Test status
Simulation time 85003219 ps
CPU time 1.08 seconds
Started Feb 04 02:36:33 PM PST 24
Finished Feb 04 02:36:40 PM PST 24
Peak memory 206868 kb
Host smart-103353eb-9071-4b39-89a8-fcb327f4452b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107297437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.107297437
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3687639745
Short name T1023
Test name
Test status
Simulation time 54118355 ps
CPU time 0.89 seconds
Started Feb 04 02:36:36 PM PST 24
Finished Feb 04 02:36:42 PM PST 24
Peak memory 205404 kb
Host smart-a08da20f-ca4a-402e-8eae-3c240faf1f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687639745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3687639745
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2471026098
Short name T239
Test name
Test status
Simulation time 5635319740 ps
CPU time 4.18 seconds
Started Feb 04 02:36:29 PM PST 24
Finished Feb 04 02:36:35 PM PST 24
Peak memory 233596 kb
Host smart-3a2d231b-a074-4a1e-9167-88ade84d0ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471026098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2471026098
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.651382023
Short name T970
Test name
Test status
Simulation time 11715439 ps
CPU time 0.72 seconds
Started Feb 04 02:36:40 PM PST 24
Finished Feb 04 02:36:50 PM PST 24
Peak memory 204928 kb
Host smart-f10f38b5-84bb-4b17-b48d-9b2d08c259da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651382023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.651382023
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2271434438
Short name T587
Test name
Test status
Simulation time 542052265 ps
CPU time 2.64 seconds
Started Feb 04 02:36:33 PM PST 24
Finished Feb 04 02:36:42 PM PST 24
Peak memory 217884 kb
Host smart-46473cb7-6073-4be0-874a-0268223b167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271434438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2271434438
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1670430118
Short name T870
Test name
Test status
Simulation time 43070912 ps
CPU time 0.8 seconds
Started Feb 04 02:36:33 PM PST 24
Finished Feb 04 02:36:40 PM PST 24
Peak memory 206144 kb
Host smart-32992e45-7f59-4105-9b6c-d5cd66440825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670430118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1670430118
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2939051348
Short name T263
Test name
Test status
Simulation time 20655336693 ps
CPU time 95.38 seconds
Started Feb 04 02:36:33 PM PST 24
Finished Feb 04 02:38:16 PM PST 24
Peak memory 265596 kb
Host smart-bcfeced6-31c1-4152-87dc-14945c9a5000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939051348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2939051348
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3013990401
Short name T834
Test name
Test status
Simulation time 6748360779 ps
CPU time 30.4 seconds
Started Feb 04 02:36:39 PM PST 24
Finished Feb 04 02:37:13 PM PST 24
Peak memory 235176 kb
Host smart-1582f4e3-87e5-456d-9cbc-881ad2e59ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013990401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3013990401
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1284521499
Short name T711
Test name
Test status
Simulation time 51617851436 ps
CPU time 403 seconds
Started Feb 04 02:36:43 PM PST 24
Finished Feb 04 02:43:36 PM PST 24
Peak memory 256272 kb
Host smart-1d06eb37-e9b4-4219-a28f-757c9f408c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284521499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1284521499
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1499531195
Short name T1012
Test name
Test status
Simulation time 658930506 ps
CPU time 20.28 seconds
Started Feb 04 02:36:45 PM PST 24
Finished Feb 04 02:37:15 PM PST 24
Peak memory 232708 kb
Host smart-fed1bab9-65cd-4316-a4d1-47598c1ed208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499531195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1499531195
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2783391528
Short name T1077
Test name
Test status
Simulation time 205706512 ps
CPU time 4.52 seconds
Started Feb 04 02:36:33 PM PST 24
Finished Feb 04 02:36:45 PM PST 24
Peak memory 233616 kb
Host smart-5c874f5d-b9cd-40ab-8b70-9cb512b6b291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783391528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2783391528
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.544116000
Short name T238
Test name
Test status
Simulation time 1828465613 ps
CPU time 6.92 seconds
Started Feb 04 02:36:27 PM PST 24
Finished Feb 04 02:36:35 PM PST 24
Peak memory 227552 kb
Host smart-fff11629-d64a-4ed8-aa58-10e5eedff4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544116000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.544116000
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.714249011
Short name T907
Test name
Test status
Simulation time 12214567513 ps
CPU time 21.83 seconds
Started Feb 04 02:36:40 PM PST 24
Finished Feb 04 02:37:11 PM PST 24
Peak memory 228644 kb
Host smart-8030bc74-04b8-4f20-8bea-bb44cb7a9b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714249011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.714249011
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3889815021
Short name T176
Test name
Test status
Simulation time 1689021597 ps
CPU time 8.23 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:36:49 PM PST 24
Peak memory 236048 kb
Host smart-dad671b9-0e35-4f2f-989e-715b76895bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889815021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3889815021
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.207893463
Short name T559
Test name
Test status
Simulation time 1677732378 ps
CPU time 6.36 seconds
Started Feb 04 02:36:37 PM PST 24
Finished Feb 04 02:36:48 PM PST 24
Peak memory 218916 kb
Host smart-502545dc-4dc3-4d6e-b510-fd62cfd18919
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=207893463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.207893463
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3437116553
Short name T1001
Test name
Test status
Simulation time 23362697360 ps
CPU time 66.32 seconds
Started Feb 04 02:36:30 PM PST 24
Finished Feb 04 02:37:37 PM PST 24
Peak memory 241044 kb
Host smart-2717eb81-f013-40a6-91f9-aaae36965f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437116553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3437116553
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2827930698
Short name T1036
Test name
Test status
Simulation time 13876183016 ps
CPU time 35.8 seconds
Started Feb 04 02:36:45 PM PST 24
Finished Feb 04 02:37:30 PM PST 24
Peak memory 216428 kb
Host smart-e36acb7a-8817-4b2a-a15a-887a5ab466a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827930698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2827930698
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1241277053
Short name T811
Test name
Test status
Simulation time 6775054832 ps
CPU time 11.13 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:36:52 PM PST 24
Peak memory 216404 kb
Host smart-f247211a-3a22-48d2-b343-3c68150bcfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241277053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1241277053
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2724625624
Short name T1114
Test name
Test status
Simulation time 76809398 ps
CPU time 1.37 seconds
Started Feb 04 02:36:27 PM PST 24
Finished Feb 04 02:36:30 PM PST 24
Peak memory 216368 kb
Host smart-bd8d7e5c-3d30-4fe5-b6c4-c3e41236aa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724625624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2724625624
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1337362084
Short name T433
Test name
Test status
Simulation time 280486526 ps
CPU time 0.9 seconds
Started Feb 04 02:36:27 PM PST 24
Finished Feb 04 02:36:29 PM PST 24
Peak memory 205448 kb
Host smart-7d1189cf-e5c3-46eb-acbf-d31dd1cda77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337362084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1337362084
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4201783960
Short name T935
Test name
Test status
Simulation time 7591838320 ps
CPU time 24.56 seconds
Started Feb 04 02:36:28 PM PST 24
Finished Feb 04 02:36:53 PM PST 24
Peak memory 239244 kb
Host smart-ca6f5ee5-7a42-433a-9dc7-cfdfbe0cf0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201783960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4201783960
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1160944039
Short name T45
Test name
Test status
Simulation time 101024562 ps
CPU time 0.72 seconds
Started Feb 04 02:36:42 PM PST 24
Finished Feb 04 02:36:52 PM PST 24
Peak memory 203664 kb
Host smart-24e80b79-f809-40dd-bd61-b4a01df11eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160944039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1160944039
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1388181414
Short name T949
Test name
Test status
Simulation time 40637859546 ps
CPU time 7.86 seconds
Started Feb 04 02:36:37 PM PST 24
Finished Feb 04 02:36:50 PM PST 24
Peak memory 234176 kb
Host smart-f67e4bf5-89e0-455d-9c4f-36ea3ca32825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388181414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1388181414
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1613730338
Short name T747
Test name
Test status
Simulation time 33426624 ps
CPU time 0.78 seconds
Started Feb 04 02:36:29 PM PST 24
Finished Feb 04 02:36:31 PM PST 24
Peak memory 205108 kb
Host smart-516f958a-c0f5-4920-83c2-d04ce9f9478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613730338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1613730338
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3057820559
Short name T637
Test name
Test status
Simulation time 87727904673 ps
CPU time 59.09 seconds
Started Feb 04 02:36:32 PM PST 24
Finished Feb 04 02:37:35 PM PST 24
Peak memory 237032 kb
Host smart-e85af79e-b440-432c-a44f-e46d3a0df5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057820559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3057820559
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3587918338
Short name T1027
Test name
Test status
Simulation time 16634137506 ps
CPU time 143.43 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:39:04 PM PST 24
Peak memory 240588 kb
Host smart-f906c55e-464a-463a-a4f8-0dba3dd178d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587918338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3587918338
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1148630165
Short name T972
Test name
Test status
Simulation time 18033285570 ps
CPU time 79.04 seconds
Started Feb 04 02:36:39 PM PST 24
Finished Feb 04 02:38:02 PM PST 24
Peak memory 251368 kb
Host smart-bdf71b16-7e8b-4890-a287-c03eaf590640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148630165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1148630165
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2294435418
Short name T890
Test name
Test status
Simulation time 2238116227 ps
CPU time 24.82 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:37:06 PM PST 24
Peak memory 238196 kb
Host smart-92aa3c80-8015-4a2c-8e98-d6fe480ba57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294435418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2294435418
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4078140061
Short name T727
Test name
Test status
Simulation time 4264087783 ps
CPU time 8.34 seconds
Started Feb 04 02:36:32 PM PST 24
Finished Feb 04 02:36:44 PM PST 24
Peak memory 224608 kb
Host smart-ef837184-8f2d-417c-bfff-53c2f8cca4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078140061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4078140061
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.462827383
Short name T846
Test name
Test status
Simulation time 1987454996 ps
CPU time 9.31 seconds
Started Feb 04 02:36:31 PM PST 24
Finished Feb 04 02:36:42 PM PST 24
Peak memory 230320 kb
Host smart-74ae81e5-0879-4b96-802e-6e189be0e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462827383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.462827383
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3040040515
Short name T713
Test name
Test status
Simulation time 10392880197 ps
CPU time 18.13 seconds
Started Feb 04 02:36:25 PM PST 24
Finished Feb 04 02:36:45 PM PST 24
Peak memory 233600 kb
Host smart-b44e6260-737b-46d9-8749-1c99948a2017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040040515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3040040515
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1217705140
Short name T1017
Test name
Test status
Simulation time 36560112817 ps
CPU time 26.61 seconds
Started Feb 04 02:36:27 PM PST 24
Finished Feb 04 02:36:55 PM PST 24
Peak memory 235132 kb
Host smart-1a8eba37-bfc1-4d14-89c1-f4dbc8da45de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217705140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1217705140
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4040532077
Short name T892
Test name
Test status
Simulation time 5257645204 ps
CPU time 5.26 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:36:54 PM PST 24
Peak memory 219004 kb
Host smart-bd8428f6-5708-4b9a-a837-ffc0fd31592d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4040532077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4040532077
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.632985171
Short name T918
Test name
Test status
Simulation time 145244144 ps
CPU time 0.9 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:36:57 PM PST 24
Peak memory 206164 kb
Host smart-8b5aca96-18eb-4c75-a1ce-a7827662c428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632985171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.632985171
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3540833999
Short name T277
Test name
Test status
Simulation time 1945798217 ps
CPU time 27.3 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:37:08 PM PST 24
Peak memory 216308 kb
Host smart-6e5e39d6-25ae-492e-9576-c4bb78b3d57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540833999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3540833999
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3389937136
Short name T684
Test name
Test status
Simulation time 6534461825 ps
CPU time 14.37 seconds
Started Feb 04 02:36:28 PM PST 24
Finished Feb 04 02:36:43 PM PST 24
Peak memory 217104 kb
Host smart-e6314e18-d5cc-417c-831f-124cdda34a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389937136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3389937136
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3050391575
Short name T281
Test name
Test status
Simulation time 214579682 ps
CPU time 2.61 seconds
Started Feb 04 02:36:32 PM PST 24
Finished Feb 04 02:36:38 PM PST 24
Peak memory 216352 kb
Host smart-3040ea60-77de-4877-b33d-81848e34e0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050391575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3050391575
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2643330926
Short name T905
Test name
Test status
Simulation time 70773339 ps
CPU time 0.75 seconds
Started Feb 04 02:36:26 PM PST 24
Finished Feb 04 02:36:29 PM PST 24
Peak memory 205432 kb
Host smart-d3d1088b-4e7d-405b-b01a-362892411afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643330926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2643330926
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3897856707
Short name T948
Test name
Test status
Simulation time 7824517430 ps
CPU time 25.62 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:37:06 PM PST 24
Peak memory 232820 kb
Host smart-66f0cc11-14c7-4f02-a2e9-427fdb3664a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897856707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3897856707
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.381682530
Short name T705
Test name
Test status
Simulation time 60245722 ps
CPU time 0.72 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:36:50 PM PST 24
Peak memory 204388 kb
Host smart-db109c99-7a71-4efa-baa5-8dc019d93f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381682530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.381682530
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2979311956
Short name T845
Test name
Test status
Simulation time 856396214 ps
CPU time 6.21 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:36:57 PM PST 24
Peak memory 233616 kb
Host smart-dd99b0f2-fd63-4cb5-a8c6-27b706cff5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979311956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2979311956
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.763318847
Short name T898
Test name
Test status
Simulation time 13291957 ps
CPU time 0.76 seconds
Started Feb 04 02:36:44 PM PST 24
Finished Feb 04 02:36:55 PM PST 24
Peak memory 205212 kb
Host smart-e5636158-b919-4fda-b349-e57e3e67ec51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763318847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.763318847
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3212576898
Short name T620
Test name
Test status
Simulation time 8383571832 ps
CPU time 41.26 seconds
Started Feb 04 02:36:42 PM PST 24
Finished Feb 04 02:37:33 PM PST 24
Peak memory 240996 kb
Host smart-f9eb74e3-9b3c-4fec-8631-da84c9f3035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212576898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3212576898
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3893970006
Short name T584
Test name
Test status
Simulation time 65824240495 ps
CPU time 149.01 seconds
Started Feb 04 02:36:37 PM PST 24
Finished Feb 04 02:39:11 PM PST 24
Peak memory 249736 kb
Host smart-2fd136d2-cacf-4097-97d7-ced0a2238317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893970006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3893970006
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1963436705
Short name T222
Test name
Test status
Simulation time 4269524246 ps
CPU time 71.61 seconds
Started Feb 04 02:36:33 PM PST 24
Finished Feb 04 02:37:51 PM PST 24
Peak memory 254972 kb
Host smart-e0b7b948-c05e-430c-9259-d9c1f95a094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963436705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1963436705
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.609569127
Short name T275
Test name
Test status
Simulation time 10036443177 ps
CPU time 19.28 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:37:09 PM PST 24
Peak memory 237252 kb
Host smart-7d8e2834-30f2-4c8f-aed6-83c4a55b121f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609569127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.609569127
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1168799850
Short name T171
Test name
Test status
Simulation time 750877866 ps
CPU time 7.05 seconds
Started Feb 04 02:36:44 PM PST 24
Finished Feb 04 02:37:02 PM PST 24
Peak memory 233576 kb
Host smart-6d304ccd-205f-4cc2-b1da-d2de513849e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168799850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1168799850
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3113187056
Short name T139
Test name
Test status
Simulation time 6979022349 ps
CPU time 22.9 seconds
Started Feb 04 02:36:44 PM PST 24
Finished Feb 04 02:37:18 PM PST 24
Peak memory 239168 kb
Host smart-7117d39a-e4a5-49e2-8f36-5e875161a9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113187056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3113187056
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.514793794
Short name T229
Test name
Test status
Simulation time 1929488993 ps
CPU time 9.11 seconds
Started Feb 04 02:36:43 PM PST 24
Finished Feb 04 02:37:01 PM PST 24
Peak memory 233628 kb
Host smart-07273f59-95bd-43f9-9538-2d441c22c6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514793794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.514793794
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2190922354
Short name T618
Test name
Test status
Simulation time 13483332778 ps
CPU time 13.25 seconds
Started Feb 04 02:36:44 PM PST 24
Finished Feb 04 02:37:08 PM PST 24
Peak memory 233776 kb
Host smart-7a213bfe-30ed-46b5-826a-a292dd49f43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190922354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2190922354
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1964159834
Short name T540
Test name
Test status
Simulation time 498873496 ps
CPU time 4.46 seconds
Started Feb 04 02:36:31 PM PST 24
Finished Feb 04 02:36:40 PM PST 24
Peak memory 222588 kb
Host smart-4d2b7d8b-8fee-4f10-bd1e-8a9ee0b197b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1964159834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1964159834
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1352196924
Short name T27
Test name
Test status
Simulation time 171208345009 ps
CPU time 316.5 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:42:06 PM PST 24
Peak memory 255096 kb
Host smart-3634b2cf-bd35-4cb0-8bf8-0e58acbf4cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352196924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1352196924
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1842680839
Short name T885
Test name
Test status
Simulation time 18545488805 ps
CPU time 74.18 seconds
Started Feb 04 02:36:48 PM PST 24
Finished Feb 04 02:38:09 PM PST 24
Peak memory 220332 kb
Host smart-8a90e88b-0f59-4ab9-a684-f55a72599607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842680839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1842680839
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.547167579
Short name T293
Test name
Test status
Simulation time 7992877019 ps
CPU time 23.68 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:37:14 PM PST 24
Peak memory 216424 kb
Host smart-76b6b7a9-dbf6-4ed8-a42b-b1a44c92068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547167579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.547167579
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1413458839
Short name T515
Test name
Test status
Simulation time 15974298 ps
CPU time 0.81 seconds
Started Feb 04 02:36:39 PM PST 24
Finished Feb 04 02:36:44 PM PST 24
Peak memory 206224 kb
Host smart-2f991c13-19e6-4c4c-bf8c-da1bd645e77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413458839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1413458839
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2832868436
Short name T72
Test name
Test status
Simulation time 90985936 ps
CPU time 0.89 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:36:59 PM PST 24
Peak memory 205664 kb
Host smart-8aaca84f-84fd-485f-9ef4-50952954d84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832868436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2832868436
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1027858854
Short name T1081
Test name
Test status
Simulation time 609903421 ps
CPU time 3.55 seconds
Started Feb 04 02:36:37 PM PST 24
Finished Feb 04 02:36:45 PM PST 24
Peak memory 224552 kb
Host smart-a613f477-dcc7-4262-a94b-c2ed2667fe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027858854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1027858854
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2621166885
Short name T724
Test name
Test status
Simulation time 67814640 ps
CPU time 0.7 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:36:50 PM PST 24
Peak memory 205276 kb
Host smart-79ade3e2-c233-481d-b9e3-dfc8feef409c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621166885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2621166885
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.764112518
Short name T483
Test name
Test status
Simulation time 514949967 ps
CPU time 2.43 seconds
Started Feb 04 02:36:42 PM PST 24
Finished Feb 04 02:36:54 PM PST 24
Peak memory 216824 kb
Host smart-979defca-48ef-443d-8155-4d43fee92ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764112518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.764112518
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2868000344
Short name T891
Test name
Test status
Simulation time 48633450 ps
CPU time 0.72 seconds
Started Feb 04 02:36:48 PM PST 24
Finished Feb 04 02:36:56 PM PST 24
Peak memory 205140 kb
Host smart-e44fb129-045b-44c5-9129-c38d74b62e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868000344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2868000344
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4063160832
Short name T1000
Test name
Test status
Simulation time 40981091463 ps
CPU time 227.77 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:40:38 PM PST 24
Peak memory 251800 kb
Host smart-c326d74d-4ecf-42b7-b30b-b5ce38546900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063160832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4063160832
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3546644887
Short name T1106
Test name
Test status
Simulation time 65596024788 ps
CPU time 155.74 seconds
Started Feb 04 02:36:50 PM PST 24
Finished Feb 04 02:39:32 PM PST 24
Peak memory 257460 kb
Host smart-5e280385-e9a4-45fc-9032-1061ac7063b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546644887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3546644887
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1494867442
Short name T276
Test name
Test status
Simulation time 1569150596 ps
CPU time 14.07 seconds
Started Feb 04 02:36:44 PM PST 24
Finished Feb 04 02:37:09 PM PST 24
Peak memory 248672 kb
Host smart-951177be-bf95-4e63-87c0-87a7e788dab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494867442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1494867442
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2085732077
Short name T241
Test name
Test status
Simulation time 752376563 ps
CPU time 3.15 seconds
Started Feb 04 02:36:37 PM PST 24
Finished Feb 04 02:36:45 PM PST 24
Peak memory 217820 kb
Host smart-ec96289c-f607-438f-8675-f9b479bf197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085732077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2085732077
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.943401531
Short name T159
Test name
Test status
Simulation time 4718087021 ps
CPU time 12.78 seconds
Started Feb 04 02:36:50 PM PST 24
Finished Feb 04 02:37:11 PM PST 24
Peak memory 233312 kb
Host smart-5038c6bc-7746-4cbb-8bea-f8f9dc2f3134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943401531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.943401531
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2961373231
Short name T1025
Test name
Test status
Simulation time 184569337 ps
CPU time 4.16 seconds
Started Feb 04 02:36:32 PM PST 24
Finished Feb 04 02:36:40 PM PST 24
Peak memory 232932 kb
Host smart-1484db92-d4f2-4b40-b900-39cce2f38411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961373231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2961373231
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2228920278
Short name T561
Test name
Test status
Simulation time 930971419 ps
CPU time 7.4 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:36:58 PM PST 24
Peak memory 233408 kb
Host smart-192886a3-67c7-45e3-a4d8-c802e44bae89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228920278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2228920278
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1990116172
Short name T772
Test name
Test status
Simulation time 1154621947 ps
CPU time 5.45 seconds
Started Feb 04 02:36:34 PM PST 24
Finished Feb 04 02:36:46 PM PST 24
Peak memory 218840 kb
Host smart-16d51b40-5d3e-4b8e-9ff4-e8aa4ecde6be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1990116172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1990116172
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2332859315
Short name T660
Test name
Test status
Simulation time 8833554954 ps
CPU time 69.58 seconds
Started Feb 04 02:36:43 PM PST 24
Finished Feb 04 02:38:02 PM PST 24
Peak memory 216480 kb
Host smart-e55c14ac-8b5f-4282-9224-7297c7e5802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332859315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2332859315
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3798832279
Short name T919
Test name
Test status
Simulation time 27800096176 ps
CPU time 32.16 seconds
Started Feb 04 02:36:36 PM PST 24
Finished Feb 04 02:37:14 PM PST 24
Peak memory 216396 kb
Host smart-314e810e-ccf9-4479-8bb9-a156f34584b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798832279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3798832279
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2325305516
Short name T778
Test name
Test status
Simulation time 93138788 ps
CPU time 1.58 seconds
Started Feb 04 02:36:44 PM PST 24
Finished Feb 04 02:36:56 PM PST 24
Peak memory 207944 kb
Host smart-cb1c3eeb-62a1-4079-9abd-93ea3a9d8c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325305516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2325305516
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2841890371
Short name T1065
Test name
Test status
Simulation time 20161813 ps
CPU time 0.77 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:36:50 PM PST 24
Peak memory 205404 kb
Host smart-3ba5ac06-2ad1-4bb4-a7e8-c411f573d385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841890371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2841890371
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1977366833
Short name T288
Test name
Test status
Simulation time 317143933 ps
CPU time 2.75 seconds
Started Feb 04 02:36:48 PM PST 24
Finished Feb 04 02:36:58 PM PST 24
Peak memory 216404 kb
Host smart-6c71fbd2-b894-4740-a051-2b2d7eae6542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977366833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1977366833
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3406345944
Short name T864
Test name
Test status
Simulation time 15697042 ps
CPU time 0.71 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:36:59 PM PST 24
Peak memory 204388 kb
Host smart-90147edf-f314-4e49-820f-c54b2d588997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406345944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3406345944
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3199710380
Short name T994
Test name
Test status
Simulation time 1862707686 ps
CPU time 3.74 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:36:54 PM PST 24
Peak memory 233536 kb
Host smart-810dfa1e-4322-4dd7-ba1b-0e458121c820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199710380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3199710380
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2617599843
Short name T640
Test name
Test status
Simulation time 21666781 ps
CPU time 0.79 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:36:59 PM PST 24
Peak memory 206192 kb
Host smart-6f2735c3-c2b7-479b-b82f-d5f3b15e2fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617599843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2617599843
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2833292009
Short name T262
Test name
Test status
Simulation time 83262252212 ps
CPU time 266.06 seconds
Started Feb 04 02:36:42 PM PST 24
Finished Feb 04 02:41:18 PM PST 24
Peak memory 268796 kb
Host smart-217532ce-1990-452b-b45d-b863d4641db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833292009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2833292009
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3380022414
Short name T517
Test name
Test status
Simulation time 4721731304 ps
CPU time 57.52 seconds
Started Feb 04 02:36:50 PM PST 24
Finished Feb 04 02:37:54 PM PST 24
Peak memory 251172 kb
Host smart-c930fc15-bbb1-4604-87de-18e670ba0995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380022414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3380022414
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.680940036
Short name T821
Test name
Test status
Simulation time 105985732020 ps
CPU time 123.78 seconds
Started Feb 04 02:36:39 PM PST 24
Finished Feb 04 02:38:47 PM PST 24
Peak memory 237168 kb
Host smart-efd140e6-df4f-469c-8a92-873b2870e715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680940036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.680940036
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.723157965
Short name T951
Test name
Test status
Simulation time 1293796947 ps
CPU time 13.96 seconds
Started Feb 04 02:36:43 PM PST 24
Finished Feb 04 02:37:08 PM PST 24
Peak memory 249552 kb
Host smart-d2b0e1d2-a8b7-4ea1-9d64-7c82eec6b386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723157965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.723157965
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3376415229
Short name T616
Test name
Test status
Simulation time 8127970785 ps
CPU time 5.74 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:37:04 PM PST 24
Peak memory 217924 kb
Host smart-d6957e8d-2c5f-4f8a-aa98-6b75d3c7622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376415229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3376415229
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2993351998
Short name T503
Test name
Test status
Simulation time 79914067 ps
CPU time 2.54 seconds
Started Feb 04 02:36:44 PM PST 24
Finished Feb 04 02:36:57 PM PST 24
Peak memory 232744 kb
Host smart-dd24a184-8aaf-4763-9bbf-bcdc498dcfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993351998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2993351998
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3264852579
Short name T603
Test name
Test status
Simulation time 2720016363 ps
CPU time 10.11 seconds
Started Feb 04 02:36:44 PM PST 24
Finished Feb 04 02:37:05 PM PST 24
Peak memory 233540 kb
Host smart-0530e43f-c69e-4519-aea1-399ce48903ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264852579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3264852579
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2158956403
Short name T954
Test name
Test status
Simulation time 7631951476 ps
CPU time 22.19 seconds
Started Feb 04 02:36:50 PM PST 24
Finished Feb 04 02:37:19 PM PST 24
Peak memory 234332 kb
Host smart-0a10e4d6-ca6d-475d-9461-287c4a026275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158956403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2158956403
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.668861427
Short name T306
Test name
Test status
Simulation time 97987473 ps
CPU time 3.42 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:37:02 PM PST 24
Peak memory 222112 kb
Host smart-914f7519-76a5-4211-8634-289ab040e87d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=668861427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.668861427
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.328833932
Short name T1092
Test name
Test status
Simulation time 22651860980 ps
CPU time 185.28 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:40:02 PM PST 24
Peak memory 249296 kb
Host smart-cd1e471e-75d6-443c-8f45-b56caae3a0ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328833932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.328833932
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3110406656
Short name T432
Test name
Test status
Simulation time 1233466005 ps
CPU time 19.14 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:37:17 PM PST 24
Peak memory 216416 kb
Host smart-674dfa32-d46b-450a-9fae-ed1a01f3424e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110406656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3110406656
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4280361469
Short name T921
Test name
Test status
Simulation time 6557235499 ps
CPU time 11.64 seconds
Started Feb 04 02:36:48 PM PST 24
Finished Feb 04 02:37:07 PM PST 24
Peak memory 216384 kb
Host smart-cbe91aea-55ee-4f7a-8c11-a4c6b67c3ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280361469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4280361469
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3443264537
Short name T980
Test name
Test status
Simulation time 440624895 ps
CPU time 4.19 seconds
Started Feb 04 02:36:50 PM PST 24
Finished Feb 04 02:37:01 PM PST 24
Peak memory 216368 kb
Host smart-937fb6c4-12d5-4172-a169-a9b6290fd052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443264537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3443264537
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3430047522
Short name T621
Test name
Test status
Simulation time 256231419 ps
CPU time 0.9 seconds
Started Feb 04 02:36:45 PM PST 24
Finished Feb 04 02:36:56 PM PST 24
Peak memory 205372 kb
Host smart-1989f3ba-6702-4462-bb4d-d659bcdedfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430047522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3430047522
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1058524305
Short name T217
Test name
Test status
Simulation time 1328437576 ps
CPU time 8.12 seconds
Started Feb 04 02:36:48 PM PST 24
Finished Feb 04 02:37:03 PM PST 24
Peak memory 224088 kb
Host smart-51ebc411-7e98-45db-a00c-02407133ccde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058524305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1058524305
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2527707236
Short name T1039
Test name
Test status
Simulation time 72946727 ps
CPU time 0.77 seconds
Started Feb 04 02:34:23 PM PST 24
Finished Feb 04 02:34:36 PM PST 24
Peak memory 205280 kb
Host smart-9147e369-c2d7-48fa-837c-07185c2923ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527707236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
527707236
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2225964731
Short name T235
Test name
Test status
Simulation time 226126124 ps
CPU time 3.05 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:34:26 PM PST 24
Peak memory 217956 kb
Host smart-6ca6639d-126d-489a-8ff9-62ae5de1a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225964731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2225964731
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.787168770
Short name T539
Test name
Test status
Simulation time 62681102 ps
CPU time 0.77 seconds
Started Feb 04 02:34:08 PM PST 24
Finished Feb 04 02:34:17 PM PST 24
Peak memory 206156 kb
Host smart-64a96ef5-14b2-472e-9106-53cde41caa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787168770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.787168770
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1988389330
Short name T194
Test name
Test status
Simulation time 26337664456 ps
CPU time 64.1 seconds
Started Feb 04 02:34:17 PM PST 24
Finished Feb 04 02:35:27 PM PST 24
Peak memory 255708 kb
Host smart-d907c1cf-55f4-4f05-a059-8bccfa451811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988389330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1988389330
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2821657518
Short name T70
Test name
Test status
Simulation time 28502541059 ps
CPU time 52.96 seconds
Started Feb 04 02:34:17 PM PST 24
Finished Feb 04 02:35:16 PM PST 24
Peak memory 251016 kb
Host smart-0359af5b-bfad-4f74-b9a7-f248dd515b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821657518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2821657518
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1034064783
Short name T812
Test name
Test status
Simulation time 53032267 ps
CPU time 2.71 seconds
Started Feb 04 02:34:15 PM PST 24
Finished Feb 04 02:34:24 PM PST 24
Peak memory 234764 kb
Host smart-22e71ea4-0240-4706-b4ee-9edf12ab6105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034064783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1034064783
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.928781117
Short name T140
Test name
Test status
Simulation time 52553243443 ps
CPU time 29.79 seconds
Started Feb 04 02:34:07 PM PST 24
Finished Feb 04 02:34:46 PM PST 24
Peak memory 240944 kb
Host smart-8028e572-fd44-4287-8c29-f28ef26bb74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928781117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.928781117
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1591293073
Short name T1049
Test name
Test status
Simulation time 58976164 ps
CPU time 1.02 seconds
Started Feb 04 02:34:15 PM PST 24
Finished Feb 04 02:34:22 PM PST 24
Peak memory 217724 kb
Host smart-bd32d59e-4271-4d1e-936c-235228a6ceab
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591293073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1591293073
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2771627096
Short name T593
Test name
Test status
Simulation time 13603987232 ps
CPU time 16.08 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:34:33 PM PST 24
Peak memory 240344 kb
Host smart-0875186a-e8ad-4caf-8bea-e5e630c36fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771627096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2771627096
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1307025247
Short name T62
Test name
Test status
Simulation time 17444848477 ps
CPU time 17.23 seconds
Started Feb 04 02:34:14 PM PST 24
Finished Feb 04 02:34:38 PM PST 24
Peak memory 238360 kb
Host smart-c4ffc040-1b83-42b3-962c-a3a74b133e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307025247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1307025247
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.1989811039
Short name T569
Test name
Test status
Simulation time 14798623 ps
CPU time 0.74 seconds
Started Feb 04 02:34:14 PM PST 24
Finished Feb 04 02:34:22 PM PST 24
Peak memory 216240 kb
Host smart-db894d76-19e6-480c-b121-8caaefbd97ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989811039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.1989811039
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.220987223
Short name T121
Test name
Test status
Simulation time 2097681615 ps
CPU time 3.44 seconds
Started Feb 04 02:34:17 PM PST 24
Finished Feb 04 02:34:26 PM PST 24
Peak memory 218696 kb
Host smart-2538630f-5e0f-458c-bfc7-026f40858685
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=220987223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.220987223
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1192438534
Short name T58
Test name
Test status
Simulation time 46498953 ps
CPU time 0.98 seconds
Started Feb 04 02:34:23 PM PST 24
Finished Feb 04 02:34:37 PM PST 24
Peak memory 234608 kb
Host smart-68622b6d-cc31-4b23-8863-e93fff8d8930
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192438534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1192438534
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2880791062
Short name T575
Test name
Test status
Simulation time 24377637580 ps
CPU time 93.6 seconds
Started Feb 04 02:34:15 PM PST 24
Finished Feb 04 02:35:55 PM PST 24
Peak memory 216272 kb
Host smart-6807f4a6-48c8-45ac-b03d-c8f35efe11de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880791062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2880791062
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3325835614
Short name T1029
Test name
Test status
Simulation time 1868597295 ps
CPU time 9.32 seconds
Started Feb 04 02:34:09 PM PST 24
Finished Feb 04 02:34:26 PM PST 24
Peak memory 216372 kb
Host smart-378b5288-9a66-4b5d-a6e0-01d02e9c3e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325835614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3325835614
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1502214336
Short name T581
Test name
Test status
Simulation time 193443558 ps
CPU time 2.04 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:34:25 PM PST 24
Peak memory 208416 kb
Host smart-2f076bc6-1b6e-4ea9-964a-e0991519121b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502214336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1502214336
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2140666218
Short name T1028
Test name
Test status
Simulation time 118842391 ps
CPU time 0.94 seconds
Started Feb 04 02:34:06 PM PST 24
Finished Feb 04 02:34:17 PM PST 24
Peak memory 205460 kb
Host smart-7026bc01-010f-46b1-9d2d-4fd08770d28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140666218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2140666218
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2406900904
Short name T1057
Test name
Test status
Simulation time 1837618877 ps
CPU time 6.33 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:34:29 PM PST 24
Peak memory 216976 kb
Host smart-c8c5abc4-867d-475b-bf37-21ea2d0bf449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406900904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2406900904
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.895749924
Short name T1101
Test name
Test status
Simulation time 144952692 ps
CPU time 0.7 seconds
Started Feb 04 02:36:48 PM PST 24
Finished Feb 04 02:36:56 PM PST 24
Peak memory 205256 kb
Host smart-7f5a3411-4065-4dae-a109-d7307e4ce05c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895749924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.895749924
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.14323509
Short name T555
Test name
Test status
Simulation time 2445291284 ps
CPU time 7.07 seconds
Started Feb 04 02:36:50 PM PST 24
Finished Feb 04 02:37:03 PM PST 24
Peak memory 233232 kb
Host smart-2a6f08dc-6011-48f3-8d9b-e2f981b2757a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14323509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.14323509
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3402434545
Short name T531
Test name
Test status
Simulation time 40687955 ps
CPU time 0.77 seconds
Started Feb 04 02:36:52 PM PST 24
Finished Feb 04 02:36:59 PM PST 24
Peak memory 206136 kb
Host smart-ea955715-685b-4226-bc9c-e513639ac006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402434545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3402434545
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3296890930
Short name T33
Test name
Test status
Simulation time 54820194144 ps
CPU time 93.63 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:38:29 PM PST 24
Peak memory 249180 kb
Host smart-a3548e8c-ede5-4741-8888-f3a93c7e8114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296890930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3296890930
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1581581503
Short name T178
Test name
Test status
Simulation time 90607749305 ps
CPU time 328.91 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:42:25 PM PST 24
Peak memory 255004 kb
Host smart-34af528d-2d77-4ed9-9cf8-05f36eb3d0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581581503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1581581503
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1417580234
Short name T138
Test name
Test status
Simulation time 5146387507 ps
CPU time 103.17 seconds
Started Feb 04 02:36:48 PM PST 24
Finished Feb 04 02:38:38 PM PST 24
Peak memory 254548 kb
Host smart-5cce1757-0a49-45c4-80ad-85c3d62decbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417580234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1417580234
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4129998452
Short name T120
Test name
Test status
Simulation time 7170610514 ps
CPU time 18.93 seconds
Started Feb 04 02:36:39 PM PST 24
Finished Feb 04 02:37:02 PM PST 24
Peak memory 249060 kb
Host smart-900d1308-30eb-4e35-9670-e31a4e5c0d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129998452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4129998452
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1270262592
Short name T161
Test name
Test status
Simulation time 11647655479 ps
CPU time 11.42 seconds
Started Feb 04 02:36:52 PM PST 24
Finished Feb 04 02:37:10 PM PST 24
Peak memory 219168 kb
Host smart-bd3d23db-7122-4055-8868-1e508d3f4424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270262592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1270262592
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1265913437
Short name T752
Test name
Test status
Simulation time 11434165756 ps
CPU time 31.16 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:37:29 PM PST 24
Peak memory 231112 kb
Host smart-813a0a20-6dd0-4fc9-b456-0fbafe7a81fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265913437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1265913437
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2899883286
Short name T544
Test name
Test status
Simulation time 94241319 ps
CPU time 2.02 seconds
Started Feb 04 02:36:40 PM PST 24
Finished Feb 04 02:36:51 PM PST 24
Peak memory 224476 kb
Host smart-8d2aa394-67bb-4c3c-ba28-ed4f4c2af3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899883286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2899883286
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2292765217
Short name T784
Test name
Test status
Simulation time 1100777922 ps
CPU time 7.45 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:36:57 PM PST 24
Peak memory 216484 kb
Host smart-a81dff62-b2e1-4c67-a9f7-2433361a6587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292765217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2292765217
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.59601704
Short name T653
Test name
Test status
Simulation time 902811311 ps
CPU time 5.57 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:37:01 PM PST 24
Peak memory 222028 kb
Host smart-13f69818-399d-4486-bad8-4c417aaa89ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=59601704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direc
t.59601704
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4187020173
Short name T1020
Test name
Test status
Simulation time 76771198512 ps
CPU time 468.65 seconds
Started Feb 04 02:36:50 PM PST 24
Finished Feb 04 02:44:46 PM PST 24
Peak memory 265704 kb
Host smart-c705c29b-397a-4940-bf78-8c1c3b88e362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187020173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4187020173
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2027239347
Short name T765
Test name
Test status
Simulation time 4609694816 ps
CPU time 17.44 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:37:07 PM PST 24
Peak memory 216456 kb
Host smart-fcd24cb4-92ff-4640-bb35-1a5b1cb34284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027239347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2027239347
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.427441025
Short name T753
Test name
Test status
Simulation time 4095608579 ps
CPU time 17.41 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:37:07 PM PST 24
Peak memory 216388 kb
Host smart-38607bc9-a229-4a5c-af6c-9d77326ef6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427441025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.427441025
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1136678940
Short name T452
Test name
Test status
Simulation time 320834008 ps
CPU time 2.71 seconds
Started Feb 04 02:36:41 PM PST 24
Finished Feb 04 02:36:53 PM PST 24
Peak memory 208156 kb
Host smart-ebe5ae2c-3718-47a2-b8e2-9d65d5397afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136678940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1136678940
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2970618754
Short name T284
Test name
Test status
Simulation time 93416304 ps
CPU time 0.88 seconds
Started Feb 04 02:36:48 PM PST 24
Finished Feb 04 02:36:56 PM PST 24
Peak memory 205024 kb
Host smart-fc2e7917-4c57-455a-95f7-700fc8a654e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970618754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2970618754
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3994955716
Short name T979
Test name
Test status
Simulation time 2279591970 ps
CPU time 6.8 seconds
Started Feb 04 02:36:50 PM PST 24
Finished Feb 04 02:37:04 PM PST 24
Peak memory 224584 kb
Host smart-ad2eecd3-5f50-4f08-b520-ac051851aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994955716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3994955716
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4085318857
Short name T499
Test name
Test status
Simulation time 30251361 ps
CPU time 0.68 seconds
Started Feb 04 02:37:02 PM PST 24
Finished Feb 04 02:37:05 PM PST 24
Peak memory 204792 kb
Host smart-6f64b9cd-ac2d-4f0b-a86f-aff6658ab423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085318857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4085318857
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1416997155
Short name T440
Test name
Test status
Simulation time 337342506 ps
CPU time 3.28 seconds
Started Feb 04 02:37:02 PM PST 24
Finished Feb 04 02:37:06 PM PST 24
Peak memory 233172 kb
Host smart-bf4b0bc3-0046-4a7b-b01e-0f570d553800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416997155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1416997155
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.698779284
Short name T516
Test name
Test status
Simulation time 53680658 ps
CPU time 0.75 seconds
Started Feb 04 02:36:43 PM PST 24
Finished Feb 04 02:36:55 PM PST 24
Peak memory 205164 kb
Host smart-69b1c19a-e410-4bd1-b68a-bccef2ac9d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698779284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.698779284
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2867817343
Short name T613
Test name
Test status
Simulation time 8904201328 ps
CPU time 81.13 seconds
Started Feb 04 02:37:02 PM PST 24
Finished Feb 04 02:38:25 PM PST 24
Peak memory 256024 kb
Host smart-83222bb6-0c8a-4476-865e-50c252e915db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867817343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2867817343
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1111928676
Short name T695
Test name
Test status
Simulation time 1603358009 ps
CPU time 26.54 seconds
Started Feb 04 02:36:47 PM PST 24
Finished Feb 04 02:37:21 PM PST 24
Peak memory 235080 kb
Host smart-450ed19e-4524-4794-853f-0d25fbdd00fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111928676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1111928676
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4206001064
Short name T790
Test name
Test status
Simulation time 8748925257 ps
CPU time 22.62 seconds
Started Feb 04 02:37:04 PM PST 24
Finished Feb 04 02:37:30 PM PST 24
Peak memory 224508 kb
Host smart-b7883e7c-50ca-466d-ae67-a0849cf26cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206001064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4206001064
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2995911612
Short name T43
Test name
Test status
Simulation time 7406229557 ps
CPU time 8.33 seconds
Started Feb 04 02:37:02 PM PST 24
Finished Feb 04 02:37:12 PM PST 24
Peak memory 233288 kb
Host smart-52e69c83-d814-4092-8388-e16af094e3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995911612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2995911612
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1724947944
Short name T808
Test name
Test status
Simulation time 1174874572 ps
CPU time 4.06 seconds
Started Feb 04 02:36:46 PM PST 24
Finished Feb 04 02:36:59 PM PST 24
Peak memory 216824 kb
Host smart-8760e873-532e-4eea-879c-fef36a56dae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724947944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1724947944
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3156570301
Short name T903
Test name
Test status
Simulation time 9005812352 ps
CPU time 11.47 seconds
Started Feb 04 02:36:47 PM PST 24
Finished Feb 04 02:37:06 PM PST 24
Peak memory 239548 kb
Host smart-26ce762b-6c04-4b0c-b697-91eeb54d9d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156570301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3156570301
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.236276120
Short name T1055
Test name
Test status
Simulation time 351274742 ps
CPU time 3.51 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:37:01 PM PST 24
Peak memory 232808 kb
Host smart-7ef06b32-57d2-4b1a-82c6-4709abb77801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236276120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.236276120
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2245141575
Short name T701
Test name
Test status
Simulation time 1662058839 ps
CPU time 5.66 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:37:03 PM PST 24
Peak memory 222532 kb
Host smart-b9aadeb2-b9f0-45a8-939b-76a9fa1ae366
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2245141575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2245141575
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1995453884
Short name T997
Test name
Test status
Simulation time 44871779 ps
CPU time 1.02 seconds
Started Feb 04 02:37:04 PM PST 24
Finished Feb 04 02:37:09 PM PST 24
Peak memory 206128 kb
Host smart-c557693f-c2ef-4b21-b29d-bba2878a93b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995453884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1995453884
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2770997472
Short name T598
Test name
Test status
Simulation time 6630639118 ps
CPU time 120.31 seconds
Started Feb 04 02:36:45 PM PST 24
Finished Feb 04 02:38:55 PM PST 24
Peak memory 216412 kb
Host smart-e70dda1a-df51-4586-b7e5-afdcbfdacdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770997472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2770997472
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3509159176
Short name T748
Test name
Test status
Simulation time 1720807427 ps
CPU time 10.07 seconds
Started Feb 04 02:36:58 PM PST 24
Finished Feb 04 02:37:10 PM PST 24
Peak memory 208236 kb
Host smart-46642aec-a049-4fa1-8df4-f92c689641bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509159176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3509159176
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.422575117
Short name T491
Test name
Test status
Simulation time 26683795 ps
CPU time 0.78 seconds
Started Feb 04 02:36:47 PM PST 24
Finished Feb 04 02:36:56 PM PST 24
Peak memory 205320 kb
Host smart-cfe40fb9-3ee5-4a5c-a053-26c119ef6457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422575117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.422575117
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2391473081
Short name T299
Test name
Test status
Simulation time 109979083 ps
CPU time 0.97 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:36:56 PM PST 24
Peak memory 205432 kb
Host smart-9619222b-002d-4118-99b0-ab0d1c8b5699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391473081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2391473081
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.844871667
Short name T560
Test name
Test status
Simulation time 952286331 ps
CPU time 5.98 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:37:01 PM PST 24
Peak memory 239704 kb
Host smart-e9c1c2fa-a25f-464f-9696-09a6f9fbf087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844871667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.844871667
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3759750509
Short name T1
Test name
Test status
Simulation time 78791919 ps
CPU time 0.72 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:36:59 PM PST 24
Peak memory 204940 kb
Host smart-11595aed-5b9b-4896-abb3-0fdb9447af8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759750509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3759750509
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.652282630
Short name T592
Test name
Test status
Simulation time 115820066 ps
CPU time 2.51 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:37:00 PM PST 24
Peak memory 224504 kb
Host smart-f14dc20f-f808-496e-844a-4c2070e231d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652282630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.652282630
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2786596279
Short name T847
Test name
Test status
Simulation time 22231163 ps
CPU time 0.75 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:36:57 PM PST 24
Peak memory 205128 kb
Host smart-1b13ded5-9954-4d89-830e-d17726abbd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786596279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2786596279
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3411019522
Short name T181
Test name
Test status
Simulation time 5240062098 ps
CPU time 25.92 seconds
Started Feb 04 02:37:02 PM PST 24
Finished Feb 04 02:37:30 PM PST 24
Peak memory 249000 kb
Host smart-058df73c-9f18-42a9-b84f-a9b0da9e0b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411019522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3411019522
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2836444695
Short name T906
Test name
Test status
Simulation time 3199650162 ps
CPU time 18.27 seconds
Started Feb 04 02:36:48 PM PST 24
Finished Feb 04 02:37:13 PM PST 24
Peak memory 237056 kb
Host smart-fdeb7448-0512-461f-85bb-95582402f147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836444695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2836444695
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3024362425
Short name T789
Test name
Test status
Simulation time 15578694451 ps
CPU time 85.7 seconds
Started Feb 04 02:36:45 PM PST 24
Finished Feb 04 02:38:20 PM PST 24
Peak memory 251252 kb
Host smart-c8797d20-97a9-41d9-aa22-94c01cd507d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024362425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3024362425
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.690690678
Short name T125
Test name
Test status
Simulation time 2033504644 ps
CPU time 9.99 seconds
Started Feb 04 02:37:04 PM PST 24
Finished Feb 04 02:37:18 PM PST 24
Peak memory 239928 kb
Host smart-291a6085-f685-4612-966b-1e779a39049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690690678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.690690678
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2720789119
Short name T657
Test name
Test status
Simulation time 243267034 ps
CPU time 4.11 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:37:00 PM PST 24
Peak memory 224596 kb
Host smart-a7677a32-073f-4817-8b18-73f2c73c06bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720789119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2720789119
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3898983574
Short name T648
Test name
Test status
Simulation time 17580436563 ps
CPU time 45.94 seconds
Started Feb 04 02:37:04 PM PST 24
Finished Feb 04 02:37:54 PM PST 24
Peak memory 240908 kb
Host smart-c723b214-104b-4a54-91e2-4daef76e7cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898983574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3898983574
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.330221826
Short name T720
Test name
Test status
Simulation time 1407909449 ps
CPU time 2.36 seconds
Started Feb 04 02:37:04 PM PST 24
Finished Feb 04 02:37:10 PM PST 24
Peak memory 216364 kb
Host smart-f3fb1b56-4381-4b6c-8ec3-d4b0715ae409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330221826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.330221826
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.328881849
Short name T1066
Test name
Test status
Simulation time 1608771305 ps
CPU time 5.93 seconds
Started Feb 04 02:36:54 PM PST 24
Finished Feb 04 02:37:05 PM PST 24
Peak memory 222536 kb
Host smart-b922c30c-c3cf-4296-81ca-bb22480e582c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=328881849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.328881849
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.503856583
Short name T435
Test name
Test status
Simulation time 56126553 ps
CPU time 1.17 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:36:56 PM PST 24
Peak memory 207408 kb
Host smart-5bf29975-a286-4be7-b386-fbef22df0c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503856583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.503856583
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2356581357
Short name T674
Test name
Test status
Simulation time 1970041337 ps
CPU time 29.47 seconds
Started Feb 04 02:37:04 PM PST 24
Finished Feb 04 02:37:37 PM PST 24
Peak memory 216372 kb
Host smart-24db7b3a-79a9-4c4c-a1c3-c29908e76a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356581357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2356581357
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3047840344
Short name T1052
Test name
Test status
Simulation time 16495169659 ps
CPU time 13.99 seconds
Started Feb 04 02:36:50 PM PST 24
Finished Feb 04 02:37:11 PM PST 24
Peak memory 217268 kb
Host smart-350c346f-40b3-41f1-a13f-8aa44cebdf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047840344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3047840344
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3150410262
Short name T652
Test name
Test status
Simulation time 87703037 ps
CPU time 2.27 seconds
Started Feb 04 02:36:47 PM PST 24
Finished Feb 04 02:36:57 PM PST 24
Peak memory 208640 kb
Host smart-32e128f2-54c5-4804-add9-4c9f347b45be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150410262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3150410262
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.264263974
Short name T302
Test name
Test status
Simulation time 333137332 ps
CPU time 1.02 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:36:57 PM PST 24
Peak memory 205448 kb
Host smart-df7e5bc6-6599-4a72-8b6f-dc797c08e9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264263974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.264263974
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1777820672
Short name T878
Test name
Test status
Simulation time 109539007 ps
CPU time 2.53 seconds
Started Feb 04 02:36:54 PM PST 24
Finished Feb 04 02:37:02 PM PST 24
Peak memory 233648 kb
Host smart-09a9a164-6e36-4f51-9e4d-2209e90505c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777820672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1777820672
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1139461689
Short name T940
Test name
Test status
Simulation time 19188669 ps
CPU time 0.68 seconds
Started Feb 04 02:36:57 PM PST 24
Finished Feb 04 02:37:01 PM PST 24
Peak memory 205268 kb
Host smart-7c373860-451b-4902-8665-1eab5e6fc6a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139461689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1139461689
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4179772215
Short name T741
Test name
Test status
Simulation time 591961848 ps
CPU time 3.51 seconds
Started Feb 04 02:36:58 PM PST 24
Finished Feb 04 02:37:04 PM PST 24
Peak memory 233532 kb
Host smart-26be6cde-c8a4-4935-9bee-42953d9559af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179772215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4179772215
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2915512517
Short name T595
Test name
Test status
Simulation time 18943647 ps
CPU time 0.82 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:36:59 PM PST 24
Peak memory 205128 kb
Host smart-52046f5e-a91b-404d-af6a-ad6e41791298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915512517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2915512517
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2577021127
Short name T732
Test name
Test status
Simulation time 5310231455 ps
CPU time 25.74 seconds
Started Feb 04 02:36:57 PM PST 24
Finished Feb 04 02:37:26 PM PST 24
Peak memory 232880 kb
Host smart-7390b097-0693-4437-886f-c073e88c8994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577021127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2577021127
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.847838413
Short name T968
Test name
Test status
Simulation time 8964776824 ps
CPU time 91.4 seconds
Started Feb 04 02:36:54 PM PST 24
Finished Feb 04 02:38:31 PM PST 24
Peak memory 264424 kb
Host smart-ebbac6c5-2dc9-47d1-b564-c28140d6aef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847838413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.847838413
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1429594798
Short name T250
Test name
Test status
Simulation time 182822883978 ps
CPU time 536.56 seconds
Started Feb 04 02:37:02 PM PST 24
Finished Feb 04 02:46:01 PM PST 24
Peak memory 253704 kb
Host smart-2e045f9f-ef8f-4cc6-8c67-21cc02c4ab97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429594798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1429594798
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1881909354
Short name T726
Test name
Test status
Simulation time 4622178095 ps
CPU time 15.27 seconds
Started Feb 04 02:37:07 PM PST 24
Finished Feb 04 02:37:24 PM PST 24
Peak memory 232668 kb
Host smart-c0f1c6d2-fa63-4ba5-8afa-b088d620a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881909354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1881909354
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2557637470
Short name T619
Test name
Test status
Simulation time 930873385 ps
CPU time 7.75 seconds
Started Feb 04 02:36:58 PM PST 24
Finished Feb 04 02:37:08 PM PST 24
Peak memory 233376 kb
Host smart-edf82097-bc67-4853-b457-944b96103c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557637470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2557637470
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3961969312
Short name T1033
Test name
Test status
Simulation time 78482092466 ps
CPU time 57.43 seconds
Started Feb 04 02:36:51 PM PST 24
Finished Feb 04 02:37:55 PM PST 24
Peak memory 240132 kb
Host smart-5f73dafe-0e9c-4e31-9908-49749c53141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961969312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3961969312
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3553881822
Short name T721
Test name
Test status
Simulation time 9184037720 ps
CPU time 12.27 seconds
Started Feb 04 02:36:58 PM PST 24
Finished Feb 04 02:37:13 PM PST 24
Peak memory 233528 kb
Host smart-90abdfec-1700-4e0f-8e73-4f9d5f71fda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553881822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3553881822
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3045463008
Short name T434
Test name
Test status
Simulation time 18497075787 ps
CPU time 49.13 seconds
Started Feb 04 02:37:04 PM PST 24
Finished Feb 04 02:37:57 PM PST 24
Peak memory 233356 kb
Host smart-0551641c-af10-4d23-b619-bfb6f8efaa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045463008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3045463008
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3822089834
Short name T981
Test name
Test status
Simulation time 3832572002 ps
CPU time 5.47 seconds
Started Feb 04 02:36:56 PM PST 24
Finished Feb 04 02:37:05 PM PST 24
Peak memory 222916 kb
Host smart-76a50865-83f0-4dd6-aa7e-f1d1bb6beebf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3822089834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3822089834
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3599968519
Short name T1076
Test name
Test status
Simulation time 165578852 ps
CPU time 0.99 seconds
Started Feb 04 02:36:54 PM PST 24
Finished Feb 04 02:37:00 PM PST 24
Peak memory 205392 kb
Host smart-c85b452d-87ef-446a-b238-85ab26d66176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599968519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3599968519
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3792009493
Short name T1082
Test name
Test status
Simulation time 30223115194 ps
CPU time 32.35 seconds
Started Feb 04 02:36:49 PM PST 24
Finished Feb 04 02:37:28 PM PST 24
Peak memory 219736 kb
Host smart-0163e939-1794-4c5c-bc34-874ab336fca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792009493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3792009493
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3783545227
Short name T1032
Test name
Test status
Simulation time 10260847767 ps
CPU time 28.87 seconds
Started Feb 04 02:37:04 PM PST 24
Finished Feb 04 02:37:37 PM PST 24
Peak memory 216436 kb
Host smart-ccb18b5c-4863-4a91-a9c1-34517e003f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783545227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3783545227
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3489831902
Short name T633
Test name
Test status
Simulation time 65921319 ps
CPU time 1.08 seconds
Started Feb 04 02:36:58 PM PST 24
Finished Feb 04 02:37:01 PM PST 24
Peak memory 206972 kb
Host smart-21fbb560-0926-4a67-bbde-3858b0c91327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489831902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3489831902
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2792473721
Short name T884
Test name
Test status
Simulation time 695301855 ps
CPU time 1.07 seconds
Started Feb 04 02:36:45 PM PST 24
Finished Feb 04 02:36:56 PM PST 24
Peak memory 206480 kb
Host smart-7a78ed1e-e72f-4ed2-89b8-e4ed64370aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792473721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2792473721
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2522714399
Short name T723
Test name
Test status
Simulation time 702391717 ps
CPU time 3.69 seconds
Started Feb 04 02:37:01 PM PST 24
Finished Feb 04 02:37:06 PM PST 24
Peak memory 235828 kb
Host smart-ca4e51c5-edcc-4109-9f4a-d048e06010da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522714399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2522714399
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3882988877
Short name T756
Test name
Test status
Simulation time 27761996 ps
CPU time 0.73 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:37:34 PM PST 24
Peak memory 204816 kb
Host smart-e544fbff-b9eb-4f84-9c61-4765bd1bab4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882988877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3882988877
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3878708093
Short name T211
Test name
Test status
Simulation time 110138934 ps
CPU time 2.58 seconds
Started Feb 04 02:36:56 PM PST 24
Finished Feb 04 02:37:02 PM PST 24
Peak memory 217080 kb
Host smart-b5954d29-3755-4560-9f26-d14819a4149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878708093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3878708093
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1670537940
Short name T768
Test name
Test status
Simulation time 28039938 ps
CPU time 0.76 seconds
Started Feb 04 02:37:00 PM PST 24
Finished Feb 04 02:37:02 PM PST 24
Peak memory 205116 kb
Host smart-1f6be8ba-8715-444c-8bad-146149908d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670537940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1670537940
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2234030584
Short name T521
Test name
Test status
Simulation time 31872395314 ps
CPU time 62.59 seconds
Started Feb 04 02:36:58 PM PST 24
Finished Feb 04 02:38:03 PM PST 24
Peak memory 249256 kb
Host smart-797af225-fc47-45a7-a5eb-84ac8ee20287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234030584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2234030584
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.555364362
Short name T680
Test name
Test status
Simulation time 8232634860 ps
CPU time 59.32 seconds
Started Feb 04 02:36:54 PM PST 24
Finished Feb 04 02:37:59 PM PST 24
Peak memory 221432 kb
Host smart-a673f78f-1add-46af-badd-f5b95298831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555364362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.555364362
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3000693221
Short name T815
Test name
Test status
Simulation time 1830323247 ps
CPU time 13.2 seconds
Started Feb 04 02:37:01 PM PST 24
Finished Feb 04 02:37:16 PM PST 24
Peak memory 233548 kb
Host smart-dc78f218-b302-4067-8767-0c85922c20a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000693221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3000693221
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.410462466
Short name T44
Test name
Test status
Simulation time 361548943 ps
CPU time 4.88 seconds
Started Feb 04 02:36:56 PM PST 24
Finished Feb 04 02:37:05 PM PST 24
Peak memory 233616 kb
Host smart-779f8497-57e8-420b-a039-13b5a526a7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410462466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.410462466
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3430105303
Short name T232
Test name
Test status
Simulation time 215707338806 ps
CPU time 46.39 seconds
Started Feb 04 02:36:55 PM PST 24
Finished Feb 04 02:37:46 PM PST 24
Peak memory 233708 kb
Host smart-4d01fc91-4670-47f5-a8c1-9a9bb3d0f167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430105303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3430105303
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3328265886
Short name T242
Test name
Test status
Simulation time 505764885 ps
CPU time 5.41 seconds
Started Feb 04 02:37:00 PM PST 24
Finished Feb 04 02:37:07 PM PST 24
Peak memory 238128 kb
Host smart-5b955047-5719-4c5d-90aa-b7e4c57729dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328265886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3328265886
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1640446232
Short name T810
Test name
Test status
Simulation time 10029315410 ps
CPU time 25.58 seconds
Started Feb 04 02:37:07 PM PST 24
Finished Feb 04 02:37:35 PM PST 24
Peak memory 219324 kb
Host smart-b2b62f68-68ac-45d1-bbe1-9dc4e02be632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640446232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1640446232
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2293129722
Short name T786
Test name
Test status
Simulation time 1679960951 ps
CPU time 3.49 seconds
Started Feb 04 02:37:04 PM PST 24
Finished Feb 04 02:37:11 PM PST 24
Peak memory 219044 kb
Host smart-fb5c6f8e-78cf-41cd-886a-3e739840f599
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2293129722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2293129722
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1267401130
Short name T467
Test name
Test status
Simulation time 33402092 ps
CPU time 0.87 seconds
Started Feb 04 02:36:53 PM PST 24
Finished Feb 04 02:37:00 PM PST 24
Peak memory 205420 kb
Host smart-142ee34a-be91-47ae-b102-a8d2b77466a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267401130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1267401130
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.492412204
Short name T888
Test name
Test status
Simulation time 393460275 ps
CPU time 6.01 seconds
Started Feb 04 02:37:02 PM PST 24
Finished Feb 04 02:37:10 PM PST 24
Peak memory 216328 kb
Host smart-893eaa8c-8351-4e2c-8a08-78fc7f3fe393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492412204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.492412204
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.337512101
Short name T923
Test name
Test status
Simulation time 34645952116 ps
CPU time 21.54 seconds
Started Feb 04 02:36:55 PM PST 24
Finished Feb 04 02:37:21 PM PST 24
Peak memory 216448 kb
Host smart-51327ea4-4851-471f-adb1-b61c24d3df7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337512101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.337512101
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3980228294
Short name T574
Test name
Test status
Simulation time 81087666 ps
CPU time 1.61 seconds
Started Feb 04 02:37:07 PM PST 24
Finished Feb 04 02:37:11 PM PST 24
Peak memory 217656 kb
Host smart-e644bf69-7e32-4718-88f4-ef5957c66208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980228294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3980228294
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3396988230
Short name T627
Test name
Test status
Simulation time 108101568 ps
CPU time 0.99 seconds
Started Feb 04 02:36:56 PM PST 24
Finished Feb 04 02:37:01 PM PST 24
Peak memory 205448 kb
Host smart-0ef9e0de-7db4-40d7-857b-a569f1b03dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396988230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3396988230
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1162814320
Short name T760
Test name
Test status
Simulation time 10027747631 ps
CPU time 29.75 seconds
Started Feb 04 02:36:57 PM PST 24
Finished Feb 04 02:37:30 PM PST 24
Peak memory 232820 kb
Host smart-aa753909-2dcf-41b8-98af-148a7d9c5822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162814320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1162814320
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.506294547
Short name T1075
Test name
Test status
Simulation time 130076487 ps
CPU time 0.72 seconds
Started Feb 04 02:37:09 PM PST 24
Finished Feb 04 02:37:11 PM PST 24
Peak memory 204936 kb
Host smart-e562256a-b212-49df-9bee-f7215aea38d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506294547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.506294547
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.165695343
Short name T714
Test name
Test status
Simulation time 1005236883 ps
CPU time 3.74 seconds
Started Feb 04 02:37:10 PM PST 24
Finished Feb 04 02:37:15 PM PST 24
Peak memory 233752 kb
Host smart-f77212c5-1683-4fb5-8a7a-a8ef8eacb748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165695343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.165695343
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.804473827
Short name T874
Test name
Test status
Simulation time 19705504 ps
CPU time 0.76 seconds
Started Feb 04 02:37:10 PM PST 24
Finished Feb 04 02:37:12 PM PST 24
Peak memory 205140 kb
Host smart-de86c97a-b7cf-4658-bc6f-21c2cb829aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804473827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.804473827
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3182072687
Short name T249
Test name
Test status
Simulation time 103372686341 ps
CPU time 483.41 seconds
Started Feb 04 02:37:22 PM PST 24
Finished Feb 04 02:45:27 PM PST 24
Peak memory 264700 kb
Host smart-3c00ef11-f34f-4bc3-a3e0-bbbd5ae6da38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182072687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3182072687
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.456549719
Short name T1013
Test name
Test status
Simulation time 60557893814 ps
CPU time 451.93 seconds
Started Feb 04 02:37:18 PM PST 24
Finished Feb 04 02:44:51 PM PST 24
Peak memory 263608 kb
Host smart-da97d973-3efe-4d32-aa7a-7dd5cd11fadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456549719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.456549719
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2755367053
Short name T642
Test name
Test status
Simulation time 34339061392 ps
CPU time 121.58 seconds
Started Feb 04 02:37:26 PM PST 24
Finished Feb 04 02:39:35 PM PST 24
Peak memory 239124 kb
Host smart-559ae09d-53f9-43ba-93fc-26588268120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755367053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2755367053
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1536993727
Short name T1070
Test name
Test status
Simulation time 25741337199 ps
CPU time 58.69 seconds
Started Feb 04 02:37:16 PM PST 24
Finished Feb 04 02:38:17 PM PST 24
Peak memory 256624 kb
Host smart-c749e2f3-f6dd-4d48-b188-8a1513e8ec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536993727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1536993727
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2000934306
Short name T550
Test name
Test status
Simulation time 1031883634 ps
CPU time 6.51 seconds
Started Feb 04 02:37:09 PM PST 24
Finished Feb 04 02:37:17 PM PST 24
Peak memory 218804 kb
Host smart-f881bc64-9cf7-460a-81a0-66fe536ae44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000934306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2000934306
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2926698590
Short name T710
Test name
Test status
Simulation time 43035185257 ps
CPU time 32.63 seconds
Started Feb 04 02:37:21 PM PST 24
Finished Feb 04 02:37:55 PM PST 24
Peak memory 249080 kb
Host smart-9b0786a0-23ad-4679-81d2-dabb251df9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926698590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2926698590
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3783489393
Short name T1105
Test name
Test status
Simulation time 202304981 ps
CPU time 2.83 seconds
Started Feb 04 02:37:09 PM PST 24
Finished Feb 04 02:37:13 PM PST 24
Peak memory 217916 kb
Host smart-85268a1b-3be4-45e4-a1dd-8fd72422baae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783489393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3783489393
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1250869293
Short name T528
Test name
Test status
Simulation time 4825356346 ps
CPU time 8.76 seconds
Started Feb 04 02:37:23 PM PST 24
Finished Feb 04 02:37:33 PM PST 24
Peak memory 233260 kb
Host smart-aa6b9665-f540-449f-8e61-51fae5a99d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250869293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1250869293
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2066933134
Short name T300
Test name
Test status
Simulation time 728741359 ps
CPU time 3.95 seconds
Started Feb 04 02:37:14 PM PST 24
Finished Feb 04 02:37:21 PM PST 24
Peak memory 218760 kb
Host smart-a6d4cfa9-48e9-45fc-96fc-d8cb1e53a9a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2066933134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2066933134
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.4286092187
Short name T118
Test name
Test status
Simulation time 5045189760 ps
CPU time 85.55 seconds
Started Feb 04 02:37:19 PM PST 24
Finished Feb 04 02:38:46 PM PST 24
Peak memory 254700 kb
Host smart-1185ee12-13d1-4c17-843d-ae299682e81a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286092187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.4286092187
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4265529009
Short name T852
Test name
Test status
Simulation time 6427227004 ps
CPU time 27.62 seconds
Started Feb 04 02:37:19 PM PST 24
Finished Feb 04 02:37:48 PM PST 24
Peak memory 216496 kb
Host smart-cd3a7916-ea71-4e13-825f-013076709c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265529009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4265529009
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1686546898
Short name T887
Test name
Test status
Simulation time 2883021075 ps
CPU time 6.99 seconds
Started Feb 04 02:37:17 PM PST 24
Finished Feb 04 02:37:26 PM PST 24
Peak memory 216240 kb
Host smart-1fdaceca-c00b-4276-a3c3-417980be6b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686546898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1686546898
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1483133049
Short name T427
Test name
Test status
Simulation time 64974899 ps
CPU time 1.1 seconds
Started Feb 04 02:37:19 PM PST 24
Finished Feb 04 02:37:21 PM PST 24
Peak memory 207976 kb
Host smart-d9fe1dd5-2d85-446b-9dd7-7e5686aa3d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483133049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1483133049
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1640785381
Short name T744
Test name
Test status
Simulation time 106013835 ps
CPU time 1.02 seconds
Started Feb 04 02:37:23 PM PST 24
Finished Feb 04 02:37:25 PM PST 24
Peak memory 206412 kb
Host smart-25bd0d5a-b620-49c3-be13-a5c42e6e989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640785381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1640785381
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2505970605
Short name T1010
Test name
Test status
Simulation time 59820738464 ps
CPU time 14.46 seconds
Started Feb 04 02:37:26 PM PST 24
Finished Feb 04 02:37:48 PM PST 24
Peak memory 234376 kb
Host smart-5ecd7264-b4d2-4bc5-8207-501a055acaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505970605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2505970605
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.789040729
Short name T649
Test name
Test status
Simulation time 72158554 ps
CPU time 0.71 seconds
Started Feb 04 02:37:23 PM PST 24
Finished Feb 04 02:37:25 PM PST 24
Peak memory 204928 kb
Host smart-61fe422b-66e2-445d-be9d-9a05dd82e66e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789040729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.789040729
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3239290422
Short name T646
Test name
Test status
Simulation time 193790474 ps
CPU time 3.45 seconds
Started Feb 04 02:37:24 PM PST 24
Finished Feb 04 02:37:28 PM PST 24
Peak memory 233620 kb
Host smart-019621d7-fb7b-4a43-ac48-83ac2d6cafcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239290422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3239290422
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.166634873
Short name T813
Test name
Test status
Simulation time 52593713 ps
CPU time 0.77 seconds
Started Feb 04 02:37:26 PM PST 24
Finished Feb 04 02:37:34 PM PST 24
Peak memory 205472 kb
Host smart-e5ec08ff-7f98-4fdb-956c-60b1433f68e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166634873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.166634873
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.21908940
Short name T231
Test name
Test status
Simulation time 26442116780 ps
CPU time 30.31 seconds
Started Feb 04 02:37:18 PM PST 24
Finished Feb 04 02:37:50 PM PST 24
Peak memory 247084 kb
Host smart-c5ca9269-4539-47c8-a483-421af70ee642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21908940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.21908940
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1281374888
Short name T840
Test name
Test status
Simulation time 9998073359 ps
CPU time 55.39 seconds
Started Feb 04 02:37:24 PM PST 24
Finished Feb 04 02:38:24 PM PST 24
Peak memory 241056 kb
Host smart-2505280e-3ad4-43e8-80ac-5926a481c4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281374888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1281374888
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.815855555
Short name T144
Test name
Test status
Simulation time 8062079824 ps
CPU time 81.32 seconds
Started Feb 04 02:37:20 PM PST 24
Finished Feb 04 02:38:42 PM PST 24
Peak memory 249596 kb
Host smart-13382d30-70e8-466c-bd67-65716101b795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815855555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.815855555
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1426872114
Short name T750
Test name
Test status
Simulation time 5173386900 ps
CPU time 12.94 seconds
Started Feb 04 02:37:19 PM PST 24
Finished Feb 04 02:37:33 PM PST 24
Peak memory 231696 kb
Host smart-9b2d4c8f-4f2a-4359-b67a-b42423042c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426872114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1426872114
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2336852056
Short name T1103
Test name
Test status
Simulation time 450556212 ps
CPU time 5.5 seconds
Started Feb 04 02:37:25 PM PST 24
Finished Feb 04 02:37:37 PM PST 24
Peak memory 219080 kb
Host smart-4633dfab-bc83-4858-9b45-749518393d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336852056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2336852056
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1489399008
Short name T445
Test name
Test status
Simulation time 2470855293 ps
CPU time 5.11 seconds
Started Feb 04 02:37:29 PM PST 24
Finished Feb 04 02:37:39 PM PST 24
Peak memory 232596 kb
Host smart-2778c431-9b20-4d2a-8fe5-55b772053b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489399008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1489399008
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3066974769
Short name T960
Test name
Test status
Simulation time 1353133648 ps
CPU time 4.66 seconds
Started Feb 04 02:37:08 PM PST 24
Finished Feb 04 02:37:14 PM PST 24
Peak memory 220076 kb
Host smart-0ce43207-05f5-4556-a0e4-57b18b86d24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066974769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3066974769
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.42530504
Short name T868
Test name
Test status
Simulation time 2943591008 ps
CPU time 7.41 seconds
Started Feb 04 02:37:16 PM PST 24
Finished Feb 04 02:37:26 PM PST 24
Peak memory 232872 kb
Host smart-25e44cf9-c625-4bb8-98ca-614d0ea7c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42530504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.42530504
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.14562654
Short name T1022
Test name
Test status
Simulation time 1796736243 ps
CPU time 6.79 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:37:40 PM PST 24
Peak memory 221968 kb
Host smart-902647ce-be7e-4b63-aa90-b1fe5402321c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=14562654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direc
t.14562654
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.516426646
Short name T191
Test name
Test status
Simulation time 404232996327 ps
CPU time 846.85 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:51:41 PM PST 24
Peak memory 269940 kb
Host smart-a655da95-b277-48cb-8892-54dea2c077d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516426646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.516426646
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2373057500
Short name T305
Test name
Test status
Simulation time 3527015962 ps
CPU time 23.9 seconds
Started Feb 04 02:37:16 PM PST 24
Finished Feb 04 02:37:42 PM PST 24
Peak memory 216444 kb
Host smart-29c8e2de-edf0-4b8c-9126-40b65c78880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373057500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2373057500
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2935792273
Short name T1056
Test name
Test status
Simulation time 1831844459 ps
CPU time 6.01 seconds
Started Feb 04 02:37:23 PM PST 24
Finished Feb 04 02:37:30 PM PST 24
Peak memory 208264 kb
Host smart-d17b309f-0880-4632-af04-cfbe8f435c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935792273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2935792273
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1980853931
Short name T807
Test name
Test status
Simulation time 1770637528 ps
CPU time 1.85 seconds
Started Feb 04 02:37:23 PM PST 24
Finished Feb 04 02:37:27 PM PST 24
Peak memory 208520 kb
Host smart-56761037-3e78-4a32-990e-b4f322beff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980853931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1980853931
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2761984004
Short name T782
Test name
Test status
Simulation time 132290576 ps
CPU time 0.81 seconds
Started Feb 04 02:37:17 PM PST 24
Finished Feb 04 02:37:20 PM PST 24
Peak memory 205460 kb
Host smart-3d9326f5-367e-40f0-8022-4a9216b6e45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761984004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2761984004
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1647214507
Short name T625
Test name
Test status
Simulation time 38905312278 ps
CPU time 35.08 seconds
Started Feb 04 02:37:23 PM PST 24
Finished Feb 04 02:37:59 PM PST 24
Peak memory 236460 kb
Host smart-a06f993b-8456-457d-befe-e3ef468c6f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647214507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1647214507
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1110364125
Short name T763
Test name
Test status
Simulation time 19191849 ps
CPU time 0.72 seconds
Started Feb 04 02:37:18 PM PST 24
Finished Feb 04 02:37:20 PM PST 24
Peak memory 204368 kb
Host smart-7543cf06-69b4-49fd-a7bf-37aa86ec483a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110364125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1110364125
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2572855343
Short name T1109
Test name
Test status
Simulation time 1167377960 ps
CPU time 2.69 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:37:36 PM PST 24
Peak memory 224488 kb
Host smart-cb504143-6e9d-4e10-bb91-88d246de806b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572855343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2572855343
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1068852541
Short name T608
Test name
Test status
Simulation time 34614133 ps
CPU time 0.81 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:37:34 PM PST 24
Peak memory 206204 kb
Host smart-5a385443-8855-407c-8808-1e4aeb5a7179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068852541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1068852541
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3684220464
Short name T566
Test name
Test status
Simulation time 45382340632 ps
CPU time 89.9 seconds
Started Feb 04 02:37:28 PM PST 24
Finished Feb 04 02:39:04 PM PST 24
Peak memory 256684 kb
Host smart-fd9b0e26-af26-4811-a201-53f7a314d83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684220464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3684220464
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2979495216
Short name T166
Test name
Test status
Simulation time 16765838356 ps
CPU time 139.04 seconds
Started Feb 04 02:37:25 PM PST 24
Finished Feb 04 02:39:51 PM PST 24
Peak memory 252684 kb
Host smart-d2974a83-4f32-4e0d-916e-aaca725882ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979495216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2979495216
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_intercept.590744818
Short name T201
Test name
Test status
Simulation time 730729722 ps
CPU time 3.24 seconds
Started Feb 04 02:37:30 PM PST 24
Finished Feb 04 02:37:37 PM PST 24
Peak memory 217400 kb
Host smart-1a3c2411-9632-4467-b1dc-0903f1cced29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590744818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.590744818
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3762101688
Short name T740
Test name
Test status
Simulation time 82960666451 ps
CPU time 59.04 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:38:33 PM PST 24
Peak memory 230736 kb
Host smart-8faf9070-8c84-4fd8-88a0-9cab0162dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762101688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3762101688
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1528620907
Short name T228
Test name
Test status
Simulation time 948344075 ps
CPU time 6.81 seconds
Started Feb 04 02:37:25 PM PST 24
Finished Feb 04 02:37:38 PM PST 24
Peak memory 224604 kb
Host smart-f35292c2-fd49-45b2-bbe3-70118e24c36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528620907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1528620907
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.188805654
Short name T439
Test name
Test status
Simulation time 10092311192 ps
CPU time 15.08 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:37:49 PM PST 24
Peak memory 224564 kb
Host smart-ede0942a-8db5-482f-a085-57a983b5a974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188805654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.188805654
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2014754158
Short name T988
Test name
Test status
Simulation time 147063984 ps
CPU time 2.96 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:37:37 PM PST 24
Peak memory 219004 kb
Host smart-01d0387b-4f43-461d-9f95-cef7496bbd40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2014754158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2014754158
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3009822075
Short name T148
Test name
Test status
Simulation time 60530660717 ps
CPU time 190.09 seconds
Started Feb 04 02:37:29 PM PST 24
Finished Feb 04 02:40:44 PM PST 24
Peak memory 273880 kb
Host smart-e11435d9-892e-4cf1-8ade-3a6db9d47fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009822075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3009822075
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3983254140
Short name T461
Test name
Test status
Simulation time 40427800922 ps
CPU time 63.66 seconds
Started Feb 04 02:37:29 PM PST 24
Finished Feb 04 02:38:37 PM PST 24
Peak memory 216472 kb
Host smart-06ebbf5f-d50c-4ef4-aa92-f5e2ce6af711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983254140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3983254140
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3645045928
Short name T792
Test name
Test status
Simulation time 1194883033 ps
CPU time 4.88 seconds
Started Feb 04 02:37:30 PM PST 24
Finished Feb 04 02:37:39 PM PST 24
Peak memory 216344 kb
Host smart-a470ea05-2835-4031-9368-680ce0ece2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645045928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3645045928
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2464846427
Short name T303
Test name
Test status
Simulation time 43254875 ps
CPU time 1.49 seconds
Started Feb 04 02:37:23 PM PST 24
Finished Feb 04 02:37:26 PM PST 24
Peak memory 208436 kb
Host smart-5d1186cb-56a1-45d7-b132-51a33f03bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464846427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2464846427
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2452580994
Short name T838
Test name
Test status
Simulation time 203143056 ps
CPU time 0.73 seconds
Started Feb 04 02:37:25 PM PST 24
Finished Feb 04 02:37:32 PM PST 24
Peak memory 205404 kb
Host smart-9a933163-b81c-4337-8ad5-525775198b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452580994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2452580994
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.662135348
Short name T950
Test name
Test status
Simulation time 2629664913 ps
CPU time 6.38 seconds
Started Feb 04 02:37:20 PM PST 24
Finished Feb 04 02:37:28 PM PST 24
Peak memory 234164 kb
Host smart-da141263-e6ce-4979-af8a-e6384e455fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662135348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.662135348
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3802480697
Short name T828
Test name
Test status
Simulation time 14739664 ps
CPU time 0.76 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:37:34 PM PST 24
Peak memory 205248 kb
Host smart-67641432-9b18-472e-b863-8b2a9fa3f763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802480697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3802480697
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1686230346
Short name T629
Test name
Test status
Simulation time 338241569 ps
CPU time 3.35 seconds
Started Feb 04 02:37:30 PM PST 24
Finished Feb 04 02:37:37 PM PST 24
Peak memory 224592 kb
Host smart-1c84b155-1eb4-4778-a7df-63507378e996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686230346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1686230346
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3613878485
Short name T492
Test name
Test status
Simulation time 15397647 ps
CPU time 0.81 seconds
Started Feb 04 02:37:26 PM PST 24
Finished Feb 04 02:37:34 PM PST 24
Peak memory 205192 kb
Host smart-89a3c8d5-e7fb-4f4e-9168-4fa02a7aa010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613878485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3613878485
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3359218019
Short name T687
Test name
Test status
Simulation time 19325048776 ps
CPU time 91.42 seconds
Started Feb 04 02:37:26 PM PST 24
Finished Feb 04 02:39:05 PM PST 24
Peak memory 237884 kb
Host smart-a7215e30-9f7e-4fa2-9817-525bc2225e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359218019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3359218019
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2830588977
Short name T643
Test name
Test status
Simulation time 6661790672 ps
CPU time 73.23 seconds
Started Feb 04 02:37:29 PM PST 24
Finished Feb 04 02:38:47 PM PST 24
Peak memory 262948 kb
Host smart-fac95eef-35cf-4dec-9f37-ab532fb4dabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830588977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2830588977
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1454177191
Short name T230
Test name
Test status
Simulation time 16810951800 ps
CPU time 35.04 seconds
Started Feb 04 02:37:28 PM PST 24
Finished Feb 04 02:38:09 PM PST 24
Peak memory 223428 kb
Host smart-10467baf-121d-4cbf-a2ee-a73c4063621a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454177191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1454177191
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.751128271
Short name T1072
Test name
Test status
Simulation time 11937404114 ps
CPU time 30.69 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:38:04 PM PST 24
Peak memory 239284 kb
Host smart-fb077ebf-2549-41b4-afb9-85ece6c394e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751128271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.751128271
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1516204786
Short name T647
Test name
Test status
Simulation time 697073011 ps
CPU time 5.71 seconds
Started Feb 04 02:37:31 PM PST 24
Finished Feb 04 02:37:41 PM PST 24
Peak memory 233524 kb
Host smart-59baf7c2-16ac-4a57-bd57-dad117343e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516204786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1516204786
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3632154877
Short name T200
Test name
Test status
Simulation time 7360507202 ps
CPU time 7.56 seconds
Started Feb 04 02:37:30 PM PST 24
Finished Feb 04 02:37:42 PM PST 24
Peak memory 233392 kb
Host smart-01e918ae-feeb-4d35-9fb4-66149a7928ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632154877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3632154877
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2246225712
Short name T992
Test name
Test status
Simulation time 4176456278 ps
CPU time 15.41 seconds
Started Feb 04 02:37:30 PM PST 24
Finished Feb 04 02:37:49 PM PST 24
Peak memory 238120 kb
Host smart-52e23e15-020e-4b0a-a5c6-5bd5963b510c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246225712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2246225712
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.997073257
Short name T209
Test name
Test status
Simulation time 8684074896 ps
CPU time 17.68 seconds
Started Feb 04 02:37:31 PM PST 24
Finished Feb 04 02:37:53 PM PST 24
Peak memory 235280 kb
Host smart-3b024429-5e6d-4b95-b5a3-885ce1f208e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997073257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.997073257
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1188925774
Short name T1063
Test name
Test status
Simulation time 246114714 ps
CPU time 4.04 seconds
Started Feb 04 02:37:33 PM PST 24
Finished Feb 04 02:37:42 PM PST 24
Peak memory 222708 kb
Host smart-232c412b-6521-435b-a7c0-bd0d669ae98e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1188925774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1188925774
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.748053703
Short name T666
Test name
Test status
Simulation time 11722716506 ps
CPU time 123.2 seconds
Started Feb 04 02:37:28 PM PST 24
Finished Feb 04 02:39:37 PM PST 24
Peak memory 250916 kb
Host smart-fd6086c9-a0a4-49ec-b81f-5a46f1f431f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748053703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.748053703
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2147384359
Short name T21
Test name
Test status
Simulation time 17712246197 ps
CPU time 41.36 seconds
Started Feb 04 02:37:30 PM PST 24
Finished Feb 04 02:38:15 PM PST 24
Peak memory 216344 kb
Host smart-77fc851e-9835-4a41-87dc-d4c1651de09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147384359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2147384359
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2002716543
Short name T292
Test name
Test status
Simulation time 603095112 ps
CPU time 3.69 seconds
Started Feb 04 02:37:24 PM PST 24
Finished Feb 04 02:37:29 PM PST 24
Peak memory 208220 kb
Host smart-c7f9a3f0-82be-4fb9-b18f-b0c6df2ca8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002716543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2002716543
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1437928297
Short name T901
Test name
Test status
Simulation time 63226108 ps
CPU time 0.92 seconds
Started Feb 04 02:37:29 PM PST 24
Finished Feb 04 02:37:35 PM PST 24
Peak memory 206152 kb
Host smart-f38cbb7b-dde1-470a-9c5b-3ada5f9fcb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437928297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1437928297
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2485047576
Short name T455
Test name
Test status
Simulation time 501791463 ps
CPU time 1.03 seconds
Started Feb 04 02:37:30 PM PST 24
Finished Feb 04 02:37:35 PM PST 24
Peak memory 206460 kb
Host smart-adf4f987-95d3-4c7c-a0d2-bc03b13e30a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485047576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2485047576
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.300836351
Short name T830
Test name
Test status
Simulation time 719655826 ps
CPU time 3.49 seconds
Started Feb 04 02:37:27 PM PST 24
Finished Feb 04 02:37:37 PM PST 24
Peak memory 233728 kb
Host smart-4f507706-e45f-4049-b88e-8224a2421ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300836351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.300836351
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3449662265
Short name T975
Test name
Test status
Simulation time 58158278 ps
CPU time 0.75 seconds
Started Feb 04 02:37:33 PM PST 24
Finished Feb 04 02:37:39 PM PST 24
Peak memory 205320 kb
Host smart-6a89e85d-d55a-4646-bb1b-e59611613f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449662265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3449662265
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2921854783
Short name T236
Test name
Test status
Simulation time 133192898 ps
CPU time 3.28 seconds
Started Feb 04 02:37:38 PM PST 24
Finished Feb 04 02:37:44 PM PST 24
Peak memory 233620 kb
Host smart-67a0e891-7d4f-4b69-a530-f5b5145e06be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921854783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2921854783
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2588491107
Short name T471
Test name
Test status
Simulation time 60777675 ps
CPU time 0.79 seconds
Started Feb 04 02:37:26 PM PST 24
Finished Feb 04 02:37:34 PM PST 24
Peak memory 206212 kb
Host smart-62bcc9e9-ebe4-4706-a7ef-806419474f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588491107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2588491107
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3003667795
Short name T734
Test name
Test status
Simulation time 62827245586 ps
CPU time 414.82 seconds
Started Feb 04 02:37:42 PM PST 24
Finished Feb 04 02:44:43 PM PST 24
Peak memory 253944 kb
Host smart-dab87ac8-869c-4b8a-b0e9-40060f7478f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003667795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3003667795
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3613987157
Short name T1090
Test name
Test status
Simulation time 14062338130 ps
CPU time 162.93 seconds
Started Feb 04 02:37:31 PM PST 24
Finished Feb 04 02:40:19 PM PST 24
Peak memory 273704 kb
Host smart-b787b3d1-2438-43bf-8910-371e80c5680c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613987157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3613987157
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4167120652
Short name T914
Test name
Test status
Simulation time 1337734243 ps
CPU time 8.89 seconds
Started Feb 04 02:37:33 PM PST 24
Finished Feb 04 02:37:47 PM PST 24
Peak memory 235532 kb
Host smart-89879af0-6928-4109-8df0-6d7d497ada59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167120652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4167120652
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1558108583
Short name T609
Test name
Test status
Simulation time 973010449 ps
CPU time 4.64 seconds
Started Feb 04 02:37:34 PM PST 24
Finished Feb 04 02:37:44 PM PST 24
Peak memory 233812 kb
Host smart-c0c3cb69-e953-49cd-8e36-ef1e307c5d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558108583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1558108583
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3463126756
Short name T186
Test name
Test status
Simulation time 15826288769 ps
CPU time 28.28 seconds
Started Feb 04 02:37:42 PM PST 24
Finished Feb 04 02:38:17 PM PST 24
Peak memory 240064 kb
Host smart-93c7ad2c-db10-4749-942c-cb291832ffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463126756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3463126756
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1482446521
Short name T554
Test name
Test status
Simulation time 3776272781 ps
CPU time 14.26 seconds
Started Feb 04 02:37:43 PM PST 24
Finished Feb 04 02:38:03 PM PST 24
Peak memory 232744 kb
Host smart-3ba2ff31-3f22-41a8-af08-9e587e44dcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482446521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1482446521
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1606013181
Short name T702
Test name
Test status
Simulation time 3288011639 ps
CPU time 5.61 seconds
Started Feb 04 02:37:40 PM PST 24
Finished Feb 04 02:37:47 PM PST 24
Peak memory 226524 kb
Host smart-5d31c6b0-9814-4f14-adb9-3b507a6ff731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606013181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1606013181
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.25331942
Short name T124
Test name
Test status
Simulation time 83041952 ps
CPU time 3.45 seconds
Started Feb 04 02:37:32 PM PST 24
Finished Feb 04 02:37:40 PM PST 24
Peak memory 221532 kb
Host smart-285cacd7-9b47-4c68-9d57-7480994cd75a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=25331942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direc
t.25331942
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3531264127
Short name T519
Test name
Test status
Simulation time 95502634229 ps
CPU time 162.43 seconds
Started Feb 04 02:37:29 PM PST 24
Finished Feb 04 02:40:16 PM PST 24
Peak memory 272096 kb
Host smart-2b194957-2598-4d11-a7ed-ceafb84229d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531264127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3531264127
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1262496607
Short name T280
Test name
Test status
Simulation time 502141979 ps
CPU time 8.25 seconds
Started Feb 04 02:37:25 PM PST 24
Finished Feb 04 02:37:41 PM PST 24
Peak memory 216372 kb
Host smart-eb23bdf3-aa01-49be-934f-ab4ec62c1b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262496607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1262496607
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2487863350
Short name T771
Test name
Test status
Simulation time 19024743863 ps
CPU time 18.35 seconds
Started Feb 04 02:37:29 PM PST 24
Finished Feb 04 02:37:52 PM PST 24
Peak memory 216424 kb
Host smart-f00819d6-0471-4cd4-9393-03505a3597f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487863350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2487863350
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2344714090
Short name T527
Test name
Test status
Simulation time 54080680 ps
CPU time 1.1 seconds
Started Feb 04 02:37:40 PM PST 24
Finished Feb 04 02:37:42 PM PST 24
Peak memory 207960 kb
Host smart-19c346e5-8b3e-4d21-b062-d7f59e377bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344714090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2344714090
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3055307429
Short name T431
Test name
Test status
Simulation time 406047326 ps
CPU time 1.04 seconds
Started Feb 04 02:37:29 PM PST 24
Finished Feb 04 02:37:35 PM PST 24
Peak memory 206484 kb
Host smart-8b640b75-9e80-4c43-ab46-a34443e16cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055307429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3055307429
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1979872693
Short name T59
Test name
Test status
Simulation time 6420931364 ps
CPU time 13.43 seconds
Started Feb 04 02:37:29 PM PST 24
Finished Feb 04 02:37:47 PM PST 24
Peak memory 240316 kb
Host smart-c336128e-3f63-4c5e-9901-7cfce9620fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979872693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1979872693
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.824764639
Short name T667
Test name
Test status
Simulation time 40796229 ps
CPU time 0.74 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:34:24 PM PST 24
Peak memory 204844 kb
Host smart-8fba437c-3ebc-4447-980b-21188723c135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824764639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.824764639
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3547272471
Short name T926
Test name
Test status
Simulation time 633530742 ps
CPU time 3.43 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:34:26 PM PST 24
Peak memory 233644 kb
Host smart-8b4dd638-07ee-4ac8-8465-0ab3b0ee51ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547272471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3547272471
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.200748910
Short name T605
Test name
Test status
Simulation time 22398345 ps
CPU time 0.76 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:34:24 PM PST 24
Peak memory 205172 kb
Host smart-ce3e019c-f551-4f77-8fea-9b7801277ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200748910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.200748910
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.536363109
Short name T759
Test name
Test status
Simulation time 15264778769 ps
CPU time 57.04 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:35:20 PM PST 24
Peak memory 256448 kb
Host smart-82ccb4f8-5f66-4477-beac-08e67beb6325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536363109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.536363109
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1092645353
Short name T943
Test name
Test status
Simulation time 91217620213 ps
CPU time 630.74 seconds
Started Feb 04 02:34:20 PM PST 24
Finished Feb 04 02:44:54 PM PST 24
Peak memory 252368 kb
Host smart-3d887241-e4d5-4596-b682-8a105d4d8a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092645353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1092645353
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2711482703
Short name T1089
Test name
Test status
Simulation time 1616240999 ps
CPU time 26.96 seconds
Started Feb 04 02:34:17 PM PST 24
Finished Feb 04 02:34:49 PM PST 24
Peak memory 233932 kb
Host smart-44bbd202-c07e-4b15-aaa6-284d84805d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711482703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2711482703
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3451090544
Short name T216
Test name
Test status
Simulation time 29189768063 ps
CPU time 11.06 seconds
Started Feb 04 02:34:17 PM PST 24
Finished Feb 04 02:34:34 PM PST 24
Peak memory 233412 kb
Host smart-69d137f1-b4c9-492e-8610-0d96ae1291d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451090544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3451090544
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2988278888
Short name T591
Test name
Test status
Simulation time 29994919314 ps
CPU time 19.24 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:34:42 PM PST 24
Peak memory 233960 kb
Host smart-c228f73f-5ace-463f-91f2-4cfeaea7a20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988278888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2988278888
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.952678610
Short name T289
Test name
Test status
Simulation time 119814984 ps
CPU time 1.08 seconds
Started Feb 04 02:34:17 PM PST 24
Finished Feb 04 02:34:24 PM PST 24
Peak memory 216648 kb
Host smart-507ce43d-ad70-41d4-af16-99dc8974f09c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952678610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.952678610
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2112672603
Short name T941
Test name
Test status
Simulation time 916919901 ps
CPU time 4.76 seconds
Started Feb 04 02:34:19 PM PST 24
Finished Feb 04 02:34:28 PM PST 24
Peak memory 232756 kb
Host smart-c2a32dc7-e7de-4941-9f60-970ad8094db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112672603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2112672603
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1041346039
Short name T801
Test name
Test status
Simulation time 549042570 ps
CPU time 8.76 seconds
Started Feb 04 02:34:15 PM PST 24
Finished Feb 04 02:34:30 PM PST 24
Peak memory 224584 kb
Host smart-f79feb94-b892-41df-9648-876d2061144f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041346039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1041346039
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.1459677762
Short name T52
Test name
Test status
Simulation time 26616804 ps
CPU time 0.72 seconds
Started Feb 04 02:34:15 PM PST 24
Finished Feb 04 02:34:22 PM PST 24
Peak memory 216280 kb
Host smart-58192009-c3c3-4a6c-918a-e696ddb157ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459677762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.1459677762
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4132919850
Short name T453
Test name
Test status
Simulation time 75746631 ps
CPU time 3.14 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:34:26 PM PST 24
Peak memory 218864 kb
Host smart-1ecd2771-31aa-449d-9f93-bf47a0a184c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4132919850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4132919850
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1374874720
Short name T55
Test name
Test status
Simulation time 339629322 ps
CPU time 1.16 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:34:24 PM PST 24
Peak memory 235396 kb
Host smart-e1ec8935-f809-4e29-9845-4db475c5f581
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374874720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1374874720
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.4154798136
Short name T832
Test name
Test status
Simulation time 172104827334 ps
CPU time 321.4 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:39:44 PM PST 24
Peak memory 263448 kb
Host smart-958493da-80d3-474d-92d2-79e6c3cce723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154798136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.4154798136
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.694626756
Short name T735
Test name
Test status
Simulation time 2047120405 ps
CPU time 5.69 seconds
Started Feb 04 02:34:19 PM PST 24
Finished Feb 04 02:34:29 PM PST 24
Peak memory 216416 kb
Host smart-0a6ceada-6e16-4cd3-a32c-9129a0c18041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694626756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.694626756
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1896046873
Short name T751
Test name
Test status
Simulation time 18444506179 ps
CPU time 12.93 seconds
Started Feb 04 02:34:15 PM PST 24
Finished Feb 04 02:34:34 PM PST 24
Peak memory 216448 kb
Host smart-82346691-c5d8-4441-b4df-1562eabef41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896046873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1896046873
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3518640411
Short name T663
Test name
Test status
Simulation time 78602306 ps
CPU time 3.17 seconds
Started Feb 04 02:34:23 PM PST 24
Finished Feb 04 02:34:39 PM PST 24
Peak memory 207888 kb
Host smart-9995ce51-65ba-4df5-97ef-25bc923aa032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518640411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3518640411
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1202780506
Short name T624
Test name
Test status
Simulation time 227291544 ps
CPU time 1.38 seconds
Started Feb 04 02:34:23 PM PST 24
Finished Feb 04 02:34:37 PM PST 24
Peak memory 206452 kb
Host smart-d4b58190-59c3-440d-8381-99181775dfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202780506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1202780506
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2616123221
Short name T896
Test name
Test status
Simulation time 5037738135 ps
CPU time 10.42 seconds
Started Feb 04 02:34:17 PM PST 24
Finished Feb 04 02:34:33 PM PST 24
Peak memory 219880 kb
Host smart-bd24b7a5-fab4-438b-ac0a-18d4514d8995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616123221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2616123221
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3598825759
Short name T1098
Test name
Test status
Simulation time 14208511 ps
CPU time 0.71 seconds
Started Feb 04 02:37:38 PM PST 24
Finished Feb 04 02:37:41 PM PST 24
Peak memory 204936 kb
Host smart-5a80d57f-04ca-47fb-9e34-4a57ddb0aab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598825759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3598825759
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3582415168
Short name T707
Test name
Test status
Simulation time 147899881 ps
CPU time 2.59 seconds
Started Feb 04 02:37:30 PM PST 24
Finished Feb 04 02:37:36 PM PST 24
Peak memory 216788 kb
Host smart-f1a823d4-420f-4111-be61-60b96b9bf372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582415168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3582415168
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1598525413
Short name T464
Test name
Test status
Simulation time 70380723 ps
CPU time 0.77 seconds
Started Feb 04 02:37:34 PM PST 24
Finished Feb 04 02:37:40 PM PST 24
Peak memory 205144 kb
Host smart-ebde1d1e-bc6f-4475-a1d7-7f6fee5e30f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598525413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1598525413
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.4238265397
Short name T213
Test name
Test status
Simulation time 7350612475 ps
CPU time 50.08 seconds
Started Feb 04 02:37:42 PM PST 24
Finished Feb 04 02:38:38 PM PST 24
Peak memory 248564 kb
Host smart-1f4fe4e7-63f6-4629-9470-03f9cfe45b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238265397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.4238265397
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1517471853
Short name T682
Test name
Test status
Simulation time 85214780104 ps
CPU time 147.38 seconds
Started Feb 04 02:37:43 PM PST 24
Finished Feb 04 02:40:16 PM PST 24
Peak memory 237208 kb
Host smart-91087b2e-d0c2-47e7-9d69-a939e21c853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517471853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1517471853
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3590202020
Short name T502
Test name
Test status
Simulation time 34243163430 ps
CPU time 245.93 seconds
Started Feb 04 02:37:36 PM PST 24
Finished Feb 04 02:41:46 PM PST 24
Peak memory 249316 kb
Host smart-693cf8ea-2603-480f-ba9e-3ab034e7b8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590202020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3590202020
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3535617879
Short name T862
Test name
Test status
Simulation time 12564405767 ps
CPU time 14.37 seconds
Started Feb 04 02:37:42 PM PST 24
Finished Feb 04 02:38:03 PM PST 24
Peak memory 224480 kb
Host smart-6d737cda-31e1-4b4e-9458-dde6152b6d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535617879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3535617879
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2005675065
Short name T175
Test name
Test status
Simulation time 111532627 ps
CPU time 3.84 seconds
Started Feb 04 02:37:41 PM PST 24
Finished Feb 04 02:37:51 PM PST 24
Peak memory 233696 kb
Host smart-ee542d8b-96d6-4cce-9dbe-a652c09b8901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005675065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2005675065
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2157160912
Short name T1030
Test name
Test status
Simulation time 3269807543 ps
CPU time 11.9 seconds
Started Feb 04 02:37:42 PM PST 24
Finished Feb 04 02:38:00 PM PST 24
Peak memory 218128 kb
Host smart-29bc4cc2-2067-4064-834c-bb9e7a4807cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157160912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2157160912
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1768593634
Short name T866
Test name
Test status
Simulation time 2812397562 ps
CPU time 5.27 seconds
Started Feb 04 02:37:32 PM PST 24
Finished Feb 04 02:37:42 PM PST 24
Peak memory 216852 kb
Host smart-a311b4f6-dcc4-492d-8226-40b5258ddaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768593634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1768593634
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3502603792
Short name T875
Test name
Test status
Simulation time 11647877065 ps
CPU time 10.69 seconds
Started Feb 04 02:37:32 PM PST 24
Finished Feb 04 02:37:47 PM PST 24
Peak memory 233788 kb
Host smart-a76acbde-9d64-4ca6-a486-ec21200a4e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502603792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3502603792
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.777855587
Short name T538
Test name
Test status
Simulation time 1077163093 ps
CPU time 3.79 seconds
Started Feb 04 02:37:38 PM PST 24
Finished Feb 04 02:37:44 PM PST 24
Peak memory 221632 kb
Host smart-b0e9cc4f-e465-4bb5-bd54-449da35d92d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=777855587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.777855587
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3806003969
Short name T833
Test name
Test status
Simulation time 49000306 ps
CPU time 1.02 seconds
Started Feb 04 02:37:40 PM PST 24
Finished Feb 04 02:37:48 PM PST 24
Peak memory 206780 kb
Host smart-2fb03e0d-0de5-428a-b0aa-f8c24a8ab38a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806003969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3806003969
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2835478661
Short name T977
Test name
Test status
Simulation time 3745931725 ps
CPU time 51.99 seconds
Started Feb 04 02:37:42 PM PST 24
Finished Feb 04 02:38:40 PM PST 24
Peak memory 216320 kb
Host smart-70f1b3b2-b216-4f24-b06c-a68123e0bba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835478661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2835478661
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3042419798
Short name T475
Test name
Test status
Simulation time 7606454788 ps
CPU time 10.32 seconds
Started Feb 04 02:37:33 PM PST 24
Finished Feb 04 02:37:49 PM PST 24
Peak memory 216432 kb
Host smart-e26c83c1-af17-414c-a32a-9d1380152767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042419798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3042419798
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1271304787
Short name T879
Test name
Test status
Simulation time 343149839 ps
CPU time 2.44 seconds
Started Feb 04 02:37:34 PM PST 24
Finished Feb 04 02:37:42 PM PST 24
Peak memory 208276 kb
Host smart-bfdac299-f8e5-49fe-a070-341b479b4fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271304787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1271304787
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.116115475
Short name T930
Test name
Test status
Simulation time 484167076 ps
CPU time 0.85 seconds
Started Feb 04 02:37:31 PM PST 24
Finished Feb 04 02:37:36 PM PST 24
Peak memory 205388 kb
Host smart-634dc855-b278-4486-a848-c58fe74e31ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116115475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.116115475
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2995955482
Short name T35
Test name
Test status
Simulation time 12043229987 ps
CPU time 8.03 seconds
Started Feb 04 02:37:34 PM PST 24
Finished Feb 04 02:37:47 PM PST 24
Peak memory 239200 kb
Host smart-783ae273-44ca-40e6-8570-cf42abe792b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995955482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2995955482
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.428795028
Short name T770
Test name
Test status
Simulation time 11434718 ps
CPU time 0.73 seconds
Started Feb 04 02:37:40 PM PST 24
Finished Feb 04 02:37:42 PM PST 24
Peak memory 205316 kb
Host smart-da8d027d-8248-4ed2-8d23-a56bab09a3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428795028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.428795028
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2306691245
Short name T576
Test name
Test status
Simulation time 91078733 ps
CPU time 2.72 seconds
Started Feb 04 02:37:39 PM PST 24
Finished Feb 04 02:37:44 PM PST 24
Peak memory 233500 kb
Host smart-fa973133-4d01-4654-baa6-ceb415853777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306691245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2306691245
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2083799805
Short name T523
Test name
Test status
Simulation time 16191491 ps
CPU time 0.73 seconds
Started Feb 04 02:37:38 PM PST 24
Finished Feb 04 02:37:41 PM PST 24
Peak memory 206532 kb
Host smart-ef0b745e-d42a-4721-bbbe-4745a490aa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083799805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2083799805
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.842631067
Short name T247
Test name
Test status
Simulation time 93476838673 ps
CPU time 255.05 seconds
Started Feb 04 02:37:34 PM PST 24
Finished Feb 04 02:41:55 PM PST 24
Peak memory 253804 kb
Host smart-e2dc42d3-4258-4362-ab9d-7f4a8f3e2997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842631067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.842631067
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1072854804
Short name T476
Test name
Test status
Simulation time 102443517250 ps
CPU time 168.5 seconds
Started Feb 04 02:37:42 PM PST 24
Finished Feb 04 02:40:37 PM PST 24
Peak memory 273116 kb
Host smart-8a4c4626-c1b8-487f-bad4-c721983d9d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072854804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1072854804
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2403971968
Short name T848
Test name
Test status
Simulation time 20327695509 ps
CPU time 143.34 seconds
Started Feb 04 02:37:42 PM PST 24
Finished Feb 04 02:40:12 PM PST 24
Peak memory 252032 kb
Host smart-84ddb09d-3ea2-4657-b13b-12fc232ea6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403971968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2403971968
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4049806393
Short name T1067
Test name
Test status
Simulation time 3704927162 ps
CPU time 6.7 seconds
Started Feb 04 02:37:38 PM PST 24
Finished Feb 04 02:37:47 PM PST 24
Peak memory 217520 kb
Host smart-9b23a65e-4e8f-4851-9e06-c34b6b07eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049806393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4049806393
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2247784523
Short name T991
Test name
Test status
Simulation time 40857138695 ps
CPU time 29.46 seconds
Started Feb 04 02:37:40 PM PST 24
Finished Feb 04 02:38:10 PM PST 24
Peak memory 231008 kb
Host smart-26d90394-1db2-4798-bf81-981b42263c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247784523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2247784523
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3401970632
Short name T582
Test name
Test status
Simulation time 9040112585 ps
CPU time 7.88 seconds
Started Feb 04 02:37:43 PM PST 24
Finished Feb 04 02:37:56 PM PST 24
Peak memory 233452 kb
Host smart-58a6604d-1616-42fb-95aa-d4128dec9b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401970632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3401970632
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4107567982
Short name T585
Test name
Test status
Simulation time 3014913509 ps
CPU time 9.25 seconds
Started Feb 04 02:37:37 PM PST 24
Finished Feb 04 02:37:50 PM PST 24
Peak memory 218948 kb
Host smart-a11fa8a5-8a2f-4fa1-b7d2-98d15f18d57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107567982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4107567982
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2729945025
Short name T430
Test name
Test status
Simulation time 93820344 ps
CPU time 3.28 seconds
Started Feb 04 02:37:37 PM PST 24
Finished Feb 04 02:37:44 PM PST 24
Peak memory 222120 kb
Host smart-2ebbcc84-3921-48e2-80df-1728edbf40c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2729945025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2729945025
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1649163660
Short name T844
Test name
Test status
Simulation time 29765941081 ps
CPU time 111.33 seconds
Started Feb 04 02:37:41 PM PST 24
Finished Feb 04 02:39:38 PM PST 24
Peak memory 251884 kb
Host smart-ae922be7-7c8a-4b80-bc2e-9f75dd024be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649163660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1649163660
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2547764350
Short name T81
Test name
Test status
Simulation time 7164686086 ps
CPU time 57.58 seconds
Started Feb 04 02:37:36 PM PST 24
Finished Feb 04 02:38:38 PM PST 24
Peak memory 216752 kb
Host smart-1143f5c2-80d3-4465-8a0a-066a241c84f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547764350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2547764350
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3135508930
Short name T1079
Test name
Test status
Simulation time 829918960 ps
CPU time 2.56 seconds
Started Feb 04 02:37:37 PM PST 24
Finished Feb 04 02:37:43 PM PST 24
Peak memory 208080 kb
Host smart-513d05ba-7028-47b2-abdc-7dc1d24b6c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135508930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3135508930
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.627191638
Short name T857
Test name
Test status
Simulation time 23308244 ps
CPU time 0.73 seconds
Started Feb 04 02:37:42 PM PST 24
Finished Feb 04 02:37:49 PM PST 24
Peak memory 205380 kb
Host smart-550b2ea9-257d-4d3b-9f56-7584bdd405c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627191638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.627191638
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4058458822
Short name T40
Test name
Test status
Simulation time 182729208 ps
CPU time 1.09 seconds
Started Feb 04 02:37:34 PM PST 24
Finished Feb 04 02:37:41 PM PST 24
Peak memory 206456 kb
Host smart-53669755-394c-47c0-8583-dc87a7a86402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058458822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4058458822
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2324439644
Short name T886
Test name
Test status
Simulation time 2252703869 ps
CPU time 11.75 seconds
Started Feb 04 02:37:33 PM PST 24
Finished Feb 04 02:37:50 PM PST 24
Peak memory 240156 kb
Host smart-d94f645c-e176-4660-bcc2-c487d5c4e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324439644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2324439644
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1440832514
Short name T739
Test name
Test status
Simulation time 36862039 ps
CPU time 0.71 seconds
Started Feb 04 02:37:48 PM PST 24
Finished Feb 04 02:37:51 PM PST 24
Peak memory 205240 kb
Host smart-65672325-5408-4fd0-838e-0e3e8eb27c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440832514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1440832514
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.942275320
Short name T204
Test name
Test status
Simulation time 3065413232 ps
CPU time 11.08 seconds
Started Feb 04 02:37:47 PM PST 24
Finished Feb 04 02:38:01 PM PST 24
Peak memory 224624 kb
Host smart-c2b1b138-8628-46ae-ad9b-c44813978bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942275320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.942275320
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2241094718
Short name T1031
Test name
Test status
Simulation time 25389223 ps
CPU time 0.78 seconds
Started Feb 04 02:37:40 PM PST 24
Finished Feb 04 02:37:42 PM PST 24
Peak memory 206564 kb
Host smart-5fc66450-03d2-4556-96ad-90722cce5aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241094718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2241094718
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1805917171
Short name T899
Test name
Test status
Simulation time 21666733431 ps
CPU time 57.94 seconds
Started Feb 04 02:37:52 PM PST 24
Finished Feb 04 02:38:51 PM PST 24
Peak memory 243988 kb
Host smart-94ed503d-f601-43ab-992c-765ee46da964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805917171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1805917171
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2506905559
Short name T68
Test name
Test status
Simulation time 4829732072 ps
CPU time 40.84 seconds
Started Feb 04 02:37:53 PM PST 24
Finished Feb 04 02:38:34 PM PST 24
Peak memory 235580 kb
Host smart-3f2971ec-8aba-4abc-b39b-1de028301229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506905559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2506905559
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2346188060
Short name T268
Test name
Test status
Simulation time 259317101210 ps
CPU time 296.45 seconds
Started Feb 04 02:37:46 PM PST 24
Finished Feb 04 02:42:45 PM PST 24
Peak memory 272896 kb
Host smart-05b02e51-94f9-4349-b98c-c70deb65ac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346188060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2346188060
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.415364208
Short name T800
Test name
Test status
Simulation time 469837341 ps
CPU time 8.85 seconds
Started Feb 04 02:37:45 PM PST 24
Finished Feb 04 02:37:58 PM PST 24
Peak memory 240340 kb
Host smart-0ec47ab2-ba8d-4ed1-bd8b-ac51349af73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415364208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.415364208
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4113534707
Short name T596
Test name
Test status
Simulation time 1887281049 ps
CPU time 4.89 seconds
Started Feb 04 02:37:52 PM PST 24
Finished Feb 04 02:37:58 PM PST 24
Peak memory 218884 kb
Host smart-269131f8-44cd-439f-94ef-02b522c2b4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113534707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4113534707
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1053286436
Short name T557
Test name
Test status
Simulation time 2960146415 ps
CPU time 16.01 seconds
Started Feb 04 02:37:46 PM PST 24
Finished Feb 04 02:38:05 PM PST 24
Peak memory 243972 kb
Host smart-fb6ab002-7780-4a8c-8a32-d85804dd4f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053286436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1053286436
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.483603490
Short name T924
Test name
Test status
Simulation time 4601258280 ps
CPU time 9.75 seconds
Started Feb 04 02:37:48 PM PST 24
Finished Feb 04 02:38:00 PM PST 24
Peak memory 218324 kb
Host smart-1b76a2ec-eee4-41fb-83dc-714b7a3d2d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483603490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.483603490
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1146660895
Short name T197
Test name
Test status
Simulation time 210954896 ps
CPU time 3 seconds
Started Feb 04 02:37:44 PM PST 24
Finished Feb 04 02:37:51 PM PST 24
Peak memory 224572 kb
Host smart-d36a0473-64ec-4053-a769-8eb16733453f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146660895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1146660895
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.64932275
Short name T989
Test name
Test status
Simulation time 16659099920 ps
CPU time 6.28 seconds
Started Feb 04 02:37:45 PM PST 24
Finished Feb 04 02:37:55 PM PST 24
Peak memory 216644 kb
Host smart-02b120f0-c482-4208-b3c5-93111c7622ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=64932275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direc
t.64932275
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.214817748
Short name T708
Test name
Test status
Simulation time 5997901093 ps
CPU time 86.53 seconds
Started Feb 04 02:37:41 PM PST 24
Finished Feb 04 02:39:13 PM PST 24
Peak memory 216388 kb
Host smart-6edf29a3-8775-429b-8670-4717962fe0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214817748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.214817748
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1378506234
Short name T733
Test name
Test status
Simulation time 358766375 ps
CPU time 2.05 seconds
Started Feb 04 02:37:35 PM PST 24
Finished Feb 04 02:37:42 PM PST 24
Peak memory 208004 kb
Host smart-21a1221e-113e-4cda-b94f-06d9b3661b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378506234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1378506234
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1445904957
Short name T286
Test name
Test status
Simulation time 47529978 ps
CPU time 1.37 seconds
Started Feb 04 02:37:36 PM PST 24
Finished Feb 04 02:37:42 PM PST 24
Peak memory 208172 kb
Host smart-33f87250-9491-49b7-98f7-9052b49b2e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445904957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1445904957
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.634287651
Short name T295
Test name
Test status
Simulation time 78212477 ps
CPU time 0.71 seconds
Started Feb 04 02:37:33 PM PST 24
Finished Feb 04 02:37:39 PM PST 24
Peak memory 205428 kb
Host smart-0086260c-1655-4b02-a3d8-f2ba93f9d833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634287651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.634287651
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1392742885
Short name T541
Test name
Test status
Simulation time 221677545 ps
CPU time 3.12 seconds
Started Feb 04 02:37:45 PM PST 24
Finished Feb 04 02:37:52 PM PST 24
Peak memory 232804 kb
Host smart-0234f4d8-24fb-4587-aa4a-5a614d02f50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392742885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1392742885
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3360420852
Short name T5
Test name
Test status
Simulation time 12703341 ps
CPU time 0.73 seconds
Started Feb 04 02:37:48 PM PST 24
Finished Feb 04 02:37:51 PM PST 24
Peak memory 204320 kb
Host smart-ff9a7576-1827-4c3a-8142-b9246244b55a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360420852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3360420852
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1020921995
Short name T477
Test name
Test status
Simulation time 1445918195 ps
CPU time 4.14 seconds
Started Feb 04 02:37:44 PM PST 24
Finished Feb 04 02:37:53 PM PST 24
Peak memory 219656 kb
Host smart-a0c44854-b7b2-41b6-b5ea-ae7d4f08f53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020921995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1020921995
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1485465460
Short name T287
Test name
Test status
Simulation time 14271943 ps
CPU time 0.77 seconds
Started Feb 04 02:37:49 PM PST 24
Finished Feb 04 02:37:51 PM PST 24
Peak memory 205168 kb
Host smart-c89c58be-8a8d-4c58-a549-53ba09ebe73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485465460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1485465460
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3907001070
Short name T895
Test name
Test status
Simulation time 45189816884 ps
CPU time 224.02 seconds
Started Feb 04 02:37:49 PM PST 24
Finished Feb 04 02:41:35 PM PST 24
Peak memory 255272 kb
Host smart-e87acb7e-7efd-4dcc-b3b2-6525d62bda80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907001070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3907001070
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3716395788
Short name T819
Test name
Test status
Simulation time 40393225690 ps
CPU time 104.6 seconds
Started Feb 04 02:37:46 PM PST 24
Finished Feb 04 02:39:34 PM PST 24
Peak memory 232888 kb
Host smart-40f056f4-bb5b-4ddf-98bf-d755fc9a7e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716395788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3716395788
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1587758009
Short name T141
Test name
Test status
Simulation time 14381008326 ps
CPU time 102.65 seconds
Started Feb 04 02:37:50 PM PST 24
Finished Feb 04 02:39:34 PM PST 24
Peak memory 233960 kb
Host smart-dfcda459-d035-4e07-90dd-8fc943fe9ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587758009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1587758009
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3354453360
Short name T272
Test name
Test status
Simulation time 4275191445 ps
CPU time 17.97 seconds
Started Feb 04 02:37:52 PM PST 24
Finished Feb 04 02:38:11 PM PST 24
Peak memory 231180 kb
Host smart-3fba8908-9154-4d70-93a8-a62d6ee8bf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354453360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3354453360
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.611524864
Short name T169
Test name
Test status
Simulation time 36088964594 ps
CPU time 10.39 seconds
Started Feb 04 02:37:47 PM PST 24
Finished Feb 04 02:38:00 PM PST 24
Peak memory 234864 kb
Host smart-92b39544-2937-4eb6-9b1d-ca6da475a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611524864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.611524864
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4208989614
Short name T237
Test name
Test status
Simulation time 44471372135 ps
CPU time 40.65 seconds
Started Feb 04 02:37:48 PM PST 24
Finished Feb 04 02:38:31 PM PST 24
Peak memory 251376 kb
Host smart-bad7ab11-6468-4d16-af29-7598a867e30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208989614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4208989614
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3856955983
Short name T976
Test name
Test status
Simulation time 4892617568 ps
CPU time 9.81 seconds
Started Feb 04 02:37:51 PM PST 24
Finished Feb 04 02:38:02 PM PST 24
Peak memory 233588 kb
Host smart-4bebf776-bade-4b70-87df-981d250efd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856955983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3856955983
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1809140246
Short name T677
Test name
Test status
Simulation time 494329381 ps
CPU time 2.71 seconds
Started Feb 04 02:37:46 PM PST 24
Finished Feb 04 02:37:52 PM PST 24
Peak memory 224588 kb
Host smart-a17c01cd-0aa5-4bfd-a5a9-e8e2018bd9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809140246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1809140246
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4294110094
Short name T806
Test name
Test status
Simulation time 259208084 ps
CPU time 3.44 seconds
Started Feb 04 02:37:51 PM PST 24
Finished Feb 04 02:37:55 PM PST 24
Peak memory 218716 kb
Host smart-b269f495-81db-4018-a5d6-b097101bcf7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4294110094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4294110094
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3905738967
Short name T986
Test name
Test status
Simulation time 521932566080 ps
CPU time 461.12 seconds
Started Feb 04 02:37:46 PM PST 24
Finished Feb 04 02:45:30 PM PST 24
Peak memory 272952 kb
Host smart-fdf2b8ad-7bae-4e72-a658-ad6acaf7b609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905738967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3905738967
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1693987810
Short name T282
Test name
Test status
Simulation time 10459960763 ps
CPU time 140.97 seconds
Started Feb 04 02:37:44 PM PST 24
Finished Feb 04 02:40:09 PM PST 24
Peak memory 216328 kb
Host smart-62388463-0a5b-4607-9aa3-7afe830d1048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693987810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1693987810
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3009180380
Short name T71
Test name
Test status
Simulation time 2584029853 ps
CPU time 7.98 seconds
Started Feb 04 02:37:48 PM PST 24
Finished Feb 04 02:37:58 PM PST 24
Peak memory 216808 kb
Host smart-6d03aa58-fbea-4f3a-9c68-347898e05b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009180380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3009180380
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2107866575
Short name T594
Test name
Test status
Simulation time 717133056 ps
CPU time 1.81 seconds
Started Feb 04 02:37:48 PM PST 24
Finished Feb 04 02:37:52 PM PST 24
Peak memory 208216 kb
Host smart-82f33657-0086-42c8-8ddc-506e8a500e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107866575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2107866575
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.137474045
Short name T423
Test name
Test status
Simulation time 72260334 ps
CPU time 0.72 seconds
Started Feb 04 02:37:47 PM PST 24
Finished Feb 04 02:37:50 PM PST 24
Peak memory 205460 kb
Host smart-35ceada8-4861-4ab6-8a4a-3a2e427d01f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137474045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.137474045
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3399770862
Short name T219
Test name
Test status
Simulation time 10096617655 ps
CPU time 11.31 seconds
Started Feb 04 02:37:45 PM PST 24
Finished Feb 04 02:38:00 PM PST 24
Peak memory 234264 kb
Host smart-04c5c6cb-de9f-400a-8433-27ec671b6803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399770862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3399770862
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3619802448
Short name T493
Test name
Test status
Simulation time 30054418 ps
CPU time 0.7 seconds
Started Feb 04 02:38:05 PM PST 24
Finished Feb 04 02:38:08 PM PST 24
Peak memory 204944 kb
Host smart-4c8325fa-85f6-4aec-9c68-c81fed9e1640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619802448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3619802448
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3015141584
Short name T794
Test name
Test status
Simulation time 240106268 ps
CPU time 5.31 seconds
Started Feb 04 02:37:47 PM PST 24
Finished Feb 04 02:37:55 PM PST 24
Peak memory 221272 kb
Host smart-6f62b18d-4b27-428f-a2d3-546a5c7e47ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015141584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3015141584
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2468339038
Short name T1100
Test name
Test status
Simulation time 41992760 ps
CPU time 0.78 seconds
Started Feb 04 02:37:46 PM PST 24
Finished Feb 04 02:37:50 PM PST 24
Peak memory 205460 kb
Host smart-e5eed83f-990c-4e89-ab89-c3ef2e8a8d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468339038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2468339038
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.679667954
Short name T498
Test name
Test status
Simulation time 56457131121 ps
CPU time 269.7 seconds
Started Feb 04 02:37:48 PM PST 24
Finished Feb 04 02:42:20 PM PST 24
Peak memory 257204 kb
Host smart-8de82109-88df-40aa-a2c5-5506236ae405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679667954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.679667954
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2676181883
Short name T535
Test name
Test status
Simulation time 22455210962 ps
CPU time 188.42 seconds
Started Feb 04 02:37:51 PM PST 24
Finished Feb 04 02:41:01 PM PST 24
Peak memory 257404 kb
Host smart-6a9ed293-7f36-4eae-a298-64497dfd2e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676181883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2676181883
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.116962739
Short name T894
Test name
Test status
Simulation time 91336891982 ps
CPU time 92.56 seconds
Started Feb 04 02:38:00 PM PST 24
Finished Feb 04 02:39:33 PM PST 24
Peak memory 249476 kb
Host smart-0338a8b4-a903-49fc-be06-5ee391183c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116962739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.116962739
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.642823583
Short name T1059
Test name
Test status
Simulation time 450902136 ps
CPU time 9.98 seconds
Started Feb 04 02:37:49 PM PST 24
Finished Feb 04 02:38:01 PM PST 24
Peak memory 232724 kb
Host smart-342175fa-ee98-4f95-8bd1-0d81dd114ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642823583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.642823583
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1139816220
Short name T220
Test name
Test status
Simulation time 3024812690 ps
CPU time 7.32 seconds
Started Feb 04 02:37:46 PM PST 24
Finished Feb 04 02:37:56 PM PST 24
Peak memory 233776 kb
Host smart-9f9fcd91-1f38-4383-bd8e-10f428ef2443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139816220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1139816220
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3258637204
Short name T877
Test name
Test status
Simulation time 555612309 ps
CPU time 6.47 seconds
Started Feb 04 02:37:50 PM PST 24
Finished Feb 04 02:37:57 PM PST 24
Peak memory 224512 kb
Host smart-a17c6436-d535-4c1a-a92f-2ede899a1b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258637204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3258637204
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3394454659
Short name T1008
Test name
Test status
Simulation time 6990987332 ps
CPU time 14.84 seconds
Started Feb 04 02:37:43 PM PST 24
Finished Feb 04 02:38:03 PM PST 24
Peak memory 233344 kb
Host smart-8beae61e-8648-44c5-b9d6-5ec8ff9263aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394454659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3394454659
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1842441983
Short name T221
Test name
Test status
Simulation time 3111383045 ps
CPU time 10.9 seconds
Started Feb 04 02:37:42 PM PST 24
Finished Feb 04 02:37:59 PM PST 24
Peak memory 233312 kb
Host smart-5ef5adc8-3c78-4b90-8eda-d3a3aba5674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842441983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1842441983
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.910933627
Short name T586
Test name
Test status
Simulation time 724903182 ps
CPU time 5.1 seconds
Started Feb 04 02:37:49 PM PST 24
Finished Feb 04 02:37:56 PM PST 24
Peak memory 222128 kb
Host smart-7ded35c8-67f2-4922-9604-3b8620ddab3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=910933627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.910933627
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3268590992
Short name T817
Test name
Test status
Simulation time 25854156591 ps
CPU time 214.93 seconds
Started Feb 04 02:38:07 PM PST 24
Finished Feb 04 02:41:44 PM PST 24
Peak memory 249252 kb
Host smart-8f681fa9-e931-4539-9bf2-559d24e25b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268590992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3268590992
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3044428990
Short name T688
Test name
Test status
Simulation time 2101307049 ps
CPU time 32.27 seconds
Started Feb 04 02:37:54 PM PST 24
Finished Feb 04 02:38:27 PM PST 24
Peak memory 216372 kb
Host smart-c52f1cf8-4333-423f-a26c-3550b7119599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044428990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3044428990
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1678548278
Short name T938
Test name
Test status
Simulation time 13117899372 ps
CPU time 22.93 seconds
Started Feb 04 02:37:47 PM PST 24
Finished Feb 04 02:38:12 PM PST 24
Peak memory 217652 kb
Host smart-0db8ed3d-4a1d-48f0-bbfd-a10f002f0700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678548278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1678548278
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2446717432
Short name T297
Test name
Test status
Simulation time 113249291 ps
CPU time 0.82 seconds
Started Feb 04 02:37:51 PM PST 24
Finished Feb 04 02:37:53 PM PST 24
Peak memory 205380 kb
Host smart-a30734f3-5b16-4011-8bbb-7b04092a32b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446717432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2446717432
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3896104133
Short name T311
Test name
Test status
Simulation time 622847149 ps
CPU time 1.1 seconds
Started Feb 04 02:37:46 PM PST 24
Finished Feb 04 02:37:50 PM PST 24
Peak memory 206512 kb
Host smart-478c9233-28b1-45a5-8ce0-bb1c954b7b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896104133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3896104133
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3026082055
Short name T1064
Test name
Test status
Simulation time 1667718403 ps
CPU time 3.89 seconds
Started Feb 04 02:37:52 PM PST 24
Finished Feb 04 02:37:57 PM PST 24
Peak memory 233508 kb
Host smart-bfbe46c4-972a-4137-b6aa-907b760d7c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026082055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3026082055
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2775756051
Short name T1080
Test name
Test status
Simulation time 22888527 ps
CPU time 0.71 seconds
Started Feb 04 02:38:06 PM PST 24
Finished Feb 04 02:38:08 PM PST 24
Peak memory 204956 kb
Host smart-5d9eda54-48d5-4555-848a-24566ef97931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775756051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2775756051
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1006763155
Short name T1093
Test name
Test status
Simulation time 1605273831 ps
CPU time 4.38 seconds
Started Feb 04 02:38:06 PM PST 24
Finished Feb 04 02:38:13 PM PST 24
Peak memory 234820 kb
Host smart-8b8930fc-2e5b-4061-ac44-68c1372e7fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006763155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1006763155
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.195717119
Short name T486
Test name
Test status
Simulation time 45412572 ps
CPU time 0.8 seconds
Started Feb 04 02:38:16 PM PST 24
Finished Feb 04 02:38:19 PM PST 24
Peak memory 205168 kb
Host smart-1b8e59c2-04e5-4b46-8afb-f9c981103060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195717119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.195717119
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.212960184
Short name T30
Test name
Test status
Simulation time 12429206505 ps
CPU time 23.82 seconds
Started Feb 04 02:37:58 PM PST 24
Finished Feb 04 02:38:22 PM PST 24
Peak memory 231588 kb
Host smart-c0d09c48-e948-4f92-b4c5-219dcefc8668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212960184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.212960184
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1189705842
Short name T115
Test name
Test status
Simulation time 134815196751 ps
CPU time 472.11 seconds
Started Feb 04 02:38:05 PM PST 24
Finished Feb 04 02:45:58 PM PST 24
Peak memory 251688 kb
Host smart-870cde04-ab74-4912-9016-45a809aee902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189705842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1189705842
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.579495245
Short name T859
Test name
Test status
Simulation time 1849048199 ps
CPU time 14.69 seconds
Started Feb 04 02:38:06 PM PST 24
Finished Feb 04 02:38:22 PM PST 24
Peak memory 236584 kb
Host smart-f80641ef-dcc8-4891-9078-4e64a6ed4c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579495245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.579495245
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3465184007
Short name T234
Test name
Test status
Simulation time 2375633490 ps
CPU time 4.91 seconds
Started Feb 04 02:38:04 PM PST 24
Finished Feb 04 02:38:10 PM PST 24
Peak memory 232964 kb
Host smart-4c033aea-7197-4227-b21a-0b99cd0bb3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465184007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3465184007
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3535093266
Short name T661
Test name
Test status
Simulation time 1901782397 ps
CPU time 6.69 seconds
Started Feb 04 02:38:04 PM PST 24
Finished Feb 04 02:38:12 PM PST 24
Peak memory 220120 kb
Host smart-5f69657b-50e1-400c-a90d-dc7a8c5ac520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535093266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3535093266
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.929723690
Short name T16
Test name
Test status
Simulation time 2097353080 ps
CPU time 13.33 seconds
Started Feb 04 02:37:58 PM PST 24
Finished Feb 04 02:38:12 PM PST 24
Peak memory 240488 kb
Host smart-1bd58828-2493-4dc9-8391-0af4495480b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929723690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.929723690
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1467553501
Short name T1058
Test name
Test status
Simulation time 263145796 ps
CPU time 3.47 seconds
Started Feb 04 02:38:01 PM PST 24
Finished Feb 04 02:38:06 PM PST 24
Peak memory 233084 kb
Host smart-c95a7c6d-6f34-4dbb-8411-b3af3e2eb0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467553501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1467553501
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1909892402
Short name T470
Test name
Test status
Simulation time 1797610932 ps
CPU time 7.74 seconds
Started Feb 04 02:38:06 PM PST 24
Finished Feb 04 02:38:16 PM PST 24
Peak memory 221644 kb
Host smart-70cb9059-4678-4e63-a06a-531a54fa9fd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1909892402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1909892402
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.734000601
Short name T889
Test name
Test status
Simulation time 15848416011 ps
CPU time 67.96 seconds
Started Feb 04 02:38:05 PM PST 24
Finished Feb 04 02:39:15 PM PST 24
Peak memory 249296 kb
Host smart-93fc3ded-8827-41ee-8558-fb8a8a0afc05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734000601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.734000601
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.785546851
Short name T60
Test name
Test status
Simulation time 6684102851 ps
CPU time 22.84 seconds
Started Feb 04 02:38:08 PM PST 24
Finished Feb 04 02:38:33 PM PST 24
Peak memory 216476 kb
Host smart-3d07b67a-abd5-461d-8897-c91ecc442698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785546851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.785546851
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3172940835
Short name T990
Test name
Test status
Simulation time 22270033759 ps
CPU time 19.98 seconds
Started Feb 04 02:38:04 PM PST 24
Finished Feb 04 02:38:25 PM PST 24
Peak memory 216424 kb
Host smart-09951a4f-d8d0-4fc4-ab56-e44edcf9952d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172940835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3172940835
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1608954577
Short name T867
Test name
Test status
Simulation time 120019411 ps
CPU time 2.54 seconds
Started Feb 04 02:38:09 PM PST 24
Finished Feb 04 02:38:14 PM PST 24
Peak memory 207968 kb
Host smart-2ffe90bf-39f2-4ccc-8464-2b322055d5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608954577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1608954577
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1544860419
Short name T294
Test name
Test status
Simulation time 148982876 ps
CPU time 0.81 seconds
Started Feb 04 02:38:08 PM PST 24
Finished Feb 04 02:38:10 PM PST 24
Peak memory 205400 kb
Host smart-0b03d4af-9ef0-4d62-bd08-323f09d07478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544860419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1544860419
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2901936602
Short name T487
Test name
Test status
Simulation time 1254038344 ps
CPU time 9.09 seconds
Started Feb 04 02:38:05 PM PST 24
Finished Feb 04 02:38:16 PM PST 24
Peak memory 217384 kb
Host smart-4d020a34-04fa-4a50-846d-627b3fdbe270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901936602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2901936602
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3300507463
Short name T922
Test name
Test status
Simulation time 44688665 ps
CPU time 0.75 seconds
Started Feb 04 02:38:00 PM PST 24
Finished Feb 04 02:38:02 PM PST 24
Peak memory 204356 kb
Host smart-999bd56f-6b60-4148-8d72-e713d179c752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300507463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3300507463
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3830423787
Short name T664
Test name
Test status
Simulation time 2470697989 ps
CPU time 5.26 seconds
Started Feb 04 02:38:13 PM PST 24
Finished Feb 04 02:38:19 PM PST 24
Peak memory 224520 kb
Host smart-8d9b43e6-79ae-4e8c-946c-e0a190b7d4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830423787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3830423787
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.654345397
Short name T952
Test name
Test status
Simulation time 64973265 ps
CPU time 0.77 seconds
Started Feb 04 02:38:09 PM PST 24
Finished Feb 04 02:38:11 PM PST 24
Peak memory 206200 kb
Host smart-25dd93d5-937a-4033-8dbd-d086573deece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654345397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.654345397
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2885761667
Short name T696
Test name
Test status
Simulation time 20050290425 ps
CPU time 100.35 seconds
Started Feb 04 02:38:07 PM PST 24
Finished Feb 04 02:39:49 PM PST 24
Peak memory 247636 kb
Host smart-aca255c3-f02d-46b6-b5c3-726a4278d5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885761667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2885761667
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3237360724
Short name T179
Test name
Test status
Simulation time 7953990951 ps
CPU time 102.65 seconds
Started Feb 04 02:38:09 PM PST 24
Finished Feb 04 02:39:53 PM PST 24
Peak memory 256592 kb
Host smart-dcb4dae1-4411-42bc-afb9-9d34fcf87958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237360724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3237360724
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1457162885
Short name T265
Test name
Test status
Simulation time 73849196639 ps
CPU time 234.11 seconds
Started Feb 04 02:38:05 PM PST 24
Finished Feb 04 02:42:01 PM PST 24
Peak memory 273420 kb
Host smart-23e5a444-0638-4ddf-93b9-74f293c31bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457162885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1457162885
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4076539667
Short name T722
Test name
Test status
Simulation time 8419953055 ps
CPU time 51.3 seconds
Started Feb 04 02:38:05 PM PST 24
Finished Feb 04 02:38:59 PM PST 24
Peak memory 234040 kb
Host smart-1d57edff-469e-401b-a7ac-1997278c8ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076539667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4076539667
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2600973987
Short name T802
Test name
Test status
Simulation time 3639656795 ps
CPU time 6.12 seconds
Started Feb 04 02:38:12 PM PST 24
Finished Feb 04 02:38:19 PM PST 24
Peak memory 233076 kb
Host smart-67b4f2e1-c6aa-4cb3-9272-749aa4bb6f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600973987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2600973987
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.706998877
Short name T543
Test name
Test status
Simulation time 159771564 ps
CPU time 2.45 seconds
Started Feb 04 02:38:07 PM PST 24
Finished Feb 04 02:38:11 PM PST 24
Peak memory 233704 kb
Host smart-e60420d1-863e-4160-9ad3-3cc56f4ad2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706998877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.706998877
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.4091722
Short name T932
Test name
Test status
Simulation time 4896457903 ps
CPU time 13.49 seconds
Started Feb 04 02:38:03 PM PST 24
Finished Feb 04 02:38:18 PM PST 24
Peak memory 236784 kb
Host smart-da17c5c8-92ab-4ad4-822d-f30267a2a8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.4091722
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1657031854
Short name T880
Test name
Test status
Simulation time 50810978486 ps
CPU time 25.55 seconds
Started Feb 04 02:38:05 PM PST 24
Finished Feb 04 02:38:33 PM PST 24
Peak memory 248056 kb
Host smart-bb11c6a7-a2d9-4755-8eb5-39c887545f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657031854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1657031854
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.563294052
Short name T788
Test name
Test status
Simulation time 402364278 ps
CPU time 3.03 seconds
Started Feb 04 02:37:58 PM PST 24
Finished Feb 04 02:38:02 PM PST 24
Peak memory 218932 kb
Host smart-443b0768-9fd4-4ae6-8d24-461e2bb32562
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=563294052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.563294052
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1959960892
Short name T48
Test name
Test status
Simulation time 155205331 ps
CPU time 0.96 seconds
Started Feb 04 02:37:59 PM PST 24
Finished Feb 04 02:38:01 PM PST 24
Peak memory 205432 kb
Host smart-c4a87d26-a92a-4ece-ae73-c0e4c15d10fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959960892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1959960892
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.463209743
Short name T18
Test name
Test status
Simulation time 6102453781 ps
CPU time 17.79 seconds
Started Feb 04 02:38:14 PM PST 24
Finished Feb 04 02:38:33 PM PST 24
Peak memory 216388 kb
Host smart-53cd9a0d-402d-4325-afff-edc4bcc4bea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463209743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.463209743
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2693264833
Short name T861
Test name
Test status
Simulation time 25930503148 ps
CPU time 9.38 seconds
Started Feb 04 02:38:05 PM PST 24
Finished Feb 04 02:38:17 PM PST 24
Peak memory 216476 kb
Host smart-e45e0eef-2ea8-4a04-b509-0b943e0dba8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693264833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2693264833
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.476083191
Short name T1047
Test name
Test status
Simulation time 487380306 ps
CPU time 4.13 seconds
Started Feb 04 02:38:04 PM PST 24
Finished Feb 04 02:38:10 PM PST 24
Peak memory 216784 kb
Host smart-47eacba5-bfc1-447c-b6b2-84dbff6815de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476083191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.476083191
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1139471984
Short name T743
Test name
Test status
Simulation time 51051536 ps
CPU time 0.87 seconds
Started Feb 04 02:38:16 PM PST 24
Finished Feb 04 02:38:19 PM PST 24
Peak memory 205448 kb
Host smart-ad9e6ffe-1940-4c05-b5f4-e0997a3dd462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139471984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1139471984
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.16620560
Short name T13
Test name
Test status
Simulation time 3087428442 ps
CPU time 13.42 seconds
Started Feb 04 02:38:20 PM PST 24
Finished Feb 04 02:38:34 PM PST 24
Peak memory 237044 kb
Host smart-43c6f160-9913-4863-9fa7-a87a27b61e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16620560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.16620560
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4082091730
Short name T482
Test name
Test status
Simulation time 13398108 ps
CPU time 0.75 seconds
Started Feb 04 02:38:15 PM PST 24
Finished Feb 04 02:38:18 PM PST 24
Peak memory 204064 kb
Host smart-d63c8cf5-d1b2-43e7-9452-e52419223ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082091730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4082091730
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1802419231
Short name T233
Test name
Test status
Simulation time 56201253 ps
CPU time 2.52 seconds
Started Feb 04 02:38:15 PM PST 24
Finished Feb 04 02:38:20 PM PST 24
Peak memory 216704 kb
Host smart-757e239e-82a6-4b28-8372-83ca4249ca7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802419231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1802419231
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.331974721
Short name T520
Test name
Test status
Simulation time 199269653 ps
CPU time 0.77 seconds
Started Feb 04 02:38:08 PM PST 24
Finished Feb 04 02:38:11 PM PST 24
Peak memory 206524 kb
Host smart-bd2146fb-bb71-453f-92ff-a2f03a5d6a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331974721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.331974721
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2883759425
Short name T266
Test name
Test status
Simulation time 35819776265 ps
CPU time 188.24 seconds
Started Feb 04 02:38:17 PM PST 24
Finished Feb 04 02:41:27 PM PST 24
Peak memory 251304 kb
Host smart-af4cb1c4-3fe6-484f-b178-c59853391ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883759425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2883759425
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.536601483
Short name T189
Test name
Test status
Simulation time 129041590872 ps
CPU time 140.77 seconds
Started Feb 04 02:38:15 PM PST 24
Finished Feb 04 02:40:38 PM PST 24
Peak memory 247704 kb
Host smart-e36c1f2e-74ec-4767-aaf8-68d7f74383b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536601483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.536601483
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.527702915
Short name T1054
Test name
Test status
Simulation time 107027159262 ps
CPU time 439.16 seconds
Started Feb 04 02:38:16 PM PST 24
Finished Feb 04 02:45:37 PM PST 24
Peak memory 257512 kb
Host smart-114f2fe5-a167-4673-afbe-3dffe3503175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527702915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.527702915
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2734265371
Short name T685
Test name
Test status
Simulation time 703405225 ps
CPU time 8.17 seconds
Started Feb 04 02:38:16 PM PST 24
Finished Feb 04 02:38:27 PM PST 24
Peak memory 234276 kb
Host smart-32a68d82-90c9-460f-a1fc-65ef10aa909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734265371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2734265371
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2870347538
Short name T913
Test name
Test status
Simulation time 2567601190 ps
CPU time 3.97 seconds
Started Feb 04 02:38:13 PM PST 24
Finished Feb 04 02:38:18 PM PST 24
Peak memory 218524 kb
Host smart-b033cb44-7a07-4a6c-8718-213e61325fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870347538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2870347538
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.403343010
Short name T774
Test name
Test status
Simulation time 3202748545 ps
CPU time 19.21 seconds
Started Feb 04 02:38:08 PM PST 24
Finished Feb 04 02:38:29 PM PST 24
Peak memory 240380 kb
Host smart-aaae8178-5dcf-43ca-99bf-1afae6d8479b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403343010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.403343010
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3583671710
Short name T225
Test name
Test status
Simulation time 14144899805 ps
CPU time 9.84 seconds
Started Feb 04 02:38:07 PM PST 24
Finished Feb 04 02:38:18 PM PST 24
Peak memory 224560 kb
Host smart-8e4a98bb-41de-494e-9d90-b2313815d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583671710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3583671710
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3198202910
Short name T900
Test name
Test status
Simulation time 1221677890 ps
CPU time 10.28 seconds
Started Feb 04 02:38:08 PM PST 24
Finished Feb 04 02:38:20 PM PST 24
Peak memory 233352 kb
Host smart-6c38c687-da27-4dba-818c-0eaac2829f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198202910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3198202910
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2479576303
Short name T985
Test name
Test status
Simulation time 2562403599 ps
CPU time 5.44 seconds
Started Feb 04 02:38:09 PM PST 24
Finished Feb 04 02:38:16 PM PST 24
Peak memory 222772 kb
Host smart-42f11132-3c9e-47b5-ad5d-f915cf68dfd0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2479576303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2479576303
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1577166158
Short name T644
Test name
Test status
Simulation time 11825118691 ps
CPU time 88.52 seconds
Started Feb 04 02:38:14 PM PST 24
Finished Feb 04 02:39:44 PM PST 24
Peak memory 216428 kb
Host smart-dac8ab51-1b2c-4914-8498-1e3924929b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577166158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1577166158
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1570409572
Short name T552
Test name
Test status
Simulation time 742013821 ps
CPU time 4.88 seconds
Started Feb 04 02:38:06 PM PST 24
Finished Feb 04 02:38:13 PM PST 24
Peak memory 208248 kb
Host smart-2d6dc579-565c-4672-a59f-646971862997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570409572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1570409572
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.970124833
Short name T532
Test name
Test status
Simulation time 28367459 ps
CPU time 1.03 seconds
Started Feb 04 02:38:07 PM PST 24
Finished Feb 04 02:38:09 PM PST 24
Peak memory 206252 kb
Host smart-4f416bee-176b-4dcf-b22f-de10f388e4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970124833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.970124833
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2694819235
Short name T443
Test name
Test status
Simulation time 31171233 ps
CPU time 0.8 seconds
Started Feb 04 02:38:13 PM PST 24
Finished Feb 04 02:38:15 PM PST 24
Peak memory 205388 kb
Host smart-286dc66a-9ccc-4fbc-a094-4770bb051418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694819235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2694819235
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1909175359
Short name T607
Test name
Test status
Simulation time 309743347 ps
CPU time 3.03 seconds
Started Feb 04 02:38:08 PM PST 24
Finished Feb 04 02:38:12 PM PST 24
Peak memory 233676 kb
Host smart-046258f7-8b5f-4454-86f8-25989b751c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909175359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1909175359
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4185937759
Short name T678
Test name
Test status
Simulation time 30734528 ps
CPU time 0.69 seconds
Started Feb 04 02:38:14 PM PST 24
Finished Feb 04 02:38:16 PM PST 24
Peak memory 204388 kb
Host smart-8938a916-b6eb-4bd1-9aa9-3a2f47300283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185937759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4185937759
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2672307096
Short name T936
Test name
Test status
Simulation time 529727966 ps
CPU time 3.56 seconds
Started Feb 04 02:38:12 PM PST 24
Finished Feb 04 02:38:17 PM PST 24
Peak memory 236020 kb
Host smart-7997aea2-007e-4d15-9f04-5ebad096a678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672307096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2672307096
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.498693891
Short name T1015
Test name
Test status
Simulation time 44374741 ps
CPU time 0.79 seconds
Started Feb 04 02:38:14 PM PST 24
Finished Feb 04 02:38:16 PM PST 24
Peak memory 206188 kb
Host smart-90213edc-c8d4-4a10-bcf3-1db8f6fd76a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498693891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.498693891
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4089096767
Short name T167
Test name
Test status
Simulation time 375152199060 ps
CPU time 333.43 seconds
Started Feb 04 02:38:20 PM PST 24
Finished Feb 04 02:43:55 PM PST 24
Peak memory 265604 kb
Host smart-0af0b689-3e97-4824-8deb-7cec441f80d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089096767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4089096767
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3915345640
Short name T961
Test name
Test status
Simulation time 33244757908 ps
CPU time 250.33 seconds
Started Feb 04 02:38:08 PM PST 24
Finished Feb 04 02:42:19 PM PST 24
Peak memory 251620 kb
Host smart-b3d926b2-d62c-4a8f-8726-cce63635197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915345640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3915345640
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.756084392
Short name T934
Test name
Test status
Simulation time 2887569057 ps
CPU time 32.68 seconds
Started Feb 04 02:38:20 PM PST 24
Finished Feb 04 02:38:54 PM PST 24
Peak memory 240984 kb
Host smart-02937e85-b092-4b35-bc15-45fa884e28ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756084392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.756084392
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1066505364
Short name T692
Test name
Test status
Simulation time 2479289656 ps
CPU time 18.55 seconds
Started Feb 04 02:38:10 PM PST 24
Finished Feb 04 02:38:30 PM PST 24
Peak memory 234068 kb
Host smart-33555f34-2aba-499e-8995-8c28c29fd791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066505364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1066505364
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2663416278
Short name T214
Test name
Test status
Simulation time 353290110 ps
CPU time 2.42 seconds
Started Feb 04 02:38:05 PM PST 24
Finished Feb 04 02:38:09 PM PST 24
Peak memory 217368 kb
Host smart-f1bc894c-cb73-4368-9dab-994eefbfc033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663416278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2663416278
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1662708930
Short name T207
Test name
Test status
Simulation time 1200078432 ps
CPU time 8.2 seconds
Started Feb 04 02:38:15 PM PST 24
Finished Feb 04 02:38:24 PM PST 24
Peak memory 233760 kb
Host smart-b9350b4b-ce39-4180-9cbe-5474ed240bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662708930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1662708930
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1374284196
Short name T444
Test name
Test status
Simulation time 123975409 ps
CPU time 3.32 seconds
Started Feb 04 02:38:06 PM PST 24
Finished Feb 04 02:38:12 PM PST 24
Peak memory 232580 kb
Host smart-6b957527-bbfd-4421-80eb-9f9400c31ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374284196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1374284196
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1285600682
Short name T310
Test name
Test status
Simulation time 12526659483 ps
CPU time 31.17 seconds
Started Feb 04 02:38:13 PM PST 24
Finished Feb 04 02:38:45 PM PST 24
Peak memory 240700 kb
Host smart-9955dfbe-b0b7-4781-a2a3-5bc5b1ba2828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285600682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1285600682
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1024277667
Short name T447
Test name
Test status
Simulation time 676271519 ps
CPU time 3.29 seconds
Started Feb 04 02:38:13 PM PST 24
Finished Feb 04 02:38:17 PM PST 24
Peak memory 220308 kb
Host smart-38480772-cf9f-4cd4-aa1f-c2d0bb4df8c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1024277667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1024277667
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1297500542
Short name T210
Test name
Test status
Simulation time 279364439866 ps
CPU time 456.34 seconds
Started Feb 04 02:38:12 PM PST 24
Finished Feb 04 02:45:50 PM PST 24
Peak memory 259580 kb
Host smart-2f0f43a6-8e8b-4d99-bc6a-08bb0a74dff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297500542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1297500542
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1623248386
Short name T854
Test name
Test status
Simulation time 9095150865 ps
CPU time 70.16 seconds
Started Feb 04 02:38:09 PM PST 24
Finished Feb 04 02:39:20 PM PST 24
Peak memory 216460 kb
Host smart-89bf2541-20a3-4fa2-a544-3474595caaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623248386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1623248386
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2416248105
Short name T309
Test name
Test status
Simulation time 12582558899 ps
CPU time 12.81 seconds
Started Feb 04 02:38:08 PM PST 24
Finished Feb 04 02:38:23 PM PST 24
Peak memory 216408 kb
Host smart-bcc095f9-ab8c-4784-8480-58f70d1ee5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416248105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2416248105
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.803375765
Short name T456
Test name
Test status
Simulation time 255400944 ps
CPU time 1.36 seconds
Started Feb 04 02:38:10 PM PST 24
Finished Feb 04 02:38:13 PM PST 24
Peak memory 207968 kb
Host smart-86eca9bb-4a51-403d-9f61-09e3f32cf5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803375765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.803375765
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3918161422
Short name T558
Test name
Test status
Simulation time 232483509 ps
CPU time 0.79 seconds
Started Feb 04 02:38:09 PM PST 24
Finished Feb 04 02:38:12 PM PST 24
Peak memory 205444 kb
Host smart-a1429539-cc78-40b0-a7af-4a8f42dcc1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918161422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3918161422
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.929651609
Short name T955
Test name
Test status
Simulation time 48361621640 ps
CPU time 24.94 seconds
Started Feb 04 02:38:15 PM PST 24
Finished Feb 04 02:38:41 PM PST 24
Peak memory 234152 kb
Host smart-3ff5d6b8-ebd5-4ec1-bfd9-752d353a62cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929651609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.929651609
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4225230820
Short name T783
Test name
Test status
Simulation time 14610585 ps
CPU time 0.77 seconds
Started Feb 04 02:38:17 PM PST 24
Finished Feb 04 02:38:20 PM PST 24
Peak memory 204944 kb
Host smart-a147f9f5-86e7-435d-94f0-adc1daf40156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225230820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4225230820
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4111583162
Short name T969
Test name
Test status
Simulation time 1084421699 ps
CPU time 3.91 seconds
Started Feb 04 02:38:15 PM PST 24
Finished Feb 04 02:38:20 PM PST 24
Peak memory 233716 kb
Host smart-f1dec591-9805-4420-a4c5-44db5b9e40f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111583162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4111583162
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.95296382
Short name T524
Test name
Test status
Simulation time 20351618 ps
CPU time 0.82 seconds
Started Feb 04 02:38:21 PM PST 24
Finished Feb 04 02:38:23 PM PST 24
Peak memory 206204 kb
Host smart-5a9f9b8a-e821-4f62-b7c8-0d68f2c4360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95296382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.95296382
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2857672968
Short name T933
Test name
Test status
Simulation time 25622820736 ps
CPU time 142.36 seconds
Started Feb 04 02:38:14 PM PST 24
Finished Feb 04 02:40:37 PM PST 24
Peak memory 250512 kb
Host smart-6bb59085-acfd-4acd-99c8-c9a4965829fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857672968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2857672968
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2998332895
Short name T818
Test name
Test status
Simulation time 92834788423 ps
CPU time 257.44 seconds
Started Feb 04 02:38:15 PM PST 24
Finished Feb 04 02:42:33 PM PST 24
Peak memory 263576 kb
Host smart-5c73f438-b250-43f0-b62f-077f179e7a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998332895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2998332895
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.93230128
Short name T1053
Test name
Test status
Simulation time 48169197214 ps
CPU time 187.01 seconds
Started Feb 04 02:38:21 PM PST 24
Finished Feb 04 02:41:29 PM PST 24
Peak memory 235936 kb
Host smart-294731fc-015e-48fa-a58f-59c2453a52fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93230128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.93230128
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2128250992
Short name T119
Test name
Test status
Simulation time 12758065173 ps
CPU time 32.98 seconds
Started Feb 04 02:38:18 PM PST 24
Finished Feb 04 02:38:52 PM PST 24
Peak memory 246708 kb
Host smart-3759d409-62aa-4d40-bd46-75a499f4fb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128250992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2128250992
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2974060912
Short name T699
Test name
Test status
Simulation time 2707550199 ps
CPU time 6.19 seconds
Started Feb 04 02:38:11 PM PST 24
Finished Feb 04 02:38:18 PM PST 24
Peak memory 219208 kb
Host smart-27e5ee79-9351-45aa-8da7-32f5691a27b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974060912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2974060912
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.32802009
Short name T1071
Test name
Test status
Simulation time 780425729 ps
CPU time 5.88 seconds
Started Feb 04 02:38:20 PM PST 24
Finished Feb 04 02:38:27 PM PST 24
Peak memory 234160 kb
Host smart-ccf9c7c4-bc3c-4f71-b8bc-bd729b16b95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32802009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.32802009
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1209414716
Short name T31
Test name
Test status
Simulation time 46071982791 ps
CPU time 19.61 seconds
Started Feb 04 02:38:20 PM PST 24
Finished Feb 04 02:38:40 PM PST 24
Peak memory 233044 kb
Host smart-8789a270-3c64-4e4a-815a-c3178510df92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209414716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1209414716
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.140735170
Short name T134
Test name
Test status
Simulation time 3024465747 ps
CPU time 9.87 seconds
Started Feb 04 02:38:10 PM PST 24
Finished Feb 04 02:38:21 PM PST 24
Peak memory 216656 kb
Host smart-3eb5989e-6a87-4981-b685-111d84fb410a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140735170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.140735170
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3284516741
Short name T1043
Test name
Test status
Simulation time 4781838868 ps
CPU time 5.41 seconds
Started Feb 04 02:38:10 PM PST 24
Finished Feb 04 02:38:17 PM PST 24
Peak memory 222180 kb
Host smart-c2d72fb6-3022-44dd-8cca-bf38f8522c8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3284516741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3284516741
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1756279805
Short name T590
Test name
Test status
Simulation time 16289361277 ps
CPU time 58.79 seconds
Started Feb 04 02:38:11 PM PST 24
Finished Feb 04 02:39:11 PM PST 24
Peak memory 216444 kb
Host smart-a19de5d4-fd4d-498b-a2bf-840fd2ed6c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756279805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1756279805
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2669578940
Short name T490
Test name
Test status
Simulation time 8200047025 ps
CPU time 14.42 seconds
Started Feb 04 02:38:16 PM PST 24
Finished Feb 04 02:38:32 PM PST 24
Peak memory 216336 kb
Host smart-90cb9ef0-2e03-43e6-8e8b-24a33b5362d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669578940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2669578940
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.388811856
Short name T1035
Test name
Test status
Simulation time 49804378 ps
CPU time 1.78 seconds
Started Feb 04 02:38:16 PM PST 24
Finished Feb 04 02:38:20 PM PST 24
Peak memory 208484 kb
Host smart-559f22a3-5ec9-4cbc-bb88-1fa4c2671c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388811856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.388811856
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2737135779
Short name T912
Test name
Test status
Simulation time 24621207 ps
CPU time 0.84 seconds
Started Feb 04 02:38:15 PM PST 24
Finished Feb 04 02:38:18 PM PST 24
Peak memory 205444 kb
Host smart-40784e11-5099-4e49-8248-7e9d3a46bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737135779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2737135779
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2463458821
Short name T479
Test name
Test status
Simulation time 4406953014 ps
CPU time 9.97 seconds
Started Feb 04 02:38:22 PM PST 24
Finished Feb 04 02:38:35 PM PST 24
Peak memory 238236 kb
Host smart-300ac00d-5dbb-4105-a1b4-58fe5dcc0fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463458821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2463458821
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1738303616
Short name T478
Test name
Test status
Simulation time 14970680 ps
CPU time 0.72 seconds
Started Feb 04 02:34:24 PM PST 24
Finished Feb 04 02:34:37 PM PST 24
Peak memory 204348 kb
Host smart-ddbeb48a-e1f3-4c72-9873-d0e8ba91918d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738303616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
738303616
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.337444944
Short name T842
Test name
Test status
Simulation time 146793567 ps
CPU time 2.42 seconds
Started Feb 04 02:34:26 PM PST 24
Finished Feb 04 02:34:40 PM PST 24
Peak memory 224564 kb
Host smart-8b130efd-5f90-4d3a-b98b-5210e8264261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337444944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.337444944
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1490838906
Short name T1004
Test name
Test status
Simulation time 61181602 ps
CPU time 0.73 seconds
Started Feb 04 02:34:20 PM PST 24
Finished Feb 04 02:34:24 PM PST 24
Peak memory 205108 kb
Host smart-a1d794d5-71fd-4625-bfb5-cb3a1302fa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490838906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1490838906
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2558520575
Short name T29
Test name
Test status
Simulation time 48046883471 ps
CPU time 115.97 seconds
Started Feb 04 02:34:33 PM PST 24
Finished Feb 04 02:36:34 PM PST 24
Peak memory 256608 kb
Host smart-1d6d236a-cb83-4e6e-a90f-a2b819e49bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558520575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2558520575
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.473102950
Short name T244
Test name
Test status
Simulation time 192288842137 ps
CPU time 253 seconds
Started Feb 04 02:34:27 PM PST 24
Finished Feb 04 02:38:51 PM PST 24
Peak memory 265688 kb
Host smart-3aa816ca-3b87-4012-8ca0-a0784fc5bd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473102950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.473102950
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.435244566
Short name T174
Test name
Test status
Simulation time 108702424858 ps
CPU time 113.68 seconds
Started Feb 04 02:34:25 PM PST 24
Finished Feb 04 02:36:32 PM PST 24
Peak memory 257652 kb
Host smart-a22efe8a-6d20-40ce-a78e-87477955dfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435244566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
435244566
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3825295963
Short name T533
Test name
Test status
Simulation time 7845433683 ps
CPU time 12.91 seconds
Started Feb 04 02:34:31 PM PST 24
Finished Feb 04 02:34:51 PM PST 24
Peak memory 238604 kb
Host smart-d7b7f156-b2fa-4bbd-9c7e-e0c608e5bd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825295963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3825295963
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2142414287
Short name T737
Test name
Test status
Simulation time 2424122259 ps
CPU time 6.21 seconds
Started Feb 04 02:34:25 PM PST 24
Finished Feb 04 02:34:44 PM PST 24
Peak memory 224640 kb
Host smart-44f8653b-f4f0-4535-84ec-a0ef5e42a903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142414287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2142414287
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1752004927
Short name T1040
Test name
Test status
Simulation time 4108520131 ps
CPU time 12.65 seconds
Started Feb 04 02:34:46 PM PST 24
Finished Feb 04 02:35:00 PM PST 24
Peak memory 218000 kb
Host smart-a913a4e8-f408-46c9-9099-466b97ae561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752004927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1752004927
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1432240824
Short name T1003
Test name
Test status
Simulation time 20991814 ps
CPU time 0.98 seconds
Started Feb 04 02:34:20 PM PST 24
Finished Feb 04 02:34:25 PM PST 24
Peak memory 217916 kb
Host smart-0a3d784e-ed17-4610-b472-a2a7a2c92d15
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432240824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1432240824
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3202885911
Short name T597
Test name
Test status
Simulation time 509562872 ps
CPU time 3.01 seconds
Started Feb 04 02:34:24 PM PST 24
Finished Feb 04 02:34:41 PM PST 24
Peak memory 233376 kb
Host smart-0bc63df0-01c6-49d1-b483-c97f866594fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202885911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3202885911
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2222573373
Short name T468
Test name
Test status
Simulation time 105252654 ps
CPU time 2.82 seconds
Started Feb 04 02:34:27 PM PST 24
Finished Feb 04 02:34:41 PM PST 24
Peak memory 218144 kb
Host smart-3bd961b9-7d64-4d8a-93f0-0d3ea9421cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222573373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2222573373
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.1256099587
Short name T893
Test name
Test status
Simulation time 23307653 ps
CPU time 0.74 seconds
Started Feb 04 02:34:16 PM PST 24
Finished Feb 04 02:34:22 PM PST 24
Peak memory 216292 kb
Host smart-2836044d-a37b-46e1-9ca9-1266bdd6168c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256099587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1256099587
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3103717149
Short name T15
Test name
Test status
Simulation time 962766529 ps
CPU time 3.33 seconds
Started Feb 04 02:34:32 PM PST 24
Finished Feb 04 02:34:42 PM PST 24
Peak memory 220232 kb
Host smart-43651eb3-07e5-4618-b485-ee0e7bd456d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3103717149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3103717149
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3436649717
Short name T987
Test name
Test status
Simulation time 366884036115 ps
CPU time 686.9 seconds
Started Feb 04 02:34:27 PM PST 24
Finished Feb 04 02:46:05 PM PST 24
Peak memory 267752 kb
Host smart-aa75aa20-0cf4-4fa3-a19f-4b5e841a709c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436649717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3436649717
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2176678634
Short name T858
Test name
Test status
Simulation time 7014337067 ps
CPU time 98.24 seconds
Started Feb 04 02:34:17 PM PST 24
Finished Feb 04 02:36:01 PM PST 24
Peak memory 216328 kb
Host smart-12f06923-0954-44b0-88ee-ea07aeaf328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176678634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2176678634
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.4267056815
Short name T651
Test name
Test status
Simulation time 2720221838 ps
CPU time 4.58 seconds
Started Feb 04 02:34:16 PM PST 24
Finished Feb 04 02:34:26 PM PST 24
Peak memory 216320 kb
Host smart-19d5632c-7e87-4f93-b1af-bd4c785bdd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267056815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.4267056815
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3002023639
Short name T563
Test name
Test status
Simulation time 64141288 ps
CPU time 1.32 seconds
Started Feb 04 02:34:28 PM PST 24
Finished Feb 04 02:34:39 PM PST 24
Peak memory 207832 kb
Host smart-c1ce53fb-5bb0-4a10-888e-c320e7dc6ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002023639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3002023639
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2765553015
Short name T745
Test name
Test status
Simulation time 336815157 ps
CPU time 0.94 seconds
Started Feb 04 02:34:18 PM PST 24
Finished Feb 04 02:34:24 PM PST 24
Peak memory 205432 kb
Host smart-0e743e5f-b6e4-4275-a43b-73e9e0ace14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765553015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2765553015
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2188700632
Short name T173
Test name
Test status
Simulation time 455319166 ps
CPU time 4.27 seconds
Started Feb 04 02:34:28 PM PST 24
Finished Feb 04 02:34:42 PM PST 24
Peak memory 234920 kb
Host smart-34563dc3-80d6-44d8-91f9-3a06a67278b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188700632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2188700632
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1905952990
Short name T534
Test name
Test status
Simulation time 15226047 ps
CPU time 0.7 seconds
Started Feb 04 02:34:37 PM PST 24
Finished Feb 04 02:34:41 PM PST 24
Peak memory 204944 kb
Host smart-654c7aff-5afb-4ba8-bb36-74cc7a40f1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905952990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
905952990
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4203652422
Short name T670
Test name
Test status
Simulation time 1547595696 ps
CPU time 4.07 seconds
Started Feb 04 02:34:37 PM PST 24
Finished Feb 04 02:34:44 PM PST 24
Peak memory 233632 kb
Host smart-4c37c359-3671-4de2-8d27-f5963320c7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203652422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4203652422
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3214932162
Short name T641
Test name
Test status
Simulation time 72826823 ps
CPU time 0.75 seconds
Started Feb 04 02:34:29 PM PST 24
Finished Feb 04 02:34:39 PM PST 24
Peak memory 205116 kb
Host smart-caaf7b2f-9b0c-434e-8cfa-f4c62578f2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214932162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3214932162
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2904132344
Short name T804
Test name
Test status
Simulation time 59462192167 ps
CPU time 156.62 seconds
Started Feb 04 02:34:37 PM PST 24
Finished Feb 04 02:37:16 PM PST 24
Peak memory 249168 kb
Host smart-94465141-5ef9-49ac-b69f-0a728dc43e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904132344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2904132344
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2108898843
Short name T26
Test name
Test status
Simulation time 103166235690 ps
CPU time 192.86 seconds
Started Feb 04 02:34:35 PM PST 24
Finished Feb 04 02:37:52 PM PST 24
Peak memory 248624 kb
Host smart-f1b24c3d-9a81-4623-9996-bf93d0555cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108898843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2108898843
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.773173202
Short name T1046
Test name
Test status
Simulation time 8820848505 ps
CPU time 65.89 seconds
Started Feb 04 02:34:36 PM PST 24
Finished Feb 04 02:35:45 PM PST 24
Peak memory 232900 kb
Host smart-1d7772ca-a1c6-4673-bad5-98be8688eb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773173202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
773173202
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.304092696
Short name T501
Test name
Test status
Simulation time 23178943859 ps
CPU time 37.01 seconds
Started Feb 04 02:34:37 PM PST 24
Finished Feb 04 02:35:17 PM PST 24
Peak memory 232764 kb
Host smart-21d1eea8-091e-4559-9085-68b01f88f16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304092696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.304092696
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2636834907
Short name T193
Test name
Test status
Simulation time 219225289 ps
CPU time 2.3 seconds
Started Feb 04 02:34:41 PM PST 24
Finished Feb 04 02:34:45 PM PST 24
Peak memory 216808 kb
Host smart-28e3e9e4-ee53-4c79-bb56-5f2dcf7b2471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636834907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2636834907
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2591175323
Short name T188
Test name
Test status
Simulation time 6479687975 ps
CPU time 8.9 seconds
Started Feb 04 02:34:24 PM PST 24
Finished Feb 04 02:34:47 PM PST 24
Peak memory 233728 kb
Host smart-ff7a87d7-e8f0-4b8a-bb72-2e6edcf87daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591175323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2591175323
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3302490898
Short name T537
Test name
Test status
Simulation time 14282562 ps
CPU time 1.04 seconds
Started Feb 04 02:34:29 PM PST 24
Finished Feb 04 02:34:39 PM PST 24
Peak memory 217856 kb
Host smart-46393bcb-30fe-4763-8f0f-94ab350bbd27
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302490898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3302490898
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3895175092
Short name T820
Test name
Test status
Simulation time 750141502 ps
CPU time 9.84 seconds
Started Feb 04 02:34:28 PM PST 24
Finished Feb 04 02:34:48 PM PST 24
Peak memory 227956 kb
Host smart-31c8daa7-467f-4e81-9317-25b9bc87ef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895175092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3895175092
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3229175205
Short name T1026
Test name
Test status
Simulation time 14539665673 ps
CPU time 19.79 seconds
Started Feb 04 02:34:38 PM PST 24
Finished Feb 04 02:35:00 PM PST 24
Peak memory 235016 kb
Host smart-fabc8938-b2b7-4adf-ac77-3f25fd493b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229175205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3229175205
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.1144361625
Short name T964
Test name
Test status
Simulation time 18559341 ps
CPU time 0.75 seconds
Started Feb 04 02:34:30 PM PST 24
Finished Feb 04 02:34:39 PM PST 24
Peak memory 216228 kb
Host smart-1ea6459f-9bc6-486e-af97-902b5380fd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144361625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.1144361625
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1151989042
Short name T1044
Test name
Test status
Simulation time 619948545 ps
CPU time 4.34 seconds
Started Feb 04 02:34:40 PM PST 24
Finished Feb 04 02:34:46 PM PST 24
Peak memory 218840 kb
Host smart-cd30f29f-179e-48d1-8b4d-f4602781aaf3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1151989042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1151989042
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4153080446
Short name T449
Test name
Test status
Simulation time 19740894319 ps
CPU time 66.16 seconds
Started Feb 04 02:34:33 PM PST 24
Finished Feb 04 02:35:44 PM PST 24
Peak memory 238084 kb
Host smart-97dafa8b-308b-42d8-937f-d3b7eadf41a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153080446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4153080446
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.34451242
Short name T835
Test name
Test status
Simulation time 5086252577 ps
CPU time 18.73 seconds
Started Feb 04 02:34:24 PM PST 24
Finished Feb 04 02:34:55 PM PST 24
Peak memory 216476 kb
Host smart-51a011e5-5797-41fa-bdd4-bda1417d3f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34451242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.34451242
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3389329290
Short name T1091
Test name
Test status
Simulation time 4802595207 ps
CPU time 8.87 seconds
Started Feb 04 02:34:29 PM PST 24
Finished Feb 04 02:34:47 PM PST 24
Peak memory 216396 kb
Host smart-4e70a497-cbbe-4dbe-b4ac-fd6d6dc0728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389329290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3389329290
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1228450930
Short name T729
Test name
Test status
Simulation time 489612880 ps
CPU time 4.97 seconds
Started Feb 04 02:34:25 PM PST 24
Finished Feb 04 02:34:43 PM PST 24
Peak memory 216360 kb
Host smart-2abb6e20-1a20-46e1-aafc-6f6d7c312947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228450930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1228450930
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1506937373
Short name T568
Test name
Test status
Simulation time 28695844 ps
CPU time 0.76 seconds
Started Feb 04 02:34:26 PM PST 24
Finished Feb 04 02:34:38 PM PST 24
Peak memory 205440 kb
Host smart-c11d66ce-c397-485e-941a-f009e463d3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506937373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1506937373
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4155895218
Short name T489
Test name
Test status
Simulation time 16494486 ps
CPU time 0.7 seconds
Started Feb 04 02:34:54 PM PST 24
Finished Feb 04 02:34:56 PM PST 24
Peak memory 204384 kb
Host smart-aa78243d-72de-4434-bc73-c5ae43a2328f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155895218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
155895218
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1593679393
Short name T945
Test name
Test status
Simulation time 4881507034 ps
CPU time 3.9 seconds
Started Feb 04 02:34:38 PM PST 24
Finished Feb 04 02:34:44 PM PST 24
Peak memory 219496 kb
Host smart-72461851-3b40-4d6f-9de1-1a62f28a6f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593679393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1593679393
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1882072677
Short name T24
Test name
Test status
Simulation time 15736892 ps
CPU time 0.77 seconds
Started Feb 04 02:34:37 PM PST 24
Finished Feb 04 02:34:41 PM PST 24
Peak memory 205160 kb
Host smart-31379531-cade-414e-8dd2-18c52e40b540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882072677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1882072677
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2913566517
Short name T983
Test name
Test status
Simulation time 1212740823 ps
CPU time 15.79 seconds
Started Feb 04 02:34:54 PM PST 24
Finished Feb 04 02:35:11 PM PST 24
Peak memory 229224 kb
Host smart-1dc2e860-6996-48a4-a957-0b83099e4b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913566517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2913566517
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3118140069
Short name T428
Test name
Test status
Simulation time 7683631142 ps
CPU time 56.23 seconds
Started Feb 04 02:35:01 PM PST 24
Finished Feb 04 02:35:58 PM PST 24
Peak memory 249928 kb
Host smart-c9760cc7-dbe0-40f2-a82f-a67fced0b545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118140069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3118140069
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2476802717
Short name T36
Test name
Test status
Simulation time 76115449524 ps
CPU time 149.26 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:37:40 PM PST 24
Peak memory 253588 kb
Host smart-fe325ae2-0fb2-408e-a299-a2048d065cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476802717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2476802717
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.371942968
Short name T273
Test name
Test status
Simulation time 14703231833 ps
CPU time 26.78 seconds
Started Feb 04 02:34:44 PM PST 24
Finished Feb 04 02:35:12 PM PST 24
Peak memory 232120 kb
Host smart-77a027ff-87cb-4104-87a3-ad919ca2aff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371942968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.371942968
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3585842250
Short name T196
Test name
Test status
Simulation time 1035299724 ps
CPU time 3.49 seconds
Started Feb 04 02:34:36 PM PST 24
Finished Feb 04 02:34:43 PM PST 24
Peak memory 232920 kb
Host smart-ad1944cd-6e90-45c2-b4bd-040c15d50471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585842250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3585842250
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2211954349
Short name T1002
Test name
Test status
Simulation time 24742940769 ps
CPU time 17.29 seconds
Started Feb 04 02:34:38 PM PST 24
Finished Feb 04 02:34:58 PM PST 24
Peak memory 233304 kb
Host smart-b9f951c0-2100-420b-9857-fb99c4050ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211954349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2211954349
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2665787063
Short name T767
Test name
Test status
Simulation time 66076126 ps
CPU time 0.97 seconds
Started Feb 04 02:34:43 PM PST 24
Finished Feb 04 02:34:44 PM PST 24
Peak memory 217840 kb
Host smart-ca54b870-4759-44db-bb37-20a056f5b0b0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665787063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2665787063
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2166207318
Short name T180
Test name
Test status
Simulation time 1563159374 ps
CPU time 10.22 seconds
Started Feb 04 02:34:40 PM PST 24
Finished Feb 04 02:34:52 PM PST 24
Peak memory 232800 kb
Host smart-04004ff7-9b86-4201-a8b1-df9be1491666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166207318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2166207318
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2579185338
Short name T208
Test name
Test status
Simulation time 2065642686 ps
CPU time 6.95 seconds
Started Feb 04 02:34:34 PM PST 24
Finished Feb 04 02:34:46 PM PST 24
Peak memory 217728 kb
Host smart-1cb5d2eb-c83a-4fe6-8811-b900b012df73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579185338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2579185338
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.3087221008
Short name T506
Test name
Test status
Simulation time 34646281 ps
CPU time 0.72 seconds
Started Feb 04 02:34:34 PM PST 24
Finished Feb 04 02:34:40 PM PST 24
Peak memory 216268 kb
Host smart-09ed47ab-4efd-4c04-a03f-e785fbc4eb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087221008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.3087221008
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1437576024
Short name T122
Test name
Test status
Simulation time 182966126 ps
CPU time 3.84 seconds
Started Feb 04 02:34:53 PM PST 24
Finished Feb 04 02:34:59 PM PST 24
Peak memory 222104 kb
Host smart-aa5c06c2-25a5-4915-87ed-85a684979f21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1437576024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1437576024
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3704188152
Short name T617
Test name
Test status
Simulation time 1634650636 ps
CPU time 20.11 seconds
Started Feb 04 02:34:35 PM PST 24
Finished Feb 04 02:34:59 PM PST 24
Peak memory 216404 kb
Host smart-3a32b8d5-91dd-4ddb-8d4a-637edbf894e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704188152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3704188152
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3864496595
Short name T484
Test name
Test status
Simulation time 2493203417 ps
CPU time 5.29 seconds
Started Feb 04 02:34:41 PM PST 24
Finished Feb 04 02:34:47 PM PST 24
Peak memory 216488 kb
Host smart-9e57dbee-19c7-4c4c-964b-bc2bae2db71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864496595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3864496595
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4169229359
Short name T589
Test name
Test status
Simulation time 186216310 ps
CPU time 3.69 seconds
Started Feb 04 02:34:30 PM PST 24
Finished Feb 04 02:34:42 PM PST 24
Peak memory 216512 kb
Host smart-32927141-b4cc-47e0-8af4-0c5872e6ec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169229359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4169229359
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1408893836
Short name T426
Test name
Test status
Simulation time 187686318 ps
CPU time 0.93 seconds
Started Feb 04 02:34:40 PM PST 24
Finished Feb 04 02:34:43 PM PST 24
Peak memory 206432 kb
Host smart-9b614e90-ea90-4f8c-82a3-b447a4c2a390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408893836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1408893836
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3192961454
Short name T205
Test name
Test status
Simulation time 20292534674 ps
CPU time 29.99 seconds
Started Feb 04 02:34:37 PM PST 24
Finished Feb 04 02:35:10 PM PST 24
Peak memory 219848 kb
Host smart-1e59a06d-3d2d-41ae-9a77-e2cd7189bcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192961454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3192961454
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1585618285
Short name T826
Test name
Test status
Simulation time 51382194 ps
CPU time 0.71 seconds
Started Feb 04 02:35:03 PM PST 24
Finished Feb 04 02:35:08 PM PST 24
Peak memory 204984 kb
Host smart-12a31575-204a-4e67-a285-c2157139353b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585618285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
585618285
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2486652977
Short name T1007
Test name
Test status
Simulation time 500646386 ps
CPU time 2.97 seconds
Started Feb 04 02:34:54 PM PST 24
Finished Feb 04 02:34:58 PM PST 24
Peak memory 224516 kb
Host smart-c81b1d43-cb1c-4298-bbed-cf348545bfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486652977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2486652977
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1449202580
Short name T446
Test name
Test status
Simulation time 16080504 ps
CPU time 0.78 seconds
Started Feb 04 02:34:55 PM PST 24
Finished Feb 04 02:34:59 PM PST 24
Peak memory 206216 kb
Host smart-0a3aa320-244e-4266-89e1-53a095ada67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449202580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1449202580
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.106847447
Short name T662
Test name
Test status
Simulation time 191345407046 ps
CPU time 236.88 seconds
Started Feb 04 02:34:52 PM PST 24
Finished Feb 04 02:38:52 PM PST 24
Peak memory 239508 kb
Host smart-3977a6af-acb3-42e2-ae0f-ec3c268c0d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106847447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.106847447
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2182770568
Short name T508
Test name
Test status
Simulation time 90162461551 ps
CPU time 192.46 seconds
Started Feb 04 02:35:09 PM PST 24
Finished Feb 04 02:38:27 PM PST 24
Peak memory 249276 kb
Host smart-7faf112f-4e27-464d-b198-79cbbd88d049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182770568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2182770568
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3989404451
Short name T258
Test name
Test status
Simulation time 2882854820 ps
CPU time 61.69 seconds
Started Feb 04 02:35:06 PM PST 24
Finished Feb 04 02:36:13 PM PST 24
Peak memory 237768 kb
Host smart-9f3581e7-710a-4398-8519-2fe4f79bb6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989404451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3989404451
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2457316486
Short name T996
Test name
Test status
Simulation time 8468688363 ps
CPU time 38.63 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:35:50 PM PST 24
Peak memory 246772 kb
Host smart-57fdf4f4-cf8e-4bc1-b235-f7b1dafffe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457316486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2457316486
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.701578989
Short name T218
Test name
Test status
Simulation time 5691502371 ps
CPU time 4.85 seconds
Started Feb 04 02:34:55 PM PST 24
Finished Feb 04 02:35:02 PM PST 24
Peak memory 219980 kb
Host smart-61a3d293-0c32-4f88-97b4-faae58469d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701578989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.701578989
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2445860809
Short name T526
Test name
Test status
Simulation time 11208439642 ps
CPU time 15.16 seconds
Started Feb 04 02:34:57 PM PST 24
Finished Feb 04 02:35:14 PM PST 24
Peak memory 250044 kb
Host smart-be3dac60-e4a6-472f-8ce7-7afff212f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445860809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2445860809
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1164440872
Short name T9
Test name
Test status
Simulation time 26713820 ps
CPU time 1.03 seconds
Started Feb 04 02:35:00 PM PST 24
Finished Feb 04 02:35:02 PM PST 24
Peak memory 216664 kb
Host smart-f15a7dab-22ed-4ab4-963b-a68ec388b468
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164440872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1164440872
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3877418856
Short name T572
Test name
Test status
Simulation time 3446054076 ps
CPU time 4.41 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:35:15 PM PST 24
Peak memory 233092 kb
Host smart-bc476b5e-c751-4d32-bdd9-23f4f92a317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877418856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3877418856
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1150081452
Short name T809
Test name
Test status
Simulation time 54272505 ps
CPU time 1.96 seconds
Started Feb 04 02:34:44 PM PST 24
Finished Feb 04 02:34:47 PM PST 24
Peak memory 216444 kb
Host smart-3233da72-2155-46c6-9934-3a7e8ab3bbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150081452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1150081452
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.174460984
Short name T454
Test name
Test status
Simulation time 18042880 ps
CPU time 0.74 seconds
Started Feb 04 02:34:55 PM PST 24
Finished Feb 04 02:34:59 PM PST 24
Peak memory 216252 kb
Host smart-df9ba393-bb6a-4a10-aabd-60f5fa5acca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174460984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.174460984
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3964357526
Short name T465
Test name
Test status
Simulation time 881410986 ps
CPU time 3.42 seconds
Started Feb 04 02:35:03 PM PST 24
Finished Feb 04 02:35:11 PM PST 24
Peak memory 218732 kb
Host smart-200d35f5-d768-4e09-aba3-1af109307f56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3964357526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3964357526
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4229571306
Short name T259
Test name
Test status
Simulation time 359971044461 ps
CPU time 613.02 seconds
Started Feb 04 02:34:54 PM PST 24
Finished Feb 04 02:45:08 PM PST 24
Peak memory 282000 kb
Host smart-ecb13d94-f43b-4b34-9d3f-572988d20109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229571306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4229571306
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2764867107
Short name T1104
Test name
Test status
Simulation time 2856000313 ps
CPU time 40.7 seconds
Started Feb 04 02:35:00 PM PST 24
Finished Feb 04 02:35:42 PM PST 24
Peak memory 216464 kb
Host smart-9fd8995f-088e-4a38-b734-7981a5cbf858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764867107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2764867107
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2327709724
Short name T672
Test name
Test status
Simulation time 43256098871 ps
CPU time 23.26 seconds
Started Feb 04 02:34:59 PM PST 24
Finished Feb 04 02:35:24 PM PST 24
Peak memory 216460 kb
Host smart-fdc3f38b-8a7f-4977-899d-2bbf3ce83ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327709724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2327709724
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1529315485
Short name T631
Test name
Test status
Simulation time 251385890 ps
CPU time 1.13 seconds
Started Feb 04 02:35:09 PM PST 24
Finished Feb 04 02:35:15 PM PST 24
Peak memory 207908 kb
Host smart-c74ad3d0-39b8-43bf-bd45-92d80862fe69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529315485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1529315485
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.145056973
Short name T494
Test name
Test status
Simulation time 958884550 ps
CPU time 1.05 seconds
Started Feb 04 02:34:54 PM PST 24
Finished Feb 04 02:34:58 PM PST 24
Peak memory 206456 kb
Host smart-951849d8-c47f-4568-bccd-0bae932ffcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145056973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.145056973
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4021291146
Short name T37
Test name
Test status
Simulation time 7945445950 ps
CPU time 30.17 seconds
Started Feb 04 02:34:55 PM PST 24
Finished Feb 04 02:35:28 PM PST 24
Peak memory 240328 kb
Host smart-4db3fe85-ed11-45a1-bb81-a2c96426f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021291146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4021291146
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.180989559
Short name T425
Test name
Test status
Simulation time 24208085 ps
CPU time 0.79 seconds
Started Feb 04 02:35:01 PM PST 24
Finished Feb 04 02:35:05 PM PST 24
Peak memory 205280 kb
Host smart-a7bc02db-10c6-445f-b3cf-9e8a777dd8db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180989559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.180989559
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3226733086
Short name T897
Test name
Test status
Simulation time 873958467 ps
CPU time 4.63 seconds
Started Feb 04 02:35:03 PM PST 24
Finished Feb 04 02:35:12 PM PST 24
Peak memory 233360 kb
Host smart-da039809-e63f-4c33-9a91-adb6f2c56826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226733086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3226733086
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1621389991
Short name T1051
Test name
Test status
Simulation time 34323101 ps
CPU time 0.8 seconds
Started Feb 04 02:35:04 PM PST 24
Finished Feb 04 02:35:11 PM PST 24
Peak memory 206516 kb
Host smart-84e431da-dc13-44a7-b701-3fd210b41393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621389991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1621389991
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2245245803
Short name T974
Test name
Test status
Simulation time 370900376 ps
CPU time 7.92 seconds
Started Feb 04 02:34:57 PM PST 24
Finished Feb 04 02:35:06 PM PST 24
Peak memory 224560 kb
Host smart-8dcb8c49-4e71-42c9-94a3-022728d29761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245245803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2245245803
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1177142197
Short name T184
Test name
Test status
Simulation time 260930976808 ps
CPU time 458.54 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:42:49 PM PST 24
Peak memory 255380 kb
Host smart-debc3680-bb52-4545-8ae7-f00a0c1fbc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177142197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1177142197
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2896174584
Short name T1006
Test name
Test status
Simulation time 2790862443 ps
CPU time 48.63 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:36:00 PM PST 24
Peak memory 223216 kb
Host smart-8f7f68bf-6390-4a57-bd4d-1556f5c6b24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896174584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2896174584
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.207131662
Short name T17
Test name
Test status
Simulation time 4466076089 ps
CPU time 27.96 seconds
Started Feb 04 02:35:06 PM PST 24
Finished Feb 04 02:35:40 PM PST 24
Peak memory 240768 kb
Host smart-43f46f32-e37d-4338-8530-aed0d94e5b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207131662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.207131662
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.707428149
Short name T172
Test name
Test status
Simulation time 3592150397 ps
CPU time 6.76 seconds
Started Feb 04 02:34:55 PM PST 24
Finished Feb 04 02:35:05 PM PST 24
Peak memory 224580 kb
Host smart-b2025519-21cf-4d37-b294-aac8184bcd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707428149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.707428149
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3501750937
Short name T215
Test name
Test status
Simulation time 9009623423 ps
CPU time 13.16 seconds
Started Feb 04 02:34:53 PM PST 24
Finished Feb 04 02:35:08 PM PST 24
Peak memory 234400 kb
Host smart-1b82927a-8a8c-4b54-aeba-07b3f58d75d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501750937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3501750937
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1752663526
Short name T799
Test name
Test status
Simulation time 39269040 ps
CPU time 1.14 seconds
Started Feb 04 02:34:52 PM PST 24
Finished Feb 04 02:34:56 PM PST 24
Peak memory 216672 kb
Host smart-2c1a968a-05f0-4e37-b195-592ffcfc6a77
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752663526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1752663526
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2713684570
Short name T749
Test name
Test status
Simulation time 484566963 ps
CPU time 3.34 seconds
Started Feb 04 02:35:03 PM PST 24
Finished Feb 04 02:35:10 PM PST 24
Peak memory 234892 kb
Host smart-cd95cbd6-14c2-4eff-8ed5-5a49f7d9bb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713684570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2713684570
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.314049238
Short name T1112
Test name
Test status
Simulation time 7503544863 ps
CPU time 6.32 seconds
Started Feb 04 02:35:07 PM PST 24
Finished Feb 04 02:35:19 PM PST 24
Peak memory 233620 kb
Host smart-e6fee0b4-aefe-4ce7-8ca1-09838fed4f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314049238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.314049238
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.3108363587
Short name T469
Test name
Test status
Simulation time 48784766 ps
CPU time 0.71 seconds
Started Feb 04 02:34:55 PM PST 24
Finished Feb 04 02:34:58 PM PST 24
Peak memory 216280 kb
Host smart-3af21587-e21c-4218-b4c9-4b0842dd9fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108363587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.3108363587
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3717510570
Short name T457
Test name
Test status
Simulation time 4773835322 ps
CPU time 5.3 seconds
Started Feb 04 02:35:02 PM PST 24
Finished Feb 04 02:35:11 PM PST 24
Peak memory 222820 kb
Host smart-8cd11abd-9fd2-4c4d-8906-cfb89f1dbd34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3717510570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3717510570
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3491920745
Short name T797
Test name
Test status
Simulation time 51859736 ps
CPU time 1.09 seconds
Started Feb 04 02:35:08 PM PST 24
Finished Feb 04 02:35:15 PM PST 24
Peak memory 206788 kb
Host smart-9ca41873-5e6d-4f7d-b40c-6f31851c73e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491920745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3491920745
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3050332546
Short name T757
Test name
Test status
Simulation time 13120889481 ps
CPU time 29.04 seconds
Started Feb 04 02:35:07 PM PST 24
Finished Feb 04 02:35:42 PM PST 24
Peak memory 216476 kb
Host smart-a33cdec6-b886-4a94-83da-741bbca5c440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050332546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3050332546
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2474338833
Short name T683
Test name
Test status
Simulation time 5120022391 ps
CPU time 16.43 seconds
Started Feb 04 02:35:00 PM PST 24
Finished Feb 04 02:35:17 PM PST 24
Peak memory 216388 kb
Host smart-1e5ba479-754f-4d72-b427-ef7b61e38640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474338833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2474338833
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2972551131
Short name T931
Test name
Test status
Simulation time 292914495 ps
CPU time 2.92 seconds
Started Feb 04 02:35:05 PM PST 24
Finished Feb 04 02:35:14 PM PST 24
Peak memory 216436 kb
Host smart-547c0f54-61bb-43fa-87b5-10f39b88af79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972551131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2972551131
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2128829099
Short name T63
Test name
Test status
Simulation time 53252533 ps
CPU time 0.93 seconds
Started Feb 04 02:35:07 PM PST 24
Finished Feb 04 02:35:13 PM PST 24
Peak memory 206472 kb
Host smart-dd09c947-8579-4b20-aa07-5f029970bcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128829099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2128829099
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3336132947
Short name T1094
Test name
Test status
Simulation time 14207067581 ps
CPU time 8.41 seconds
Started Feb 04 02:34:57 PM PST 24
Finished Feb 04 02:35:07 PM PST 24
Peak memory 217256 kb
Host smart-1dd97cb8-8ac1-4885-a536-1add37fc6b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336132947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3336132947
Directory /workspace/9.spi_device_upload/latest
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