Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8102568	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6721466

1

T1

136

T2

4

T3

893

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10463542	1			T1	504		T2	1		T3	27
values[0x0]	2178588	1			T1	49		T2	10		T3	434
values[0x1]	2181904	1			T1	23		T2	9		T3	455

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5784339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9039695

1

T1

278

T2

8

T3

898

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55115	1			T1	1		T5	5		T6	304
valid_sources[0x01]	58841	1			T5	5		T6	328		T7	13
valid_sources[0x02]	62275	1			T5	2		T6	347		T7	92
valid_sources[0x03]	57036	1			T1	1		T5	1		T6	296
valid_sources[0x04]	57987	1			T1	6		T5	2		T6	334
valid_sources[0x05]	62649	1			T2	1		T5	3		T6	293
valid_sources[0x06]	55652	1			T1	6		T5	2		T6	314
valid_sources[0x07]	59836	1			T1	4		T5	2		T6	330
valid_sources[0x08]	61301	1			T1	2		T5	2		T6	305
valid_sources[0x09]	60629	1			T5	7		T6	345		T7	819
valid_sources[0x0a]	55292	1			T1	3		T6	332		T7	79
valid_sources[0x0b]	52859	1			T1	2		T5	3		T6	355
valid_sources[0x0c]	57814	1			T5	2		T6	325		T7	230
valid_sources[0x0d]	56717	1			T5	5		T6	318		T7	409
valid_sources[0x0e]	56961	1			T5	2		T6	322		T7	651
valid_sources[0x0f]	58337	1			T1	1		T5	4		T6	331
valid_sources[0x10]	63764	1			T1	2		T5	7		T6	283
valid_sources[0x11]	56917	1			T6	322		T7	84		T10	113
valid_sources[0x12]	63487	1			T5	3		T6	320		T7	207
valid_sources[0x13]	59898	1			T1	1		T5	4		T6	352
valid_sources[0x14]	55273	1			T1	4		T5	3		T6	336
valid_sources[0x15]	60988	1			T5	2		T6	292		T7	109
valid_sources[0x16]	59277	1			T1	1		T5	6		T6	340
valid_sources[0x17]	60779	1			T5	4		T6	314		T7	107
valid_sources[0x18]	55697	1			T1	1		T5	1		T6	322
valid_sources[0x19]	57990	1			T5	6		T6	320		T7	128
valid_sources[0x1a]	57518	1			T1	4		T5	3		T6	360
valid_sources[0x1b]	55004	1			T1	3		T5	4		T6	329
valid_sources[0x1c]	57169	1			T5	2		T6	322		T7	260
valid_sources[0x1d]	55771	1			T1	2		T5	2		T6	298
valid_sources[0x1e]	66871	1			T1	4		T5	4		T6	332
valid_sources[0x1f]	57129	1			T1	2		T6	341		T7	268
valid_sources[0x20]	56176	1			T1	1		T5	1		T6	284
valid_sources[0x21]	56268	1			T5	4		T6	353		T7	460
valid_sources[0x22]	56804	1			T1	1		T5	1		T6	304
valid_sources[0x23]	57421	1			T5	8		T6	357		T7	823
valid_sources[0x24]	60469	1			T5	4		T6	326		T7	591
valid_sources[0x25]	57944	1			T1	4		T5	1		T6	287
valid_sources[0x26]	60337	1			T1	2		T5	8		T6	336
valid_sources[0x27]	56418	1			T1	2		T5	4		T6	305
valid_sources[0x28]	56367	1			T1	4		T5	4		T6	343
valid_sources[0x29]	60777	1			T5	4		T6	329		T7	171
valid_sources[0x2a]	55914	1			T5	2		T6	333		T7	230
valid_sources[0x2b]	55432	1			T1	7		T5	5		T6	318
valid_sources[0x2c]	60355	1			T5	6		T6	323		T7	1199
valid_sources[0x2d]	78049	1			T5	5		T6	368		T7	47
valid_sources[0x2e]	59068	1			T1	3		T5	4		T6	314
valid_sources[0x2f]	68131	1			T1	3		T5	3		T6	326
valid_sources[0x30]	55457	1			T1	8		T5	2		T6	305
valid_sources[0x31]	55491	1			T5	6		T6	319		T7	132
valid_sources[0x32]	54574	1			T5	2		T6	347		T7	64
valid_sources[0x33]	59270	1			T5	1		T6	332		T7	239
valid_sources[0x34]	54830	1			T1	7		T2	1		T5	4
valid_sources[0x35]	58817	1			T5	1		T6	334		T7	255
valid_sources[0x36]	57187	1			T1	3		T5	7		T6	299
valid_sources[0x37]	59771	1			T1	4		T5	2		T6	323
valid_sources[0x38]	54871	1			T1	2		T5	4		T6	336
valid_sources[0x39]	62996	1			T1	5		T5	7		T6	312
valid_sources[0x3a]	57970	1			T1	5		T5	4		T6	327
valid_sources[0x3b]	55437	1			T1	8		T5	4		T6	311
valid_sources[0x3c]	57602	1			T1	5		T6	314		T7	431
valid_sources[0x3d]	59908	1			T5	4		T6	289		T7	213
valid_sources[0x3e]	59070	1			T5	3		T6	331		T7	51
valid_sources[0x3f]	62256	1			T5	5		T6	287		T7	87
valid_sources[0x40]	57037	1			T1	1		T5	4		T6	273
valid_sources[0x41]	55297	1			T1	3		T5	3		T6	319
valid_sources[0x42]	55173	1			T1	3		T5	5		T6	362
valid_sources[0x43]	57625	1			T1	3		T5	3		T6	328
valid_sources[0x44]	57232	1			T2	1		T5	4		T6	352
valid_sources[0x45]	56286	1			T5	2		T6	300		T7	122
valid_sources[0x46]	64051	1			T1	1		T5	3		T6	300
valid_sources[0x47]	56114	1			T1	3		T5	2		T6	325
valid_sources[0x48]	56308	1			T1	3		T5	3		T6	351
valid_sources[0x49]	58446	1			T1	2		T5	3		T6	307
valid_sources[0x4a]	54454	1			T6	340		T7	159		T10	127
valid_sources[0x4b]	53872	1			T1	11		T5	9		T6	342
valid_sources[0x4c]	56136	1			T5	1		T6	325		T7	147
valid_sources[0x4d]	57172	1			T1	2		T5	2		T6	347
valid_sources[0x4e]	57198	1			T1	2		T5	3		T6	308
valid_sources[0x4f]	62851	1			T1	2		T2	1		T5	3
valid_sources[0x50]	58777	1			T5	3		T6	341		T7	325
valid_sources[0x51]	56587	1			T1	17		T5	1		T6	318
valid_sources[0x52]	54561	1			T1	3		T6	320		T7	31
valid_sources[0x53]	54418	1			T1	9		T5	6		T6	333
valid_sources[0x54]	55433	1			T1	8		T5	2		T6	336
valid_sources[0x55]	63154	1			T5	2		T6	366		T7	102
valid_sources[0x56]	55954	1			T1	1		T5	3		T6	332
valid_sources[0x57]	59584	1			T1	1		T5	3		T6	317
valid_sources[0x58]	55157	1			T1	6		T5	6		T6	310
valid_sources[0x59]	61587	1			T5	2		T6	315		T7	208
valid_sources[0x5a]	55776	1			T1	3		T5	4		T6	320
valid_sources[0x5b]	59620	1			T1	5		T5	3		T6	337
valid_sources[0x5c]	61475	1			T1	2		T5	5		T6	341
valid_sources[0x5d]	56102	1			T5	6		T6	353		T7	159
valid_sources[0x5e]	56952	1			T1	7		T2	1		T5	4
valid_sources[0x5f]	59012	1			T1	5		T5	5		T6	327
valid_sources[0x60]	54562	1			T1	1		T5	6		T6	317
valid_sources[0x61]	58088	1			T1	1		T5	5		T6	320
valid_sources[0x62]	63794	1			T5	1		T6	309		T7	632
valid_sources[0x63]	56687	1			T1	1		T5	5		T6	295
valid_sources[0x64]	54743	1			T1	2		T5	2		T6	316
valid_sources[0x65]	54658	1			T1	3		T5	4		T6	345
valid_sources[0x66]	59179	1			T1	7		T5	1		T6	309
valid_sources[0x67]	55259	1			T5	3		T6	385		T7	59
valid_sources[0x68]	59289	1			T5	4		T6	345		T7	68
valid_sources[0x69]	59252	1			T5	7		T6	307		T7	134
valid_sources[0x6a]	54426	1			T1	6		T5	7		T6	354
valid_sources[0x6b]	59979	1			T1	2		T5	2		T6	333
valid_sources[0x6c]	68845	1			T1	6		T5	3		T6	312
valid_sources[0x6d]	57244	1			T1	4		T5	8		T6	310
valid_sources[0x6e]	59161	1			T1	2		T2	2		T5	1
valid_sources[0x6f]	59808	1			T5	6		T6	326		T7	544
valid_sources[0x70]	56210	1			T1	4		T5	1		T6	311
valid_sources[0x71]	57290	1			T1	2		T5	5		T6	327
valid_sources[0x72]	62449	1			T1	2		T5	2		T6	337
valid_sources[0x73]	66431	1			T1	1		T5	3		T6	304
valid_sources[0x74]	61156	1			T5	9		T6	348		T7	66
valid_sources[0x75]	53904	1			T1	1		T5	6		T6	310
valid_sources[0x76]	63212	1			T1	2		T5	3		T6	338
valid_sources[0x77]	55901	1			T1	1		T5	1		T6	292
valid_sources[0x78]	61903	1			T5	3		T6	342		T7	49
valid_sources[0x79]	57188	1			T5	4		T6	309		T7	88
valid_sources[0x7a]	59439	1			T1	2		T5	1		T6	319
valid_sources[0x7b]	62282	1			T1	3		T5	5		T6	326
valid_sources[0x7c]	58764	1			T1	3		T5	10		T6	331
valid_sources[0x7d]	65064	1			T1	10		T5	2		T6	319
valid_sources[0x7e]	57106	1			T1	9		T5	2		T6	308
valid_sources[0x7f]	58017	1			T1	1		T5	1		T6	363
valid_sources[0x80]	61450	1			T5	1		T6	355		T7	464

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2715872

1

T1

71

T3

13

T5

1

values[0x0]

all_enables

biggest_size

2012465

1

T1

42

T2

4

T3

431

values[0x1]

all_enables

biggest_size

1993129

1

T1

23

T3

449

T5

446