Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

8123690

1

T1

440

T2

16

T3

23

full_word

6720568

1

T1

136

T2

4

T3

893

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	14843838	1			T1	576		T2	20		T3	916
auto[TlIntgErrCmd]	133	1			T44	4		T75	4		T76	7
auto[TlIntgErrData]	129	1			T44	2		T75	5		T76	5
auto[TlIntgErrBoth]	158	1			T44	4		T75	11		T76	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10465372

1

T1

504

T2

1

T3

27

auto[1]

4378886

1

T1

72

T2

19

T3

889

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7749193	1			T1	433		T2	1		T3	14
auto[TlIntgErrNone]	partial	auto[1]	374110	1			T1	7		T2	15		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	2715985	1			T1	71		T3	13		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	4004550	1			T1	65		T2	4		T3	880
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T44	1		T75	3		T76	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T44	3		T75	1		T76	4
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T76	1		T237	1		T236	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T91	1		T138	1		T238	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T44	1		T75	3		T76	3
auto[TlIntgErrData]	partial	auto[1]	61	1			T44	1		T75	2		T76	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T90	1		T91	1		T237	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T91	1		T239	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T44	1		T75	1		T76	4
auto[TlIntgErrBoth]	partial	auto[1]	85	1			T44	3		T75	9		T76	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T76	1		T88	1		T91	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T75	1		T88	2		T91	1