Unified Coverage Report :: Module Instance :: tb.dut.u_tlul2sram_ingress.u_sramreqfifo

Module Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.81	100.00	69.23			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.89	95.00	69.23			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.66	94.03	73.28			83.33	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.03	100.00	76.47			91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.12	95.00	76.47			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.66	94.03	73.28			83.33	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.85	100.00	65.38			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.96	100.00	65.38			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Total	Covered	Percent
Conditions	26	18	69.23
Logical	26	18	69.23
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T11

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T11

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T11

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T11

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T11

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T11
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T11

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	574941707	57034	0	0
DepthKnown_A	574941707	574858285	0	0
RvalidKnown_A	574941707	574858285	0	0
WreadyKnown_A	574941707	574858285	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	574941707	57034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	57034	0	0
T6	257954	64	0	0
T7	283083	1102	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	352	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	960	0	0
T23	0	481	0	0
T27	0	64	0	0
T28	0	130	0	0
T29	0	97	0	0
T30	0	288	0	0
T31	0	1256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	57034	0	0
T6	257954	64	0	0
T7	283083	1102	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	352	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	960	0	0
T23	0	481	0	0
T27	0	64	0	0
T28	0	130	0	0
T29	0	97	0	0
T30	0	288	0	0
T31	0	1256	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
172	1	1
173	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Total	Covered	Percent
Conditions	34	26	76.47
Logical	34	26	76.47
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T23,T27

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T11

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T11,T22,T23
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T11

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T23,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T11

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T23,T27

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T11

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T11

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T11,T23,T27
1	0	Covered	T6,T7,T11
1	1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
TERNARY	88	3	2	66.67
TERNARY	172	2	2	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T23,T27
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T11

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	574941707	124479	0	0
DepthKnown_A	574941707	574858285	0	0
RvalidKnown_A	574941707	574858285	0	0
WreadyKnown_A	574941707	574858285	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	574941707	124479	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	124479	0	0
T6	257954	64	0	0
T7	283083	1102	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	586	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	960	0	0
T23	0	2146	0	0
T27	0	294	0	0
T28	0	130	0	0
T29	0	97	0	0
T30	0	288	0	0
T31	0	1256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	124479	0	0
T6	257954	64	0	0
T7	283083	1102	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	586	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	960	0	0
T23	0	2146	0	0
T27	0	294	0	0
T28	0	130	0	0
T29	0	97	0	0
T30	0	288	0	0
T31	0	1256	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	26	17	65.38
Logical	26	17	65.38
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T11

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T11

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T11

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T6,T7,T11

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T11

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	574941707	61610	0	0
DepthKnown_A	574941707	574858285	0	0
RvalidKnown_A	574941707	574858285	0	0
WreadyKnown_A	574941707	574858285	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	574941707	61610	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	61610	0	0
T6	257954	67	0	0
T7	283083	1174	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	387	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	1004	0	0
T23	0	502	0	0
T28	0	138	0	0
T29	0	109	0	0
T30	0	305	0	0
T31	0	1345	0	0
T34	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	61610	0	0
T6	257954	67	0	0
T7	283083	1174	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	387	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	1004	0	0
T23	0	502	0	0
T28	0	138	0	0
T29	0	109	0	0
T30	0	305	0	0
T31	0	1345	0	0
T34	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577415372	17121860	0	0
DepthKnown_A	577415372	577286215	0	0
RvalidKnown_A	577415372	577286215	0	0
WreadyKnown_A	577415372	577286215	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	17121860	0	0
T1	11786	576	0	0
T2	1175	20	0	0
T3	99011	916	0	0
T4	1201	1	0	0
T5	724174	895	0	0
T6	257954	90926	0	0
T7	283083	80071	0	0
T8	1029	69	0	0
T9	986066	1349	0	0
T10	366182	29817	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577415372	30659657	0	0
DepthKnown_A	577415372	577286215	0	0
RvalidKnown_A	577415372	577286215	0	0
WreadyKnown_A	577415372	577286215	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	30659657	0	0
T1	11786	1736	0	0
T2	1175	80	0	0
T3	99011	916	0	0
T4	1201	1	0	0
T5	724174	895	0	0
T6	257954	303147	0	0
T7	283083	70330	0	0
T8	1029	69	0	0
T9	986066	1349	0	0
T10	366182	29589	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577415372	3434878	0	0
DepthKnown_A	577415372	577286215	0	0
RvalidKnown_A	577415372	577286215	0	0
WreadyKnown_A	577415372	577286215	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	3434878	0	0
T3	99011	832	0	0
T4	1201	0	0	0
T5	724174	832	0	0
T6	257954	4996	0	0
T7	283083	36597	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T12	55763	832	0	0
T13	12915	832	0	0
T14	0	832	0	0
T15	0	1663	0	0
T16	0	1664	0	0
T17	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577415372	3559313	0	0
DepthKnown_A	577415372	577286215	0	0
RvalidKnown_A	577415372	577286215	0	0
WreadyKnown_A	577415372	577286215	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	3559313	0	0
T3	99011	832	0	0
T4	1201	0	0	0
T5	724174	832	0	0
T6	257954	6379	0	0
T7	283083	27456	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T12	55763	832	0	0
T13	12915	2546	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	833	0	0
T17	0	3744	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0