Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577415372	63362	0	0
DepthKnown_A	577415372	577286215	0	0
RvalidKnown_A	577415372	577286215	0	0
WreadyKnown_A	577415372	577286215	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	63362	0	0
T6	257954	64	0	0
T7	283083	1102	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	352	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	960	0	0
T23	0	481	0	0
T27	0	64	0	0
T28	0	130	0	0
T29	0	97	0	0
T30	0	288	0	0
T31	0	1256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577415372	136981	0	0
DepthKnown_A	577415372	577286215	0	0
RvalidKnown_A	577415372	577286215	0	0
WreadyKnown_A	577415372	577286215	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	136981	0	0
T6	257954	64	0	0
T7	283083	1102	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	586	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	960	0	0
T23	0	2146	0	0
T27	0	294	0	0
T28	0	130	0	0
T29	0	97	0	0
T30	0	288	0	0
T31	0	1256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577415372	13271741	0	0
DepthKnown_A	577415372	577286215	0	0
RvalidKnown_A	577415372	577286215	0	0
WreadyKnown_A	577415372	577286215	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	13271741	0	0
T1	11786	576	0	0
T2	1175	20	0	0
T3	99011	84	0	0
T4	1201	1	0	0
T5	724174	63	0	0
T6	257954	84501	0	0
T7	283083	41932	0	0
T8	1029	69	0	0
T9	986066	1349	0	0
T10	366182	29817	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577415372	26963363	0	0
DepthKnown_A	577415372	577286215	0	0
RvalidKnown_A	577415372	577286215	0	0
WreadyKnown_A	577415372	577286215	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	26963363	0	0
T1	11786	1736	0	0
T2	1175	80	0	0
T3	99011	84	0	0
T4	1201	1	0	0
T5	724174	63	0	0
T6	257954	296704	0	0
T7	283083	41772	0	0
T8	1029	69	0	0
T9	986066	1349	0	0
T10	366182	29589	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577415372	577286215	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0