Unified Coverage Report :: Module :: spid_readbuffer

Module : spid_readbuffer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	97.30	97.14			90.48	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_readcmd.u_readbuffer	96.23	97.30	97.14			90.48	100.00

---

Module Instance : tb.dut.u_readcmd.u_readbuffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	97.30	97.14			90.48	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	97.30	97.14			90.48	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.19	96.32	100.00		80.00	84.62	100.00	u_readcmd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_readbuffer

	Line No.	Total	Covered	Percent
TOTAL		37	36	97.30
ALWAYS	103	4	4	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
ALWAYS	118	4	4	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	135	6	6	100.00
ALWAYS	147	6	5	83.33
ALWAYS	166	5	5	100.00
ALWAYS	175	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
103	1	1
104	1	1
105	1	1
106	1	1
			MISSING_ELSE
111	1	1
112	1	1
118	2	2
119	2	2
			MISSING_ELSE
122	1	1
131	1	1
135	1	1
136	1	1
137	1	1
140	1	1
141	1	1
142	1	1
			MISSING_ELSE
147	1	1
149	1	1
150	1	1
151	1	1
152	1	1
157	0	1
			MISSING_ELSE
			MISSING_ELSE
166	2	2
167	1	1
168	1	1
170	1	1
175	1	1
177	1	1
179	1	1
181	1	1
183	1	1
185	1	1
			MISSING_ELSE
191	1	1
193	1	1

---

Cond Coverage for Module : spid_readbuffer

	Total	Covered	Percent
Conditions	35	34	97.14
Logical	35	34	97.14
Non-Logical	0	0
Event	0	0

 LINE       105
 EXPRESSION (active && flip)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T7,T22,T23
1	0	Covered	T3,T12,T16
1	1	Covered	T3,T12,T16

 LINE       112
 EXPRESSION (current_buffer_idx == next_buffer_addr)
            --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T12

 LINE       122
 EXPRESSION (active && flip && ((!flip_q)))
             ---1--    --2-    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T22,T23
1	0	1	Covered	T3,T12,T16
1	1	0	Not Covered
1	1	1	Covered	T3,T12,T16

 LINE       131
 EXPRESSION ((current_address_i[(spi_device_pkg::SramBufferAw - 1):0] >= threshold_i) && ((|threshold_i)))
             ------------------------------------1-----------------------------------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       137
 EXPRESSION (active && watermark_cross)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T12,T16
1	1	Covered	T3,T12,T16

 LINE       141
 EXPRESSION (active && flip)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T7,T22,T23
1	0	Covered	T3,T12,T16
1	1	Covered	T3,T12,T16

 LINE       149
 EXPRESSION (active && watermark_cross)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T12,T16
1	1	Covered	T3,T12,T16

 LINE       167
 EXPRESSION (spi_mode_i != FlashMode)
            ------------1------------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T5,T7,T13

 LINE       181
 EXPRESSION (start_i && (spi_mode_i == FlashMode) && ((!sfdp_hit_i)) && ( ! (mailbox_en_i && mailbox_hit_i) ))
             ---1---    ------------2------------    -------3-------    ------------------4------------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T5,T7,T14
1	1	0	1	Covered	T6,T7,T11
1	1	1	0	Covered	T6,T7,T11
1	1	1	1	Covered	T3,T12,T16

 LINE       181
 SUB-EXPRESSION (spi_mode_i == FlashMode)
                ------------1------------

-1-	Status	Tests
0	Covered	T5,T7,T13
1	Covered	T1,T2,T3

 LINE       181
 SUB-EXPRESSION ( ! (mailbox_en_i && mailbox_hit_i) )
                    ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T14

 LINE       181
 SUB-EXPRESSION (mailbox_en_i && mailbox_hit_i)
                 ------1-----    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T7,T14

---

Branch Coverage for Module : spid_readbuffer

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
IF	103	3	3	100.00
IF	118	3	3	100.00
IF	135	4	4	100.00
IF	149	4	3	75.00
IF	166	3	3	100.00
CASE	179	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	103	if ((!sys_rst_ni))
-2-:	105	if ((active && flip))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T12,T16
0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	118	if ((!sys_rst_ni))
-2-:	119	if (active)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T12,T16
0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	135	if ((!sys_rst_ni))
-2-:	137	if ((active && watermark_cross))
-3-:	141	if ((active && flip))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T12,T16
0	0	1	Covered	T3,T12,T16
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	149	if ((active && watermark_cross))
-2-:	150	if ((!watermark_crossed))
-3-:	152	if (flip)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T3,T12,T16
1	0	1	Not Covered
1	0	0	Covered	T3,T12,T16
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	if ((!rst_ni))
-2-:	167	if ((spi_mode_i != FlashMode))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T7,T13
0	0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	179	case (st_q)
-2-:	181	if ((((start_i && (spi_mode_i == FlashMode)) && (!sfdp_hit_i)) && (!(mailbox_en_i && mailbox_hit_i))))

Branches:

-1-	-2-	Status	Tests
StIdle	1	Covered	T3,T12,T16
StIdle	0	Covered	T1,T2,T3
StActive	-	Covered	T3,T12,T16
default	-	Not Covered

---

Assert Coverage for Module : spid_readbuffer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StartWithAddressUpdate_A	183604572	9465	0	0

StartWithAddressUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183604572	9465	0	0
T3	19251	8	0	0
T5	180463	2	0	0
T6	317953	14	0	0
T7	184975	125	0	0
T9	141593	0	0	0
T10	158530	0	0	0
T11	0	23	0	0
T12	15544	8	0	0
T13	709	0	0	0
T14	257572	6	0	0
T15	29362	6	0	0
T16	0	8	0	0
T32	0	2	0	0