| T361 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1294272409 |
|
|
Feb 07 12:35:27 PM PST 24 |
Feb 07 12:35:39 PM PST 24 |
19959499 ps |
| T233 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3909939268 |
|
|
Feb 07 12:34:44 PM PST 24 |
Feb 07 12:34:48 PM PST 24 |
109335059 ps |
| T362 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1507207723 |
|
|
Feb 07 12:35:24 PM PST 24 |
Feb 07 12:35:28 PM PST 24 |
54786942 ps |
| T363 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1653496864 |
|
|
Feb 07 12:35:10 PM PST 24 |
Feb 07 12:35:20 PM PST 24 |
907409865 ps |
| T364 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3880247348 |
|
|
Feb 07 12:35:11 PM PST 24 |
Feb 07 12:35:23 PM PST 24 |
105032273 ps |
| T365 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.883419509 |
|
|
Feb 07 12:35:07 PM PST 24 |
Feb 07 12:35:15 PM PST 24 |
720007160 ps |
| T62 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3444845251 |
|
|
Feb 07 12:35:02 PM PST 24 |
Feb 07 12:35:08 PM PST 24 |
168024513 ps |
| T366 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.605713998 |
|
|
Feb 07 12:35:27 PM PST 24 |
Feb 07 12:35:38 PM PST 24 |
13013424 ps |
| T367 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.515769836 |
|
|
Feb 07 12:35:07 PM PST 24 |
Feb 07 12:35:12 PM PST 24 |
20485811 ps |
| T368 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.1165297871 |
|
|
Feb 07 12:35:23 PM PST 24 |
Feb 07 12:35:26 PM PST 24 |
51577434 ps |
| T369 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3263807985 |
|
|
Feb 07 12:35:08 PM PST 24 |
Feb 07 12:35:16 PM PST 24 |
46906384 ps |
| T370 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2586792833 |
|
|
Feb 07 12:34:57 PM PST 24 |
Feb 07 12:35:26 PM PST 24 |
1284835608 ps |
| T371 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1710217080 |
|
|
Feb 07 12:35:07 PM PST 24 |
Feb 07 12:35:16 PM PST 24 |
194406588 ps |
| T372 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2437866640 |
|
|
Feb 07 12:35:02 PM PST 24 |
Feb 07 12:35:16 PM PST 24 |
407720887 ps |
| T373 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.253646952 |
|
|
Feb 07 12:35:32 PM PST 24 |
Feb 07 12:35:43 PM PST 24 |
124782609 ps |
| T374 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.842214038 |
|
|
Feb 07 12:35:27 PM PST 24 |
Feb 07 12:35:37 PM PST 24 |
34416460 ps |
| T375 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1324195503 |
|
|
Feb 07 12:35:08 PM PST 24 |
Feb 07 12:35:14 PM PST 24 |
571211102 ps |
| T85 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3693256370 |
|
|
Feb 07 12:35:08 PM PST 24 |
Feb 07 12:35:33 PM PST 24 |
3647861375 ps |
| T376 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.3245873043 |
|
|
Feb 07 12:35:14 PM PST 24 |
Feb 07 12:35:19 PM PST 24 |
56762910 ps |
| T377 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3120546253 |
|
|
Feb 07 12:35:01 PM PST 24 |
Feb 07 12:35:07 PM PST 24 |
37921761 ps |
| T378 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1352326646 |
|
|
Feb 07 12:35:00 PM PST 24 |
Feb 07 12:35:21 PM PST 24 |
2635619115 ps |
| T379 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3932759727 |
|
|
Feb 07 12:35:23 PM PST 24 |
Feb 07 12:35:26 PM PST 24 |
46670765 ps |
| T380 |
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.4112775109 |
|
|
Feb 07 12:35:24 PM PST 24 |
Feb 07 12:35:28 PM PST 24 |
14746003 ps |
| T381 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3959726950 |
|
|
Feb 07 12:35:14 PM PST 24 |
Feb 07 12:35:21 PM PST 24 |
324239940 ps |
| T382 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.507167949 |
|
|
Feb 07 12:35:10 PM PST 24 |
Feb 07 12:35:18 PM PST 24 |
128013500 ps |
| T383 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1320477647 |
|
|
Feb 07 12:35:14 PM PST 24 |
Feb 07 12:35:20 PM PST 24 |
178677363 ps |
| T384 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1688523739 |
|
|
Feb 07 12:34:59 PM PST 24 |
Feb 07 12:35:05 PM PST 24 |
258391138 ps |
| T385 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3841726812 |
|
|
Feb 07 12:35:06 PM PST 24 |
Feb 07 12:35:13 PM PST 24 |
117331917 ps |
| T386 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.155524327 |
|
|
Feb 07 12:35:47 PM PST 24 |
Feb 07 12:35:51 PM PST 24 |
68039883 ps |
| T387 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2897058501 |
|
|
Feb 07 12:34:57 PM PST 24 |
Feb 07 12:35:00 PM PST 24 |
35854169 ps |
| T388 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.737541570 |
|
|
Feb 07 12:35:22 PM PST 24 |
Feb 07 12:35:26 PM PST 24 |
80653355 ps |
| T389 |
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2505295305 |
|
|
Feb 07 12:35:01 PM PST 24 |
Feb 07 12:35:08 PM PST 24 |
74560620 ps |
| T390 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2070467302 |
|
|
Feb 07 12:35:02 PM PST 24 |
Feb 07 12:35:10 PM PST 24 |
254619415 ps |
| T391 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.876942380 |
|
|
Feb 07 12:35:13 PM PST 24 |
Feb 07 12:35:20 PM PST 24 |
507890348 ps |
| T392 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.3139071827 |
|
|
Feb 07 12:35:25 PM PST 24 |
Feb 07 12:35:28 PM PST 24 |
14479132 ps |
| T393 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1371373173 |
|
|
Feb 07 12:35:07 PM PST 24 |
Feb 07 12:35:13 PM PST 24 |
62752613 ps |
| T394 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.1078652606 |
|
|
Feb 07 12:35:17 PM PST 24 |
Feb 07 12:35:21 PM PST 24 |
11026378 ps |
| T395 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.613709364 |
|
|
Feb 07 12:35:10 PM PST 24 |
Feb 07 12:35:19 PM PST 24 |
44821326 ps |
| T396 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2623261441 |
|
|
Feb 07 12:35:14 PM PST 24 |
Feb 07 12:35:22 PM PST 24 |
388361169 ps |
| T397 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4134474802 |
|
|
Feb 07 12:35:01 PM PST 24 |
Feb 07 12:35:09 PM PST 24 |
112413057 ps |
| T398 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.575448550 |
|
|
Feb 07 12:35:32 PM PST 24 |
Feb 07 12:35:44 PM PST 24 |
65354605 ps |
| T399 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3911904657 |
|
|
Feb 07 12:34:55 PM PST 24 |
Feb 07 12:34:58 PM PST 24 |
215907536 ps |
| T234 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2177072422 |
|
|
Feb 07 12:35:04 PM PST 24 |
Feb 07 12:35:13 PM PST 24 |
744811804 ps |
| T400 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.741525175 |
|
|
Feb 07 12:35:04 PM PST 24 |
Feb 07 12:35:10 PM PST 24 |
133340794 ps |
| T401 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.257817254 |
|
|
Feb 07 12:35:26 PM PST 24 |
Feb 07 12:35:33 PM PST 24 |
49406972 ps |
| T402 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3183973954 |
|
|
Feb 07 12:35:00 PM PST 24 |
Feb 07 12:35:07 PM PST 24 |
43114484 ps |
| T403 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.1073397941 |
|
|
Feb 07 12:35:05 PM PST 24 |
Feb 07 12:35:09 PM PST 24 |
14091555 ps |
| T404 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.573428020 |
|
|
Feb 07 12:35:00 PM PST 24 |
Feb 07 12:35:13 PM PST 24 |
407036589 ps |
| T405 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.2150243445 |
|
|
Feb 07 12:34:49 PM PST 24 |
Feb 07 12:34:51 PM PST 24 |
15331309 ps |
| T406 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.509267132 |
|
|
Feb 07 12:35:01 PM PST 24 |
Feb 07 12:35:14 PM PST 24 |
1145663678 ps |
| T407 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2548001157 |
|
|
Feb 07 12:34:59 PM PST 24 |
Feb 07 12:35:03 PM PST 24 |
17583232 ps |
| T408 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3291119297 |
|
|
Feb 07 12:35:02 PM PST 24 |
Feb 07 12:35:11 PM PST 24 |
1238959035 ps |
| T409 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1355256857 |
|
|
Feb 07 12:35:12 PM PST 24 |
Feb 07 12:35:39 PM PST 24 |
821029204 ps |
| T410 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.3305465197 |
|
|
Feb 07 12:34:57 PM PST 24 |
Feb 07 12:34:59 PM PST 24 |
47877099 ps |
| T411 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1800678263 |
|
|
Feb 07 12:34:59 PM PST 24 |
Feb 07 12:35:04 PM PST 24 |
54226738 ps |
| T412 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.3939345395 |
|
|
Feb 07 12:35:37 PM PST 24 |
Feb 07 12:35:44 PM PST 24 |
88814324 ps |
| T413 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2290236530 |
|
|
Feb 07 12:35:00 PM PST 24 |
Feb 07 12:35:07 PM PST 24 |
315574957 ps |
| T414 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2979738435 |
|
|
Feb 07 12:35:14 PM PST 24 |
Feb 07 12:35:27 PM PST 24 |
378312240 ps |
| T415 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.4008984802 |
|
|
Feb 07 12:35:28 PM PST 24 |
Feb 07 12:35:39 PM PST 24 |
149992521 ps |
| T416 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2902547483 |
|
|
Feb 07 12:35:04 PM PST 24 |
Feb 07 12:35:10 PM PST 24 |
79574434 ps |
| T417 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3619373166 |
|
|
Feb 07 12:34:56 PM PST 24 |
Feb 07 12:34:59 PM PST 24 |
11958424 ps |
| T418 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2374733809 |
|
|
Feb 07 12:35:07 PM PST 24 |
Feb 07 12:35:12 PM PST 24 |
20576154 ps |
| T419 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.2958387357 |
|
|
Feb 07 12:35:14 PM PST 24 |
Feb 07 12:35:19 PM PST 24 |
167096455 ps |
| T420 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3975733398 |
|
|
Feb 07 12:34:59 PM PST 24 |
Feb 07 12:35:04 PM PST 24 |
14942286 ps |
| T265 |
/workspace/coverage/default/49.spi_device_mailbox.2709242803 |
|
|
Feb 07 01:46:05 PM PST 24 |
Feb 07 01:46:52 PM PST 24 |
17358909622 ps |
| T26 |
/workspace/coverage/default/7.spi_device_mem_parity.924767362 |
|
|
Feb 07 01:43:00 PM PST 24 |
Feb 07 01:43:08 PM PST 24 |
25185980 ps |
| T256 |
/workspace/coverage/default/12.spi_device_upload.2572032866 |
|
|
Feb 07 01:43:25 PM PST 24 |
Feb 07 01:43:43 PM PST 24 |
22496620816 ps |
| T421 |
/workspace/coverage/default/11.spi_device_csb_read.3089619175 |
|
|
Feb 07 01:43:14 PM PST 24 |
Feb 07 01:43:15 PM PST 24 |
17641294 ps |
| T422 |
/workspace/coverage/default/10.spi_device_upload.538006862 |
|
|
Feb 07 01:43:06 PM PST 24 |
Feb 07 01:43:16 PM PST 24 |
980000079 ps |
| T423 |
/workspace/coverage/default/9.spi_device_mem_parity.2363664128 |
|
|
Feb 07 01:43:14 PM PST 24 |
Feb 07 01:43:16 PM PST 24 |
26930723 ps |
| T424 |
/workspace/coverage/default/0.spi_device_ram_cfg.1653193709 |
|
|
Feb 07 01:42:15 PM PST 24 |
Feb 07 01:42:16 PM PST 24 |
38560185 ps |
| T425 |
/workspace/coverage/default/39.spi_device_tpm_sts_read.2984177771 |
|
|
Feb 07 01:45:22 PM PST 24 |
Feb 07 01:45:24 PM PST 24 |
103659956 ps |
| T266 |
/workspace/coverage/default/20.spi_device_pass_cmd_filtering.1535782219 |
|
|
Feb 07 01:44:03 PM PST 24 |
Feb 07 01:44:10 PM PST 24 |
1301644380 ps |
| T276 |
/workspace/coverage/default/3.spi_device_flash_and_tpm.225252462 |
|
|
Feb 07 01:42:40 PM PST 24 |
Feb 07 01:45:40 PM PST 24 |
111950926649 ps |
| T426 |
/workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2344568570 |
|
|
Feb 07 01:45:30 PM PST 24 |
Feb 07 01:45:32 PM PST 24 |
500086456 ps |
| T167 |
/workspace/coverage/default/26.spi_device_cfg_cmd.671745498 |
|
|
Feb 07 01:44:34 PM PST 24 |
Feb 07 01:44:39 PM PST 24 |
370697496 ps |
| T427 |
/workspace/coverage/default/18.spi_device_csb_read.2507196423 |
|
|
Feb 07 01:43:49 PM PST 24 |
Feb 07 01:43:51 PM PST 24 |
41177878 ps |
| T199 |
/workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1020085131 |
|
|
Feb 07 01:45:26 PM PST 24 |
Feb 07 01:45:37 PM PST 24 |
2187025489 ps |
| T428 |
/workspace/coverage/default/48.spi_device_csb_read.2340649061 |
|
|
Feb 07 01:45:48 PM PST 24 |
Feb 07 01:45:53 PM PST 24 |
14277422 ps |
| T162 |
/workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2757497939 |
|
|
Feb 07 01:45:13 PM PST 24 |
Feb 07 01:45:35 PM PST 24 |
23562579495 ps |
| T251 |
/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2920087379 |
|
|
Feb 07 01:43:00 PM PST 24 |
Feb 07 01:44:42 PM PST 24 |
6985589902 ps |
| T260 |
/workspace/coverage/default/30.spi_device_upload.1226092957 |
|
|
Feb 07 01:44:33 PM PST 24 |
Feb 07 01:44:58 PM PST 24 |
23084413258 ps |
| T429 |
/workspace/coverage/default/19.spi_device_tpm_sts_read.1176256788 |
|
|
Feb 07 01:44:03 PM PST 24 |
Feb 07 01:44:05 PM PST 24 |
101397609 ps |
| T279 |
/workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2231931307 |
|
|
Feb 07 01:45:47 PM PST 24 |
Feb 07 01:46:49 PM PST 24 |
6738439068 ps |
| T430 |
/workspace/coverage/default/27.spi_device_alert_test.3561553433 |
|
|
Feb 07 01:44:42 PM PST 24 |
Feb 07 01:44:44 PM PST 24 |
14155812 ps |
| T431 |
/workspace/coverage/default/32.spi_device_read_buffer_direct.3008058449 |
|
|
Feb 07 01:44:43 PM PST 24 |
Feb 07 01:44:47 PM PST 24 |
130549140 ps |
| T432 |
/workspace/coverage/default/29.spi_device_cfg_cmd.260092010 |
|
|
Feb 07 01:44:33 PM PST 24 |
Feb 07 01:44:38 PM PST 24 |
577810146 ps |
| T268 |
/workspace/coverage/default/20.spi_device_flash_mode.655757313 |
|
|
Feb 07 01:44:00 PM PST 24 |
Feb 07 01:44:09 PM PST 24 |
2553718745 ps |
| T433 |
/workspace/coverage/default/9.spi_device_csb_read.2551718540 |
|
|
Feb 07 01:43:07 PM PST 24 |
Feb 07 01:43:11 PM PST 24 |
18462292 ps |
| T174 |
/workspace/coverage/default/3.spi_device_intercept.3446593694 |
|
|
Feb 07 01:42:39 PM PST 24 |
Feb 07 01:42:42 PM PST 24 |
372361345 ps |
| T434 |
/workspace/coverage/default/38.spi_device_tpm_rw.3143376401 |
|
|
Feb 07 01:45:26 PM PST 24 |
Feb 07 01:45:30 PM PST 24 |
800202268 ps |
| T264 |
/workspace/coverage/default/21.spi_device_upload.1339870184 |
|
|
Feb 07 01:44:03 PM PST 24 |
Feb 07 01:44:17 PM PST 24 |
44420394534 ps |
| T169 |
/workspace/coverage/default/4.spi_device_flash_and_tpm.3161456741 |
|
|
Feb 07 01:42:53 PM PST 24 |
Feb 07 01:43:13 PM PST 24 |
1196698741 ps |
| T435 |
/workspace/coverage/default/30.spi_device_tpm_read_hw_reg.140103516 |
|
|
Feb 07 01:44:38 PM PST 24 |
Feb 07 01:44:58 PM PST 24 |
14425842901 ps |
| T436 |
/workspace/coverage/default/42.spi_device_pass_cmd_filtering.988898381 |
|
|
Feb 07 01:45:32 PM PST 24 |
Feb 07 01:45:36 PM PST 24 |
105801285 ps |
| T437 |
/workspace/coverage/default/36.spi_device_alert_test.1853079811 |
|
|
Feb 07 01:45:26 PM PST 24 |
Feb 07 01:45:28 PM PST 24 |
11190597 ps |
| T272 |
/workspace/coverage/default/15.spi_device_tpm_all.1926438536 |
|
|
Feb 07 01:43:28 PM PST 24 |
Feb 07 01:46:33 PM PST 24 |
19062680988 ps |
| T269 |
/workspace/coverage/default/19.spi_device_flash_mode.1803152332 |
|
|
Feb 07 01:44:01 PM PST 24 |
Feb 07 01:44:34 PM PST 24 |
18196684648 ps |
| T273 |
/workspace/coverage/default/0.spi_device_tpm_all.3958589467 |
|
|
Feb 07 01:42:17 PM PST 24 |
Feb 07 01:42:57 PM PST 24 |
3067658539 ps |
| T438 |
/workspace/coverage/default/26.spi_device_read_buffer_direct.2589475924 |
|
|
Feb 07 01:44:30 PM PST 24 |
Feb 07 01:44:34 PM PST 24 |
512501114 ps |
| T439 |
/workspace/coverage/default/23.spi_device_tpm_sts_read.846172120 |
|
|
Feb 07 01:44:29 PM PST 24 |
Feb 07 01:44:32 PM PST 24 |
269794342 ps |
| T156 |
/workspace/coverage/default/41.spi_device_flash_all.3001644363 |
|
|
Feb 07 01:45:30 PM PST 24 |
Feb 07 01:46:15 PM PST 24 |
8714715571 ps |
| T440 |
/workspace/coverage/default/38.spi_device_alert_test.328098724 |
|
|
Feb 07 01:45:24 PM PST 24 |
Feb 07 01:45:27 PM PST 24 |
37749236 ps |
| T441 |
/workspace/coverage/default/2.spi_device_mem_parity.1317644475 |
|
|
Feb 07 01:42:24 PM PST 24 |
Feb 07 01:42:26 PM PST 24 |
83506246 ps |
| T175 |
/workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1667418217 |
|
|
Feb 07 01:44:00 PM PST 24 |
Feb 07 01:44:16 PM PST 24 |
29636048642 ps |
| T257 |
/workspace/coverage/default/21.spi_device_flash_and_tpm.345622411 |
|
|
Feb 07 01:44:04 PM PST 24 |
Feb 07 01:45:43 PM PST 24 |
14768567357 ps |
| T442 |
/workspace/coverage/default/11.spi_device_read_buffer_direct.3795768883 |
|
|
Feb 07 01:43:20 PM PST 24 |
Feb 07 01:43:24 PM PST 24 |
281813888 ps |
| T184 |
/workspace/coverage/default/33.spi_device_flash_all.40839983 |
|
|
Feb 07 01:44:50 PM PST 24 |
Feb 07 01:49:49 PM PST 24 |
58960017083 ps |
| T443 |
/workspace/coverage/default/19.spi_device_mem_parity.4187657496 |
|
|
Feb 07 01:44:01 PM PST 24 |
Feb 07 01:44:04 PM PST 24 |
91642257 ps |
| T444 |
/workspace/coverage/default/43.spi_device_flash_mode.4204817695 |
|
|
Feb 07 01:45:30 PM PST 24 |
Feb 07 01:45:44 PM PST 24 |
732679912 ps |
| T445 |
/workspace/coverage/default/47.spi_device_cfg_cmd.3459602738 |
|
|
Feb 07 01:45:49 PM PST 24 |
Feb 07 01:45:56 PM PST 24 |
873754516 ps |
| T446 |
/workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1319183061 |
|
|
Feb 07 01:43:31 PM PST 24 |
Feb 07 01:43:38 PM PST 24 |
4240827679 ps |
| T447 |
/workspace/coverage/default/39.spi_device_stress_all.1294446109 |
|
|
Feb 07 01:45:29 PM PST 24 |
Feb 07 01:45:31 PM PST 24 |
81924930 ps |
| T164 |
/workspace/coverage/default/39.spi_device_flash_and_tpm.906771183 |
|
|
Feb 07 01:45:24 PM PST 24 |
Feb 07 01:47:33 PM PST 24 |
140358002206 ps |
| T448 |
/workspace/coverage/default/12.spi_device_mem_parity.3420888475 |
|
|
Feb 07 01:43:19 PM PST 24 |
Feb 07 01:43:20 PM PST 24 |
125734663 ps |
| T248 |
/workspace/coverage/default/7.spi_device_flash_mode.1234581459 |
|
|
Feb 07 01:43:01 PM PST 24 |
Feb 07 01:43:22 PM PST 24 |
4616512165 ps |
| T168 |
/workspace/coverage/default/35.spi_device_intercept.3550059299 |
|
|
Feb 07 01:44:50 PM PST 24 |
Feb 07 01:44:54 PM PST 24 |
161783107 ps |
| T449 |
/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3131491822 |
|
|
Feb 07 01:43:30 PM PST 24 |
Feb 07 01:43:39 PM PST 24 |
230951111 ps |
| T146 |
/workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3421399256 |
|
|
Feb 07 01:45:43 PM PST 24 |
Feb 07 01:47:46 PM PST 24 |
10474328582 ps |
| T450 |
/workspace/coverage/default/30.spi_device_pass_cmd_filtering.1395062090 |
|
|
Feb 07 01:44:31 PM PST 24 |
Feb 07 01:44:37 PM PST 24 |
3012301513 ps |
| T451 |
/workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1615543962 |
|
|
Feb 07 01:44:19 PM PST 24 |
Feb 07 01:44:25 PM PST 24 |
936250460 ps |
| T259 |
/workspace/coverage/default/7.spi_device_flash_all.512811136 |
|
|
Feb 07 01:43:00 PM PST 24 |
Feb 07 01:43:41 PM PST 24 |
2913790817 ps |
| T452 |
/workspace/coverage/default/41.spi_device_tpm_sts_read.573463857 |
|
|
Feb 07 01:45:33 PM PST 24 |
Feb 07 01:45:35 PM PST 24 |
15060297 ps |
| T255 |
/workspace/coverage/default/33.spi_device_flash_mode.3344522421 |
|
|
Feb 07 01:44:59 PM PST 24 |
Feb 07 01:45:10 PM PST 24 |
2155883103 ps |
| T453 |
/workspace/coverage/default/15.spi_device_flash_all.1219072255 |
|
|
Feb 07 01:43:27 PM PST 24 |
Feb 07 01:46:04 PM PST 24 |
33100844868 ps |
| T262 |
/workspace/coverage/default/46.spi_device_cfg_cmd.4143556312 |
|
|
Feb 07 01:45:43 PM PST 24 |
Feb 07 01:45:50 PM PST 24 |
1337318904 ps |
| T454 |
/workspace/coverage/default/5.spi_device_mem_parity.1302260490 |
|
|
Feb 07 01:43:01 PM PST 24 |
Feb 07 01:43:08 PM PST 24 |
18455263 ps |
| T252 |
/workspace/coverage/default/3.spi_device_stress_all.2615601264 |
|
|
Feb 07 01:42:40 PM PST 24 |
Feb 07 01:50:42 PM PST 24 |
86477676412 ps |
| T455 |
/workspace/coverage/default/48.spi_device_tpm_rw.4272908211 |
|
|
Feb 07 01:45:52 PM PST 24 |
Feb 07 01:46:01 PM PST 24 |
181500341 ps |
| T170 |
/workspace/coverage/default/47.spi_device_flash_and_tpm.482667444 |
|
|
Feb 07 01:45:45 PM PST 24 |
Feb 07 01:53:52 PM PST 24 |
937760872424 ps |
| T456 |
/workspace/coverage/default/12.spi_device_ram_cfg.3339760107 |
|
|
Feb 07 01:43:19 PM PST 24 |
Feb 07 01:43:21 PM PST 24 |
32478335 ps |
| T181 |
/workspace/coverage/default/15.spi_device_flash_and_tpm.2714991883 |
|
|
Feb 07 01:43:33 PM PST 24 |
Feb 07 01:44:52 PM PST 24 |
10573265607 ps |
| T457 |
/workspace/coverage/default/35.spi_device_pass_cmd_filtering.3957019339 |
|
|
Feb 07 01:44:55 PM PST 24 |
Feb 07 01:45:07 PM PST 24 |
5797623792 ps |
| T458 |
/workspace/coverage/default/13.spi_device_tpm_sts_read.1091161552 |
|
|
Feb 07 01:43:18 PM PST 24 |
Feb 07 01:43:19 PM PST 24 |
25180907 ps |
| T459 |
/workspace/coverage/default/16.spi_device_csb_read.1372564644 |
|
|
Feb 07 01:43:45 PM PST 24 |
Feb 07 01:43:47 PM PST 24 |
67572818 ps |
| T277 |
/workspace/coverage/default/30.spi_device_tpm_all.3930911454 |
|
|
Feb 07 01:44:39 PM PST 24 |
Feb 07 01:45:20 PM PST 24 |
18755883269 ps |
| T243 |
/workspace/coverage/default/32.spi_device_intercept.850775194 |
|
|
Feb 07 01:44:42 PM PST 24 |
Feb 07 01:44:47 PM PST 24 |
1311002436 ps |
| T460 |
/workspace/coverage/default/20.spi_device_tpm_rw.404675653 |
|
|
Feb 07 01:44:00 PM PST 24 |
Feb 07 01:44:03 PM PST 24 |
405320555 ps |
| T49 |
/workspace/coverage/default/1.spi_device_sec_cm.755793882 |
|
|
Feb 07 01:42:31 PM PST 24 |
Feb 07 01:42:32 PM PST 24 |
70479760 ps |
| T249 |
/workspace/coverage/default/1.spi_device_flash_and_tpm.3278459130 |
|
|
Feb 07 01:42:24 PM PST 24 |
Feb 07 01:45:43 PM PST 24 |
30909511878 ps |
| T219 |
/workspace/coverage/default/28.spi_device_flash_and_tpm.340346119 |
|
|
Feb 07 01:44:34 PM PST 24 |
Feb 07 01:45:33 PM PST 24 |
19942618575 ps |
| T192 |
/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1943238524 |
|
|
Feb 07 01:44:23 PM PST 24 |
Feb 07 01:44:29 PM PST 24 |
1702787066 ps |
| T461 |
/workspace/coverage/default/7.spi_device_tpm_all.1643660395 |
|
|
Feb 07 01:43:07 PM PST 24 |
Feb 07 01:45:41 PM PST 24 |
50900609593 ps |
| T462 |
/workspace/coverage/default/1.spi_device_upload.3981266113 |
|
|
Feb 07 01:42:22 PM PST 24 |
Feb 07 01:42:29 PM PST 24 |
413776050 ps |
| T241 |
/workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1485942465 |
|
|
Feb 07 01:45:33 PM PST 24 |
Feb 07 01:45:38 PM PST 24 |
1257462561 ps |
| T278 |
/workspace/coverage/default/41.spi_device_tpm_all.2348001056 |
|
|
Feb 07 01:45:29 PM PST 24 |
Feb 07 01:46:51 PM PST 24 |
5850832752 ps |
| T463 |
/workspace/coverage/default/14.spi_device_mem_parity.2234658423 |
|
|
Feb 07 01:43:32 PM PST 24 |
Feb 07 01:43:35 PM PST 24 |
173637381 ps |
| T182 |
/workspace/coverage/default/19.spi_device_mailbox.4004469834 |
|
|
Feb 07 01:44:01 PM PST 24 |
Feb 07 01:44:07 PM PST 24 |
958440416 ps |
| T263 |
/workspace/coverage/default/16.spi_device_pass_cmd_filtering.3646556226 |
|
|
Feb 07 01:43:40 PM PST 24 |
Feb 07 01:44:07 PM PST 24 |
32226200897 ps |
| T464 |
/workspace/coverage/default/46.spi_device_mailbox.3259512872 |
|
|
Feb 07 01:45:34 PM PST 24 |
Feb 07 01:46:16 PM PST 24 |
15678157367 ps |
| T193 |
/workspace/coverage/default/2.spi_device_upload.3383389904 |
|
|
Feb 07 01:42:27 PM PST 24 |
Feb 07 01:42:30 PM PST 24 |
132158649 ps |
| T465 |
/workspace/coverage/default/18.spi_device_ram_cfg.2871725387 |
|
|
Feb 07 01:43:46 PM PST 24 |
Feb 07 01:43:48 PM PST 24 |
16531456 ps |
| T165 |
/workspace/coverage/default/25.spi_device_flash_all.71145992 |
|
|
Feb 07 01:44:20 PM PST 24 |
Feb 07 01:46:10 PM PST 24 |
11474182172 ps |
| T466 |
/workspace/coverage/default/16.spi_device_read_buffer_direct.3105902609 |
|
|
Feb 07 01:43:38 PM PST 24 |
Feb 07 01:43:46 PM PST 24 |
4196096551 ps |
| T467 |
/workspace/coverage/default/8.spi_device_mem_parity.570545673 |
|
|
Feb 07 01:43:02 PM PST 24 |
Feb 07 01:43:08 PM PST 24 |
71348056 ps |
| T177 |
/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1064366417 |
|
|
Feb 07 01:45:40 PM PST 24 |
Feb 07 01:45:49 PM PST 24 |
5405347511 ps |
| T468 |
/workspace/coverage/default/3.spi_device_cfg_cmd.2847285848 |
|
|
Feb 07 01:42:40 PM PST 24 |
Feb 07 01:42:43 PM PST 24 |
118587486 ps |
| T469 |
/workspace/coverage/default/35.spi_device_tpm_sts_read.1508789098 |
|
|
Feb 07 01:44:53 PM PST 24 |
Feb 07 01:44:54 PM PST 24 |
80312419 ps |
| T470 |
/workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1778857983 |
|
|
Feb 07 01:42:59 PM PST 24 |
Feb 07 01:43:22 PM PST 24 |
4625983679 ps |
| T471 |
/workspace/coverage/default/33.spi_device_csb_read.3468164689 |
|
|
Feb 07 01:44:40 PM PST 24 |
Feb 07 01:44:41 PM PST 24 |
16364744 ps |
| T247 |
/workspace/coverage/default/29.spi_device_upload.3984144064 |
|
|
Feb 07 01:44:31 PM PST 24 |
Feb 07 01:44:53 PM PST 24 |
4570989263 ps |
| T472 |
/workspace/coverage/default/23.spi_device_flash_mode.1888373980 |
|
|
Feb 07 01:44:26 PM PST 24 |
Feb 07 01:44:36 PM PST 24 |
968174716 ps |
| T473 |
/workspace/coverage/default/10.spi_device_mem_parity.3949409575 |
|
|
Feb 07 01:43:09 PM PST 24 |
Feb 07 01:43:12 PM PST 24 |
123586087 ps |
| T270 |
/workspace/coverage/default/27.spi_device_flash_mode.1556100771 |
|
|
Feb 07 01:44:34 PM PST 24 |
Feb 07 01:45:04 PM PST 24 |
17343937461 ps |
| T474 |
/workspace/coverage/default/42.spi_device_read_buffer_direct.3689429249 |
|
|
Feb 07 01:45:36 PM PST 24 |
Feb 07 01:45:44 PM PST 24 |
18031090082 ps |
| T229 |
/workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.341147944 |
|
|
Feb 07 01:43:19 PM PST 24 |
Feb 07 01:45:00 PM PST 24 |
18353227523 ps |
| T475 |
/workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.184021374 |
|
|
Feb 07 01:45:46 PM PST 24 |
Feb 07 01:47:33 PM PST 24 |
7805037026 ps |
| T476 |
/workspace/coverage/default/1.spi_device_mailbox.2850916586 |
|
|
Feb 07 01:42:27 PM PST 24 |
Feb 07 01:42:44 PM PST 24 |
16516901436 ps |
| T154 |
/workspace/coverage/default/39.spi_device_flash_all.35050447 |
|
|
Feb 07 01:45:25 PM PST 24 |
Feb 07 01:45:49 PM PST 24 |
1028074831 ps |
| T477 |
/workspace/coverage/default/20.spi_device_tpm_all.3929983030 |
|
|
Feb 07 01:44:03 PM PST 24 |
Feb 07 01:45:10 PM PST 24 |
16257161463 ps |
| T173 |
/workspace/coverage/default/40.spi_device_cfg_cmd.2119494668 |
|
|
Feb 07 01:45:19 PM PST 24 |
Feb 07 01:45:29 PM PST 24 |
5653119220 ps |
| T478 |
/workspace/coverage/default/22.spi_device_tpm_sts_read.4244312710 |
|
|
Feb 07 01:44:08 PM PST 24 |
Feb 07 01:44:10 PM PST 24 |
113657244 ps |
| T479 |
/workspace/coverage/default/11.spi_device_ram_cfg.3576193435 |
|
|
Feb 07 01:43:17 PM PST 24 |
Feb 07 01:43:19 PM PST 24 |
40610718 ps |
| T480 |
/workspace/coverage/default/15.spi_device_read_buffer_direct.3013010841 |
|
|
Feb 07 01:43:33 PM PST 24 |
Feb 07 01:43:39 PM PST 24 |
120427208 ps |
| T246 |
/workspace/coverage/default/48.spi_device_mailbox.15466936 |
|
|
Feb 07 01:45:47 PM PST 24 |
Feb 07 01:46:06 PM PST 24 |
9980342472 ps |
| T481 |
/workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.4141916124 |
|
|
Feb 07 01:45:18 PM PST 24 |
Feb 07 01:46:13 PM PST 24 |
3526675186 ps |
| T185 |
/workspace/coverage/default/47.spi_device_stress_all.560925837 |
|
|
Feb 07 01:45:51 PM PST 24 |
Feb 07 01:48:03 PM PST 24 |
65087620308 ps |
| T482 |
/workspace/coverage/default/6.spi_device_intercept.4032528684 |
|
|
Feb 07 01:42:55 PM PST 24 |
Feb 07 01:43:08 PM PST 24 |
599878351 ps |
| T483 |
/workspace/coverage/default/9.spi_device_cfg_cmd.3835323310 |
|
|
Feb 07 01:43:11 PM PST 24 |
Feb 07 01:43:16 PM PST 24 |
1054996692 ps |
| T484 |
/workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2782091179 |
|
|
Feb 07 01:45:27 PM PST 24 |
Feb 07 01:45:33 PM PST 24 |
801325492 ps |
| T485 |
/workspace/coverage/default/5.spi_device_alert_test.2182330819 |
|
|
Feb 07 01:43:00 PM PST 24 |
Feb 07 01:43:07 PM PST 24 |
41508646 ps |
| T486 |
/workspace/coverage/default/10.spi_device_tpm_rw.4052350652 |
|
|
Feb 07 01:43:12 PM PST 24 |
Feb 07 01:43:15 PM PST 24 |
72222128 ps |
| T487 |
/workspace/coverage/default/16.spi_device_ram_cfg.710038679 |
|
|
Feb 07 01:43:45 PM PST 24 |
Feb 07 01:43:47 PM PST 24 |
29013922 ps |
| T488 |
/workspace/coverage/default/29.spi_device_intercept.3095759559 |
|
|
Feb 07 01:44:41 PM PST 24 |
Feb 07 01:44:47 PM PST 24 |
805447912 ps |
| T489 |
/workspace/coverage/default/14.spi_device_read_buffer_direct.1530598697 |
|
|
Feb 07 01:43:39 PM PST 24 |
Feb 07 01:43:45 PM PST 24 |
1213110699 ps |
| T161 |
/workspace/coverage/default/28.spi_device_pass_addr_payload_swap.289236761 |
|
|
Feb 07 01:44:42 PM PST 24 |
Feb 07 01:44:47 PM PST 24 |
207302084 ps |
| T490 |
/workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2384764694 |
|
|
Feb 07 01:43:18 PM PST 24 |
Feb 07 01:43:26 PM PST 24 |
2187781023 ps |
| T491 |
/workspace/coverage/default/31.spi_device_tpm_read_hw_reg.475469972 |
|
|
Feb 07 01:44:41 PM PST 24 |
Feb 07 01:44:43 PM PST 24 |
84580003 ps |
| T492 |
/workspace/coverage/default/21.spi_device_read_buffer_direct.2082867527 |
|
|
Feb 07 01:44:06 PM PST 24 |
Feb 07 01:44:13 PM PST 24 |
3092137412 ps |
| T493 |
/workspace/coverage/default/26.spi_device_pass_cmd_filtering.2435474333 |
|
|
Feb 07 01:44:34 PM PST 24 |
Feb 07 01:44:48 PM PST 24 |
15273370782 ps |
| T253 |
/workspace/coverage/default/6.spi_device_pass_cmd_filtering.910688007 |
|
|
Feb 07 01:42:50 PM PST 24 |
Feb 07 01:43:16 PM PST 24 |
22812487714 ps |
| T494 |
/workspace/coverage/default/7.spi_device_intercept.1924231753 |
|
|
Feb 07 01:43:05 PM PST 24 |
Feb 07 01:43:13 PM PST 24 |
304287732 ps |
| T495 |
/workspace/coverage/default/12.spi_device_flash_mode.1483421603 |
|
|
Feb 07 01:43:19 PM PST 24 |
Feb 07 01:43:52 PM PST 24 |
51217631943 ps |
| T496 |
/workspace/coverage/default/31.spi_device_upload.2528922514 |
|
|
Feb 07 01:44:38 PM PST 24 |
Feb 07 01:44:45 PM PST 24 |
375431790 ps |
| T214 |
/workspace/coverage/default/11.spi_device_stress_all.2674613475 |
|
|
Feb 07 01:43:25 PM PST 24 |
Feb 07 01:58:30 PM PST 24 |
336626929955 ps |
| T497 |
/workspace/coverage/default/21.spi_device_pass_cmd_filtering.2603849701 |
|
|
Feb 07 01:44:04 PM PST 24 |
Feb 07 01:44:16 PM PST 24 |
854386175 ps |
| T498 |
/workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3995962445 |
|
|
Feb 07 01:45:35 PM PST 24 |
Feb 07 01:45:52 PM PST 24 |
6740993969 ps |
| T499 |
/workspace/coverage/default/47.spi_device_read_buffer_direct.2706412955 |
|
|
Feb 07 01:45:51 PM PST 24 |
Feb 07 01:46:00 PM PST 24 |
1014701496 ps |
| T178 |
/workspace/coverage/default/22.spi_device_flash_all.1851499940 |
|
|
Feb 07 01:44:20 PM PST 24 |
Feb 07 01:46:41 PM PST 24 |
48577907166 ps |
| T500 |
/workspace/coverage/default/30.spi_device_intercept.421857202 |
|
|
Feb 07 01:44:34 PM PST 24 |
Feb 07 01:44:44 PM PST 24 |
2460125426 ps |
| T501 |
/workspace/coverage/default/45.spi_device_csb_read.2170237186 |
|
|
Feb 07 01:45:34 PM PST 24 |
Feb 07 01:45:37 PM PST 24 |
24295743 ps |
| T502 |
/workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.726585939 |
|
|
Feb 07 01:45:25 PM PST 24 |
Feb 07 01:47:01 PM PST 24 |
8138235277 ps |
| T503 |
/workspace/coverage/default/27.spi_device_cfg_cmd.1233884123 |
|
|
Feb 07 01:44:29 PM PST 24 |
Feb 07 01:44:35 PM PST 24 |
338274238 ps |
| T224 |
/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2656082162 |
|
|
Feb 07 01:43:07 PM PST 24 |
Feb 07 01:43:17 PM PST 24 |
883036926 ps |
| T189 |
/workspace/coverage/default/28.spi_device_pass_cmd_filtering.450782206 |
|
|
Feb 07 01:44:30 PM PST 24 |
Feb 07 01:44:44 PM PST 24 |
3515176204 ps |
| T504 |
/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.502202647 |
|
|
Feb 07 01:44:40 PM PST 24 |
Feb 07 01:44:45 PM PST 24 |
2072792435 ps |
| T208 |
/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1825483498 |
|
|
Feb 07 01:43:01 PM PST 24 |
Feb 07 01:48:25 PM PST 24 |
152031400149 ps |
| T505 |
/workspace/coverage/default/19.spi_device_alert_test.3475144837 |
|
|
Feb 07 01:44:02 PM PST 24 |
Feb 07 01:44:04 PM PST 24 |
55069482 ps |
| T506 |
/workspace/coverage/default/27.spi_device_read_buffer_direct.2229724874 |
|
|
Feb 07 01:44:32 PM PST 24 |
Feb 07 01:44:38 PM PST 24 |
1818641484 ps |
| T217 |
/workspace/coverage/default/18.spi_device_stress_all.741625847 |
|
|
Feb 07 01:44:01 PM PST 24 |
Feb 07 01:46:05 PM PST 24 |
135550608292 ps |
| T507 |
/workspace/coverage/default/19.spi_device_csb_read.2140261885 |
|
|
Feb 07 01:44:01 PM PST 24 |
Feb 07 01:44:04 PM PST 24 |
19013275 ps |
| T508 |
/workspace/coverage/default/19.spi_device_ram_cfg.2618548025 |
|
|
Feb 07 01:44:02 PM PST 24 |
Feb 07 01:44:04 PM PST 24 |
25719281 ps |
| T509 |
/workspace/coverage/default/2.spi_device_intercept.3905220853 |
|
|
Feb 07 01:42:24 PM PST 24 |
Feb 07 01:42:29 PM PST 24 |
551350578 ps |
| T510 |
/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1147639348 |
|
|
Feb 07 01:44:34 PM PST 24 |
Feb 07 01:44:37 PM PST 24 |
104166553 ps |
| T511 |
/workspace/coverage/default/23.spi_device_read_buffer_direct.479801664 |
|
|
Feb 07 01:44:24 PM PST 24 |
Feb 07 01:44:30 PM PST 24 |
729649772 ps |
| T512 |
/workspace/coverage/default/25.spi_device_csb_read.3135472093 |
|
|
Feb 07 01:44:20 PM PST 24 |
Feb 07 01:44:22 PM PST 24 |
21787827 ps |
| T513 |
/workspace/coverage/default/11.spi_device_intercept.2367516533 |
|
|
Feb 07 01:43:18 PM PST 24 |
Feb 07 01:43:22 PM PST 24 |
743004106 ps |
| T514 |
/workspace/coverage/default/45.spi_device_stress_all.3760460126 |
|
|
Feb 07 01:45:33 PM PST 24 |
Feb 07 01:45:36 PM PST 24 |
200601904 ps |
| T515 |
/workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3757980925 |
|
|
Feb 07 01:44:01 PM PST 24 |
Feb 07 01:44:13 PM PST 24 |
14190302763 ps |
| T516 |
/workspace/coverage/default/18.spi_device_flash_and_tpm.2295510542 |
|
|
Feb 07 01:43:59 PM PST 24 |
Feb 07 01:46:49 PM PST 24 |
93598730141 ps |
| T517 |
/workspace/coverage/default/31.spi_device_tpm_rw.3772933186 |
|
|
Feb 07 01:44:42 PM PST 24 |
Feb 07 01:44:44 PM PST 24 |
13608693 ps |
| T518 |
/workspace/coverage/default/44.spi_device_flash_mode.2045139018 |
|
|
Feb 07 01:45:34 PM PST 24 |
Feb 07 01:46:00 PM PST 24 |
6244325561 ps |
| T519 |
/workspace/coverage/default/20.spi_device_flash_and_tpm.461464492 |
|
|
Feb 07 01:43:58 PM PST 24 |
Feb 07 01:45:54 PM PST 24 |
19604323314 ps |
| T520 |
/workspace/coverage/default/29.spi_device_flash_mode.663281186 |
|
|
Feb 07 01:44:43 PM PST 24 |
Feb 07 01:45:08 PM PST 24 |
4117468178 ps |
| T521 |
/workspace/coverage/default/22.spi_device_pass_cmd_filtering.1280611340 |
|
|
Feb 07 01:44:09 PM PST 24 |
Feb 07 01:44:28 PM PST 24 |
13866093544 ps |
| T522 |
/workspace/coverage/default/30.spi_device_read_buffer_direct.1521530758 |
|
|
Feb 07 01:44:38 PM PST 24 |
Feb 07 01:44:42 PM PST 24 |
121790591 ps |
| T523 |
/workspace/coverage/default/15.spi_device_csb_read.805046279 |
|
|
Feb 07 01:43:34 PM PST 24 |
Feb 07 01:43:38 PM PST 24 |
21761764 ps |
| T524 |
/workspace/coverage/default/19.spi_device_tpm_rw.3418364005 |
|
|
Feb 07 01:44:03 PM PST 24 |
Feb 07 01:44:06 PM PST 24 |
223738102 ps |
| T525 |
/workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3656312118 |
|
|
Feb 07 01:44:02 PM PST 24 |
Feb 07 01:44:18 PM PST 24 |
7696042233 ps |
| T526 |
/workspace/coverage/default/33.spi_device_read_buffer_direct.2922951168 |
|
|
Feb 07 01:44:52 PM PST 24 |
Feb 07 01:44:56 PM PST 24 |
148941089 ps |
| T527 |
/workspace/coverage/default/17.spi_device_flash_and_tpm.1408274495 |
|
|
Feb 07 01:43:49 PM PST 24 |
Feb 07 01:45:48 PM PST 24 |
14497645043 ps |
| T528 |
/workspace/coverage/default/38.spi_device_mailbox.346604629 |
|
|
Feb 07 01:45:15 PM PST 24 |
Feb 07 01:45:32 PM PST 24 |
3521462338 ps |
| T529 |
/workspace/coverage/default/10.spi_device_tpm_all.4009120491 |
|
|
Feb 07 01:43:12 PM PST 24 |
Feb 07 01:43:45 PM PST 24 |
11256188936 ps |
| T530 |
/workspace/coverage/default/47.spi_device_intercept.1092524799 |
|
|
Feb 07 01:45:55 PM PST 24 |
Feb 07 01:46:00 PM PST 24 |
175444322 ps |
| T531 |
/workspace/coverage/default/37.spi_device_alert_test.87744903 |
|
|
Feb 07 01:45:19 PM PST 24 |
Feb 07 01:45:23 PM PST 24 |
42422470 ps |
| T532 |
/workspace/coverage/default/4.spi_device_cfg_cmd.3151774502 |
|
|
Feb 07 01:42:40 PM PST 24 |
Feb 07 01:42:43 PM PST 24 |
86244456 ps |
| T533 |
/workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2512149330 |
|
|
Feb 07 01:45:30 PM PST 24 |
Feb 07 01:45:41 PM PST 24 |
3361300333 ps |
| T534 |
/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1261939264 |
|
|
Feb 07 01:44:42 PM PST 24 |
Feb 07 01:44:52 PM PST 24 |
659327344 ps |
| T535 |
/workspace/coverage/default/19.spi_device_tpm_all.1364943009 |
|
|
Feb 07 01:43:58 PM PST 24 |
Feb 07 01:44:12 PM PST 24 |
1576877629 ps |
| T536 |
/workspace/coverage/default/39.spi_device_tpm_rw.3379416414 |
|
|
Feb 07 01:45:20 PM PST 24 |
Feb 07 01:45:24 PM PST 24 |
345481598 ps |
| T537 |
/workspace/coverage/default/40.spi_device_pass_cmd_filtering.4139431985 |
|
|
Feb 07 01:45:22 PM PST 24 |
Feb 07 01:45:26 PM PST 24 |
705128966 ps |
| T538 |
/workspace/coverage/default/34.spi_device_alert_test.2195954722 |
|
|
Feb 07 01:44:54 PM PST 24 |
Feb 07 01:44:55 PM PST 24 |
45855296 ps |
| T539 |
/workspace/coverage/default/4.spi_device_tpm_all.4108610285 |
|
|
Feb 07 01:42:37 PM PST 24 |
Feb 07 01:42:56 PM PST 24 |
2083108428 ps |
| T230 |
/workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2643411367 |
|
|
Feb 07 01:43:32 PM PST 24 |
Feb 07 01:45:01 PM PST 24 |
11309789961 ps |
| T540 |
/workspace/coverage/default/30.spi_device_flash_all.1018475127 |
|
|
Feb 07 01:44:39 PM PST 24 |
Feb 07 01:45:34 PM PST 24 |
46384697556 ps |
| T541 |
/workspace/coverage/default/15.spi_device_mem_parity.584925069 |
|
|
Feb 07 01:43:32 PM PST 24 |
Feb 07 01:43:35 PM PST 24 |
17678403 ps |
| T542 |
/workspace/coverage/default/13.spi_device_alert_test.1534530817 |
|
|
Feb 07 01:43:32 PM PST 24 |
Feb 07 01:43:35 PM PST 24 |
14649475 ps |
| T543 |
/workspace/coverage/default/43.spi_device_flash_and_tpm.2702585439 |
|
|
Feb 07 01:45:36 PM PST 24 |
Feb 07 01:46:24 PM PST 24 |
2742629331 ps |
| T544 |
/workspace/coverage/default/32.spi_device_csb_read.1547875398 |
|
|
Feb 07 01:44:46 PM PST 24 |
Feb 07 01:44:48 PM PST 24 |
55727168 ps |
| T179 |
/workspace/coverage/default/24.spi_device_flash_and_tpm.881367779 |
|
|
Feb 07 01:44:27 PM PST 24 |
Feb 07 01:58:15 PM PST 24 |
507122912183 ps |