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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.18 98.50 94.92 98.60 89.36 97.30 96.40 98.14


Total test records in report: 1114
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T202 /workspace/coverage/default/46.spi_device_flash_and_tpm.264644175 Feb 07 01:45:37 PM PST 24 Feb 07 01:46:23 PM PST 24 8775545995 ps
T1006 /workspace/coverage/default/42.spi_device_tpm_rw.3574588727 Feb 07 01:45:32 PM PST 24 Feb 07 01:45:43 PM PST 24 411398246 ps
T1007 /workspace/coverage/default/18.spi_device_alert_test.2115375755 Feb 07 01:44:00 PM PST 24 Feb 07 01:44:02 PM PST 24 62437902 ps
T1008 /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3505429658 Feb 07 01:44:46 PM PST 24 Feb 07 01:47:12 PM PST 24 34903858309 ps
T204 /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.736615427 Feb 07 01:42:24 PM PST 24 Feb 07 01:46:15 PM PST 24 306687420562 ps
T1009 /workspace/coverage/default/11.spi_device_flash_all.1788127397 Feb 07 01:43:20 PM PST 24 Feb 07 01:43:29 PM PST 24 648638329 ps
T1010 /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1090933251 Feb 07 01:44:15 PM PST 24 Feb 07 01:44:22 PM PST 24 1286685163 ps
T1011 /workspace/coverage/default/28.spi_device_stress_all.1380319789 Feb 07 01:44:32 PM PST 24 Feb 07 01:50:57 PM PST 24 443127498836 ps
T1012 /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1847227259 Feb 07 01:44:54 PM PST 24 Feb 07 01:46:53 PM PST 24 9600121372 ps
T1013 /workspace/coverage/default/11.spi_device_mem_parity.2504104011 Feb 07 01:43:11 PM PST 24 Feb 07 01:43:13 PM PST 24 91134338 ps
T1014 /workspace/coverage/default/30.spi_device_mailbox.2810696298 Feb 07 01:44:33 PM PST 24 Feb 07 01:44:40 PM PST 24 1386412453 ps
T1015 /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.152420710 Feb 07 01:44:59 PM PST 24 Feb 07 01:45:08 PM PST 24 5887652167 ps
T1016 /workspace/coverage/default/15.spi_device_tpm_sts_read.2818110664 Feb 07 01:43:40 PM PST 24 Feb 07 01:43:41 PM PST 24 154745350 ps
T1017 /workspace/coverage/default/16.spi_device_tpm_rw.633909610 Feb 07 01:43:46 PM PST 24 Feb 07 01:43:49 PM PST 24 46165263 ps
T1018 /workspace/coverage/default/9.spi_device_flash_all.4162332787 Feb 07 01:43:06 PM PST 24 Feb 07 01:44:04 PM PST 24 6346120149 ps
T1019 /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2961685468 Feb 07 01:44:50 PM PST 24 Feb 07 01:48:51 PM PST 24 192085815704 ps
T1020 /workspace/coverage/default/16.spi_device_tpm_all.2214919287 Feb 07 01:43:45 PM PST 24 Feb 07 01:44:37 PM PST 24 6250484706 ps
T1021 /workspace/coverage/default/12.spi_device_flash_all.1187640518 Feb 07 01:43:16 PM PST 24 Feb 07 01:44:31 PM PST 24 13425953167 ps
T1022 /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3554385107 Feb 07 01:43:03 PM PST 24 Feb 07 01:48:36 PM PST 24 52133032565 ps
T1023 /workspace/coverage/default/9.spi_device_stress_all.1050757224 Feb 07 01:43:11 PM PST 24 Feb 07 01:43:13 PM PST 24 45635660 ps
T1024 /workspace/coverage/default/6.spi_device_flash_all.1708139685 Feb 07 01:43:02 PM PST 24 Feb 07 01:44:04 PM PST 24 7515126546 ps
T1025 /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2653317487 Feb 07 01:42:17 PM PST 24 Feb 07 01:42:39 PM PST 24 5562570912 ps
T1026 /workspace/coverage/default/28.spi_device_flash_all.1305068942 Feb 07 01:44:34 PM PST 24 Feb 07 01:45:40 PM PST 24 27990616959 ps
T1027 /workspace/coverage/default/20.spi_device_csb_read.3350914738 Feb 07 01:44:00 PM PST 24 Feb 07 01:44:01 PM PST 24 17884637 ps
T1028 /workspace/coverage/default/15.spi_device_stress_all.3417641306 Feb 07 01:43:26 PM PST 24 Feb 07 01:43:29 PM PST 24 76711050 ps
T1029 /workspace/coverage/default/31.spi_device_mailbox.2441685387 Feb 07 01:44:40 PM PST 24 Feb 07 01:45:08 PM PST 24 11525730625 ps
T1030 /workspace/coverage/default/42.spi_device_flash_mode.4218899556 Feb 07 01:45:32 PM PST 24 Feb 07 01:46:06 PM PST 24 2733660994 ps
T1031 /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1554636912 Feb 07 01:44:29 PM PST 24 Feb 07 01:44:51 PM PST 24 18608558543 ps
T1032 /workspace/coverage/default/22.spi_device_flash_and_tpm.2069199604 Feb 07 01:44:19 PM PST 24 Feb 07 01:45:32 PM PST 24 3613646840 ps
T1033 /workspace/coverage/default/26.spi_device_flash_mode.3811849162 Feb 07 01:44:40 PM PST 24 Feb 07 01:44:54 PM PST 24 1736676593 ps
T1034 /workspace/coverage/default/35.spi_device_flash_all.2763503550 Feb 07 01:44:53 PM PST 24 Feb 07 01:46:11 PM PST 24 4216328610 ps
T1035 /workspace/coverage/default/16.spi_device_cfg_cmd.2229329557 Feb 07 01:43:45 PM PST 24 Feb 07 01:43:48 PM PST 24 102005244 ps
T1036 /workspace/coverage/default/47.spi_device_alert_test.977087946 Feb 07 01:45:48 PM PST 24 Feb 07 01:45:52 PM PST 24 18525373 ps
T1037 /workspace/coverage/default/49.spi_device_stress_all.3349328007 Feb 07 01:46:00 PM PST 24 Feb 07 01:50:30 PM PST 24 149048844916 ps
T1038 /workspace/coverage/default/31.spi_device_flash_and_tpm.2805529476 Feb 07 01:44:50 PM PST 24 Feb 07 01:47:20 PM PST 24 97459030930 ps
T1039 /workspace/coverage/default/2.spi_device_stress_all.4202593191 Feb 07 01:42:22 PM PST 24 Feb 07 01:45:31 PM PST 24 20126023166 ps
T1040 /workspace/coverage/default/21.spi_device_flash_mode.2646209666 Feb 07 01:44:02 PM PST 24 Feb 07 01:44:47 PM PST 24 46873711127 ps
T1041 /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4200332331 Feb 07 01:43:33 PM PST 24 Feb 07 01:43:45 PM PST 24 8224183359 ps
T1042 /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2347520786 Feb 07 01:44:05 PM PST 24 Feb 07 01:45:24 PM PST 24 81978141968 ps
T1043 /workspace/coverage/default/41.spi_device_csb_read.1516789677 Feb 07 01:45:29 PM PST 24 Feb 07 01:45:31 PM PST 24 14570900 ps
T1044 /workspace/coverage/default/8.spi_device_flash_all.1528838070 Feb 07 01:43:20 PM PST 24 Feb 07 01:44:00 PM PST 24 10361064330 ps
T1045 /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1538469220 Feb 07 01:45:03 PM PST 24 Feb 07 01:45:22 PM PST 24 66678646410 ps
T1046 /workspace/coverage/default/47.spi_device_tpm_rw.2369152480 Feb 07 01:45:41 PM PST 24 Feb 07 01:45:43 PM PST 24 69023970 ps
T1047 /workspace/coverage/default/6.spi_device_mem_parity.450803236 Feb 07 01:42:53 PM PST 24 Feb 07 01:42:59 PM PST 24 15816530 ps
T1048 /workspace/coverage/default/4.spi_device_mem_parity.434928734 Feb 07 01:42:35 PM PST 24 Feb 07 01:42:36 PM PST 24 118271726 ps
T1049 /workspace/coverage/default/15.spi_device_alert_test.912531463 Feb 07 01:43:36 PM PST 24 Feb 07 01:43:40 PM PST 24 43438228 ps
T1050 /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3593745458 Feb 07 01:44:28 PM PST 24 Feb 07 01:45:51 PM PST 24 8711965812 ps
T1051 /workspace/coverage/default/0.spi_device_upload.4218433530 Feb 07 01:42:13 PM PST 24 Feb 07 01:42:32 PM PST 24 100238942378 ps
T1052 /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1711906871 Feb 07 01:45:34 PM PST 24 Feb 07 01:45:40 PM PST 24 471256183 ps
T223 /workspace/coverage/default/7.spi_device_stress_all.2972902958 Feb 07 01:43:02 PM PST 24 Feb 07 01:51:17 PM PST 24 506083231298 ps
T1053 /workspace/coverage/default/42.spi_device_upload.2989440122 Feb 07 01:45:25 PM PST 24 Feb 07 01:45:46 PM PST 24 29550648753 ps
T1054 /workspace/coverage/default/5.spi_device_upload.2619786626 Feb 07 01:42:51 PM PST 24 Feb 07 01:42:59 PM PST 24 287524537 ps
T1055 /workspace/coverage/default/42.spi_device_flash_all.1863121227 Feb 07 01:45:30 PM PST 24 Feb 07 01:50:56 PM PST 24 681242357587 ps
T1056 /workspace/coverage/default/40.spi_device_flash_all.1074632699 Feb 07 01:45:19 PM PST 24 Feb 07 01:48:53 PM PST 24 49617990654 ps
T1057 /workspace/coverage/default/40.spi_device_tpm_all.639917085 Feb 07 01:45:14 PM PST 24 Feb 07 01:45:56 PM PST 24 20304380632 ps
T1058 /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2433222543 Feb 07 01:43:59 PM PST 24 Feb 07 01:44:09 PM PST 24 2940151884 ps
T1059 /workspace/coverage/default/36.spi_device_stress_all.3338288032 Feb 07 01:45:12 PM PST 24 Feb 07 01:47:10 PM PST 24 10356130812 ps
T1060 /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.105157601 Feb 07 01:44:53 PM PST 24 Feb 07 01:45:19 PM PST 24 8158251709 ps
T1061 /workspace/coverage/default/35.spi_device_flash_mode.1279538324 Feb 07 01:44:48 PM PST 24 Feb 07 01:44:55 PM PST 24 1060254835 ps
T1062 /workspace/coverage/default/46.spi_device_tpm_all.1595276972 Feb 07 01:45:46 PM PST 24 Feb 07 01:46:19 PM PST 24 2130959151 ps
T1063 /workspace/coverage/default/17.spi_device_read_buffer_direct.320957252 Feb 07 01:43:47 PM PST 24 Feb 07 01:43:56 PM PST 24 3206723962 ps
T1064 /workspace/coverage/default/6.spi_device_tpm_rw.3533768053 Feb 07 01:43:01 PM PST 24 Feb 07 01:43:10 PM PST 24 196785273 ps
T1065 /workspace/coverage/default/11.spi_device_tpm_rw.3829247841 Feb 07 01:43:14 PM PST 24 Feb 07 01:43:17 PM PST 24 170616443 ps
T1066 /workspace/coverage/default/6.spi_device_stress_all.1662526870 Feb 07 01:43:02 PM PST 24 Feb 07 01:43:08 PM PST 24 126708467 ps
T1067 /workspace/coverage/default/17.spi_device_tpm_all.4034285119 Feb 07 01:43:39 PM PST 24 Feb 07 01:43:47 PM PST 24 506362854 ps
T1068 /workspace/coverage/default/3.spi_device_alert_test.2640511789 Feb 07 01:42:34 PM PST 24 Feb 07 01:42:35 PM PST 24 18045256 ps
T1069 /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2652359859 Feb 07 01:42:49 PM PST 24 Feb 07 01:42:55 PM PST 24 3497225139 ps
T1070 /workspace/coverage/default/28.spi_device_read_buffer_direct.258265771 Feb 07 01:44:32 PM PST 24 Feb 07 01:44:38 PM PST 24 2608795186 ps
T1071 /workspace/coverage/default/39.spi_device_flash_mode.3118094707 Feb 07 01:45:24 PM PST 24 Feb 07 01:45:43 PM PST 24 1202720839 ps
T1072 /workspace/coverage/default/2.spi_device_tpm_all.3976984486 Feb 07 01:42:24 PM PST 24 Feb 07 01:43:23 PM PST 24 5890699223 ps
T1073 /workspace/coverage/default/3.spi_device_tpm_all.971355882 Feb 07 01:42:34 PM PST 24 Feb 07 01:42:54 PM PST 24 15000109462 ps
T1074 /workspace/coverage/default/45.spi_device_flash_and_tpm.1399029705 Feb 07 01:45:34 PM PST 24 Feb 07 01:47:51 PM PST 24 68347760391 ps
T216 /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.755075322 Feb 07 01:43:09 PM PST 24 Feb 07 01:45:39 PM PST 24 27707166558 ps
T1075 /workspace/coverage/default/37.spi_device_tpm_rw.1384000760 Feb 07 01:45:15 PM PST 24 Feb 07 01:45:22 PM PST 24 41975742 ps
T1076 /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1844574826 Feb 07 01:44:01 PM PST 24 Feb 07 01:44:09 PM PST 24 1384662144 ps
T1077 /workspace/coverage/default/13.spi_device_flash_mode.712815127 Feb 07 01:43:16 PM PST 24 Feb 07 01:43:48 PM PST 24 8040573894 ps
T1078 /workspace/coverage/default/24.spi_device_stress_all.256661556 Feb 07 01:44:30 PM PST 24 Feb 07 01:46:31 PM PST 24 25955255612 ps
T52 /workspace/coverage/default/0.spi_device_sec_cm.1768162661 Feb 07 01:42:13 PM PST 24 Feb 07 01:42:15 PM PST 24 35575144 ps
T1079 /workspace/coverage/default/17.spi_device_mailbox.2978130362 Feb 07 01:43:36 PM PST 24 Feb 07 01:43:44 PM PST 24 2303853414 ps
T1080 /workspace/coverage/default/1.spi_device_tpm_sts_read.3640309178 Feb 07 01:42:21 PM PST 24 Feb 07 01:42:23 PM PST 24 755921071 ps
T1081 /workspace/coverage/default/13.spi_device_mem_parity.205488343 Feb 07 01:43:22 PM PST 24 Feb 07 01:43:25 PM PST 24 16347437 ps
T1082 /workspace/coverage/default/4.spi_device_tpm_sts_read.225232000 Feb 07 01:42:32 PM PST 24 Feb 07 01:42:34 PM PST 24 359744729 ps
T1083 /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.96348457 Feb 07 01:43:33 PM PST 24 Feb 07 01:44:42 PM PST 24 5347751556 ps
T1084 /workspace/coverage/default/41.spi_device_flash_mode.106966854 Feb 07 01:45:28 PM PST 24 Feb 07 01:45:41 PM PST 24 774521734 ps
T1085 /workspace/coverage/default/1.spi_device_alert_test.957888226 Feb 07 01:42:24 PM PST 24 Feb 07 01:42:26 PM PST 24 38897849 ps
T1086 /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1054012502 Feb 07 01:45:27 PM PST 24 Feb 07 01:46:33 PM PST 24 6702828896 ps
T1087 /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3546171683 Feb 07 01:45:33 PM PST 24 Feb 07 01:45:38 PM PST 24 739876257 ps
T1088 /workspace/coverage/default/3.spi_device_ram_cfg.1166868791 Feb 07 01:42:32 PM PST 24 Feb 07 01:42:34 PM PST 24 17173075 ps
T1089 /workspace/coverage/default/13.spi_device_tpm_rw.2146742232 Feb 07 01:43:21 PM PST 24 Feb 07 01:43:24 PM PST 24 725143509 ps
T1090 /workspace/coverage/default/7.spi_device_alert_test.2695730651 Feb 07 01:43:00 PM PST 24 Feb 07 01:43:07 PM PST 24 13433651 ps
T1091 /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.924361715 Feb 07 01:44:16 PM PST 24 Feb 07 01:44:28 PM PST 24 24151219576 ps
T1092 /workspace/coverage/default/23.spi_device_cfg_cmd.1743954481 Feb 07 01:44:22 PM PST 24 Feb 07 01:44:26 PM PST 24 298649411 ps
T1093 /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3517725779 Feb 07 01:45:30 PM PST 24 Feb 07 01:45:39 PM PST 24 12203378034 ps
T1094 /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.807770393 Feb 07 01:42:48 PM PST 24 Feb 07 01:42:58 PM PST 24 1462912918 ps
T1095 /workspace/coverage/default/9.spi_device_intercept.2673038478 Feb 07 01:43:07 PM PST 24 Feb 07 01:43:17 PM PST 24 2576473846 ps
T1096 /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2601135486 Feb 07 01:44:39 PM PST 24 Feb 07 01:44:50 PM PST 24 1496108704 ps
T1097 /workspace/coverage/default/29.spi_device_read_buffer_direct.1038582239 Feb 07 01:44:42 PM PST 24 Feb 07 01:44:47 PM PST 24 239028907 ps
T1098 /workspace/coverage/default/25.spi_device_upload.4244698921 Feb 07 01:44:24 PM PST 24 Feb 07 01:44:27 PM PST 24 40777214 ps
T1099 /workspace/coverage/default/8.spi_device_flash_and_tpm.989528720 Feb 07 01:43:07 PM PST 24 Feb 07 01:47:21 PM PST 24 55017952185 ps
T1100 /workspace/coverage/default/26.spi_device_upload.3992793522 Feb 07 01:44:31 PM PST 24 Feb 07 01:44:35 PM PST 24 652251815 ps
T1101 /workspace/coverage/default/16.spi_device_flash_mode.4199581799 Feb 07 01:43:35 PM PST 24 Feb 07 01:43:48 PM PST 24 2893776293 ps
T1102 /workspace/coverage/default/7.spi_device_upload.672220629 Feb 07 01:43:02 PM PST 24 Feb 07 01:43:22 PM PST 24 18824973769 ps
T1103 /workspace/coverage/default/13.spi_device_pass_cmd_filtering.170280284 Feb 07 01:43:23 PM PST 24 Feb 07 01:43:35 PM PST 24 13652160099 ps
T1104 /workspace/coverage/default/39.spi_device_upload.3338390252 Feb 07 01:45:22 PM PST 24 Feb 07 01:45:28 PM PST 24 1104283310 ps
T1105 /workspace/coverage/default/28.spi_device_tpm_rw.2871719835 Feb 07 01:44:42 PM PST 24 Feb 07 01:44:45 PM PST 24 402046937 ps
T1106 /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.129192792 Feb 07 01:46:08 PM PST 24 Feb 07 01:46:18 PM PST 24 1741450829 ps
T1107 /workspace/coverage/default/49.spi_device_read_buffer_direct.1884176994 Feb 07 01:46:00 PM PST 24 Feb 07 01:46:06 PM PST 24 1593898863 ps
T1108 /workspace/coverage/default/17.spi_device_upload.3939261160 Feb 07 01:43:35 PM PST 24 Feb 07 01:43:58 PM PST 24 11014508634 ps
T1109 /workspace/coverage/default/31.spi_device_cfg_cmd.2774285374 Feb 07 01:44:40 PM PST 24 Feb 07 01:44:45 PM PST 24 3493676023 ps
T1110 /workspace/coverage/default/9.spi_device_read_buffer_direct.782270749 Feb 07 01:43:08 PM PST 24 Feb 07 01:43:16 PM PST 24 13012070030 ps
T1111 /workspace/coverage/default/35.spi_device_csb_read.2801235239 Feb 07 01:44:50 PM PST 24 Feb 07 01:44:52 PM PST 24 21057244 ps
T1112 /workspace/coverage/default/25.spi_device_intercept.3304237502 Feb 07 01:44:15 PM PST 24 Feb 07 01:44:23 PM PST 24 3692452250 ps
T1113 /workspace/coverage/default/21.spi_device_flash_all.2489748101 Feb 07 01:44:03 PM PST 24 Feb 07 01:46:51 PM PST 24 35811252026 ps
T1114 /workspace/coverage/default/28.spi_device_cfg_cmd.3680026391 Feb 07 01:44:34 PM PST 24 Feb 07 01:44:43 PM PST 24 3585329934 ps

Test location /workspace/coverage/default/17.spi_device_stress_all.803811206
Short name T7
Test name
Test status
Simulation time 28308332188 ps
CPU time 253.54 seconds
Started Feb 07 01:43:49 PM PST 24
Finished Feb 07 01:48:04 PM PST 24
Peak memory 290108 kb
Host smart-7266985e-98d4-47c7-ba8e-e8ec0232c690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803811206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.803811206
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.493817883
Short name T31
Test name
Test status
Simulation time 330917637015 ps
CPU time 622.31 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:55:52 PM PST 24
Peak memory 283308 kb
Host smart-972e6eb7-e33f-4d99-ad0f-4ccb495312fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493817883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.493817883
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1316085447
Short name T77
Test name
Test status
Simulation time 527571608 ps
CPU time 11.9 seconds
Started Feb 07 01:42:25 PM PST 24
Finished Feb 07 01:42:38 PM PST 24
Peak memory 238448 kb
Host smart-b1ac14f7-a93e-4963-bb94-2f0390a9fb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316085447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1316085447
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2705134075
Short name T44
Test name
Test status
Simulation time 334110146 ps
CPU time 7.17 seconds
Started Feb 07 12:35:01 PM PST 24
Finished Feb 07 12:35:14 PM PST 24
Peak memory 214760 kb
Host smart-392bb4a0-2d4f-4902-8ec7-46b495fd92af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705134075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2705134075
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2172147883
Short name T38
Test name
Test status
Simulation time 72873318595 ps
CPU time 313 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:49:54 PM PST 24
Peak memory 257656 kb
Host smart-422f4db9-2188-46d5-b3d5-280e72bc615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172147883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2172147883
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.606820419
Short name T22
Test name
Test status
Simulation time 31862454184 ps
CPU time 178.78 seconds
Started Feb 07 01:43:37 PM PST 24
Finished Feb 07 01:46:38 PM PST 24
Peak memory 273992 kb
Host smart-ccf418a6-a34b-4eb7-a9cf-3e9b586394d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606820419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.606820419
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1653193709
Short name T424
Test name
Test status
Simulation time 38560185 ps
CPU time 0.72 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:42:16 PM PST 24
Peak memory 216216 kb
Host smart-3ca1011b-89ff-4336-b608-29d2e28d9dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653193709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1653193709
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.728439626
Short name T81
Test name
Test status
Simulation time 638553083 ps
CPU time 3.79 seconds
Started Feb 07 12:35:14 PM PST 24
Finished Feb 07 12:35:22 PM PST 24
Peak memory 214948 kb
Host smart-aad8f341-530a-4d70-898e-6aac0bdd31a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728439626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.728439626
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3544126300
Short name T10
Test name
Test status
Simulation time 3814550626 ps
CPU time 53.91 seconds
Started Feb 07 01:44:32 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 216328 kb
Host smart-5d8a6247-77ae-4a27-9996-22cd144ce7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544126300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3544126300
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4180842450
Short name T206
Test name
Test status
Simulation time 1147617347565 ps
CPU time 1218.29 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 02:02:35 PM PST 24
Peak memory 305976 kb
Host smart-b1a2c7fe-41a5-4c7a-b3b6-7506b4b16a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180842450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4180842450
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.472448821
Short name T166
Test name
Test status
Simulation time 76610707862 ps
CPU time 378.53 seconds
Started Feb 07 01:44:53 PM PST 24
Finished Feb 07 01:51:13 PM PST 24
Peak memory 262796 kb
Host smart-27ce8dc3-870b-4edf-9cdf-aa549f301fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472448821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.472448821
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.780317622
Short name T94
Test name
Test status
Simulation time 31111283 ps
CPU time 2.04 seconds
Started Feb 07 12:35:03 PM PST 24
Finished Feb 07 12:35:10 PM PST 24
Peak memory 214776 kb
Host smart-d5dcf19b-ef8f-4649-ac0f-8de245d86354
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780317622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.780317622
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2244148693
Short name T30
Test name
Test status
Simulation time 342376805909 ps
CPU time 371.24 seconds
Started Feb 07 01:43:43 PM PST 24
Finished Feb 07 01:49:55 PM PST 24
Peak memory 264024 kb
Host smart-674724c5-80d8-4350-bfa5-bb3fa56e00b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244148693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2244148693
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2348001056
Short name T278
Test name
Test status
Simulation time 5850832752 ps
CPU time 81.4 seconds
Started Feb 07 01:45:29 PM PST 24
Finished Feb 07 01:46:51 PM PST 24
Peak memory 216360 kb
Host smart-c6fd25d4-7f60-4250-8b0b-0985f4bbf199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348001056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2348001056
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.482667444
Short name T170
Test name
Test status
Simulation time 937760872424 ps
CPU time 481.5 seconds
Started Feb 07 01:45:45 PM PST 24
Finished Feb 07 01:53:52 PM PST 24
Peak memory 273064 kb
Host smart-f8b4b4f9-3a15-4f51-a7d9-cba1b9cb0b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482667444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.482667444
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.251527812
Short name T132
Test name
Test status
Simulation time 13806744060 ps
CPU time 69.42 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:45:37 PM PST 24
Peak memory 239224 kb
Host smart-e0a2eea2-ad5e-44ce-ab22-15dbf51f92f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251527812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.251527812
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2831617097
Short name T48
Test name
Test status
Simulation time 287205356 ps
CPU time 1.12 seconds
Started Feb 07 01:42:31 PM PST 24
Finished Feb 07 01:42:32 PM PST 24
Peak memory 235692 kb
Host smart-2518a31b-a624-40f6-a124-a910ac610016
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831617097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2831617097
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2615601264
Short name T252
Test name
Test status
Simulation time 86477676412 ps
CPU time 480.95 seconds
Started Feb 07 01:42:40 PM PST 24
Finished Feb 07 01:50:42 PM PST 24
Peak memory 290524 kb
Host smart-4a1b6e7f-1e9b-43bc-b005-d522ef30613f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615601264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2615601264
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.881367779
Short name T179
Test name
Test status
Simulation time 507122912183 ps
CPU time 827.4 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:58:15 PM PST 24
Peak memory 265484 kb
Host smart-92704eb3-7879-4836-912a-0f5811f47620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881367779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.881367779
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2495544285
Short name T91
Test name
Test status
Simulation time 290448045 ps
CPU time 17.01 seconds
Started Feb 07 12:35:01 PM PST 24
Finished Feb 07 12:35:23 PM PST 24
Peak memory 214760 kb
Host smart-87513cc6-ed8e-4439-9b54-ef7dd70f082e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495544285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2495544285
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1851499940
Short name T178
Test name
Test status
Simulation time 48577907166 ps
CPU time 140.02 seconds
Started Feb 07 01:44:20 PM PST 24
Finished Feb 07 01:46:41 PM PST 24
Peak memory 265592 kb
Host smart-06e54631-c35b-4ba7-886c-b59fce12264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851499940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1851499940
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2077591003
Short name T39
Test name
Test status
Simulation time 14340337709 ps
CPU time 126.26 seconds
Started Feb 07 01:45:45 PM PST 24
Finished Feb 07 01:47:56 PM PST 24
Peak memory 281324 kb
Host smart-4f3e4973-9557-4317-b28e-c33af25824ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077591003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2077591003
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1083612594
Short name T9
Test name
Test status
Simulation time 19721361761 ps
CPU time 29.08 seconds
Started Feb 07 01:42:14 PM PST 24
Finished Feb 07 01:42:44 PM PST 24
Peak memory 216600 kb
Host smart-ae687722-338c-48b1-9900-c8e6d6457105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083612594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1083612594
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4057218453
Short name T37
Test name
Test status
Simulation time 173923261038 ps
CPU time 308.12 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:49:38 PM PST 24
Peak memory 257528 kb
Host smart-6d117d52-73ac-484c-b53d-cb92e5f1753d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057218453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4057218453
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.560925837
Short name T185
Test name
Test status
Simulation time 65087620308 ps
CPU time 127.98 seconds
Started Feb 07 01:45:51 PM PST 24
Finished Feb 07 01:48:03 PM PST 24
Peak memory 240592 kb
Host smart-7c79b598-cba2-43c4-b512-54a61efd2e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560925837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.560925837
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.367205731
Short name T24
Test name
Test status
Simulation time 86866067 ps
CPU time 1.01 seconds
Started Feb 07 01:42:17 PM PST 24
Finished Feb 07 01:42:19 PM PST 24
Peak memory 216640 kb
Host smart-c3fe5be5-3fb0-46c9-943c-65dde3bce584
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367205731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.367205731
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3367872683
Short name T32
Test name
Test status
Simulation time 47160863436 ps
CPU time 34.74 seconds
Started Feb 07 01:43:01 PM PST 24
Finished Feb 07 01:43:42 PM PST 24
Peak memory 229580 kb
Host smart-0648b8f8-9955-4f16-aab3-089494033d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367872683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3367872683
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2674613475
Short name T214
Test name
Test status
Simulation time 336626929955 ps
CPU time 903.04 seconds
Started Feb 07 01:43:25 PM PST 24
Finished Feb 07 01:58:30 PM PST 24
Peak memory 286384 kb
Host smart-0861319e-814a-498f-9f87-9e7b6ff4c624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674613475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2674613475
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.792168347
Short name T210
Test name
Test status
Simulation time 62003878479 ps
CPU time 185.41 seconds
Started Feb 07 01:43:48 PM PST 24
Finished Feb 07 01:46:55 PM PST 24
Peak memory 259572 kb
Host smart-6425ca89-13e5-454e-bcb5-c71c6a4ca09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792168347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.792168347
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.40839983
Short name T184
Test name
Test status
Simulation time 58960017083 ps
CPU time 298.81 seconds
Started Feb 07 01:44:50 PM PST 24
Finished Feb 07 01:49:49 PM PST 24
Peak memory 266904 kb
Host smart-0c3cc53e-9519-48e6-a4d8-dda4dff28436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40839983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.40839983
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3909939268
Short name T233
Test name
Test status
Simulation time 109335059 ps
CPU time 3.17 seconds
Started Feb 07 12:34:44 PM PST 24
Finished Feb 07 12:34:48 PM PST 24
Peak memory 214964 kb
Host smart-0c5ef764-d77f-4ed4-b63e-2dc0bacc7554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909939268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
909939268
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1909659037
Short name T11
Test name
Test status
Simulation time 16049071894 ps
CPU time 150.48 seconds
Started Feb 07 01:44:46 PM PST 24
Finished Feb 07 01:47:18 PM PST 24
Peak memory 251588 kb
Host smart-6d6345c7-a9d8-47c5-a7af-d7a4beb804cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909659037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1909659037
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2174278137
Short name T76
Test name
Test status
Simulation time 1466366131 ps
CPU time 16.72 seconds
Started Feb 07 12:35:07 PM PST 24
Finished Feb 07 12:35:29 PM PST 24
Peak memory 214816 kb
Host smart-e95c9c53-b787-4b33-8a8b-dab9b9b6a9b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174278137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2174278137
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1803152332
Short name T269
Test name
Test status
Simulation time 18196684648 ps
CPU time 31.62 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:34 PM PST 24
Peak memory 245752 kb
Host smart-ecc4b1c3-2e71-4d8e-952e-95c7f5b84482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803152332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1803152332
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.35050447
Short name T154
Test name
Test status
Simulation time 1028074831 ps
CPU time 22.23 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:45:49 PM PST 24
Peak memory 233956 kb
Host smart-ab5d25d5-a95c-4af4-b7e3-215ce77441e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35050447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.35050447
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2711137567
Short name T63
Test name
Test status
Simulation time 138845027754 ps
CPU time 155.87 seconds
Started Feb 07 01:43:33 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 238704 kb
Host smart-2e9ad41d-ad6a-4e4e-aa77-3b2f81853b8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711137567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2711137567
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1413437622
Short name T337
Test name
Test status
Simulation time 29815652 ps
CPU time 2.54 seconds
Started Feb 07 12:34:53 PM PST 24
Finished Feb 07 12:34:57 PM PST 24
Peak memory 217016 kb
Host smart-10195fec-940a-43b7-93b6-6f26cbbce8f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413437622 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1413437622
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3960181991
Short name T228
Test name
Test status
Simulation time 3605198001 ps
CPU time 77.99 seconds
Started Feb 07 01:42:18 PM PST 24
Finished Feb 07 01:43:37 PM PST 24
Peak memory 264700 kb
Host smart-7a2f2112-b7e4-4b5a-aee9-35d13a5f7e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960181991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3960181991
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3236947074
Short name T69
Test name
Test status
Simulation time 176134595 ps
CPU time 4.38 seconds
Started Feb 07 01:42:16 PM PST 24
Finished Feb 07 01:42:21 PM PST 24
Peak memory 233440 kb
Host smart-ce52da1d-c240-4272-af5f-f575c969ff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236947074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3236947074
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.913127850
Short name T197
Test name
Test status
Simulation time 162427830615 ps
CPU time 1208.08 seconds
Started Feb 07 01:44:24 PM PST 24
Finished Feb 07 02:04:33 PM PST 24
Peak memory 306888 kb
Host smart-2163fb55-37fc-42ec-b104-926ea8b253eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913127850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.913127850
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3614278792
Short name T227
Test name
Test status
Simulation time 73291269120 ps
CPU time 90.56 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:46:05 PM PST 24
Peak memory 243848 kb
Host smart-8accdc9e-ca54-4a51-a4f1-28fbe8d064e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614278792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3614278792
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.662375201
Short name T299
Test name
Test status
Simulation time 17113890 ps
CPU time 0.7 seconds
Started Feb 07 01:43:32 PM PST 24
Finished Feb 07 01:43:35 PM PST 24
Peak memory 205048 kb
Host smart-a4cf8e55-a2cb-4a49-aac6-36d0dfed25cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662375201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.662375201
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3387929985
Short name T357
Test name
Test status
Simulation time 33061999 ps
CPU time 1.84 seconds
Started Feb 07 12:34:52 PM PST 24
Finished Feb 07 12:34:55 PM PST 24
Peak memory 214916 kb
Host smart-8e1e802b-5521-413d-b1b6-c5d650c25e00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387929985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
387929985
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3693256370
Short name T85
Test name
Test status
Simulation time 3647861375 ps
CPU time 20.15 seconds
Started Feb 07 12:35:08 PM PST 24
Finished Feb 07 12:35:33 PM PST 24
Peak memory 223108 kb
Host smart-45519baa-8616-43d6-b9b9-e094e9d189d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693256370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3693256370
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3444845251
Short name T62
Test name
Test status
Simulation time 168024513 ps
CPU time 1.41 seconds
Started Feb 07 12:35:02 PM PST 24
Finished Feb 07 12:35:08 PM PST 24
Peak memory 215724 kb
Host smart-1d770da0-1571-4448-acf4-fcc8066b5d15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444845251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3444845251
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.573428020
Short name T404
Test name
Test status
Simulation time 407036589 ps
CPU time 8.44 seconds
Started Feb 07 12:35:00 PM PST 24
Finished Feb 07 12:35:13 PM PST 24
Peak memory 206540 kb
Host smart-9783db2f-d447-4787-aed4-04c5ec259d64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573428020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.573428020
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2249217667
Short name T108
Test name
Test status
Simulation time 1256585214 ps
CPU time 25.3 seconds
Started Feb 07 12:34:52 PM PST 24
Finished Feb 07 12:35:19 PM PST 24
Peak memory 206516 kb
Host smart-ea480efa-a0d4-4ef0-a835-933a5507f760
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249217667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2249217667
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3120546253
Short name T377
Test name
Test status
Simulation time 37921761 ps
CPU time 0.96 seconds
Started Feb 07 12:35:01 PM PST 24
Finished Feb 07 12:35:07 PM PST 24
Peak memory 205576 kb
Host smart-2ef4b4ed-748f-4bf4-972c-1cc9239d9f54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120546253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3120546253
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.358907656
Short name T355
Test name
Test status
Simulation time 38441302 ps
CPU time 2.44 seconds
Started Feb 07 12:34:55 PM PST 24
Finished Feb 07 12:34:59 PM PST 24
Peak memory 206548 kb
Host smart-e581d5f0-9a41-4e03-8b21-344a8518f19e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358907656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.358907656
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2814031127
Short name T310
Test name
Test status
Simulation time 58397839 ps
CPU time 0.76 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:03 PM PST 24
Peak memory 202720 kb
Host smart-9f35bf1d-f044-4527-a564-455a19380352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814031127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
814031127
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2290236530
Short name T413
Test name
Test status
Simulation time 315574957 ps
CPU time 2.13 seconds
Started Feb 07 12:35:00 PM PST 24
Finished Feb 07 12:35:07 PM PST 24
Peak memory 214760 kb
Host smart-65616567-6487-466e-8dcf-2e6540c26d6e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290236530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2290236530
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.449739080
Short name T341
Test name
Test status
Simulation time 14039901 ps
CPU time 0.67 seconds
Started Feb 07 12:34:53 PM PST 24
Finished Feb 07 12:34:56 PM PST 24
Peak memory 202452 kb
Host smart-bdde9809-ab61-4876-881a-ad087a48acdd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449739080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.449739080
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1436568588
Short name T345
Test name
Test status
Simulation time 83288463 ps
CPU time 1.66 seconds
Started Feb 07 12:34:57 PM PST 24
Finished Feb 07 12:35:01 PM PST 24
Peak memory 206540 kb
Host smart-a612c256-65f3-4df0-82f4-f3a24f56dd8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436568588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1436568588
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3605697603
Short name T350
Test name
Test status
Simulation time 1097862809 ps
CPU time 6.41 seconds
Started Feb 07 12:35:01 PM PST 24
Finished Feb 07 12:35:12 PM PST 24
Peak memory 214740 kb
Host smart-adef1bdb-8fbb-4408-aeab-2ba07f4b20fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605697603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3605697603
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1670017428
Short name T358
Test name
Test status
Simulation time 640396878 ps
CPU time 22.94 seconds
Started Feb 07 12:35:01 PM PST 24
Finished Feb 07 12:35:29 PM PST 24
Peak memory 214800 kb
Host smart-4bf4c381-dfbb-4072-bc0a-fb78777c2ba6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670017428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1670017428
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2449132744
Short name T137
Test name
Test status
Simulation time 1961492571 ps
CPU time 14.21 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:18 PM PST 24
Peak memory 206648 kb
Host smart-589a96e7-b50c-4247-827c-834c848dc311
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449132744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2449132744
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2360834031
Short name T325
Test name
Test status
Simulation time 33278700 ps
CPU time 1.15 seconds
Started Feb 07 12:34:57 PM PST 24
Finished Feb 07 12:34:59 PM PST 24
Peak memory 214836 kb
Host smart-8e57abae-c157-4a3d-bfd7-0a6109675480
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360834031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2360834031
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4192757640
Short name T143
Test name
Test status
Simulation time 26727343 ps
CPU time 1.77 seconds
Started Feb 07 12:35:00 PM PST 24
Finished Feb 07 12:35:06 PM PST 24
Peak memory 215764 kb
Host smart-5aac281f-24c0-4b07-b910-333deb84e51d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192757640 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4192757640
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2897058501
Short name T387
Test name
Test status
Simulation time 35854169 ps
CPU time 2.11 seconds
Started Feb 07 12:34:57 PM PST 24
Finished Feb 07 12:35:00 PM PST 24
Peak memory 214724 kb
Host smart-5685ad5b-5e0a-4806-95e9-7271b9a9f0fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897058501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
897058501
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4004951540
Short name T330
Test name
Test status
Simulation time 21656334 ps
CPU time 0.7 seconds
Started Feb 07 12:34:57 PM PST 24
Finished Feb 07 12:35:00 PM PST 24
Peak memory 202740 kb
Host smart-b487ecad-9be3-45e1-9707-d70efdf08f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004951540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
004951540
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2374733809
Short name T418
Test name
Test status
Simulation time 20576154 ps
CPU time 1.3 seconds
Started Feb 07 12:35:07 PM PST 24
Finished Feb 07 12:35:12 PM PST 24
Peak memory 214820 kb
Host smart-51a39460-5a39-42ca-b1ae-cb997b057ef9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374733809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2374733809
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2548001157
Short name T407
Test name
Test status
Simulation time 17583232 ps
CPU time 0.63 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:03 PM PST 24
Peak memory 202376 kb
Host smart-4040d87a-0ee2-4703-af85-2814cfa68fb8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548001157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2548001157
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2505295305
Short name T389
Test name
Test status
Simulation time 74560620 ps
CPU time 1.81 seconds
Started Feb 07 12:35:01 PM PST 24
Finished Feb 07 12:35:08 PM PST 24
Peak memory 214496 kb
Host smart-6b5d4afd-c9a9-413f-8f53-f50076a7720d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505295305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2505295305
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.299810169
Short name T238
Test name
Test status
Simulation time 4623587328 ps
CPU time 7.27 seconds
Started Feb 07 12:34:53 PM PST 24
Finished Feb 07 12:35:02 PM PST 24
Peak memory 214900 kb
Host smart-b85b4461-d7cd-4c21-a7f8-87a7c57c5866
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299810169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.299810169
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3117597602
Short name T281
Test name
Test status
Simulation time 61923121 ps
CPU time 1.73 seconds
Started Feb 07 12:35:09 PM PST 24
Finished Feb 07 12:35:16 PM PST 24
Peak memory 215160 kb
Host smart-615af3bb-3875-4ed9-b0cb-10b434ee9774
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117597602 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3117597602
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3959726950
Short name T381
Test name
Test status
Simulation time 324239940 ps
CPU time 2.35 seconds
Started Feb 07 12:35:14 PM PST 24
Finished Feb 07 12:35:21 PM PST 24
Peak memory 214796 kb
Host smart-3d24c41d-3c5f-41f8-a326-83d2d74813f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959726950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3959726950
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1561800791
Short name T346
Test name
Test status
Simulation time 11987628 ps
CPU time 0.74 seconds
Started Feb 07 12:35:14 PM PST 24
Finished Feb 07 12:35:23 PM PST 24
Peak memory 202492 kb
Host smart-03304516-bb84-4c3f-b349-e133f426a1d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561800791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1561800791
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.883419509
Short name T365
Test name
Test status
Simulation time 720007160 ps
CPU time 2.69 seconds
Started Feb 07 12:35:07 PM PST 24
Finished Feb 07 12:35:15 PM PST 24
Peak memory 206556 kb
Host smart-490b913c-d60e-42cc-b238-2a4418ce087d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883419509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.883419509
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4134474802
Short name T397
Test name
Test status
Simulation time 112413057 ps
CPU time 2.98 seconds
Started Feb 07 12:35:01 PM PST 24
Finished Feb 07 12:35:09 PM PST 24
Peak memory 215952 kb
Host smart-87510374-6d7a-4bb6-8890-8a9e52acaa31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134474802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4134474802
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2341433187
Short name T237
Test name
Test status
Simulation time 3826604514 ps
CPU time 20.44 seconds
Started Feb 07 12:35:11 PM PST 24
Finished Feb 07 12:35:37 PM PST 24
Peak memory 214948 kb
Host smart-e4b7c458-814c-43e6-a04f-8d82350f6c67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341433187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2341433187
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3559307252
Short name T102
Test name
Test status
Simulation time 22173478 ps
CPU time 1.32 seconds
Started Feb 07 12:35:22 PM PST 24
Finished Feb 07 12:35:25 PM PST 24
Peak memory 214856 kb
Host smart-e405b93e-2f3b-4f6e-8b71-354396facefa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559307252 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3559307252
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2950198201
Short name T115
Test name
Test status
Simulation time 117136927 ps
CPU time 1.94 seconds
Started Feb 07 12:35:11 PM PST 24
Finished Feb 07 12:35:18 PM PST 24
Peak memory 214780 kb
Host smart-71b6dd3e-9d30-4ac6-87cb-bff281256832
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950198201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2950198201
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2958387357
Short name T419
Test name
Test status
Simulation time 167096455 ps
CPU time 0.73 seconds
Started Feb 07 12:35:14 PM PST 24
Finished Feb 07 12:35:19 PM PST 24
Peak memory 202796 kb
Host smart-5e3dd1f2-da47-4cff-b2cb-4db7012a1edd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958387357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2958387357
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4052410384
Short name T335
Test name
Test status
Simulation time 400851979 ps
CPU time 3.01 seconds
Started Feb 07 12:35:11 PM PST 24
Finished Feb 07 12:35:20 PM PST 24
Peak memory 206404 kb
Host smart-e139cc21-bd31-4435-a704-33fd5bc574ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052410384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4052410384
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.876942380
Short name T391
Test name
Test status
Simulation time 507890348 ps
CPU time 2.52 seconds
Started Feb 07 12:35:13 PM PST 24
Finished Feb 07 12:35:20 PM PST 24
Peak memory 214952 kb
Host smart-171ef8e9-2630-4c9e-b5de-bdadecd1f131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876942380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.876942380
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3880247348
Short name T364
Test name
Test status
Simulation time 105032273 ps
CPU time 6.15 seconds
Started Feb 07 12:35:11 PM PST 24
Finished Feb 07 12:35:23 PM PST 24
Peak memory 214816 kb
Host smart-36ac1f27-2f52-4446-96ef-965ab6afe3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880247348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3880247348
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.613709364
Short name T395
Test name
Test status
Simulation time 44821326 ps
CPU time 2.49 seconds
Started Feb 07 12:35:10 PM PST 24
Finished Feb 07 12:35:19 PM PST 24
Peak memory 216980 kb
Host smart-628886c6-2553-482d-99aa-501875b46503
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613709364 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.613709364
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.507167949
Short name T382
Test name
Test status
Simulation time 128013500 ps
CPU time 1.26 seconds
Started Feb 07 12:35:10 PM PST 24
Finished Feb 07 12:35:18 PM PST 24
Peak memory 214728 kb
Host smart-1f910e2f-3702-4e32-8a0e-2d5c86d43f3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507167949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.507167949
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1489212795
Short name T139
Test name
Test status
Simulation time 17973565 ps
CPU time 0.71 seconds
Started Feb 07 12:35:08 PM PST 24
Finished Feb 07 12:35:13 PM PST 24
Peak memory 202408 kb
Host smart-1b00f361-4dee-41f2-9e11-1bbd2dffabbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489212795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1489212795
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.60140539
Short name T315
Test name
Test status
Simulation time 236759308 ps
CPU time 2.69 seconds
Started Feb 07 12:35:11 PM PST 24
Finished Feb 07 12:35:19 PM PST 24
Peak memory 206568 kb
Host smart-215b69d1-b61e-438b-81e7-476de798b30d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60140539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sp
i_device_same_csr_outstanding.60140539
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2177072422
Short name T234
Test name
Test status
Simulation time 744811804 ps
CPU time 4.79 seconds
Started Feb 07 12:35:04 PM PST 24
Finished Feb 07 12:35:13 PM PST 24
Peak memory 215032 kb
Host smart-fdd39eef-8675-4b3b-93d9-1a18320055c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177072422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2177072422
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2726494376
Short name T360
Test name
Test status
Simulation time 2730263000 ps
CPU time 15.19 seconds
Started Feb 07 12:35:09 PM PST 24
Finished Feb 07 12:35:30 PM PST 24
Peak memory 214820 kb
Host smart-de92d74c-0568-49d2-a642-260a2951cc53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726494376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2726494376
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2606532992
Short name T71
Test name
Test status
Simulation time 25654436 ps
CPU time 1.51 seconds
Started Feb 07 12:35:12 PM PST 24
Finished Feb 07 12:35:18 PM PST 24
Peak memory 214996 kb
Host smart-ec1de811-22bc-4b41-b735-022d5c502c70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606532992 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2606532992
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3549158671
Short name T110
Test name
Test status
Simulation time 118723707 ps
CPU time 2.57 seconds
Started Feb 07 12:35:10 PM PST 24
Finished Feb 07 12:35:19 PM PST 24
Peak memory 206680 kb
Host smart-d14d52c5-e6b4-490d-9a72-0aae5a3c8188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549158671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3549158671
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.364091774
Short name T316
Test name
Test status
Simulation time 87983721 ps
CPU time 0.73 seconds
Started Feb 07 12:35:08 PM PST 24
Finished Feb 07 12:35:14 PM PST 24
Peak memory 202496 kb
Host smart-5ae85350-00b6-44ec-8119-831d5ba186c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364091774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.364091774
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1129908971
Short name T312
Test name
Test status
Simulation time 977720334 ps
CPU time 3.21 seconds
Started Feb 07 12:35:15 PM PST 24
Finished Feb 07 12:35:22 PM PST 24
Peak memory 206616 kb
Host smart-7e6c9ffb-4bbd-4d38-b389-0df51b3cc6d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129908971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1129908971
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1320477647
Short name T383
Test name
Test status
Simulation time 178677363 ps
CPU time 2.22 seconds
Started Feb 07 12:35:14 PM PST 24
Finished Feb 07 12:35:20 PM PST 24
Peak memory 215032 kb
Host smart-21808aac-9308-464b-a606-9ec4bda130d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320477647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1320477647
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3770227438
Short name T101
Test name
Test status
Simulation time 14582605 ps
CPU time 1.17 seconds
Started Feb 07 12:35:05 PM PST 24
Finished Feb 07 12:35:10 PM PST 24
Peak memory 214864 kb
Host smart-3eea5f2b-36f3-4569-9920-372b041976fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770227438 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3770227438
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.737541570
Short name T388
Test name
Test status
Simulation time 80653355 ps
CPU time 2.06 seconds
Started Feb 07 12:35:22 PM PST 24
Finished Feb 07 12:35:26 PM PST 24
Peak memory 214776 kb
Host smart-0636a9ae-1198-4ab3-8d5a-3ce267e73c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737541570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.737541570
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.323268685
Short name T352
Test name
Test status
Simulation time 12855684 ps
CPU time 0.7 seconds
Started Feb 07 12:35:06 PM PST 24
Finished Feb 07 12:35:11 PM PST 24
Peak memory 202440 kb
Host smart-fb1104bc-7d64-4dc7-84f4-579d5094af02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323268685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.323268685
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.949886855
Short name T99
Test name
Test status
Simulation time 1605194387 ps
CPU time 4.19 seconds
Started Feb 07 12:35:13 PM PST 24
Finished Feb 07 12:35:22 PM PST 24
Peak memory 206660 kb
Host smart-f27a898a-ac00-4f08-992a-c5772b761612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949886855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.949886855
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3434477321
Short name T82
Test name
Test status
Simulation time 171077241 ps
CPU time 3.43 seconds
Started Feb 07 12:35:08 PM PST 24
Finished Feb 07 12:35:16 PM PST 24
Peak memory 214952 kb
Host smart-15b7cd04-182e-4305-b31d-367e072bd654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434477321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3434477321
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2484192635
Short name T356
Test name
Test status
Simulation time 140376023 ps
CPU time 2.23 seconds
Started Feb 07 12:35:08 PM PST 24
Finished Feb 07 12:35:16 PM PST 24
Peak memory 215964 kb
Host smart-677ca401-03d1-4948-8c44-45b6aa0a341b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484192635 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2484192635
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3167801001
Short name T321
Test name
Test status
Simulation time 33396088 ps
CPU time 1.26 seconds
Started Feb 07 12:35:17 PM PST 24
Finished Feb 07 12:35:21 PM PST 24
Peak memory 214788 kb
Host smart-5c032ab9-ad75-4429-b8ad-ece0817099cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167801001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3167801001
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3075540199
Short name T92
Test name
Test status
Simulation time 59922453 ps
CPU time 0.78 seconds
Started Feb 07 12:35:04 PM PST 24
Finished Feb 07 12:35:09 PM PST 24
Peak memory 202496 kb
Host smart-fe916b14-d70e-4b7e-8ede-603061fcb781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075540199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3075540199
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4107986224
Short name T106
Test name
Test status
Simulation time 110803115 ps
CPU time 2.99 seconds
Started Feb 07 12:35:07 PM PST 24
Finished Feb 07 12:35:15 PM PST 24
Peak memory 206420 kb
Host smart-88d3c8f4-c6db-46a3-9741-3a4c3d1dfd2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107986224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4107986224
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2979738435
Short name T414
Test name
Test status
Simulation time 378312240 ps
CPU time 8.67 seconds
Started Feb 07 12:35:14 PM PST 24
Finished Feb 07 12:35:27 PM PST 24
Peak memory 214780 kb
Host smart-47e678a7-a0f4-42e8-af37-eaf250c61342
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979738435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2979738435
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3183747500
Short name T280
Test name
Test status
Simulation time 30200542 ps
CPU time 1.49 seconds
Started Feb 07 12:35:09 PM PST 24
Finished Feb 07 12:35:17 PM PST 24
Peak memory 214908 kb
Host smart-ec29e845-8bd3-4fd4-b809-6cac9ac0928c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183747500 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3183747500
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2556777161
Short name T113
Test name
Test status
Simulation time 98208058 ps
CPU time 2.7 seconds
Started Feb 07 12:35:13 PM PST 24
Finished Feb 07 12:35:20 PM PST 24
Peak memory 214632 kb
Host smart-522723cb-0428-47b0-95cc-43f384cbf2ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556777161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2556777161
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.515769836
Short name T367
Test name
Test status
Simulation time 20485811 ps
CPU time 0.71 seconds
Started Feb 07 12:35:07 PM PST 24
Finished Feb 07 12:35:12 PM PST 24
Peak memory 202500 kb
Host smart-b4d5ff14-b55f-432c-a160-ccd00c3e4ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515769836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.515769836
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2697030475
Short name T124
Test name
Test status
Simulation time 80763306 ps
CPU time 2.97 seconds
Started Feb 07 12:35:16 PM PST 24
Finished Feb 07 12:35:22 PM PST 24
Peak memory 214748 kb
Host smart-84abc42a-7594-4879-be4a-39f95910656e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697030475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2697030475
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.17899967
Short name T83
Test name
Test status
Simulation time 90507746 ps
CPU time 3 seconds
Started Feb 07 12:35:21 PM PST 24
Finished Feb 07 12:35:26 PM PST 24
Peak memory 216008 kb
Host smart-e282a136-f419-48f9-a8cc-66f8ad31399e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17899967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.17899967
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.305242213
Short name T75
Test name
Test status
Simulation time 347261973 ps
CPU time 11.98 seconds
Started Feb 07 12:35:03 PM PST 24
Finished Feb 07 12:35:20 PM PST 24
Peak memory 214796 kb
Host smart-84ecb598-7d3f-43e3-89b7-62902f0b6251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305242213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.305242213
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4225603958
Short name T89
Test name
Test status
Simulation time 57483889 ps
CPU time 1.26 seconds
Started Feb 07 12:35:10 PM PST 24
Finished Feb 07 12:35:18 PM PST 24
Peak memory 214928 kb
Host smart-745478f0-91b9-45fe-b716-a03d454b9fb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225603958 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4225603958
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.741525175
Short name T400
Test name
Test status
Simulation time 133340794 ps
CPU time 1.8 seconds
Started Feb 07 12:35:04 PM PST 24
Finished Feb 07 12:35:10 PM PST 24
Peak memory 206596 kb
Host smart-07be777b-a59e-411e-ac58-bf3ec0570c37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741525175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.741525175
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2641047340
Short name T340
Test name
Test status
Simulation time 78642772 ps
CPU time 0.7 seconds
Started Feb 07 12:35:05 PM PST 24
Finished Feb 07 12:35:10 PM PST 24
Peak memory 202760 kb
Host smart-b2fa0e04-7808-4a10-b45e-5cfd52ee1fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641047340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2641047340
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1594216657
Short name T125
Test name
Test status
Simulation time 742917168 ps
CPU time 2.69 seconds
Started Feb 07 12:35:11 PM PST 24
Finished Feb 07 12:35:19 PM PST 24
Peak memory 214852 kb
Host smart-900b4c79-464c-4c0f-8e75-fa03002bea96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594216657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1594216657
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1917785686
Short name T84
Test name
Test status
Simulation time 450990757 ps
CPU time 4.57 seconds
Started Feb 07 12:35:06 PM PST 24
Finished Feb 07 12:35:15 PM PST 24
Peak memory 214880 kb
Host smart-4afda9e0-c8bb-4626-923f-07bf7fc83f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917785686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1917785686
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3579880827
Short name T359
Test name
Test status
Simulation time 522886184 ps
CPU time 7.07 seconds
Started Feb 07 12:35:13 PM PST 24
Finished Feb 07 12:35:24 PM PST 24
Peak memory 214596 kb
Host smart-21924e28-f01c-480f-84d8-766dabb7e538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579880827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3579880827
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.579527056
Short name T348
Test name
Test status
Simulation time 31926686 ps
CPU time 1.23 seconds
Started Feb 07 12:35:37 PM PST 24
Finished Feb 07 12:35:45 PM PST 24
Peak memory 214984 kb
Host smart-1da36e4b-4ff2-477f-8244-e01860d89c5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579527056 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.579527056
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.897081899
Short name T109
Test name
Test status
Simulation time 163598017 ps
CPU time 1.3 seconds
Started Feb 07 12:35:11 PM PST 24
Finished Feb 07 12:35:18 PM PST 24
Peak memory 206604 kb
Host smart-37e84e11-8eaf-42fe-a03b-c01c052c9940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897081899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.897081899
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.406625030
Short name T320
Test name
Test status
Simulation time 57284197 ps
CPU time 0.8 seconds
Started Feb 07 12:35:12 PM PST 24
Finished Feb 07 12:35:18 PM PST 24
Peak memory 202812 kb
Host smart-2660d678-a825-4e86-83d4-5269b0f0387d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406625030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.406625030
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4271855756
Short name T339
Test name
Test status
Simulation time 368916389 ps
CPU time 4.16 seconds
Started Feb 07 12:35:26 PM PST 24
Finished Feb 07 12:35:40 PM PST 24
Peak memory 214864 kb
Host smart-a87d35b1-a8b0-40c7-bd74-bc97a540ca52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271855756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4271855756
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1653496864
Short name T363
Test name
Test status
Simulation time 907409865 ps
CPU time 4.24 seconds
Started Feb 07 12:35:10 PM PST 24
Finished Feb 07 12:35:20 PM PST 24
Peak memory 215088 kb
Host smart-7c710deb-bac1-4c9e-a587-c33f532e3492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653496864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1653496864
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1355256857
Short name T409
Test name
Test status
Simulation time 821029204 ps
CPU time 22.4 seconds
Started Feb 07 12:35:12 PM PST 24
Finished Feb 07 12:35:39 PM PST 24
Peak memory 214912 kb
Host smart-6608a0cc-0dba-4ef7-9de4-9793fe69215d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355256857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1355256857
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.253646952
Short name T373
Test name
Test status
Simulation time 124782609 ps
CPU time 3.53 seconds
Started Feb 07 12:35:32 PM PST 24
Finished Feb 07 12:35:43 PM PST 24
Peak memory 216068 kb
Host smart-b1ad748f-d2d8-4547-bc17-65d6a90423e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253646952 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.253646952
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1294272409
Short name T361
Test name
Test status
Simulation time 19959499 ps
CPU time 1.4 seconds
Started Feb 07 12:35:27 PM PST 24
Finished Feb 07 12:35:39 PM PST 24
Peak memory 214684 kb
Host smart-3a74f14f-c70f-4842-b59c-f0207bc231b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294272409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1294272409
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3880576219
Short name T322
Test name
Test status
Simulation time 110595317 ps
CPU time 0.68 seconds
Started Feb 07 12:35:25 PM PST 24
Finished Feb 07 12:35:37 PM PST 24
Peak memory 202748 kb
Host smart-f1d491dd-03de-423a-a729-33a4573a17d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880576219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3880576219
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1507207723
Short name T362
Test name
Test status
Simulation time 54786942 ps
CPU time 1.81 seconds
Started Feb 07 12:35:24 PM PST 24
Finished Feb 07 12:35:28 PM PST 24
Peak memory 206584 kb
Host smart-3faf3c9a-a5c1-4cd7-96db-7c59a2aab4b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507207723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1507207723
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3750815688
Short name T73
Test name
Test status
Simulation time 54944623 ps
CPU time 3.77 seconds
Started Feb 07 12:35:19 PM PST 24
Finished Feb 07 12:35:24 PM PST 24
Peak memory 214924 kb
Host smart-0d83b803-228c-46aa-835a-a2b623e12c14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750815688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3750815688
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2472304240
Short name T235
Test name
Test status
Simulation time 1171061410 ps
CPU time 17.66 seconds
Started Feb 07 12:35:36 PM PST 24
Finished Feb 07 12:36:01 PM PST 24
Peak memory 215092 kb
Host smart-a30b69f2-8bf2-4b8b-94c1-561049c045eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472304240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2472304240
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3305856383
Short name T343
Test name
Test status
Simulation time 1667101947 ps
CPU time 22.54 seconds
Started Feb 07 12:35:00 PM PST 24
Finished Feb 07 12:35:27 PM PST 24
Peak memory 214620 kb
Host smart-26158a82-8188-4fa7-94ff-d83ffd8fba03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305856383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3305856383
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2586792833
Short name T370
Test name
Test status
Simulation time 1284835608 ps
CPU time 27.06 seconds
Started Feb 07 12:34:57 PM PST 24
Finished Feb 07 12:35:26 PM PST 24
Peak memory 206584 kb
Host smart-cc60ef20-31c0-4093-a49c-3a2d20f74f4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586792833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2586792833
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2391849710
Short name T135
Test name
Test status
Simulation time 26155063 ps
CPU time 2.53 seconds
Started Feb 07 12:34:51 PM PST 24
Finished Feb 07 12:34:55 PM PST 24
Peak memory 217228 kb
Host smart-651502fa-17cd-4b19-bb76-42b107e35653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391849710 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2391849710
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1688523739
Short name T384
Test name
Test status
Simulation time 258391138 ps
CPU time 1.9 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:05 PM PST 24
Peak memory 214828 kb
Host smart-fe87f47c-ae02-4d06-b9f2-c2da26085af1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688523739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
688523739
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1736959568
Short name T344
Test name
Test status
Simulation time 15292339 ps
CPU time 0.68 seconds
Started Feb 07 12:35:10 PM PST 24
Finished Feb 07 12:35:17 PM PST 24
Peak memory 202480 kb
Host smart-8b8999a3-49e3-40f9-9c53-4323bda8d4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736959568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
736959568
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2459914612
Short name T354
Test name
Test status
Simulation time 35605583 ps
CPU time 1.53 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:04 PM PST 24
Peak memory 214840 kb
Host smart-14d5bf2d-6dae-4c3b-a9d4-bac00db8f71f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459914612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2459914612
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3619373166
Short name T417
Test name
Test status
Simulation time 11958424 ps
CPU time 0.63 seconds
Started Feb 07 12:34:56 PM PST 24
Finished Feb 07 12:34:59 PM PST 24
Peak memory 202388 kb
Host smart-7489cb4a-547c-467c-a6ed-9cc77c02aebc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619373166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3619373166
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3841726812
Short name T385
Test name
Test status
Simulation time 117331917 ps
CPU time 3.07 seconds
Started Feb 07 12:35:06 PM PST 24
Finished Feb 07 12:35:13 PM PST 24
Peak memory 206712 kb
Host smart-fc2fd970-9153-436c-8933-83f697bfe517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841726812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3841726812
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1175385131
Short name T70
Test name
Test status
Simulation time 279282392 ps
CPU time 2.53 seconds
Started Feb 07 12:35:01 PM PST 24
Finished Feb 07 12:35:09 PM PST 24
Peak memory 214960 kb
Host smart-b122be5b-8b20-4dd4-9cbc-cfd97a569f95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175385131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
175385131
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.842214038
Short name T374
Test name
Test status
Simulation time 34416460 ps
CPU time 0.75 seconds
Started Feb 07 12:35:27 PM PST 24
Finished Feb 07 12:35:37 PM PST 24
Peak memory 202500 kb
Host smart-4b1edaf3-fc48-4bf0-8f21-ec9058c12a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842214038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.842214038
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3139071827
Short name T392
Test name
Test status
Simulation time 14479132 ps
CPU time 0.74 seconds
Started Feb 07 12:35:25 PM PST 24
Finished Feb 07 12:35:28 PM PST 24
Peak memory 202444 kb
Host smart-5e6b38dd-4417-49b3-b482-1d6ee0a4c0de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139071827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3139071827
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.257817254
Short name T401
Test name
Test status
Simulation time 49406972 ps
CPU time 0.77 seconds
Started Feb 07 12:35:26 PM PST 24
Finished Feb 07 12:35:33 PM PST 24
Peak memory 202492 kb
Host smart-9dce099c-2bde-434c-bd8e-fe17d0e0ba8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257817254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.257817254
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.575448550
Short name T398
Test name
Test status
Simulation time 65354605 ps
CPU time 0.75 seconds
Started Feb 07 12:35:32 PM PST 24
Finished Feb 07 12:35:44 PM PST 24
Peak memory 202836 kb
Host smart-da78ab43-35a0-4998-a706-28d97377cd45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575448550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.575448550
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3932759727
Short name T379
Test name
Test status
Simulation time 46670765 ps
CPU time 0.77 seconds
Started Feb 07 12:35:23 PM PST 24
Finished Feb 07 12:35:26 PM PST 24
Peak memory 202464 kb
Host smart-aa41b4e8-973a-4b5e-84fd-f8c4def8cf9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932759727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3932759727
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1078652606
Short name T394
Test name
Test status
Simulation time 11026378 ps
CPU time 0.74 seconds
Started Feb 07 12:35:17 PM PST 24
Finished Feb 07 12:35:21 PM PST 24
Peak memory 202460 kb
Host smart-0ff2dc34-25c8-4042-826e-a09a1a96c183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078652606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1078652606
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1130647308
Short name T353
Test name
Test status
Simulation time 13478505 ps
CPU time 0.78 seconds
Started Feb 07 12:35:19 PM PST 24
Finished Feb 07 12:35:22 PM PST 24
Peak memory 202492 kb
Host smart-2776d72f-af18-4a5c-9b48-e97cd8007f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130647308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1130647308
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3107751040
Short name T314
Test name
Test status
Simulation time 14545357 ps
CPU time 0.73 seconds
Started Feb 07 12:35:19 PM PST 24
Finished Feb 07 12:35:21 PM PST 24
Peak memory 202488 kb
Host smart-75422e81-cacb-45e9-983d-f04a73c3f82f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107751040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3107751040
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2502272708
Short name T93
Test name
Test status
Simulation time 27222253 ps
CPU time 0.75 seconds
Started Feb 07 12:35:18 PM PST 24
Finished Feb 07 12:35:21 PM PST 24
Peak memory 202756 kb
Host smart-0b98b05a-882b-48a0-8e0e-eab1b4490822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502272708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2502272708
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2138798959
Short name T326
Test name
Test status
Simulation time 21252628 ps
CPU time 0.69 seconds
Started Feb 07 12:35:25 PM PST 24
Finished Feb 07 12:35:33 PM PST 24
Peak memory 202796 kb
Host smart-dad572fd-116e-4e8d-b1ca-de8e54cb90ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138798959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2138798959
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2437866640
Short name T372
Test name
Test status
Simulation time 407720887 ps
CPU time 9.31 seconds
Started Feb 07 12:35:02 PM PST 24
Finished Feb 07 12:35:16 PM PST 24
Peak memory 206544 kb
Host smart-c969f27e-369b-4100-bf6f-54886f1042a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437866640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2437866640
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1256155292
Short name T95
Test name
Test status
Simulation time 21918690104 ps
CPU time 36.05 seconds
Started Feb 07 12:35:06 PM PST 24
Finished Feb 07 12:35:46 PM PST 24
Peak memory 206712 kb
Host smart-adfc49cc-c4c1-4910-9f0a-a0b883403dc2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256155292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1256155292
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1102951813
Short name T112
Test name
Test status
Simulation time 88611845 ps
CPU time 0.92 seconds
Started Feb 07 12:34:48 PM PST 24
Finished Feb 07 12:34:50 PM PST 24
Peak memory 206244 kb
Host smart-3ccbe8b6-6a37-4e70-a26b-1494fe7d238d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102951813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1102951813
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3183973954
Short name T402
Test name
Test status
Simulation time 43114484 ps
CPU time 2.39 seconds
Started Feb 07 12:35:00 PM PST 24
Finished Feb 07 12:35:07 PM PST 24
Peak memory 215872 kb
Host smart-baa2f9c2-7a5e-4cbf-9c53-aab05f6b03e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183973954 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3183973954
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2237599048
Short name T117
Test name
Test status
Simulation time 217697164 ps
CPU time 2.73 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:05 PM PST 24
Peak memory 214732 kb
Host smart-967b0c0b-6939-4d67-b567-4288accd1048
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237599048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
237599048
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2150243445
Short name T405
Test name
Test status
Simulation time 15331309 ps
CPU time 0.72 seconds
Started Feb 07 12:34:49 PM PST 24
Finished Feb 07 12:34:51 PM PST 24
Peak memory 202504 kb
Host smart-5bb89142-8f44-4ec1-a6e1-55690f591f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150243445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
150243445
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1800678263
Short name T411
Test name
Test status
Simulation time 54226738 ps
CPU time 1.69 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:04 PM PST 24
Peak memory 214752 kb
Host smart-40c1180e-6c40-4a83-84d8-e9b292a84a27
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800678263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1800678263
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.925776992
Short name T105
Test name
Test status
Simulation time 17401693 ps
CPU time 0.64 seconds
Started Feb 07 12:35:01 PM PST 24
Finished Feb 07 12:35:07 PM PST 24
Peak memory 202296 kb
Host smart-b56c4427-ce1f-45b8-82dd-3e9b0bb95b05
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925776992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.925776992
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3354288380
Short name T324
Test name
Test status
Simulation time 64845494 ps
CPU time 1.96 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:05 PM PST 24
Peak memory 206544 kb
Host smart-c1a13307-5f39-4971-90ab-ef832fa922ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354288380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3354288380
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1710217080
Short name T371
Test name
Test status
Simulation time 194406588 ps
CPU time 4.8 seconds
Started Feb 07 12:35:07 PM PST 24
Finished Feb 07 12:35:16 PM PST 24
Peak memory 215012 kb
Host smart-4505304d-dd74-44ed-816f-23e5248a805f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710217080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
710217080
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4160162699
Short name T331
Test name
Test status
Simulation time 24321774 ps
CPU time 0.72 seconds
Started Feb 07 12:35:26 PM PST 24
Finished Feb 07 12:35:33 PM PST 24
Peak memory 202796 kb
Host smart-f1335ec6-2af4-4ebb-bffd-5bbcd64c57f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160162699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4160162699
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1391179261
Short name T351
Test name
Test status
Simulation time 18227121 ps
CPU time 0.76 seconds
Started Feb 07 12:35:24 PM PST 24
Finished Feb 07 12:35:27 PM PST 24
Peak memory 202496 kb
Host smart-c6f92957-7b84-4182-934d-42e6c213ea20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391179261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1391179261
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3409714799
Short name T97
Test name
Test status
Simulation time 51019663 ps
CPU time 0.7 seconds
Started Feb 07 12:35:24 PM PST 24
Finished Feb 07 12:35:26 PM PST 24
Peak memory 202424 kb
Host smart-ae3072cf-2ebb-4447-88ee-cb5e6bc015c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409714799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3409714799
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.605713998
Short name T366
Test name
Test status
Simulation time 13013424 ps
CPU time 0.71 seconds
Started Feb 07 12:35:27 PM PST 24
Finished Feb 07 12:35:38 PM PST 24
Peak memory 202280 kb
Host smart-008aef5a-e730-4a9d-8e13-1421bd97495c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605713998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.605713998
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3202111345
Short name T323
Test name
Test status
Simulation time 55023733 ps
CPU time 0.75 seconds
Started Feb 07 12:35:25 PM PST 24
Finished Feb 07 12:35:33 PM PST 24
Peak memory 202492 kb
Host smart-6414f356-8eb6-4984-80e0-bf81c46467e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202111345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3202111345
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3012094684
Short name T107
Test name
Test status
Simulation time 16020678 ps
CPU time 0.75 seconds
Started Feb 07 12:35:25 PM PST 24
Finished Feb 07 12:35:28 PM PST 24
Peak memory 202436 kb
Host smart-3ac425a7-80fd-4535-a968-973694d18c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012094684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3012094684
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3830161001
Short name T329
Test name
Test status
Simulation time 13507124 ps
CPU time 0.73 seconds
Started Feb 07 12:35:27 PM PST 24
Finished Feb 07 12:35:37 PM PST 24
Peak memory 202520 kb
Host smart-66e19cb2-4031-427a-a2d8-7d0911542433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830161001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3830161001
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4112775109
Short name T380
Test name
Test status
Simulation time 14746003 ps
CPU time 0.71 seconds
Started Feb 07 12:35:24 PM PST 24
Finished Feb 07 12:35:28 PM PST 24
Peak memory 202440 kb
Host smart-9277f073-e626-4610-a28a-a4b04bf865d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112775109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4112775109
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.155524327
Short name T386
Test name
Test status
Simulation time 68039883 ps
CPU time 0.74 seconds
Started Feb 07 12:35:47 PM PST 24
Finished Feb 07 12:35:51 PM PST 24
Peak memory 202808 kb
Host smart-5fc1e20f-29d4-4d3d-b7e1-346bfa1d216a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155524327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.155524327
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3379127873
Short name T333
Test name
Test status
Simulation time 14561446 ps
CPU time 0.69 seconds
Started Feb 07 12:35:24 PM PST 24
Finished Feb 07 12:35:27 PM PST 24
Peak memory 202512 kb
Host smart-8810f471-f355-414f-a621-2bcaa4fe568d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379127873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3379127873
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1352326646
Short name T378
Test name
Test status
Simulation time 2635619115 ps
CPU time 16.38 seconds
Started Feb 07 12:35:00 PM PST 24
Finished Feb 07 12:35:21 PM PST 24
Peak memory 214756 kb
Host smart-18ca4af9-4191-46b8-9750-6cd11fb5f52c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352326646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1352326646
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2114822983
Short name T111
Test name
Test status
Simulation time 5188041882 ps
CPU time 13.92 seconds
Started Feb 07 12:35:02 PM PST 24
Finished Feb 07 12:35:21 PM PST 24
Peak memory 206424 kb
Host smart-06e6906e-7b48-46ec-b902-44771e4f2540
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114822983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2114822983
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3817846165
Short name T136
Test name
Test status
Simulation time 188984836 ps
CPU time 1.55 seconds
Started Feb 07 12:34:54 PM PST 24
Finished Feb 07 12:34:57 PM PST 24
Peak memory 214820 kb
Host smart-8af57ffd-8032-4041-9dd9-252c36a0740d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817846165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3817846165
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1753809955
Short name T338
Test name
Test status
Simulation time 52029525 ps
CPU time 1.16 seconds
Started Feb 07 12:34:58 PM PST 24
Finished Feb 07 12:35:03 PM PST 24
Peak memory 214852 kb
Host smart-61c9f718-056e-48ef-a4b5-75320861995f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753809955 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1753809955
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3305465197
Short name T410
Test name
Test status
Simulation time 47877099 ps
CPU time 0.74 seconds
Started Feb 07 12:34:57 PM PST 24
Finished Feb 07 12:34:59 PM PST 24
Peak memory 202496 kb
Host smart-fc91f76b-8f61-487a-ada9-4c12687ff88c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305465197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
305465197
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1324195503
Short name T375
Test name
Test status
Simulation time 571211102 ps
CPU time 1.41 seconds
Started Feb 07 12:35:08 PM PST 24
Finished Feb 07 12:35:14 PM PST 24
Peak memory 214804 kb
Host smart-767c2418-8838-4904-b4e4-ef29156043d0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324195503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1324195503
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.354334362
Short name T100
Test name
Test status
Simulation time 151055853 ps
CPU time 0.62 seconds
Started Feb 07 12:34:56 PM PST 24
Finished Feb 07 12:34:58 PM PST 24
Peak memory 202796 kb
Host smart-170f7dc7-2cb1-4462-820f-c138725267cb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354334362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.354334362
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3720031536
Short name T342
Test name
Test status
Simulation time 134086387 ps
CPU time 1.87 seconds
Started Feb 07 12:35:00 PM PST 24
Finished Feb 07 12:35:07 PM PST 24
Peak memory 206572 kb
Host smart-4bc35fdb-be90-473f-883a-f8c579bbb790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720031536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3720031536
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.560619267
Short name T72
Test name
Test status
Simulation time 47232757 ps
CPU time 3.8 seconds
Started Feb 07 12:34:51 PM PST 24
Finished Feb 07 12:34:56 PM PST 24
Peak memory 214960 kb
Host smart-954d843d-a9c4-4104-8840-545ef6e2d925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560619267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.560619267
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1098524542
Short name T236
Test name
Test status
Simulation time 1023838509 ps
CPU time 17.28 seconds
Started Feb 07 12:34:56 PM PST 24
Finished Feb 07 12:35:15 PM PST 24
Peak memory 214792 kb
Host smart-2affaa04-f8fc-4fdb-bf6c-52be49c2c850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098524542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1098524542
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1997146277
Short name T327
Test name
Test status
Simulation time 46173476 ps
CPU time 0.73 seconds
Started Feb 07 12:35:21 PM PST 24
Finished Feb 07 12:35:23 PM PST 24
Peak memory 202464 kb
Host smart-9326471a-5f5d-452a-a5ac-4d122886efe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997146277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1997146277
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2055213496
Short name T96
Test name
Test status
Simulation time 25769436 ps
CPU time 0.75 seconds
Started Feb 07 12:35:44 PM PST 24
Finished Feb 07 12:35:50 PM PST 24
Peak memory 202484 kb
Host smart-880e47a2-117a-4bcb-97cd-73d7d5be4c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055213496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2055213496
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4008984802
Short name T415
Test name
Test status
Simulation time 149992521 ps
CPU time 0.69 seconds
Started Feb 07 12:35:28 PM PST 24
Finished Feb 07 12:35:39 PM PST 24
Peak memory 202532 kb
Host smart-df59db18-7a3c-4810-9e11-684208d31ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008984802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4008984802
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2953693104
Short name T349
Test name
Test status
Simulation time 13399383 ps
CPU time 0.73 seconds
Started Feb 07 12:35:19 PM PST 24
Finished Feb 07 12:35:21 PM PST 24
Peak memory 202496 kb
Host smart-1b022b8d-dd4c-4103-852e-ff0360a7e6a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953693104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2953693104
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1585179282
Short name T318
Test name
Test status
Simulation time 21290601 ps
CPU time 0.76 seconds
Started Feb 07 12:35:54 PM PST 24
Finished Feb 07 12:35:57 PM PST 24
Peak memory 202484 kb
Host smart-d826e4fa-b1fa-48ce-8330-7e2ca846a4b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585179282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1585179282
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3939345395
Short name T412
Test name
Test status
Simulation time 88814324 ps
CPU time 0.73 seconds
Started Feb 07 12:35:37 PM PST 24
Finished Feb 07 12:35:44 PM PST 24
Peak memory 202472 kb
Host smart-14e86df8-0181-4043-945e-61addd3418c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939345395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3939345395
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1580342347
Short name T317
Test name
Test status
Simulation time 33890872 ps
CPU time 0.78 seconds
Started Feb 07 12:35:41 PM PST 24
Finished Feb 07 12:35:48 PM PST 24
Peak memory 202480 kb
Host smart-ac4530d2-915a-4c01-b927-a263fbf6e9e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580342347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1580342347
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1165297871
Short name T368
Test name
Test status
Simulation time 51577434 ps
CPU time 0.79 seconds
Started Feb 07 12:35:23 PM PST 24
Finished Feb 07 12:35:26 PM PST 24
Peak memory 202780 kb
Host smart-9968713b-1ce8-4ad6-b3fe-5c3b0f8991c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165297871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1165297871
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1442631199
Short name T347
Test name
Test status
Simulation time 39533052 ps
CPU time 0.68 seconds
Started Feb 07 12:35:25 PM PST 24
Finished Feb 07 12:35:28 PM PST 24
Peak memory 202540 kb
Host smart-8d221547-75ef-4ffe-94bd-e89f91ca03ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442631199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1442631199
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1767567057
Short name T328
Test name
Test status
Simulation time 19204614 ps
CPU time 0.7 seconds
Started Feb 07 12:35:27 PM PST 24
Finished Feb 07 12:35:37 PM PST 24
Peak memory 202484 kb
Host smart-94a1eb07-ec6b-4831-b679-7621705c33bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767567057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1767567057
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3975733398
Short name T420
Test name
Test status
Simulation time 14942286 ps
CPU time 1.22 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:04 PM PST 24
Peak memory 214916 kb
Host smart-0c8d509a-2313-4792-aedb-ad66f5598e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975733398 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3975733398
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2045189790
Short name T332
Test name
Test status
Simulation time 198034043 ps
CPU time 2.86 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:06 PM PST 24
Peak memory 206564 kb
Host smart-88c496d5-3521-420d-965e-dce530f8f50f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045189790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
045189790
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3088950367
Short name T309
Test name
Test status
Simulation time 15155815 ps
CPU time 0.73 seconds
Started Feb 07 12:34:59 PM PST 24
Finished Feb 07 12:35:04 PM PST 24
Peak memory 202412 kb
Host smart-fac62cb7-3644-4be6-8a26-c7441353a10f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088950367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
088950367
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.893886464
Short name T311
Test name
Test status
Simulation time 59241628 ps
CPU time 1.93 seconds
Started Feb 07 12:35:00 PM PST 24
Finished Feb 07 12:35:08 PM PST 24
Peak memory 206132 kb
Host smart-06dda21a-4964-4780-8264-72f0d2478edd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893886464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.893886464
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.31083725
Short name T86
Test name
Test status
Simulation time 56128827 ps
CPU time 1.57 seconds
Started Feb 07 12:34:58 PM PST 24
Finished Feb 07 12:35:02 PM PST 24
Peak memory 215076 kb
Host smart-f9e715a6-ccdf-483f-a02f-d7540f988e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31083725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.31083725
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.509267132
Short name T406
Test name
Test status
Simulation time 1145663678 ps
CPU time 7.55 seconds
Started Feb 07 12:35:01 PM PST 24
Finished Feb 07 12:35:14 PM PST 24
Peak memory 214648 kb
Host smart-63ba05ef-ede8-4443-8233-4e4c0d0b72df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509267132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.509267132
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3128958543
Short name T334
Test name
Test status
Simulation time 30998932 ps
CPU time 2.71 seconds
Started Feb 07 12:34:52 PM PST 24
Finished Feb 07 12:34:56 PM PST 24
Peak memory 215964 kb
Host smart-6d763217-4e3c-4390-b9cf-9fa22281fcb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128958543 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3128958543
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2000990260
Short name T114
Test name
Test status
Simulation time 421479860 ps
CPU time 2.69 seconds
Started Feb 07 12:34:58 PM PST 24
Finished Feb 07 12:35:05 PM PST 24
Peak memory 214700 kb
Host smart-8c58fcfb-d82f-4604-9daf-38674f52915b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000990260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
000990260
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2955862503
Short name T319
Test name
Test status
Simulation time 41460253 ps
CPU time 0.67 seconds
Started Feb 07 12:35:00 PM PST 24
Finished Feb 07 12:35:06 PM PST 24
Peak memory 202436 kb
Host smart-a4b484e7-1088-49dc-afee-a422076a7441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955862503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
955862503
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3911904657
Short name T399
Test name
Test status
Simulation time 215907536 ps
CPU time 1.65 seconds
Started Feb 07 12:34:55 PM PST 24
Finished Feb 07 12:34:58 PM PST 24
Peak memory 206284 kb
Host smart-b322f654-f469-46df-87a3-dcc1c72c713e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911904657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3911904657
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3291119297
Short name T408
Test name
Test status
Simulation time 1238959035 ps
CPU time 4.06 seconds
Started Feb 07 12:35:02 PM PST 24
Finished Feb 07 12:35:11 PM PST 24
Peak memory 214972 kb
Host smart-d454975c-51ff-43d1-a481-ad9952dbe777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291119297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
291119297
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.885286698
Short name T239
Test name
Test status
Simulation time 3290715293 ps
CPU time 20.64 seconds
Started Feb 07 12:34:57 PM PST 24
Finished Feb 07 12:35:19 PM PST 24
Peak memory 215928 kb
Host smart-56af035c-68f1-4868-b486-5f32b7db136c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885286698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.885286698
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3263807985
Short name T369
Test name
Test status
Simulation time 46906384 ps
CPU time 2.5 seconds
Started Feb 07 12:35:08 PM PST 24
Finished Feb 07 12:35:16 PM PST 24
Peak memory 216316 kb
Host smart-c7ca58e2-4bf5-42b6-b91a-0ec4788b80f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263807985 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3263807985
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.53077407
Short name T98
Test name
Test status
Simulation time 73675253 ps
CPU time 2.07 seconds
Started Feb 07 12:35:08 PM PST 24
Finished Feb 07 12:35:16 PM PST 24
Peak memory 214868 kb
Host smart-e432705e-b319-4f4e-984f-a6d3a1d00ffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53077407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.53077407
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3245873043
Short name T376
Test name
Test status
Simulation time 56762910 ps
CPU time 0.72 seconds
Started Feb 07 12:35:14 PM PST 24
Finished Feb 07 12:35:19 PM PST 24
Peak memory 202488 kb
Host smart-78a884d0-5567-4b23-93a0-83d905d50d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245873043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
245873043
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1621961035
Short name T126
Test name
Test status
Simulation time 45078325 ps
CPU time 2.72 seconds
Started Feb 07 12:35:05 PM PST 24
Finished Feb 07 12:35:12 PM PST 24
Peak memory 206636 kb
Host smart-945a6faf-3910-41b0-978f-c646cd4e2146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621961035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1621961035
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2070467302
Short name T390
Test name
Test status
Simulation time 254619415 ps
CPU time 3.35 seconds
Started Feb 07 12:35:02 PM PST 24
Finished Feb 07 12:35:10 PM PST 24
Peak memory 214884 kb
Host smart-d1ccab1f-f272-4aba-86c7-401b24d0182a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070467302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
070467302
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.480183713
Short name T90
Test name
Test status
Simulation time 312354347 ps
CPU time 18.93 seconds
Started Feb 07 12:35:19 PM PST 24
Finished Feb 07 12:35:40 PM PST 24
Peak memory 214776 kb
Host smart-75adcca2-cdcc-433b-b329-28fa755ead4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480183713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.480183713
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2770412748
Short name T74
Test name
Test status
Simulation time 61055260 ps
CPU time 1.25 seconds
Started Feb 07 12:35:05 PM PST 24
Finished Feb 07 12:35:10 PM PST 24
Peak memory 214884 kb
Host smart-c96ca69b-339f-4d3e-92c9-86c22b95446f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770412748 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2770412748
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3530656528
Short name T116
Test name
Test status
Simulation time 266137411 ps
CPU time 2.6 seconds
Started Feb 07 12:35:14 PM PST 24
Finished Feb 07 12:35:21 PM PST 24
Peak memory 214884 kb
Host smart-a5973f64-b66f-42b2-87fb-bbb93945a198
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530656528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
530656528
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1073397941
Short name T403
Test name
Test status
Simulation time 14091555 ps
CPU time 0.69 seconds
Started Feb 07 12:35:05 PM PST 24
Finished Feb 07 12:35:09 PM PST 24
Peak memory 202472 kb
Host smart-83551b4b-7773-4a67-8b84-01d9eeb9a11b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073397941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
073397941
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2623261441
Short name T396
Test name
Test status
Simulation time 388361169 ps
CPU time 3.76 seconds
Started Feb 07 12:35:14 PM PST 24
Finished Feb 07 12:35:22 PM PST 24
Peak memory 206700 kb
Host smart-06516ba4-94e8-41c0-82f8-a4c03aed7f20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623261441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2623261441
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2902547483
Short name T416
Test name
Test status
Simulation time 79574434 ps
CPU time 1.62 seconds
Started Feb 07 12:35:04 PM PST 24
Finished Feb 07 12:35:10 PM PST 24
Peak memory 215024 kb
Host smart-e9d6a1ca-fbca-4328-8b2c-d061c20590a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902547483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
902547483
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2342174758
Short name T88
Test name
Test status
Simulation time 1147996376 ps
CPU time 24.01 seconds
Started Feb 07 12:35:13 PM PST 24
Finished Feb 07 12:35:41 PM PST 24
Peak memory 214872 kb
Host smart-9eadfb5b-70f9-4bb0-81d9-282e20493cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342174758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2342174758
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1371373173
Short name T393
Test name
Test status
Simulation time 62752613 ps
CPU time 1.44 seconds
Started Feb 07 12:35:07 PM PST 24
Finished Feb 07 12:35:13 PM PST 24
Peak memory 214932 kb
Host smart-594fc33e-6fc6-4023-8a04-25eb698fafb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371373173 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1371373173
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3781885855
Short name T127
Test name
Test status
Simulation time 21325328 ps
CPU time 1.31 seconds
Started Feb 07 12:35:17 PM PST 24
Finished Feb 07 12:35:21 PM PST 24
Peak memory 214876 kb
Host smart-528f6df8-b200-452e-af29-f6c11694c0bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781885855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
781885855
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.601957446
Short name T313
Test name
Test status
Simulation time 11586027 ps
CPU time 0.71 seconds
Started Feb 07 12:35:07 PM PST 24
Finished Feb 07 12:35:13 PM PST 24
Peak memory 202504 kb
Host smart-41119d28-6aab-4258-a6d7-331ff4653b22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601957446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.601957446
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1064927888
Short name T336
Test name
Test status
Simulation time 151599463 ps
CPU time 3.92 seconds
Started Feb 07 12:35:10 PM PST 24
Finished Feb 07 12:35:20 PM PST 24
Peak memory 214860 kb
Host smart-63ac1277-bcde-47a5-9179-a89666ffb5ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064927888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1064927888
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2399927883
Short name T87
Test name
Test status
Simulation time 111524443 ps
CPU time 3.81 seconds
Started Feb 07 12:35:04 PM PST 24
Finished Feb 07 12:35:12 PM PST 24
Peak memory 214908 kb
Host smart-13319dbe-ecfc-493a-8595-b226c1765ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399927883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
399927883
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3186791230
Short name T138
Test name
Test status
Simulation time 676300611 ps
CPU time 15 seconds
Started Feb 07 12:35:11 PM PST 24
Finished Feb 07 12:35:32 PM PST 24
Peak memory 214804 kb
Host smart-34ae52a6-a58c-4117-85cf-857d875a2858
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186791230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3186791230
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.588413149
Short name T854
Test name
Test status
Simulation time 55791433 ps
CPU time 0.69 seconds
Started Feb 07 01:42:19 PM PST 24
Finished Feb 07 01:42:20 PM PST 24
Peak memory 204448 kb
Host smart-9d21c275-1f23-4eef-ac0a-60e3b25c1d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588413149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.588413149
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3435661824
Short name T191
Test name
Test status
Simulation time 2469973132 ps
CPU time 6.26 seconds
Started Feb 07 01:42:18 PM PST 24
Finished Feb 07 01:42:25 PM PST 24
Peak memory 233684 kb
Host smart-fe70b821-df38-4d64-b598-d222144bbaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435661824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3435661824
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4074401627
Short name T980
Test name
Test status
Simulation time 17996567 ps
CPU time 0.76 seconds
Started Feb 07 01:42:20 PM PST 24
Finished Feb 07 01:42:21 PM PST 24
Peak memory 205172 kb
Host smart-140b21a5-acf8-4505-a8c1-2ca329e34d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074401627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4074401627
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3316401562
Short name T196
Test name
Test status
Simulation time 31792337966 ps
CPU time 192.49 seconds
Started Feb 07 01:42:19 PM PST 24
Finished Feb 07 01:45:32 PM PST 24
Peak memory 265444 kb
Host smart-691a987c-2067-4236-8649-7b7c74ec87cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316401562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3316401562
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3240381070
Short name T738
Test name
Test status
Simulation time 23028360555 ps
CPU time 25.94 seconds
Started Feb 07 01:42:19 PM PST 24
Finished Feb 07 01:42:45 PM PST 24
Peak memory 238300 kb
Host smart-02febc48-6a3b-452e-b594-24296a8a06da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240381070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3240381070
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1455830233
Short name T905
Test name
Test status
Simulation time 1846438343 ps
CPU time 14.73 seconds
Started Feb 07 01:42:19 PM PST 24
Finished Feb 07 01:42:34 PM PST 24
Peak memory 239716 kb
Host smart-9faa152a-a189-49a8-bd31-74feb1649190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455830233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1455830233
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4234049084
Short name T763
Test name
Test status
Simulation time 7236707955 ps
CPU time 5.03 seconds
Started Feb 07 01:42:17 PM PST 24
Finished Feb 07 01:42:22 PM PST 24
Peak memory 234024 kb
Host smart-54adca96-8670-4e4a-95e5-4c40ed3e6146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234049084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4234049084
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2419552824
Short name T892
Test name
Test status
Simulation time 10355901283 ps
CPU time 27.89 seconds
Started Feb 07 01:42:19 PM PST 24
Finished Feb 07 01:42:47 PM PST 24
Peak memory 233108 kb
Host smart-eed395e1-3f9b-483f-ba54-b6be5c4e51b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419552824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2419552824
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2653317487
Short name T1025
Test name
Test status
Simulation time 5562570912 ps
CPU time 21.11 seconds
Started Feb 07 01:42:17 PM PST 24
Finished Feb 07 01:42:39 PM PST 24
Peak memory 232124 kb
Host smart-bd9e3d10-dba2-4856-928a-4d3e9acd53ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653317487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2653317487
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.130471369
Short name T128
Test name
Test status
Simulation time 611896300 ps
CPU time 4.45 seconds
Started Feb 07 01:42:20 PM PST 24
Finished Feb 07 01:42:25 PM PST 24
Peak memory 218960 kb
Host smart-d4e9988f-5e8d-4120-948a-00c8f8b67c2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=130471369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.130471369
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1768162661
Short name T52
Test name
Test status
Simulation time 35575144 ps
CPU time 0.94 seconds
Started Feb 07 01:42:13 PM PST 24
Finished Feb 07 01:42:15 PM PST 24
Peak memory 234856 kb
Host smart-a050edb8-8a32-43dd-af11-3f28783d3d5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768162661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1768162661
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3958589467
Short name T273
Test name
Test status
Simulation time 3067658539 ps
CPU time 39.46 seconds
Started Feb 07 01:42:17 PM PST 24
Finished Feb 07 01:42:57 PM PST 24
Peak memory 216660 kb
Host smart-31c3b5f4-4180-4180-a284-cbe35a692f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958589467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3958589467
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3061671959
Short name T288
Test name
Test status
Simulation time 21249712 ps
CPU time 1.26 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:42:17 PM PST 24
Peak memory 208496 kb
Host smart-d1615ad0-69ab-4c0e-a639-b6eef0703e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061671959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3061671959
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3569646914
Short name T304
Test name
Test status
Simulation time 283467582 ps
CPU time 1.02 seconds
Started Feb 07 01:42:16 PM PST 24
Finished Feb 07 01:42:17 PM PST 24
Peak memory 205492 kb
Host smart-dd3f3d0c-2276-4ec8-96da-4561502f490d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569646914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3569646914
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4218433530
Short name T1051
Test name
Test status
Simulation time 100238942378 ps
CPU time 18.24 seconds
Started Feb 07 01:42:13 PM PST 24
Finished Feb 07 01:42:32 PM PST 24
Peak memory 234596 kb
Host smart-d1847aeb-c857-4f1d-8f48-11c3abc11829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218433530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4218433530
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.957888226
Short name T1085
Test name
Test status
Simulation time 38897849 ps
CPU time 0.7 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:42:26 PM PST 24
Peak memory 205356 kb
Host smart-ff587b12-df5e-4ecf-b000-49d83d2a92c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957888226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.957888226
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3299501748
Short name T194
Test name
Test status
Simulation time 1682714066 ps
CPU time 3.71 seconds
Started Feb 07 01:42:29 PM PST 24
Finished Feb 07 01:42:33 PM PST 24
Peak memory 233568 kb
Host smart-67851391-5f8b-442f-bb93-1e9e5bb359ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299501748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3299501748
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.480767087
Short name T670
Test name
Test status
Simulation time 62185414 ps
CPU time 0.74 seconds
Started Feb 07 01:42:22 PM PST 24
Finished Feb 07 01:42:23 PM PST 24
Peak memory 205204 kb
Host smart-98945bac-04e7-4d28-ba44-f2a0e776256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480767087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.480767087
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1025610341
Short name T628
Test name
Test status
Simulation time 158264795 ps
CPU time 3.76 seconds
Started Feb 07 01:42:25 PM PST 24
Finished Feb 07 01:42:30 PM PST 24
Peak memory 234836 kb
Host smart-c9ff9a02-d67c-422f-a51e-795690d01bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025610341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1025610341
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3278459130
Short name T249
Test name
Test status
Simulation time 30909511878 ps
CPU time 197.51 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:45:43 PM PST 24
Peak memory 255172 kb
Host smart-de9c9598-0660-456b-a1a6-4e4680bbc3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278459130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3278459130
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3840465805
Short name T939
Test name
Test status
Simulation time 20997720567 ps
CPU time 101.5 seconds
Started Feb 07 01:42:26 PM PST 24
Finished Feb 07 01:44:09 PM PST 24
Peak memory 249544 kb
Host smart-5beb9fb3-5220-4133-adf1-37d421e2bda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840465805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3840465805
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1757110729
Short name T861
Test name
Test status
Simulation time 188830771 ps
CPU time 2.88 seconds
Started Feb 07 01:42:25 PM PST 24
Finished Feb 07 01:42:29 PM PST 24
Peak memory 224744 kb
Host smart-e643e919-a24f-488b-accf-7d111ff1354b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757110729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1757110729
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2850916586
Short name T476
Test name
Test status
Simulation time 16516901436 ps
CPU time 16.49 seconds
Started Feb 07 01:42:27 PM PST 24
Finished Feb 07 01:42:44 PM PST 24
Peak memory 224580 kb
Host smart-0cb8d4b3-247b-46d6-99d1-8f8f3752b538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850916586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2850916586
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1488147834
Short name T708
Test name
Test status
Simulation time 17108078 ps
CPU time 1.03 seconds
Started Feb 07 01:42:23 PM PST 24
Finished Feb 07 01:42:24 PM PST 24
Peak memory 216604 kb
Host smart-14194753-7593-4e17-8c43-f96f52e36442
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488147834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1488147834
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3445868911
Short name T171
Test name
Test status
Simulation time 7949327755 ps
CPU time 6.42 seconds
Started Feb 07 01:42:26 PM PST 24
Finished Feb 07 01:42:33 PM PST 24
Peak memory 218092 kb
Host smart-6fa4716d-0397-4298-b043-7a1b60448dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445868911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3445868911
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2536561404
Short name T695
Test name
Test status
Simulation time 33696435916 ps
CPU time 23.23 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:42:48 PM PST 24
Peak memory 235204 kb
Host smart-b456639f-a13e-4e5e-89fb-bf2a12848077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536561404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2536561404
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.1853437224
Short name T930
Test name
Test status
Simulation time 31527555 ps
CPU time 0.71 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:42:26 PM PST 24
Peak memory 216332 kb
Host smart-7089cfd1-0604-4799-bc7e-d353fd961eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853437224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.1853437224
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2922988582
Short name T579
Test name
Test status
Simulation time 4020167186 ps
CPU time 3.85 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:42:29 PM PST 24
Peak memory 220288 kb
Host smart-adfdf74c-bbcd-45b7-858c-16f95131de8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2922988582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2922988582
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.755793882
Short name T49
Test name
Test status
Simulation time 70479760 ps
CPU time 0.96 seconds
Started Feb 07 01:42:31 PM PST 24
Finished Feb 07 01:42:32 PM PST 24
Peak memory 235640 kb
Host smart-11046f73-1e23-4582-97ca-b283b44d34f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755793882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.755793882
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2120241789
Short name T671
Test name
Test status
Simulation time 129375309858 ps
CPU time 170.66 seconds
Started Feb 07 01:42:26 PM PST 24
Finished Feb 07 01:45:17 PM PST 24
Peak memory 252276 kb
Host smart-fafaab9b-d0f2-4cf1-8a44-17e3216e637b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120241789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2120241789
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3724133810
Short name T67
Test name
Test status
Simulation time 44136027930 ps
CPU time 96.27 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:44:01 PM PST 24
Peak memory 216668 kb
Host smart-9c9fd3e4-ad2e-4146-b1c2-0be1eae8a372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724133810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3724133810
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3486419354
Short name T292
Test name
Test status
Simulation time 2126458389 ps
CPU time 7.91 seconds
Started Feb 07 01:42:27 PM PST 24
Finished Feb 07 01:42:35 PM PST 24
Peak memory 216528 kb
Host smart-602cda1f-0703-4d9f-8d5c-fe7557ea13b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486419354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3486419354
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2081710558
Short name T724
Test name
Test status
Simulation time 147474917 ps
CPU time 1.45 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:42:26 PM PST 24
Peak memory 207996 kb
Host smart-712f01a4-7db3-471b-bffa-2c82797b3568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081710558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2081710558
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3640309178
Short name T1080
Test name
Test status
Simulation time 755921071 ps
CPU time 0.87 seconds
Started Feb 07 01:42:21 PM PST 24
Finished Feb 07 01:42:23 PM PST 24
Peak memory 206504 kb
Host smart-bd714d46-569a-4b13-bb52-e809ffc5647e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640309178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3640309178
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3981266113
Short name T462
Test name
Test status
Simulation time 413776050 ps
CPU time 6.29 seconds
Started Feb 07 01:42:22 PM PST 24
Finished Feb 07 01:42:29 PM PST 24
Peak memory 229972 kb
Host smart-bf7a5670-692a-49df-8f7b-d228b78b25df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981266113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3981266113
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2371481690
Short name T595
Test name
Test status
Simulation time 22753293 ps
CPU time 0.72 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:43:11 PM PST 24
Peak memory 205064 kb
Host smart-4dae1127-0a2d-4adb-9611-628a44f0e024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371481690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2371481690
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3461602168
Short name T801
Test name
Test status
Simulation time 1281493642 ps
CPU time 5.81 seconds
Started Feb 07 01:43:15 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 233008 kb
Host smart-6f0fbb21-b325-4834-9de4-e1a783365d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461602168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3461602168
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1058716270
Short name T664
Test name
Test status
Simulation time 52796841 ps
CPU time 0.77 seconds
Started Feb 07 01:43:14 PM PST 24
Finished Feb 07 01:43:15 PM PST 24
Peak memory 206188 kb
Host smart-aece9204-f5d8-426f-892a-5b13f0c8650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058716270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1058716270
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2052621765
Short name T832
Test name
Test status
Simulation time 2156308683 ps
CPU time 15.14 seconds
Started Feb 07 01:43:15 PM PST 24
Finished Feb 07 01:43:32 PM PST 24
Peak memory 242744 kb
Host smart-f3e07c75-0048-4475-be99-e357c3c0a332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052621765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2052621765
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.998316755
Short name T813
Test name
Test status
Simulation time 23218700614 ps
CPU time 177.24 seconds
Started Feb 07 01:43:08 PM PST 24
Finished Feb 07 01:46:08 PM PST 24
Peak memory 250580 kb
Host smart-70a59b37-f6f5-468b-a1d5-62347f61be15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998316755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.998316755
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2608180746
Short name T186
Test name
Test status
Simulation time 76393497164 ps
CPU time 294.6 seconds
Started Feb 07 01:43:17 PM PST 24
Finished Feb 07 01:48:13 PM PST 24
Peak memory 254628 kb
Host smart-9e559ad8-5611-4de9-a259-c240bde3ca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608180746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2608180746
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3393346851
Short name T781
Test name
Test status
Simulation time 6713757240 ps
CPU time 23.92 seconds
Started Feb 07 01:43:14 PM PST 24
Finished Feb 07 01:43:39 PM PST 24
Peak memory 234000 kb
Host smart-89bd9d09-26e8-422b-ab5d-24a3be9059b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393346851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3393346851
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.149680048
Short name T160
Test name
Test status
Simulation time 3017798768 ps
CPU time 4.39 seconds
Started Feb 07 01:43:10 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 233716 kb
Host smart-b9ec13ea-149e-459c-904d-c463bf6330f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149680048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.149680048
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3835953443
Short name T986
Test name
Test status
Simulation time 24772957060 ps
CPU time 20.35 seconds
Started Feb 07 01:43:10 PM PST 24
Finished Feb 07 01:43:32 PM PST 24
Peak memory 241220 kb
Host smart-cdd550e0-fb2f-4862-9f0b-00a2f16e4061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835953443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3835953443
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3949409575
Short name T473
Test name
Test status
Simulation time 123586087 ps
CPU time 1.09 seconds
Started Feb 07 01:43:09 PM PST 24
Finished Feb 07 01:43:12 PM PST 24
Peak memory 216644 kb
Host smart-4fe14357-a31d-496d-aadd-635958885761
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949409575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3949409575
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3576391255
Short name T198
Test name
Test status
Simulation time 9954963074 ps
CPU time 16.35 seconds
Started Feb 07 01:43:12 PM PST 24
Finished Feb 07 01:43:29 PM PST 24
Peak memory 233072 kb
Host smart-2d5cc2b0-079e-4678-a9ad-30cff2831d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576391255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3576391255
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2739651307
Short name T145
Test name
Test status
Simulation time 611994529 ps
CPU time 8.78 seconds
Started Feb 07 01:43:08 PM PST 24
Finished Feb 07 01:43:20 PM PST 24
Peak memory 218296 kb
Host smart-33efa09c-7285-4bcb-85e8-de260796adaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739651307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2739651307
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2474231051
Short name T984
Test name
Test status
Simulation time 31854355 ps
CPU time 0.68 seconds
Started Feb 07 01:43:15 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 216384 kb
Host smart-ccbe974d-7a30-49d3-9d48-13be140e4c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474231051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2474231051
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.308656167
Short name T948
Test name
Test status
Simulation time 3305011086 ps
CPU time 4.89 seconds
Started Feb 07 01:43:08 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 220604 kb
Host smart-e3dcc30e-2ebb-4ca0-81f2-4a48494bacd0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=308656167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.308656167
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2607504795
Short name T891
Test name
Test status
Simulation time 184843470004 ps
CPU time 439.24 seconds
Started Feb 07 01:43:10 PM PST 24
Finished Feb 07 01:50:31 PM PST 24
Peak memory 283516 kb
Host smart-d6a1394b-bea5-4131-9cbb-1f1a43fcda99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607504795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2607504795
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4009120491
Short name T529
Test name
Test status
Simulation time 11256188936 ps
CPU time 32.02 seconds
Started Feb 07 01:43:12 PM PST 24
Finished Feb 07 01:43:45 PM PST 24
Peak memory 216916 kb
Host smart-7e11c27b-cb16-4881-9aa9-392fb91eb3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009120491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4009120491
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.966049641
Short name T961
Test name
Test status
Simulation time 60376715411 ps
CPU time 11.91 seconds
Started Feb 07 01:43:11 PM PST 24
Finished Feb 07 01:43:24 PM PST 24
Peak memory 216568 kb
Host smart-86786fcb-0499-4eec-b50c-0007bc7bad9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966049641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.966049641
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4052350652
Short name T486
Test name
Test status
Simulation time 72222128 ps
CPU time 1.37 seconds
Started Feb 07 01:43:12 PM PST 24
Finished Feb 07 01:43:15 PM PST 24
Peak memory 216492 kb
Host smart-81e5c923-ef61-4a26-8be4-473ba270b7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052350652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4052350652
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2859561780
Short name T667
Test name
Test status
Simulation time 156163241 ps
CPU time 1.1 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:43:12 PM PST 24
Peak memory 206544 kb
Host smart-714e23a4-0b54-4e25-a2f4-763f0d006138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859561780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2859561780
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.538006862
Short name T422
Test name
Test status
Simulation time 980000079 ps
CPU time 5.8 seconds
Started Feb 07 01:43:06 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 223968 kb
Host smart-3061fc04-83fc-49c6-bb8e-bc82f400d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538006862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.538006862
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2864308459
Short name T985
Test name
Test status
Simulation time 29371420 ps
CPU time 0.75 seconds
Started Feb 07 01:43:17 PM PST 24
Finished Feb 07 01:43:19 PM PST 24
Peak memory 204404 kb
Host smart-64aa1da9-478e-4c2a-a103-44d65df8beed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864308459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2864308459
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2987153291
Short name T994
Test name
Test status
Simulation time 845887382 ps
CPU time 4.16 seconds
Started Feb 07 01:43:20 PM PST 24
Finished Feb 07 01:43:25 PM PST 24
Peak memory 219136 kb
Host smart-e571bccd-a8fe-4a73-ac2a-da610396aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987153291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2987153291
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3089619175
Short name T421
Test name
Test status
Simulation time 17641294 ps
CPU time 0.79 seconds
Started Feb 07 01:43:14 PM PST 24
Finished Feb 07 01:43:15 PM PST 24
Peak memory 206144 kb
Host smart-8d5bd1cd-3edd-4176-9423-ec645a53977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089619175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3089619175
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1788127397
Short name T1009
Test name
Test status
Simulation time 648638329 ps
CPU time 7.37 seconds
Started Feb 07 01:43:20 PM PST 24
Finished Feb 07 01:43:29 PM PST 24
Peak memory 238644 kb
Host smart-1568a932-98c2-4188-975d-1d0b49757cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788127397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1788127397
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3215511009
Short name T669
Test name
Test status
Simulation time 6561764946 ps
CPU time 56.56 seconds
Started Feb 07 01:43:19 PM PST 24
Finished Feb 07 01:44:17 PM PST 24
Peak memory 234196 kb
Host smart-51313777-c1f7-4c3f-b6ca-47b86c843dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215511009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3215511009
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2391090028
Short name T818
Test name
Test status
Simulation time 8176202782 ps
CPU time 98 seconds
Started Feb 07 01:43:17 PM PST 24
Finished Feb 07 01:44:56 PM PST 24
Peak memory 253348 kb
Host smart-4c91f9c1-433c-4363-b00e-da6f7d59bbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391090028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2391090028
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2819692961
Short name T941
Test name
Test status
Simulation time 605819838 ps
CPU time 5.42 seconds
Started Feb 07 01:43:22 PM PST 24
Finished Feb 07 01:43:29 PM PST 24
Peak memory 233368 kb
Host smart-22d1a2f2-24ab-4056-a0f1-524e676cd245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819692961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2819692961
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2367516533
Short name T513
Test name
Test status
Simulation time 743004106 ps
CPU time 3.18 seconds
Started Feb 07 01:43:18 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 233316 kb
Host smart-c0f8176b-5254-4919-b775-fed9b1b5944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367516533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2367516533
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.903007996
Short name T877
Test name
Test status
Simulation time 7141738518 ps
CPU time 14.94 seconds
Started Feb 07 01:43:25 PM PST 24
Finished Feb 07 01:43:41 PM PST 24
Peak memory 224808 kb
Host smart-3da5f8e3-151b-416a-8ede-93be8d1b5b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903007996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.903007996
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2504104011
Short name T1013
Test name
Test status
Simulation time 91134338 ps
CPU time 1.02 seconds
Started Feb 07 01:43:11 PM PST 24
Finished Feb 07 01:43:13 PM PST 24
Peak memory 216472 kb
Host smart-c25a5233-2f4e-4354-b8a9-c8784d4db15f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504104011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2504104011
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.789492779
Short name T998
Test name
Test status
Simulation time 11164413102 ps
CPU time 31.95 seconds
Started Feb 07 01:43:12 PM PST 24
Finished Feb 07 01:43:45 PM PST 24
Peak memory 237476 kb
Host smart-ed997db8-687f-4e2e-944c-1f22906d6508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789492779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.789492779
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1381074206
Short name T586
Test name
Test status
Simulation time 27772786860 ps
CPU time 25.59 seconds
Started Feb 07 01:43:17 PM PST 24
Finished Feb 07 01:43:44 PM PST 24
Peak memory 241260 kb
Host smart-6520e8ca-03e7-4b8c-ad61-3090d8712401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381074206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1381074206
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3576193435
Short name T479
Test name
Test status
Simulation time 40610718 ps
CPU time 0.75 seconds
Started Feb 07 01:43:17 PM PST 24
Finished Feb 07 01:43:19 PM PST 24
Peak memory 216328 kb
Host smart-9993ff89-b2e3-4870-8bbe-93b29f3e4300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576193435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3576193435
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3795768883
Short name T442
Test name
Test status
Simulation time 281813888 ps
CPU time 3.83 seconds
Started Feb 07 01:43:20 PM PST 24
Finished Feb 07 01:43:24 PM PST 24
Peak memory 220120 kb
Host smart-086aad28-77df-4b7e-bbfc-cbda29b87c4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3795768883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3795768883
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1904682526
Short name T812
Test name
Test status
Simulation time 2847441855 ps
CPU time 42.51 seconds
Started Feb 07 01:43:13 PM PST 24
Finished Feb 07 01:43:56 PM PST 24
Peak memory 216560 kb
Host smart-2460d17a-e301-4529-b5a2-bb469fc2e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904682526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1904682526
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.510891675
Short name T282
Test name
Test status
Simulation time 1829123713 ps
CPU time 8.06 seconds
Started Feb 07 01:43:08 PM PST 24
Finished Feb 07 01:43:19 PM PST 24
Peak memory 208228 kb
Host smart-a0629b62-dc1a-42db-8aa4-6d017d09a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510891675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.510891675
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3829247841
Short name T1065
Test name
Test status
Simulation time 170616443 ps
CPU time 2.06 seconds
Started Feb 07 01:43:14 PM PST 24
Finished Feb 07 01:43:17 PM PST 24
Peak memory 216740 kb
Host smart-3a7b03e7-161d-4c95-b627-6f0e86c1e63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829247841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3829247841
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.4027433130
Short name T839
Test name
Test status
Simulation time 563626373 ps
CPU time 1.12 seconds
Started Feb 07 01:43:14 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 206408 kb
Host smart-86f1e97d-077d-458f-96e4-a99ad8505a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027433130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4027433130
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2833640075
Short name T735
Test name
Test status
Simulation time 2227506733 ps
CPU time 10.06 seconds
Started Feb 07 01:43:16 PM PST 24
Finished Feb 07 01:43:27 PM PST 24
Peak memory 233088 kb
Host smart-4d1c6a98-448a-4198-bafa-0cf2b5a84821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833640075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2833640075
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4223664013
Short name T712
Test name
Test status
Simulation time 22782987 ps
CPU time 0.71 seconds
Started Feb 07 01:43:17 PM PST 24
Finished Feb 07 01:43:18 PM PST 24
Peak memory 205080 kb
Host smart-c7974fec-b7fd-4962-904f-f64020c95b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223664013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4223664013
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.556032014
Short name T797
Test name
Test status
Simulation time 154681284 ps
CPU time 2.63 seconds
Started Feb 07 01:43:20 PM PST 24
Finished Feb 07 01:43:24 PM PST 24
Peak memory 233796 kb
Host smart-a0896283-427e-44fd-8944-6a6a32c1306b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556032014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.556032014
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1945865817
Short name T921
Test name
Test status
Simulation time 51926470 ps
CPU time 0.79 seconds
Started Feb 07 01:43:25 PM PST 24
Finished Feb 07 01:43:27 PM PST 24
Peak memory 206516 kb
Host smart-7986e5c2-ce41-4504-919d-d4acf2e90cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945865817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1945865817
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1187640518
Short name T1021
Test name
Test status
Simulation time 13425953167 ps
CPU time 74.01 seconds
Started Feb 07 01:43:16 PM PST 24
Finished Feb 07 01:44:31 PM PST 24
Peak memory 249464 kb
Host smart-08dc564c-f288-411b-9074-cfd4cd5a15cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187640518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1187640518
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2863476643
Short name T679
Test name
Test status
Simulation time 23664296564 ps
CPU time 196.89 seconds
Started Feb 07 01:43:21 PM PST 24
Finished Feb 07 01:46:39 PM PST 24
Peak memory 264708 kb
Host smart-2a85098d-115c-4f0e-abaf-8932ed836041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863476643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2863476643
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3297838098
Short name T584
Test name
Test status
Simulation time 5759686753 ps
CPU time 79.67 seconds
Started Feb 07 01:43:22 PM PST 24
Finished Feb 07 01:44:43 PM PST 24
Peak memory 256160 kb
Host smart-263747e8-c1fa-4381-a0bf-1057645eb275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297838098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3297838098
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1483421603
Short name T495
Test name
Test status
Simulation time 51217631943 ps
CPU time 31.8 seconds
Started Feb 07 01:43:19 PM PST 24
Finished Feb 07 01:43:52 PM PST 24
Peak memory 243228 kb
Host smart-34435fad-f55e-4aa1-afa6-b5316ed02d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483421603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1483421603
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3571868537
Short name T636
Test name
Test status
Simulation time 2632555889 ps
CPU time 4.06 seconds
Started Feb 07 01:43:27 PM PST 24
Finished Feb 07 01:43:33 PM PST 24
Peak memory 232964 kb
Host smart-1cd68f2f-4056-4f1f-8d09-2b38dbcbdc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571868537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3571868537
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3831426271
Short name T784
Test name
Test status
Simulation time 44395635565 ps
CPU time 28.89 seconds
Started Feb 07 01:43:23 PM PST 24
Finished Feb 07 01:43:53 PM PST 24
Peak memory 233956 kb
Host smart-2eec54ba-7be7-4a6f-8e27-0ffee207acd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831426271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3831426271
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3420888475
Short name T448
Test name
Test status
Simulation time 125734663 ps
CPU time 1.02 seconds
Started Feb 07 01:43:19 PM PST 24
Finished Feb 07 01:43:20 PM PST 24
Peak memory 216624 kb
Host smart-e3f7c88e-53d1-4bc5-a9be-08838bf75b5f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420888475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3420888475
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.873091604
Short name T865
Test name
Test status
Simulation time 42934275140 ps
CPU time 29.36 seconds
Started Feb 07 01:43:17 PM PST 24
Finished Feb 07 01:43:47 PM PST 24
Peak memory 233700 kb
Host smart-68abab5b-0a28-48be-a9a0-cc4e73fefdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873091604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.873091604
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1773270988
Short name T756
Test name
Test status
Simulation time 13959708525 ps
CPU time 40.69 seconds
Started Feb 07 01:43:19 PM PST 24
Finished Feb 07 01:44:00 PM PST 24
Peak memory 239740 kb
Host smart-74eb186d-dd53-4e85-b252-646f192dee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773270988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1773270988
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3339760107
Short name T456
Test name
Test status
Simulation time 32478335 ps
CPU time 0.73 seconds
Started Feb 07 01:43:19 PM PST 24
Finished Feb 07 01:43:21 PM PST 24
Peak memory 216356 kb
Host smart-d47a3347-b389-442c-aab1-910b1628b4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339760107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3339760107
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.634323169
Short name T639
Test name
Test status
Simulation time 2172085334 ps
CPU time 5.5 seconds
Started Feb 07 01:43:27 PM PST 24
Finished Feb 07 01:43:34 PM PST 24
Peak memory 222040 kb
Host smart-ffc6f138-0412-4db7-84af-5b1f16b68091
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=634323169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.634323169
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3189798640
Short name T45
Test name
Test status
Simulation time 47841938 ps
CPU time 1.02 seconds
Started Feb 07 01:43:25 PM PST 24
Finished Feb 07 01:43:28 PM PST 24
Peak memory 206628 kb
Host smart-21f210f0-878a-423b-ad43-d185c60521c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189798640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3189798640
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2079943215
Short name T61
Test name
Test status
Simulation time 4978029434 ps
CPU time 50.6 seconds
Started Feb 07 01:43:19 PM PST 24
Finished Feb 07 01:44:11 PM PST 24
Peak memory 216684 kb
Host smart-e49bb44c-1b63-4624-b466-d92dc81ed872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079943215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2079943215
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3483660002
Short name T290
Test name
Test status
Simulation time 6077555868 ps
CPU time 14.55 seconds
Started Feb 07 01:43:21 PM PST 24
Finished Feb 07 01:43:37 PM PST 24
Peak memory 216592 kb
Host smart-8c2e9b79-b148-40ae-8c0c-26d75c77f95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483660002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3483660002
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3534542516
Short name T970
Test name
Test status
Simulation time 300174013 ps
CPU time 1.4 seconds
Started Feb 07 01:43:20 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 216416 kb
Host smart-73c8509e-02fd-4bc3-b985-244d4e466c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534542516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3534542516
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1709657141
Short name T974
Test name
Test status
Simulation time 75310309 ps
CPU time 0.97 seconds
Started Feb 07 01:43:20 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 205492 kb
Host smart-62773548-cf60-479d-9ba2-cdff94c521ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709657141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1709657141
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2572032866
Short name T256
Test name
Test status
Simulation time 22496620816 ps
CPU time 16.62 seconds
Started Feb 07 01:43:25 PM PST 24
Finished Feb 07 01:43:43 PM PST 24
Peak memory 226924 kb
Host smart-ed387fa2-f3e1-4c55-afdb-2ffda4d5b5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572032866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2572032866
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1534530817
Short name T542
Test name
Test status
Simulation time 14649475 ps
CPU time 0.73 seconds
Started Feb 07 01:43:32 PM PST 24
Finished Feb 07 01:43:35 PM PST 24
Peak memory 205028 kb
Host smart-df8bac2f-59a5-4fa7-a9db-a3204b5a8d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534530817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1534530817
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1115477753
Short name T647
Test name
Test status
Simulation time 6342087047 ps
CPU time 6.16 seconds
Started Feb 07 01:43:20 PM PST 24
Finished Feb 07 01:43:27 PM PST 24
Peak memory 224756 kb
Host smart-e1e733ea-17d9-406f-9522-ac68c31facb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115477753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1115477753
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2883716747
Short name T859
Test name
Test status
Simulation time 214375765 ps
CPU time 0.73 seconds
Started Feb 07 01:43:16 PM PST 24
Finished Feb 07 01:43:18 PM PST 24
Peak memory 205220 kb
Host smart-8d17ecdb-5552-4e07-b294-7ab6846f362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883716747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2883716747
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2244139055
Short name T943
Test name
Test status
Simulation time 2854100593 ps
CPU time 25.85 seconds
Started Feb 07 01:43:25 PM PST 24
Finished Feb 07 01:43:53 PM PST 24
Peak memory 251596 kb
Host smart-5a8bc7ca-2075-4aa1-a852-8bd118d875f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244139055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2244139055
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.718616687
Short name T147
Test name
Test status
Simulation time 136111779666 ps
CPU time 308.97 seconds
Started Feb 07 01:43:23 PM PST 24
Finished Feb 07 01:48:33 PM PST 24
Peak memory 241496 kb
Host smart-34be3c1b-4283-4868-9ecd-a6a3688d2048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718616687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.718616687
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.341147944
Short name T229
Test name
Test status
Simulation time 18353227523 ps
CPU time 100.25 seconds
Started Feb 07 01:43:19 PM PST 24
Finished Feb 07 01:45:00 PM PST 24
Peak memory 249564 kb
Host smart-def69143-b3a0-4692-8814-75a6e8e2bdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341147944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.341147944
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.712815127
Short name T1077
Test name
Test status
Simulation time 8040573894 ps
CPU time 31.39 seconds
Started Feb 07 01:43:16 PM PST 24
Finished Feb 07 01:43:48 PM PST 24
Peak memory 236736 kb
Host smart-7c22f674-eb1c-4681-aeee-356a6678f3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712815127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.712815127
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1683577055
Short name T291
Test name
Test status
Simulation time 841973128 ps
CPU time 2.8 seconds
Started Feb 07 01:43:19 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 216748 kb
Host smart-73bc11ff-4486-4aff-8e16-8a8fcc7b3245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683577055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1683577055
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2159361799
Short name T988
Test name
Test status
Simulation time 43312157 ps
CPU time 2.88 seconds
Started Feb 07 01:43:25 PM PST 24
Finished Feb 07 01:43:30 PM PST 24
Peak memory 234620 kb
Host smart-3343dc65-aa45-47a7-b9b4-d44e0bd13889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159361799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2159361799
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.205488343
Short name T1081
Test name
Test status
Simulation time 16347437 ps
CPU time 1.04 seconds
Started Feb 07 01:43:22 PM PST 24
Finished Feb 07 01:43:25 PM PST 24
Peak memory 216616 kb
Host smart-1b34aca4-59c0-48d0-b069-8b6f3c71d979
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205488343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.205488343
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.22237991
Short name T952
Test name
Test status
Simulation time 11466035707 ps
CPU time 31.17 seconds
Started Feb 07 01:43:28 PM PST 24
Finished Feb 07 01:44:00 PM PST 24
Peak memory 236816 kb
Host smart-9a930a88-2455-4b63-8de0-9f6a03ad05ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22237991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.22237991
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.170280284
Short name T1103
Test name
Test status
Simulation time 13652160099 ps
CPU time 11.24 seconds
Started Feb 07 01:43:23 PM PST 24
Finished Feb 07 01:43:35 PM PST 24
Peak memory 228936 kb
Host smart-55ae4171-ba71-4fdb-a0aa-adc923f14f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170280284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.170280284
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.689971952
Short name T47
Test name
Test status
Simulation time 32739249 ps
CPU time 0.72 seconds
Started Feb 07 01:43:20 PM PST 24
Finished Feb 07 01:43:21 PM PST 24
Peak memory 216336 kb
Host smart-fb19ae72-5213-426d-ac92-f57a0f902f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689971952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.689971952
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.155592967
Short name T681
Test name
Test status
Simulation time 1041762946 ps
CPU time 3.69 seconds
Started Feb 07 01:43:17 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 216592 kb
Host smart-0abbf5e9-784f-4ffa-83f2-6bb27e6ebec2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=155592967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.155592967
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3987500505
Short name T906
Test name
Test status
Simulation time 8493971331 ps
CPU time 32.08 seconds
Started Feb 07 01:43:18 PM PST 24
Finished Feb 07 01:43:51 PM PST 24
Peak memory 216888 kb
Host smart-0bde1466-2219-4092-9886-bc6b46fad03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987500505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3987500505
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2384764694
Short name T490
Test name
Test status
Simulation time 2187781023 ps
CPU time 6.95 seconds
Started Feb 07 01:43:18 PM PST 24
Finished Feb 07 01:43:26 PM PST 24
Peak memory 208492 kb
Host smart-2248bbdd-59bc-410b-8490-1194efc08afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384764694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2384764694
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2146742232
Short name T1089
Test name
Test status
Simulation time 725143509 ps
CPU time 1.99 seconds
Started Feb 07 01:43:21 PM PST 24
Finished Feb 07 01:43:24 PM PST 24
Peak memory 208576 kb
Host smart-0ce345aa-e09b-4824-bc85-72d687980647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146742232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2146742232
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1091161552
Short name T458
Test name
Test status
Simulation time 25180907 ps
CPU time 0.76 seconds
Started Feb 07 01:43:18 PM PST 24
Finished Feb 07 01:43:19 PM PST 24
Peak memory 205440 kb
Host smart-e309eac7-99d7-4c03-ab74-e7c1c7cd2624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091161552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1091161552
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4081780492
Short name T58
Test name
Test status
Simulation time 1761133708 ps
CPU time 6.2 seconds
Started Feb 07 01:43:22 PM PST 24
Finished Feb 07 01:43:29 PM PST 24
Peak memory 234596 kb
Host smart-ac975080-ad84-49bf-b1b2-0406a1af59a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081780492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4081780492
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2496088050
Short name T744
Test name
Test status
Simulation time 4017981813 ps
CPU time 5.26 seconds
Started Feb 07 01:43:36 PM PST 24
Finished Feb 07 01:43:44 PM PST 24
Peak memory 224780 kb
Host smart-1efbe8ec-6f91-4aff-9b67-6150bfee5b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496088050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2496088050
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1019373021
Short name T614
Test name
Test status
Simulation time 16321973 ps
CPU time 0.77 seconds
Started Feb 07 01:43:27 PM PST 24
Finished Feb 07 01:43:29 PM PST 24
Peak memory 205148 kb
Host smart-fc622aa8-07ac-41fc-ae2a-e0e0d3b8bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019373021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1019373021
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3854699747
Short name T879
Test name
Test status
Simulation time 88649744988 ps
CPU time 108.28 seconds
Started Feb 07 01:43:31 PM PST 24
Finished Feb 07 01:45:22 PM PST 24
Peak memory 249444 kb
Host smart-0ed20af3-5f31-483a-9042-16a81f5ff08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854699747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3854699747
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3173913127
Short name T743
Test name
Test status
Simulation time 6013579320 ps
CPU time 48.54 seconds
Started Feb 07 01:43:28 PM PST 24
Finished Feb 07 01:44:21 PM PST 24
Peak memory 221276 kb
Host smart-5d712b2f-c7df-43e2-b5db-fa04a3d40354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173913127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3173913127
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.96348457
Short name T1083
Test name
Test status
Simulation time 5347751556 ps
CPU time 67.48 seconds
Started Feb 07 01:43:33 PM PST 24
Finished Feb 07 01:44:42 PM PST 24
Peak memory 249080 kb
Host smart-eb4460f3-9b74-40a9-91b6-e08a3c65a9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96348457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.96348457
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.123382492
Short name T587
Test name
Test status
Simulation time 253133362 ps
CPU time 11.28 seconds
Started Feb 07 01:43:28 PM PST 24
Finished Feb 07 01:43:44 PM PST 24
Peak memory 224828 kb
Host smart-fd191ea3-7489-4e0b-a5e9-4c9041aa3757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123382492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.123382492
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1145216890
Short name T687
Test name
Test status
Simulation time 13855177380 ps
CPU time 7.64 seconds
Started Feb 07 01:43:29 PM PST 24
Finished Feb 07 01:43:42 PM PST 24
Peak memory 219584 kb
Host smart-2c6f4156-91ed-49be-b630-642dfc9efdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145216890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1145216890
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1826830814
Short name T884
Test name
Test status
Simulation time 133491966977 ps
CPU time 57.33 seconds
Started Feb 07 01:43:40 PM PST 24
Finished Feb 07 01:44:39 PM PST 24
Peak memory 240656 kb
Host smart-ef50fbe0-7a18-43b9-9ffd-10ccf62131ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826830814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1826830814
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2234658423
Short name T463
Test name
Test status
Simulation time 173637381 ps
CPU time 1.06 seconds
Started Feb 07 01:43:32 PM PST 24
Finished Feb 07 01:43:35 PM PST 24
Peak memory 216656 kb
Host smart-a8c473f6-2cc5-432c-81dc-f044e05226a9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234658423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2234658423
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3131491822
Short name T449
Test name
Test status
Simulation time 230951111 ps
CPU time 4.9 seconds
Started Feb 07 01:43:30 PM PST 24
Finished Feb 07 01:43:39 PM PST 24
Peak memory 233232 kb
Host smart-ed64b7ab-dda0-4293-9cfe-3eaccb65d8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131491822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3131491822
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1262546885
Short name T915
Test name
Test status
Simulation time 7085514563 ps
CPU time 7.16 seconds
Started Feb 07 01:43:32 PM PST 24
Finished Feb 07 01:43:41 PM PST 24
Peak memory 233612 kb
Host smart-44b56d3c-4756-40ba-9b78-77dd4fbcc641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262546885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1262546885
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2351857400
Short name T767
Test name
Test status
Simulation time 18634516 ps
CPU time 0.74 seconds
Started Feb 07 01:43:33 PM PST 24
Finished Feb 07 01:43:37 PM PST 24
Peak memory 216360 kb
Host smart-2251abaf-79d9-4024-9929-5d320621bfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351857400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2351857400
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1530598697
Short name T489
Test name
Test status
Simulation time 1213110699 ps
CPU time 4.35 seconds
Started Feb 07 01:43:39 PM PST 24
Finished Feb 07 01:43:45 PM PST 24
Peak memory 222092 kb
Host smart-4c14108b-1691-4ec0-a2e6-1f33301cd57d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1530598697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1530598697
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.641754921
Short name T807
Test name
Test status
Simulation time 7198242119 ps
CPU time 20.59 seconds
Started Feb 07 01:43:35 PM PST 24
Finished Feb 07 01:43:59 PM PST 24
Peak memory 216684 kb
Host smart-160fc276-31d9-4f29-99be-f8a3df429ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641754921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.641754921
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2646854173
Short name T880
Test name
Test status
Simulation time 15394845840 ps
CPU time 38.49 seconds
Started Feb 07 01:43:32 PM PST 24
Finished Feb 07 01:44:13 PM PST 24
Peak memory 216616 kb
Host smart-907f5b37-575e-47ad-8a67-cf69657591a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646854173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2646854173
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3424587701
Short name T301
Test name
Test status
Simulation time 106811245 ps
CPU time 1.97 seconds
Started Feb 07 01:43:28 PM PST 24
Finished Feb 07 01:43:35 PM PST 24
Peak memory 208512 kb
Host smart-f45ab75b-851a-4a4f-a0ec-c245f8f28d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424587701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3424587701
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1646177685
Short name T66
Test name
Test status
Simulation time 294213739 ps
CPU time 1.07 seconds
Started Feb 07 01:43:39 PM PST 24
Finished Feb 07 01:43:41 PM PST 24
Peak memory 206468 kb
Host smart-4a3fa3d6-c185-45a8-858b-7125a9755e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646177685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1646177685
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2247427707
Short name T28
Test name
Test status
Simulation time 2541243143 ps
CPU time 8.62 seconds
Started Feb 07 01:43:32 PM PST 24
Finished Feb 07 01:43:43 PM PST 24
Peak memory 232916 kb
Host smart-494cbb68-6676-4530-a789-30639f73e89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247427707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2247427707
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.912531463
Short name T1049
Test name
Test status
Simulation time 43438228 ps
CPU time 0.75 seconds
Started Feb 07 01:43:36 PM PST 24
Finished Feb 07 01:43:40 PM PST 24
Peak memory 205064 kb
Host smart-8aad62c0-eb0f-4a40-be8d-877d25fbc3c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912531463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.912531463
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2075878269
Short name T176
Test name
Test status
Simulation time 4339784448 ps
CPU time 6.01 seconds
Started Feb 07 01:43:29 PM PST 24
Finished Feb 07 01:43:39 PM PST 24
Peak memory 237228 kb
Host smart-dc25be83-b586-4e2f-9c84-b327adc7279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075878269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2075878269
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.805046279
Short name T523
Test name
Test status
Simulation time 21761764 ps
CPU time 0.82 seconds
Started Feb 07 01:43:34 PM PST 24
Finished Feb 07 01:43:38 PM PST 24
Peak memory 206172 kb
Host smart-10db9181-7fe3-4f8b-914c-e8ab1ff5e083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805046279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.805046279
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1219072255
Short name T453
Test name
Test status
Simulation time 33100844868 ps
CPU time 155.35 seconds
Started Feb 07 01:43:27 PM PST 24
Finished Feb 07 01:46:04 PM PST 24
Peak memory 250504 kb
Host smart-81427331-6301-4c9b-9b95-6eb6135ec65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219072255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1219072255
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2714991883
Short name T181
Test name
Test status
Simulation time 10573265607 ps
CPU time 77.7 seconds
Started Feb 07 01:43:33 PM PST 24
Finished Feb 07 01:44:52 PM PST 24
Peak memory 249496 kb
Host smart-9c88fb71-1abd-4fa5-aead-01a543bb1d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714991883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2714991883
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2643411367
Short name T230
Test name
Test status
Simulation time 11309789961 ps
CPU time 87.16 seconds
Started Feb 07 01:43:32 PM PST 24
Finished Feb 07 01:45:01 PM PST 24
Peak memory 262044 kb
Host smart-b9bb7874-1239-4411-9f95-8dd3be5be478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643411367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2643411367
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3740661666
Short name T995
Test name
Test status
Simulation time 4370441671 ps
CPU time 25.75 seconds
Started Feb 07 01:43:39 PM PST 24
Finished Feb 07 01:44:06 PM PST 24
Peak memory 238196 kb
Host smart-a586e18d-b2e7-4bfc-b7af-ba709aa79659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740661666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3740661666
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2905295965
Short name T953
Test name
Test status
Simulation time 724506046 ps
CPU time 2.86 seconds
Started Feb 07 01:43:27 PM PST 24
Finished Feb 07 01:43:31 PM PST 24
Peak memory 216568 kb
Host smart-c8b17899-46aa-45e0-9053-8077cf790b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905295965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2905295965
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3336712584
Short name T960
Test name
Test status
Simulation time 592833635 ps
CPU time 10.92 seconds
Started Feb 07 01:43:36 PM PST 24
Finished Feb 07 01:43:50 PM PST 24
Peak memory 233732 kb
Host smart-ed07571b-336a-43c7-b963-5c347dc830d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336712584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3336712584
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.584925069
Short name T541
Test name
Test status
Simulation time 17678403 ps
CPU time 1.04 seconds
Started Feb 07 01:43:32 PM PST 24
Finished Feb 07 01:43:35 PM PST 24
Peak memory 217816 kb
Host smart-d2640752-005a-4775-afea-c3fa313584df
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584925069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.584925069
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4200332331
Short name T1041
Test name
Test status
Simulation time 8224183359 ps
CPU time 11.09 seconds
Started Feb 07 01:43:33 PM PST 24
Finished Feb 07 01:43:45 PM PST 24
Peak memory 233088 kb
Host smart-d39ea9d1-4ff1-48d3-afd1-c535f1636bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200332331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4200332331
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2847934153
Short name T121
Test name
Test status
Simulation time 47822032665 ps
CPU time 34.86 seconds
Started Feb 07 01:43:39 PM PST 24
Finished Feb 07 01:44:15 PM PST 24
Peak memory 236812 kb
Host smart-5aff4241-615b-45a5-b1e8-43b55753ee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847934153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2847934153
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.3004876349
Short name T4
Test name
Test status
Simulation time 30818536 ps
CPU time 0.79 seconds
Started Feb 07 01:43:28 PM PST 24
Finished Feb 07 01:43:30 PM PST 24
Peak memory 216308 kb
Host smart-4cff9686-e2ff-4f30-8214-b0ebacd50155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004876349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.3004876349
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3013010841
Short name T480
Test name
Test status
Simulation time 120427208 ps
CPU time 3.81 seconds
Started Feb 07 01:43:33 PM PST 24
Finished Feb 07 01:43:39 PM PST 24
Peak memory 222580 kb
Host smart-7987beb4-4763-45c2-b650-4a3f5f53eeec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3013010841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3013010841
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3417641306
Short name T1028
Test name
Test status
Simulation time 76711050 ps
CPU time 0.92 seconds
Started Feb 07 01:43:26 PM PST 24
Finished Feb 07 01:43:29 PM PST 24
Peak memory 206492 kb
Host smart-2b9098f2-8a92-40fd-87be-0fecd657132b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417641306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3417641306
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1926438536
Short name T272
Test name
Test status
Simulation time 19062680988 ps
CPU time 183.54 seconds
Started Feb 07 01:43:28 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 216608 kb
Host smart-f8f5a776-dcd4-419b-90e8-9cf1cb500f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926438536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1926438536
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1319183061
Short name T446
Test name
Test status
Simulation time 4240827679 ps
CPU time 3.52 seconds
Started Feb 07 01:43:31 PM PST 24
Finished Feb 07 01:43:38 PM PST 24
Peak memory 216596 kb
Host smart-d534db39-6f42-4f24-bbd7-e23eb8fc6f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319183061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1319183061
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.984668226
Short name T663
Test name
Test status
Simulation time 134766881 ps
CPU time 1.18 seconds
Started Feb 07 01:43:36 PM PST 24
Finished Feb 07 01:43:40 PM PST 24
Peak memory 208324 kb
Host smart-24749670-a111-44db-9dc2-7478bb84bc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984668226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.984668226
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2818110664
Short name T1016
Test name
Test status
Simulation time 154745350 ps
CPU time 0.87 seconds
Started Feb 07 01:43:40 PM PST 24
Finished Feb 07 01:43:41 PM PST 24
Peak memory 205468 kb
Host smart-5b4745be-0dde-4f46-bd2d-5b041e731e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818110664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2818110664
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.415809287
Short name T764
Test name
Test status
Simulation time 5909632811 ps
CPU time 20.26 seconds
Started Feb 07 01:43:32 PM PST 24
Finished Feb 07 01:43:55 PM PST 24
Peak memory 248512 kb
Host smart-e0fc35bc-0d36-4692-926a-204f6ef22c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415809287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.415809287
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3028631674
Short name T704
Test name
Test status
Simulation time 10895264 ps
CPU time 0.69 seconds
Started Feb 07 01:43:34 PM PST 24
Finished Feb 07 01:43:38 PM PST 24
Peak memory 204468 kb
Host smart-781dd382-9e63-4d69-a26f-c4dc20f7723c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028631674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3028631674
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2229329557
Short name T1035
Test name
Test status
Simulation time 102005244 ps
CPU time 2.19 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:43:48 PM PST 24
Peak memory 224280 kb
Host smart-af558d14-8956-46e4-917e-8f5ffb2caeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229329557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2229329557
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1372564644
Short name T459
Test name
Test status
Simulation time 67572818 ps
CPU time 0.76 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:43:47 PM PST 24
Peak memory 206084 kb
Host smart-c9b695b0-e41c-4d69-81a9-a126c67b5caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372564644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1372564644
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2252804608
Short name T661
Test name
Test status
Simulation time 255832422053 ps
CPU time 139.86 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:46:05 PM PST 24
Peak memory 255592 kb
Host smart-3d994d4c-f223-491e-a89d-12a3879e9700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252804608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2252804608
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3216664826
Short name T706
Test name
Test status
Simulation time 48778470231 ps
CPU time 192.92 seconds
Started Feb 07 01:43:37 PM PST 24
Finished Feb 07 01:46:52 PM PST 24
Peak memory 237236 kb
Host smart-d9563ce3-6d57-45dd-8fe9-569f9f0457d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216664826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3216664826
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3096015719
Short name T274
Test name
Test status
Simulation time 3283089914 ps
CPU time 42.57 seconds
Started Feb 07 01:43:37 PM PST 24
Finished Feb 07 01:44:21 PM PST 24
Peak memory 251456 kb
Host smart-85de8bee-128d-4613-a87b-105a45925fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096015719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3096015719
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4199581799
Short name T1101
Test name
Test status
Simulation time 2893776293 ps
CPU time 9.71 seconds
Started Feb 07 01:43:35 PM PST 24
Finished Feb 07 01:43:48 PM PST 24
Peak memory 245816 kb
Host smart-15834d21-6f2d-4154-a759-c9a5e3dae696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199581799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4199581799
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1597809956
Short name T163
Test name
Test status
Simulation time 196327299 ps
CPU time 3.44 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:43:49 PM PST 24
Peak memory 224720 kb
Host smart-055ba2b0-cfc4-470b-b379-404796e6dad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597809956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1597809956
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3033671790
Short name T583
Test name
Test status
Simulation time 1125689412 ps
CPU time 7.13 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:43:53 PM PST 24
Peak memory 221352 kb
Host smart-137f1754-f9b0-4b17-a3a1-959892271b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033671790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3033671790
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.646383529
Short name T836
Test name
Test status
Simulation time 15020763 ps
CPU time 0.99 seconds
Started Feb 07 01:43:40 PM PST 24
Finished Feb 07 01:43:41 PM PST 24
Peak memory 216416 kb
Host smart-65e19fc2-2899-4c0e-b348-4b4823f81335
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646383529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.646383529
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3073555990
Short name T209
Test name
Test status
Simulation time 1072191507 ps
CPU time 11.58 seconds
Started Feb 07 01:43:40 PM PST 24
Finished Feb 07 01:43:52 PM PST 24
Peak memory 232544 kb
Host smart-8f67f406-be0c-48b6-bb37-9be0ea881c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073555990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3073555990
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3646556226
Short name T263
Test name
Test status
Simulation time 32226200897 ps
CPU time 26.02 seconds
Started Feb 07 01:43:40 PM PST 24
Finished Feb 07 01:44:07 PM PST 24
Peak memory 234568 kb
Host smart-c26c1949-225b-4f24-84ea-39001cd21ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646556226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3646556226
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.710038679
Short name T487
Test name
Test status
Simulation time 29013922 ps
CPU time 0.69 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:43:47 PM PST 24
Peak memory 216364 kb
Host smart-1cb9b1f5-7ffb-4cfd-b366-a22938c53cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710038679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.710038679
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3105902609
Short name T466
Test name
Test status
Simulation time 4196096551 ps
CPU time 6.17 seconds
Started Feb 07 01:43:38 PM PST 24
Finished Feb 07 01:43:46 PM PST 24
Peak memory 219104 kb
Host smart-e7f656e4-24c5-49db-9e44-5678a2a36062
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3105902609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3105902609
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2214919287
Short name T1020
Test name
Test status
Simulation time 6250484706 ps
CPU time 50.57 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:44:37 PM PST 24
Peak memory 216472 kb
Host smart-93c7a54a-933a-46c2-b9f3-b728add92ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214919287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2214919287
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3034547736
Short name T954
Test name
Test status
Simulation time 3397886025 ps
CPU time 10.54 seconds
Started Feb 07 01:43:39 PM PST 24
Finished Feb 07 01:43:51 PM PST 24
Peak memory 216376 kb
Host smart-90469508-967e-402a-9b6a-236041871206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034547736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3034547736
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.633909610
Short name T1017
Test name
Test status
Simulation time 46165263 ps
CPU time 1.61 seconds
Started Feb 07 01:43:46 PM PST 24
Finished Feb 07 01:43:49 PM PST 24
Peak memory 216768 kb
Host smart-eac905b7-6b70-4c73-8086-c5cf3d36288a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633909610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.633909610
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3974322387
Short name T778
Test name
Test status
Simulation time 66469635 ps
CPU time 0.69 seconds
Started Feb 07 01:43:44 PM PST 24
Finished Feb 07 01:43:46 PM PST 24
Peak memory 205292 kb
Host smart-e42aee7d-8570-4d6a-8e0f-9c480ca9f002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974322387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3974322387
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2472293065
Short name T918
Test name
Test status
Simulation time 5306243136 ps
CPU time 12.5 seconds
Started Feb 07 01:43:34 PM PST 24
Finished Feb 07 01:43:50 PM PST 24
Peak memory 233916 kb
Host smart-9f2469e4-de43-4d28-9420-a71c47329ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472293065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2472293065
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.448751358
Short name T567
Test name
Test status
Simulation time 36615965 ps
CPU time 0.73 seconds
Started Feb 07 01:43:46 PM PST 24
Finished Feb 07 01:43:48 PM PST 24
Peak memory 204456 kb
Host smart-2e2bf26c-e816-4c05-8697-ff71c9a72edb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448751358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.448751358
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4239803512
Short name T897
Test name
Test status
Simulation time 2937737377 ps
CPU time 3.18 seconds
Started Feb 07 01:43:47 PM PST 24
Finished Feb 07 01:43:52 PM PST 24
Peak memory 224888 kb
Host smart-9d864c8e-5549-48b1-bb78-6d08425aa031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239803512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4239803512
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.371094632
Short name T635
Test name
Test status
Simulation time 20014908 ps
CPU time 0.76 seconds
Started Feb 07 01:43:40 PM PST 24
Finished Feb 07 01:43:42 PM PST 24
Peak memory 205024 kb
Host smart-8bdee58d-c3a7-48b4-a8a4-8e36ff551d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371094632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.371094632
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1850377914
Short name T148
Test name
Test status
Simulation time 19344692521 ps
CPU time 92.71 seconds
Started Feb 07 01:43:47 PM PST 24
Finished Feb 07 01:45:22 PM PST 24
Peak memory 251312 kb
Host smart-447a729c-7d03-43db-8d87-50e74b53187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850377914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1850377914
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1408274495
Short name T527
Test name
Test status
Simulation time 14497645043 ps
CPU time 118.21 seconds
Started Feb 07 01:43:49 PM PST 24
Finished Feb 07 01:45:48 PM PST 24
Peak memory 238288 kb
Host smart-ebf56182-d560-401c-8896-3c3fe73e1230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408274495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1408274495
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3857984991
Short name T978
Test name
Test status
Simulation time 1004992353 ps
CPU time 6.65 seconds
Started Feb 07 01:43:46 PM PST 24
Finished Feb 07 01:43:53 PM PST 24
Peak memory 241080 kb
Host smart-ae6cffbe-e54d-413d-af63-6b0131c8da02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857984991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3857984991
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2486926752
Short name T649
Test name
Test status
Simulation time 261716280 ps
CPU time 2.71 seconds
Started Feb 07 01:43:37 PM PST 24
Finished Feb 07 01:43:42 PM PST 24
Peak memory 224284 kb
Host smart-8ab5e64c-3eee-41de-a021-434a763773f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486926752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2486926752
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2978130362
Short name T1079
Test name
Test status
Simulation time 2303853414 ps
CPU time 6.17 seconds
Started Feb 07 01:43:36 PM PST 24
Finished Feb 07 01:43:44 PM PST 24
Peak memory 227548 kb
Host smart-e7a73f8e-846e-45e6-9581-959b63cd2135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978130362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2978130362
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2969375112
Short name T25
Test name
Test status
Simulation time 15526190 ps
CPU time 0.95 seconds
Started Feb 07 01:43:35 PM PST 24
Finished Feb 07 01:43:39 PM PST 24
Peak memory 217900 kb
Host smart-21931d8f-066b-4133-b66e-48598179663b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969375112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2969375112
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.64015035
Short name T267
Test name
Test status
Simulation time 2764591311 ps
CPU time 11.21 seconds
Started Feb 07 01:43:36 PM PST 24
Finished Feb 07 01:43:50 PM PST 24
Peak memory 224856 kb
Host smart-659d65ac-d943-48a2-82cc-8fe647313574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64015035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.64015035
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2415820063
Short name T646
Test name
Test status
Simulation time 798907299 ps
CPU time 6.11 seconds
Started Feb 07 01:43:36 PM PST 24
Finished Feb 07 01:43:45 PM PST 24
Peak memory 233640 kb
Host smart-626de423-9a61-4765-ab8e-9f64e3695d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415820063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2415820063
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.2168895401
Short name T637
Test name
Test status
Simulation time 67720301 ps
CPU time 0.72 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:43:47 PM PST 24
Peak memory 216360 kb
Host smart-90081c42-c8dd-4fc6-b5a2-e32e28fb441b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168895401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.2168895401
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.320957252
Short name T1063
Test name
Test status
Simulation time 3206723962 ps
CPU time 7.18 seconds
Started Feb 07 01:43:47 PM PST 24
Finished Feb 07 01:43:56 PM PST 24
Peak memory 220468 kb
Host smart-78e598d8-cc39-47a1-92bb-d65a59d7bb06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=320957252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.320957252
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4034285119
Short name T1067
Test name
Test status
Simulation time 506362854 ps
CPU time 7.36 seconds
Started Feb 07 01:43:39 PM PST 24
Finished Feb 07 01:43:47 PM PST 24
Peak memory 216524 kb
Host smart-13cb1790-0311-4a8c-8c3f-ffeec9aae34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034285119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4034285119
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.612982614
Short name T307
Test name
Test status
Simulation time 7464399223 ps
CPU time 9.76 seconds
Started Feb 07 01:43:37 PM PST 24
Finished Feb 07 01:43:48 PM PST 24
Peak memory 216604 kb
Host smart-5bb76a8e-a972-4144-b5cb-27edeb332cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612982614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.612982614
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1512343285
Short name T59
Test name
Test status
Simulation time 410613402 ps
CPU time 2.56 seconds
Started Feb 07 01:43:38 PM PST 24
Finished Feb 07 01:43:42 PM PST 24
Peak memory 216524 kb
Host smart-0e5c6659-3090-46b0-988a-e813a9a8a70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512343285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1512343285
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3064004727
Short name T20
Test name
Test status
Simulation time 78087452 ps
CPU time 0.96 seconds
Started Feb 07 01:43:36 PM PST 24
Finished Feb 07 01:43:39 PM PST 24
Peak memory 205896 kb
Host smart-3084c5b0-b2f4-4c4e-8a01-ebd27ca6cae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064004727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3064004727
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3939261160
Short name T1108
Test name
Test status
Simulation time 11014508634 ps
CPU time 19.66 seconds
Started Feb 07 01:43:35 PM PST 24
Finished Feb 07 01:43:58 PM PST 24
Peak memory 246408 kb
Host smart-bbc23539-7558-465f-9145-491799453fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939261160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3939261160
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2115375755
Short name T1007
Test name
Test status
Simulation time 62437902 ps
CPU time 0.72 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:02 PM PST 24
Peak memory 204456 kb
Host smart-4f73aac9-16de-4cae-bca0-ae28bfb89f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115375755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2115375755
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.561649801
Short name T844
Test name
Test status
Simulation time 1743770009 ps
CPU time 8.05 seconds
Started Feb 07 01:43:47 PM PST 24
Finished Feb 07 01:43:56 PM PST 24
Peak memory 220248 kb
Host smart-a49167d2-7882-4525-acfc-936bcad6e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561649801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.561649801
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2507196423
Short name T427
Test name
Test status
Simulation time 41177878 ps
CPU time 0.74 seconds
Started Feb 07 01:43:49 PM PST 24
Finished Feb 07 01:43:51 PM PST 24
Peak memory 205560 kb
Host smart-416112d7-0abb-4806-ba1b-a2ec15434cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507196423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2507196423
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.538309543
Short name T885
Test name
Test status
Simulation time 8088590726 ps
CPU time 45.55 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:50 PM PST 24
Peak memory 235640 kb
Host smart-81bf236f-ae9e-4e96-9519-fb67df6adf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538309543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.538309543
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2295510542
Short name T516
Test name
Test status
Simulation time 93598730141 ps
CPU time 169.4 seconds
Started Feb 07 01:43:59 PM PST 24
Finished Feb 07 01:46:49 PM PST 24
Peak memory 250276 kb
Host smart-9b44d929-e150-4d3e-ac6b-46c7c7d0cb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295510542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2295510542
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2987120658
Short name T245
Test name
Test status
Simulation time 15779253745 ps
CPU time 81.05 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:45:21 PM PST 24
Peak memory 256760 kb
Host smart-524a025f-fea2-4d71-b5f9-f84638240285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987120658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2987120658
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.122193923
Short name T949
Test name
Test status
Simulation time 13445290345 ps
CPU time 16.07 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:20 PM PST 24
Peak memory 234888 kb
Host smart-7e955287-a4f7-4fcc-9278-7a5b66573ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122193923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.122193923
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3878504830
Short name T733
Test name
Test status
Simulation time 27451770393 ps
CPU time 12.88 seconds
Started Feb 07 01:43:49 PM PST 24
Finished Feb 07 01:44:03 PM PST 24
Peak memory 218008 kb
Host smart-3064b66b-ea70-45a2-962e-9dcc7236ae79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878504830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3878504830
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.587953408
Short name T835
Test name
Test status
Simulation time 7616700742 ps
CPU time 9.97 seconds
Started Feb 07 01:43:50 PM PST 24
Finished Feb 07 01:44:01 PM PST 24
Peak memory 233504 kb
Host smart-9124a4a2-acb1-4267-b1b0-7654a7007f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587953408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.587953408
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3560545449
Short name T648
Test name
Test status
Simulation time 25895476 ps
CPU time 1.04 seconds
Started Feb 07 01:43:48 PM PST 24
Finished Feb 07 01:43:51 PM PST 24
Peak memory 217796 kb
Host smart-07793662-5be4-4a82-b799-b2292f8448ca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560545449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3560545449
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3662954942
Short name T242
Test name
Test status
Simulation time 544859865 ps
CPU time 9.61 seconds
Started Feb 07 01:43:46 PM PST 24
Finished Feb 07 01:43:57 PM PST 24
Peak memory 240724 kb
Host smart-ef16fe1d-3814-45c0-870c-eb0fd3ca25d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662954942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3662954942
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1394507362
Short name T873
Test name
Test status
Simulation time 147481523 ps
CPU time 4.1 seconds
Started Feb 07 01:43:47 PM PST 24
Finished Feb 07 01:43:53 PM PST 24
Peak memory 237916 kb
Host smart-1c3d2227-1974-43f0-b65a-c7fb41013bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394507362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1394507362
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2871725387
Short name T465
Test name
Test status
Simulation time 16531456 ps
CPU time 0.75 seconds
Started Feb 07 01:43:46 PM PST 24
Finished Feb 07 01:43:48 PM PST 24
Peak memory 216352 kb
Host smart-48c658da-87a0-48e1-b8e2-cd4f9caf8520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871725387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2871725387
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2977175928
Short name T572
Test name
Test status
Simulation time 217720446 ps
CPU time 3.42 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:07 PM PST 24
Peak memory 220308 kb
Host smart-59dc3a11-8eb5-4d5c-ac69-3e2910ecaba0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2977175928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2977175928
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.741625847
Short name T217
Test name
Test status
Simulation time 135550608292 ps
CPU time 122.71 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:46:05 PM PST 24
Peak memory 252024 kb
Host smart-80282ee8-6954-4b14-a588-563cd77637ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741625847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.741625847
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.529886115
Short name T629
Test name
Test status
Simulation time 4344882940 ps
CPU time 12.05 seconds
Started Feb 07 01:43:49 PM PST 24
Finished Feb 07 01:44:02 PM PST 24
Peak memory 216640 kb
Host smart-00e535b5-62b6-4aa1-a763-d41d36b94829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529886115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.529886115
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3388278697
Short name T638
Test name
Test status
Simulation time 180561249 ps
CPU time 1.29 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:43:47 PM PST 24
Peak memory 206712 kb
Host smart-2c15c157-38fa-44bd-95dc-4ba612e21c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388278697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3388278697
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2396232914
Short name T843
Test name
Test status
Simulation time 166757642 ps
CPU time 1.34 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:43:47 PM PST 24
Peak memory 208548 kb
Host smart-4d0a0421-c2da-4d8b-befa-4f7d60885410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396232914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2396232914
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1455355522
Short name T660
Test name
Test status
Simulation time 248517714 ps
CPU time 1 seconds
Started Feb 07 01:43:49 PM PST 24
Finished Feb 07 01:43:51 PM PST 24
Peak memory 206508 kb
Host smart-2a96cf22-545e-4c75-b36a-448788075d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455355522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1455355522
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1369569701
Short name T569
Test name
Test status
Simulation time 190242757 ps
CPU time 3.73 seconds
Started Feb 07 01:43:45 PM PST 24
Finished Feb 07 01:43:50 PM PST 24
Peak memory 234164 kb
Host smart-54916214-8c6e-4a9d-a753-af0c44757158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369569701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1369569701
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3475144837
Short name T505
Test name
Test status
Simulation time 55069482 ps
CPU time 0.76 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:04 PM PST 24
Peak memory 205400 kb
Host smart-a9d62e26-c11d-4d7c-b453-d0192570bd96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475144837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3475144837
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1963774830
Short name T562
Test name
Test status
Simulation time 80036322 ps
CPU time 2.8 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:07 PM PST 24
Peak memory 233376 kb
Host smart-fb9103e4-4a9e-416d-b39a-b78b759b395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963774830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1963774830
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2140261885
Short name T507
Test name
Test status
Simulation time 19013275 ps
CPU time 0.89 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:04 PM PST 24
Peak memory 206544 kb
Host smart-2003b51f-57f3-4f30-a176-14e544a7f2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140261885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2140261885
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1553518529
Short name T27
Test name
Test status
Simulation time 8840202581 ps
CPU time 12.9 seconds
Started Feb 07 01:43:58 PM PST 24
Finished Feb 07 01:44:12 PM PST 24
Peak memory 224816 kb
Host smart-68572a31-b8d7-4c2c-b4a3-d113444425b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553518529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1553518529
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3457888611
Short name T857
Test name
Test status
Simulation time 22217845778 ps
CPU time 98.5 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:45:41 PM PST 24
Peak memory 244996 kb
Host smart-b3a045dc-3112-4a45-ba11-f28307c97d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457888611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3457888611
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2347520786
Short name T1042
Test name
Test status
Simulation time 81978141968 ps
CPU time 78.01 seconds
Started Feb 07 01:44:05 PM PST 24
Finished Feb 07 01:45:24 PM PST 24
Peak memory 250736 kb
Host smart-d9b815cf-9365-4f34-a365-79a0bb54a4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347520786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2347520786
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_intercept.790898908
Short name T904
Test name
Test status
Simulation time 44704547383 ps
CPU time 11.24 seconds
Started Feb 07 01:43:57 PM PST 24
Finished Feb 07 01:44:09 PM PST 24
Peak memory 234468 kb
Host smart-cc397b9b-db4e-4a96-9ca5-7b29864058c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790898908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.790898908
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.4004469834
Short name T182
Test name
Test status
Simulation time 958440416 ps
CPU time 5.33 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:07 PM PST 24
Peak memory 240688 kb
Host smart-66f34986-c993-4545-9f44-ba66f619e979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004469834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4004469834
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.4187657496
Short name T443
Test name
Test status
Simulation time 91642257 ps
CPU time 1.1 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:04 PM PST 24
Peak memory 216580 kb
Host smart-513782e2-09f7-4fe3-b319-a0637122f7ed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187657496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.4187657496
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1667418217
Short name T175
Test name
Test status
Simulation time 29636048642 ps
CPU time 15.47 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:16 PM PST 24
Peak memory 234640 kb
Host smart-4486e0f2-08f6-4320-a01b-7d0f8ba55233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667418217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1667418217
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4285087411
Short name T785
Test name
Test status
Simulation time 985536712 ps
CPU time 6.23 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:08 PM PST 24
Peak memory 218384 kb
Host smart-1a6f4bf2-de68-4f52-afc3-66c2e1b9dfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285087411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4285087411
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.2618548025
Short name T508
Test name
Test status
Simulation time 25719281 ps
CPU time 0.7 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:04 PM PST 24
Peak memory 216312 kb
Host smart-578544c2-3ed7-49c5-82d4-6d144aef0ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618548025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2618548025
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1532321904
Short name T894
Test name
Test status
Simulation time 6951780681 ps
CPU time 4.74 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:06 PM PST 24
Peak memory 220212 kb
Host smart-c79e2c06-2cae-4f7b-96c5-0b9c610b7f16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1532321904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1532321904
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.525680275
Short name T195
Test name
Test status
Simulation time 35926535024 ps
CPU time 152.96 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:46:35 PM PST 24
Peak memory 255692 kb
Host smart-8f5757fb-2f77-4df1-80b9-818571c6d512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525680275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.525680275
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1364943009
Short name T535
Test name
Test status
Simulation time 1576877629 ps
CPU time 13.44 seconds
Started Feb 07 01:43:58 PM PST 24
Finished Feb 07 01:44:12 PM PST 24
Peak memory 216552 kb
Host smart-e06de9d8-81e8-4cc4-8d58-2c13e0f5cfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364943009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1364943009
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2433222543
Short name T1058
Test name
Test status
Simulation time 2940151884 ps
CPU time 10.07 seconds
Started Feb 07 01:43:59 PM PST 24
Finished Feb 07 01:44:09 PM PST 24
Peak memory 216604 kb
Host smart-a624b8ae-7caa-4497-b6f1-93ee1bea5adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433222543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2433222543
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3418364005
Short name T524
Test name
Test status
Simulation time 223738102 ps
CPU time 1.73 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:06 PM PST 24
Peak memory 208112 kb
Host smart-fce53305-a25a-4c11-bcf2-d784caa19ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418364005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3418364005
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1176256788
Short name T429
Test name
Test status
Simulation time 101397609 ps
CPU time 0.74 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:05 PM PST 24
Peak memory 205516 kb
Host smart-14702bbb-d768-415c-98e6-55f64a934cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176256788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1176256788
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.412352435
Short name T991
Test name
Test status
Simulation time 777443427 ps
CPU time 6.37 seconds
Started Feb 07 01:43:59 PM PST 24
Finished Feb 07 01:44:06 PM PST 24
Peak memory 224744 kb
Host smart-0d0e82d0-b3bd-4d28-8199-4cdc9343f06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412352435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.412352435
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3021565285
Short name T43
Test name
Test status
Simulation time 23102578 ps
CPU time 0.72 seconds
Started Feb 07 01:42:35 PM PST 24
Finished Feb 07 01:42:36 PM PST 24
Peak memory 204412 kb
Host smart-7a0cf4c9-fc60-42b6-8a1a-39483a713881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021565285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
021565285
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2599427263
Short name T295
Test name
Test status
Simulation time 36414476 ps
CPU time 2.19 seconds
Started Feb 07 01:42:21 PM PST 24
Finished Feb 07 01:42:24 PM PST 24
Peak memory 233768 kb
Host smart-bd0a4728-972b-49bf-9c9b-198373b37e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599427263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2599427263
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.205644898
Short name T791
Test name
Test status
Simulation time 24371882 ps
CPU time 0.77 seconds
Started Feb 07 01:42:25 PM PST 24
Finished Feb 07 01:42:27 PM PST 24
Peak memory 205196 kb
Host smart-931c920a-0628-4676-964e-bb9ccd0cd002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205644898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.205644898
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2582703990
Short name T203
Test name
Test status
Simulation time 36082351036 ps
CPU time 61.86 seconds
Started Feb 07 01:42:26 PM PST 24
Finished Feb 07 01:43:29 PM PST 24
Peak memory 255752 kb
Host smart-5156e7a7-b80c-47de-83a1-66095cb45d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582703990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2582703990
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1179221295
Short name T601
Test name
Test status
Simulation time 50095713493 ps
CPU time 98.01 seconds
Started Feb 07 01:42:22 PM PST 24
Finished Feb 07 01:44:00 PM PST 24
Peak memory 266868 kb
Host smart-46be2e09-4cd7-4a37-beea-3d100f4eacfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179221295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1179221295
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.736615427
Short name T204
Test name
Test status
Simulation time 306687420562 ps
CPU time 229.56 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 256904 kb
Host smart-b25621d8-998e-4511-9076-8fd9738a3c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736615427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
736615427
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.935258263
Short name T751
Test name
Test status
Simulation time 5140822529 ps
CPU time 29.22 seconds
Started Feb 07 01:42:31 PM PST 24
Finished Feb 07 01:43:00 PM PST 24
Peak memory 244608 kb
Host smart-7febc744-31e4-47e3-b706-f1669be1e14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935258263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.935258263
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3905220853
Short name T509
Test name
Test status
Simulation time 551350578 ps
CPU time 3.45 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:42:29 PM PST 24
Peak memory 236944 kb
Host smart-d380ac51-a8e7-41dc-b4d8-6b7f85897656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905220853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3905220853
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2985816873
Short name T594
Test name
Test status
Simulation time 3495036609 ps
CPU time 8.17 seconds
Started Feb 07 01:42:23 PM PST 24
Finished Feb 07 01:42:32 PM PST 24
Peak memory 238696 kb
Host smart-8561c2f7-2779-47e4-a259-bf5a60675dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985816873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2985816873
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1317644475
Short name T441
Test name
Test status
Simulation time 83506246 ps
CPU time 1.08 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:42:26 PM PST 24
Peak memory 216612 kb
Host smart-026dbb26-4277-458d-9244-11b6bf35ff24
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317644475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1317644475
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2922640540
Short name T55
Test name
Test status
Simulation time 1318676317 ps
CPU time 5.41 seconds
Started Feb 07 01:42:25 PM PST 24
Finished Feb 07 01:42:31 PM PST 24
Peak memory 233664 kb
Host smart-34fd1657-9a54-4d21-8e51-6be93d881a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922640540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2922640540
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2747225964
Short name T123
Test name
Test status
Simulation time 207257992 ps
CPU time 3.99 seconds
Started Feb 07 01:42:26 PM PST 24
Finished Feb 07 01:42:31 PM PST 24
Peak memory 233556 kb
Host smart-a20c7d4b-7e7b-450e-9cd8-dfb8f92ea1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747225964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2747225964
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2747386946
Short name T620
Test name
Test status
Simulation time 37295288 ps
CPU time 0.73 seconds
Started Feb 07 01:42:26 PM PST 24
Finished Feb 07 01:42:28 PM PST 24
Peak memory 216240 kb
Host smart-9c5ea271-1228-4094-b40d-940ad7e4d30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747386946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2747386946
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1574964801
Short name T134
Test name
Test status
Simulation time 1575231971 ps
CPU time 6.72 seconds
Started Feb 07 01:42:23 PM PST 24
Finished Feb 07 01:42:31 PM PST 24
Peak memory 221564 kb
Host smart-e63a5b11-4b8d-4cfa-a608-32df2c4894c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1574964801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1574964801
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4202593191
Short name T1039
Test name
Test status
Simulation time 20126023166 ps
CPU time 188.49 seconds
Started Feb 07 01:42:22 PM PST 24
Finished Feb 07 01:45:31 PM PST 24
Peak memory 249508 kb
Host smart-1634f9b0-7bb7-4aae-a1d1-8bc0bfe758b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202593191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4202593191
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3976984486
Short name T1072
Test name
Test status
Simulation time 5890699223 ps
CPU time 58.34 seconds
Started Feb 07 01:42:24 PM PST 24
Finished Feb 07 01:43:23 PM PST 24
Peak memory 216620 kb
Host smart-912ebb44-5b4b-4313-979b-ae115ee6ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976984486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3976984486
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3060154809
Short name T971
Test name
Test status
Simulation time 1565456347 ps
CPU time 7.75 seconds
Started Feb 07 01:42:27 PM PST 24
Finished Feb 07 01:42:35 PM PST 24
Peak memory 208324 kb
Host smart-8bb5b9a8-4ef5-42f0-a245-e51d01fdfd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060154809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3060154809
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.858310289
Short name T618
Test name
Test status
Simulation time 42792891 ps
CPU time 1.01 seconds
Started Feb 07 01:42:31 PM PST 24
Finished Feb 07 01:42:32 PM PST 24
Peak memory 206616 kb
Host smart-0fa80712-7668-4525-a8c2-39538d34696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858310289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.858310289
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4008048658
Short name T737
Test name
Test status
Simulation time 85004372 ps
CPU time 0.97 seconds
Started Feb 07 01:42:25 PM PST 24
Finished Feb 07 01:42:27 PM PST 24
Peak memory 205980 kb
Host smart-0c880e68-2409-4be5-bae2-e001850a7874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008048658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4008048658
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3383389904
Short name T193
Test name
Test status
Simulation time 132158649 ps
CPU time 3.02 seconds
Started Feb 07 01:42:27 PM PST 24
Finished Feb 07 01:42:30 PM PST 24
Peak memory 235564 kb
Host smart-615a74b1-e05f-4cc3-bab0-289807e9d72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383389904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3383389904
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1070422076
Short name T673
Test name
Test status
Simulation time 22791803 ps
CPU time 0.75 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:01 PM PST 24
Peak memory 205052 kb
Host smart-d81c6427-4980-4052-a10e-bb9eb5bf9518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070422076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1070422076
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3341455325
Short name T576
Test name
Test status
Simulation time 873579890 ps
CPU time 3.58 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:08 PM PST 24
Peak memory 219244 kb
Host smart-9fae2676-af5b-4e71-96f9-729fc1b22292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341455325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3341455325
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3350914738
Short name T1027
Test name
Test status
Simulation time 17884637 ps
CPU time 0.81 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:01 PM PST 24
Peak memory 205216 kb
Host smart-114188db-993c-4fc8-ba48-1ab4b8c0f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350914738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3350914738
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.973153442
Short name T655
Test name
Test status
Simulation time 18801567313 ps
CPU time 37.83 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:42 PM PST 24
Peak memory 249336 kb
Host smart-3d81191d-c0c6-4f3e-a43c-63e9979bb249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973153442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.973153442
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.461464492
Short name T519
Test name
Test status
Simulation time 19604323314 ps
CPU time 115.1 seconds
Started Feb 07 01:43:58 PM PST 24
Finished Feb 07 01:45:54 PM PST 24
Peak memory 253528 kb
Host smart-9296e9ee-fd35-4a42-b534-5cb776d8323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461464492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.461464492
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3743635359
Short name T207
Test name
Test status
Simulation time 6840211817 ps
CPU time 24.32 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:27 PM PST 24
Peak memory 233412 kb
Host smart-74af99d9-11ba-4bb8-9ccc-90f91d4b3354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743635359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3743635359
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.655757313
Short name T268
Test name
Test status
Simulation time 2553718745 ps
CPU time 8.82 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:09 PM PST 24
Peak memory 248812 kb
Host smart-850d46a4-9ba8-4d43-81d8-83fb5c5add7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655757313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.655757313
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1800299409
Short name T796
Test name
Test status
Simulation time 1672559094 ps
CPU time 4.84 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:08 PM PST 24
Peak memory 233504 kb
Host smart-23f6f3f9-47e2-4c75-9afb-ec6c27002959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800299409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1800299409
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1747180751
Short name T183
Test name
Test status
Simulation time 12615235836 ps
CPU time 29.21 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:33 PM PST 24
Peak memory 231196 kb
Host smart-cd9423cc-c62c-47af-9bd9-8d971447b629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747180751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1747180751
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.581934749
Short name T231
Test name
Test status
Simulation time 775995591 ps
CPU time 8.65 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:09 PM PST 24
Peak memory 239824 kb
Host smart-df2f0a0b-42d7-41a3-8020-6b53fe08529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581934749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.581934749
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1535782219
Short name T266
Test name
Test status
Simulation time 1301644380 ps
CPU time 5.5 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:10 PM PST 24
Peak memory 233512 kb
Host smart-70e107f1-b2b6-4926-a3ec-343acfd8adc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535782219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1535782219
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.370995841
Short name T924
Test name
Test status
Simulation time 3159531993 ps
CPU time 5.27 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:09 PM PST 24
Peak memory 221036 kb
Host smart-e50cf2a7-8c95-40c9-be53-d6bc4925dcd7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=370995841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.370995841
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1874493926
Short name T975
Test name
Test status
Simulation time 72379937 ps
CPU time 1.18 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:02 PM PST 24
Peak memory 206640 kb
Host smart-73f65022-b1c4-46d2-bc54-b8a66095ec4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874493926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1874493926
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3929983030
Short name T477
Test name
Test status
Simulation time 16257161463 ps
CPU time 65.8 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:45:10 PM PST 24
Peak memory 216576 kb
Host smart-a30d18d9-8fe9-4333-be70-bb83103d594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929983030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3929983030
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1844574826
Short name T1076
Test name
Test status
Simulation time 1384662144 ps
CPU time 5.77 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:09 PM PST 24
Peak memory 216572 kb
Host smart-25b671c2-4fb2-4db6-b376-42167220013d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844574826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1844574826
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.404675653
Short name T460
Test name
Test status
Simulation time 405320555 ps
CPU time 2.01 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:03 PM PST 24
Peak memory 208648 kb
Host smart-377c341c-b60f-4b13-9669-e1c2256892d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404675653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.404675653
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2681795568
Short name T745
Test name
Test status
Simulation time 84992274 ps
CPU time 0.98 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:05 PM PST 24
Peak memory 206496 kb
Host smart-f7c355f3-6770-4cf6-95f8-c0ab9c4a64cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681795568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2681795568
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.188674716
Short name T640
Test name
Test status
Simulation time 2648723404 ps
CPU time 10.74 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:11 PM PST 24
Peak memory 236196 kb
Host smart-4eb2e10f-ce9f-4074-bafa-bd3e4700d188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188674716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.188674716
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1566607612
Short name T700
Test name
Test status
Simulation time 10275347 ps
CPU time 0.72 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:02 PM PST 24
Peak memory 205048 kb
Host smart-8069922a-25fd-494c-8448-f72b5198bb6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566607612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1566607612
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3211270320
Short name T965
Test name
Test status
Simulation time 1306967421 ps
CPU time 4.62 seconds
Started Feb 07 01:44:06 PM PST 24
Finished Feb 07 01:44:11 PM PST 24
Peak memory 218712 kb
Host smart-fe67346f-c5e2-4159-aec1-3993f3eaedbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211270320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3211270320
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.127659581
Short name T286
Test name
Test status
Simulation time 135277614 ps
CPU time 0.81 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:05 PM PST 24
Peak memory 206236 kb
Host smart-bcad90a0-4b51-4f58-aff6-8e8994d4b44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127659581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.127659581
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2489748101
Short name T1113
Test name
Test status
Simulation time 35811252026 ps
CPU time 166.41 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:46:51 PM PST 24
Peak memory 249888 kb
Host smart-15ff0a5b-e41f-4a5d-96ad-66c1ee972d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489748101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2489748101
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.345622411
Short name T257
Test name
Test status
Simulation time 14768567357 ps
CPU time 97.56 seconds
Started Feb 07 01:44:04 PM PST 24
Finished Feb 07 01:45:43 PM PST 24
Peak memory 249556 kb
Host smart-90f2c88b-fa12-4c5f-a09a-6c5cddeeb3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345622411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.345622411
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3184854300
Short name T793
Test name
Test status
Simulation time 54851219616 ps
CPU time 126.64 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:46:10 PM PST 24
Peak memory 252680 kb
Host smart-460f7660-dc39-4240-b7ce-2d4f7ae41cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184854300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3184854300
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2646209666
Short name T1040
Test name
Test status
Simulation time 46873711127 ps
CPU time 42.56 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:47 PM PST 24
Peak memory 255456 kb
Host smart-30bb9ac9-b2cb-446a-af5e-7ffd4daec584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646209666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2646209666
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1510036758
Short name T976
Test name
Test status
Simulation time 3480486532 ps
CPU time 12.17 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:16 PM PST 24
Peak memory 233240 kb
Host smart-2ed82ccb-6737-4599-98ce-afb69f81b094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510036758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1510036758
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1964422489
Short name T938
Test name
Test status
Simulation time 1084089213 ps
CPU time 5.48 seconds
Started Feb 07 01:44:06 PM PST 24
Finished Feb 07 01:44:12 PM PST 24
Peak memory 231056 kb
Host smart-894cd5db-9abd-4ec2-8fdc-b24d56c23041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964422489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1964422489
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3656312118
Short name T525
Test name
Test status
Simulation time 7696042233 ps
CPU time 14.81 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:18 PM PST 24
Peak memory 233956 kb
Host smart-dfe4c05b-606b-42db-b3f2-cc8c1d133ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656312118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3656312118
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2603849701
Short name T497
Test name
Test status
Simulation time 854386175 ps
CPU time 11.15 seconds
Started Feb 07 01:44:04 PM PST 24
Finished Feb 07 01:44:16 PM PST 24
Peak memory 239564 kb
Host smart-4b8df324-5b02-4ec9-9a86-5b2b082f8d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603849701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2603849701
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2082867527
Short name T492
Test name
Test status
Simulation time 3092137412 ps
CPU time 6.68 seconds
Started Feb 07 01:44:06 PM PST 24
Finished Feb 07 01:44:13 PM PST 24
Peak memory 216588 kb
Host smart-c38cde3e-7580-4568-abc1-503aa5e44dc6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2082867527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2082867527
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3783078168
Short name T808
Test name
Test status
Simulation time 30564610099 ps
CPU time 76 seconds
Started Feb 07 01:44:08 PM PST 24
Finished Feb 07 01:45:25 PM PST 24
Peak memory 256836 kb
Host smart-7ab0ad2c-8ea2-45e7-bb7e-77371e94527b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783078168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3783078168
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.786992554
Short name T21
Test name
Test status
Simulation time 618045867 ps
CPU time 2.71 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:07 PM PST 24
Peak memory 216476 kb
Host smart-9a15eac6-2dbf-485c-b84c-99d50b6362e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786992554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.786992554
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3757980925
Short name T515
Test name
Test status
Simulation time 14190302763 ps
CPU time 11.16 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:13 PM PST 24
Peak memory 216596 kb
Host smart-d5b35dad-0dad-4fc9-abcf-c79c15957f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757980925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3757980925
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3385554200
Short name T711
Test name
Test status
Simulation time 78974826 ps
CPU time 1.48 seconds
Started Feb 07 01:44:00 PM PST 24
Finished Feb 07 01:44:02 PM PST 24
Peak memory 208392 kb
Host smart-81f95839-22e6-4489-93c6-aefd4b47e3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385554200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3385554200
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.182037242
Short name T306
Test name
Test status
Simulation time 171905623 ps
CPU time 0.96 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:03 PM PST 24
Peak memory 206552 kb
Host smart-e9968b78-77df-4dc5-8006-986d94b66eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182037242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.182037242
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1339870184
Short name T264
Test name
Test status
Simulation time 44420394534 ps
CPU time 12.02 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:17 PM PST 24
Peak memory 234052 kb
Host smart-dc1ebb5a-ef5f-4cb2-b3a2-55bc5956fdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339870184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1339870184
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1635204173
Short name T305
Test name
Test status
Simulation time 37624552 ps
CPU time 0.71 seconds
Started Feb 07 01:44:24 PM PST 24
Finished Feb 07 01:44:25 PM PST 24
Peak memory 204472 kb
Host smart-8ad664ae-125d-44d1-89d4-be2015943a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635204173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1635204173
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3915356568
Short name T779
Test name
Test status
Simulation time 3758456049 ps
CPU time 5.11 seconds
Started Feb 07 01:44:18 PM PST 24
Finished Feb 07 01:44:24 PM PST 24
Peak memory 234144 kb
Host smart-889cf426-e673-450b-a847-bc1409024f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915356568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3915356568
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3330280085
Short name T727
Test name
Test status
Simulation time 62051505 ps
CPU time 0.78 seconds
Started Feb 07 01:44:05 PM PST 24
Finished Feb 07 01:44:07 PM PST 24
Peak memory 205124 kb
Host smart-1257d601-843d-479c-8b81-558d1f187406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330280085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3330280085
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2069199604
Short name T1032
Test name
Test status
Simulation time 3613646840 ps
CPU time 72.66 seconds
Started Feb 07 01:44:19 PM PST 24
Finished Feb 07 01:45:32 PM PST 24
Peak memory 252852 kb
Host smart-afc7ae37-a817-4405-8b39-2b1cefc537e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069199604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2069199604
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2436635159
Short name T218
Test name
Test status
Simulation time 98468711783 ps
CPU time 506.54 seconds
Started Feb 07 01:44:18 PM PST 24
Finished Feb 07 01:52:45 PM PST 24
Peak memory 268716 kb
Host smart-065e479f-13c2-4c24-ac23-0c387b2c62a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436635159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2436635159
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_intercept.701531338
Short name T690
Test name
Test status
Simulation time 535682722 ps
CPU time 5.12 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:08 PM PST 24
Peak memory 233696 kb
Host smart-6e915bad-59fe-4024-a976-1e87773458a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701531338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.701531338
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2355741823
Short name T780
Test name
Test status
Simulation time 58955489155 ps
CPU time 50.46 seconds
Started Feb 07 01:44:04 PM PST 24
Finished Feb 07 01:44:55 PM PST 24
Peak memory 240624 kb
Host smart-aa1085c9-b25c-4d1d-8dd0-b99619e7350e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355741823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2355741823
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3331703801
Short name T172
Test name
Test status
Simulation time 163157145 ps
CPU time 4.69 seconds
Started Feb 07 01:44:03 PM PST 24
Finished Feb 07 01:44:09 PM PST 24
Peak memory 233004 kb
Host smart-941e65db-6caa-40c8-bdbe-c60c852a258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331703801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3331703801
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1280611340
Short name T521
Test name
Test status
Simulation time 13866093544 ps
CPU time 18.49 seconds
Started Feb 07 01:44:09 PM PST 24
Finished Feb 07 01:44:28 PM PST 24
Peak memory 229344 kb
Host smart-9aa045f9-23d6-43f1-91b3-2214e33f7ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280611340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1280611340
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4225868041
Short name T133
Test name
Test status
Simulation time 98377623 ps
CPU time 3.63 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:44:31 PM PST 24
Peak memory 222132 kb
Host smart-b18f6175-80a8-41c5-9954-88d80273c3ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4225868041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4225868041
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1809410629
Short name T57
Test name
Test status
Simulation time 108644441663 ps
CPU time 400.32 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:51:08 PM PST 24
Peak memory 254824 kb
Host smart-5b3c9782-94d7-4632-9fab-5cd3422a9e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809410629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1809410629
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2910112462
Short name T940
Test name
Test status
Simulation time 13562044102 ps
CPU time 41.78 seconds
Started Feb 07 01:44:04 PM PST 24
Finished Feb 07 01:44:47 PM PST 24
Peak memory 221276 kb
Host smart-b7fedbd7-cc6c-4f1b-aff9-cee25d85d222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910112462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2910112462
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2282839734
Short name T285
Test name
Test status
Simulation time 388213130 ps
CPU time 1.41 seconds
Started Feb 07 01:44:01 PM PST 24
Finished Feb 07 01:44:05 PM PST 24
Peak memory 206780 kb
Host smart-e63131fe-7f4e-4cc0-9221-c823a7ad1afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282839734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2282839734
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3965621580
Short name T762
Test name
Test status
Simulation time 113369819 ps
CPU time 1.88 seconds
Started Feb 07 01:44:02 PM PST 24
Finished Feb 07 01:44:05 PM PST 24
Peak memory 208668 kb
Host smart-2b39c330-0162-4855-ad01-23813f950b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965621580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3965621580
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4244312710
Short name T478
Test name
Test status
Simulation time 113657244 ps
CPU time 0.76 seconds
Started Feb 07 01:44:08 PM PST 24
Finished Feb 07 01:44:10 PM PST 24
Peak memory 205344 kb
Host smart-b8377d2f-202e-4dd1-8a0c-e0c21828dcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244312710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4244312710
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2567598960
Short name T753
Test name
Test status
Simulation time 3336210457 ps
CPU time 12.53 seconds
Started Feb 07 01:44:18 PM PST 24
Finished Feb 07 01:44:32 PM PST 24
Peak memory 232568 kb
Host smart-310a775c-937d-4de5-8f88-8f1aaa9b73b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567598960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2567598960
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2291152569
Short name T42
Test name
Test status
Simulation time 63709801 ps
CPU time 0.77 seconds
Started Feb 07 01:44:26 PM PST 24
Finished Feb 07 01:44:27 PM PST 24
Peak memory 205040 kb
Host smart-7cf8a91a-e940-4160-8d5a-a703e063d306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291152569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2291152569
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1743954481
Short name T1092
Test name
Test status
Simulation time 298649411 ps
CPU time 3.87 seconds
Started Feb 07 01:44:22 PM PST 24
Finished Feb 07 01:44:26 PM PST 24
Peak memory 218756 kb
Host smart-3f2dfb92-1798-486b-ac61-eeed97897a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743954481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1743954481
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3949276421
Short name T802
Test name
Test status
Simulation time 13902824 ps
CPU time 0.73 seconds
Started Feb 07 01:44:19 PM PST 24
Finished Feb 07 01:44:20 PM PST 24
Peak memory 205540 kb
Host smart-aeb65452-d82a-41d9-941c-c032de017c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949276421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3949276421
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3976550174
Short name T40
Test name
Test status
Simulation time 40385217224 ps
CPU time 204.45 seconds
Started Feb 07 01:44:23 PM PST 24
Finished Feb 07 01:47:49 PM PST 24
Peak memory 254520 kb
Host smart-7363d543-e606-46b1-9c7f-ee3144d38e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976550174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3976550174
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2843947710
Short name T548
Test name
Test status
Simulation time 11573228927 ps
CPU time 52.48 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:45:20 PM PST 24
Peak memory 233128 kb
Host smart-8328810b-0ad1-491d-863f-2106e549c0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843947710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2843947710
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.277040968
Short name T736
Test name
Test status
Simulation time 37903197379 ps
CPU time 233.26 seconds
Started Feb 07 01:44:19 PM PST 24
Finished Feb 07 01:48:13 PM PST 24
Peak memory 256452 kb
Host smart-2f3ffee8-829d-4420-b5d4-b41edb63767f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277040968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.277040968
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1888373980
Short name T472
Test name
Test status
Simulation time 968174716 ps
CPU time 9.19 seconds
Started Feb 07 01:44:26 PM PST 24
Finished Feb 07 01:44:36 PM PST 24
Peak memory 232964 kb
Host smart-3f5c9fdd-5997-42e0-abcb-5b3192b11a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888373980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1888373980
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2526860975
Short name T776
Test name
Test status
Simulation time 2384671267 ps
CPU time 8.08 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:44:38 PM PST 24
Peak memory 218996 kb
Host smart-c388acc0-9ca2-4614-a51a-7621ca53d497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526860975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2526860975
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1677711033
Short name T610
Test name
Test status
Simulation time 25788395606 ps
CPU time 24.48 seconds
Started Feb 07 01:44:26 PM PST 24
Finished Feb 07 01:44:51 PM PST 24
Peak memory 230480 kb
Host smart-698c62f9-1352-498b-b4dc-5e75dd0dc77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677711033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1677711033
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1615543962
Short name T451
Test name
Test status
Simulation time 936250460 ps
CPU time 4.9 seconds
Started Feb 07 01:44:19 PM PST 24
Finished Feb 07 01:44:25 PM PST 24
Peak memory 233184 kb
Host smart-cf5712c4-481d-48e5-99e5-d0da607bccae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615543962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1615543962
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1016186411
Short name T951
Test name
Test status
Simulation time 3573443619 ps
CPU time 8.17 seconds
Started Feb 07 01:44:28 PM PST 24
Finished Feb 07 01:44:37 PM PST 24
Peak memory 235148 kb
Host smart-7dc0857c-195d-41b1-8380-07d0cfa0e523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016186411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1016186411
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.479801664
Short name T511
Test name
Test status
Simulation time 729649772 ps
CPU time 5.03 seconds
Started Feb 07 01:44:24 PM PST 24
Finished Feb 07 01:44:30 PM PST 24
Peak memory 219944 kb
Host smart-7d4f2999-0fea-4743-9f26-503f3a5729c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=479801664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.479801664
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4129252771
Short name T275
Test name
Test status
Simulation time 9658558165 ps
CPU time 148.39 seconds
Started Feb 07 01:44:19 PM PST 24
Finished Feb 07 01:46:49 PM PST 24
Peak memory 221416 kb
Host smart-360eb96c-554e-489d-8c96-d2891096d325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129252771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4129252771
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3469288659
Short name T825
Test name
Test status
Simulation time 1448343736 ps
CPU time 6.39 seconds
Started Feb 07 01:44:26 PM PST 24
Finished Feb 07 01:44:33 PM PST 24
Peak memory 216476 kb
Host smart-c4841f59-b4d1-439b-803f-a66c4b74a9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469288659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3469288659
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3299945783
Short name T592
Test name
Test status
Simulation time 260447132 ps
CPU time 6.18 seconds
Started Feb 07 01:44:17 PM PST 24
Finished Feb 07 01:44:24 PM PST 24
Peak memory 216448 kb
Host smart-ff5e3751-33b9-444b-b4d2-7ff6c5421e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299945783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3299945783
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.846172120
Short name T439
Test name
Test status
Simulation time 269794342 ps
CPU time 1.04 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:44:32 PM PST 24
Peak memory 206520 kb
Host smart-e44ad75a-7ce2-4820-b38d-01595cff5ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846172120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.846172120
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4276991211
Short name T573
Test name
Test status
Simulation time 1246891497 ps
CPU time 10.39 seconds
Started Feb 07 01:44:19 PM PST 24
Finished Feb 07 01:44:30 PM PST 24
Peak memory 236300 kb
Host smart-e23fe474-4775-495d-bb39-a2d334118289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276991211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4276991211
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2837112617
Short name T732
Test name
Test status
Simulation time 35634677 ps
CPU time 0.66 seconds
Started Feb 07 01:44:25 PM PST 24
Finished Feb 07 01:44:26 PM PST 24
Peak memory 204952 kb
Host smart-b1cd6c82-fe72-4da1-a14f-6583aead816b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837112617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2837112617
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3582447765
Short name T1003
Test name
Test status
Simulation time 224158073 ps
CPU time 2.22 seconds
Started Feb 07 01:44:21 PM PST 24
Finished Feb 07 01:44:24 PM PST 24
Peak memory 216528 kb
Host smart-50786efb-5437-469d-8dee-fbcdd63fe982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582447765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3582447765
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.459649107
Short name T308
Test name
Test status
Simulation time 29970283 ps
CPU time 0.85 seconds
Started Feb 07 01:44:18 PM PST 24
Finished Feb 07 01:44:20 PM PST 24
Peak memory 205544 kb
Host smart-12a34f1e-df2c-48aa-889f-5a617deaac79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459649107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.459649107
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1188352571
Short name T730
Test name
Test status
Simulation time 57102613645 ps
CPU time 149.3 seconds
Started Feb 07 01:44:23 PM PST 24
Finished Feb 07 01:46:53 PM PST 24
Peak memory 244856 kb
Host smart-00c19c93-6ab2-4921-9f34-6b73803245eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188352571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1188352571
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3593745458
Short name T1050
Test name
Test status
Simulation time 8711965812 ps
CPU time 81.85 seconds
Started Feb 07 01:44:28 PM PST 24
Finished Feb 07 01:45:51 PM PST 24
Peak memory 250596 kb
Host smart-a0ab12f9-16a9-4771-9c27-d046160eae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593745458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3593745458
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3925637310
Short name T845
Test name
Test status
Simulation time 12657960695 ps
CPU time 33.54 seconds
Started Feb 07 01:44:17 PM PST 24
Finished Feb 07 01:44:51 PM PST 24
Peak memory 236728 kb
Host smart-91bae13d-d5c2-4ab6-9326-f008e90e0b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925637310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3925637310
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2761167391
Short name T616
Test name
Test status
Simulation time 1563999503 ps
CPU time 4.66 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:44:34 PM PST 24
Peak memory 233736 kb
Host smart-3eb98cfb-869d-444a-a3aa-b50a5a971f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761167391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2761167391
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2128064520
Short name T917
Test name
Test status
Simulation time 3581976659 ps
CPU time 12.63 seconds
Started Feb 07 01:44:18 PM PST 24
Finished Feb 07 01:44:31 PM PST 24
Peak memory 250476 kb
Host smart-4f464ec7-fe01-48da-b1b0-be07f69b3a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128064520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2128064520
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.924361715
Short name T1091
Test name
Test status
Simulation time 24151219576 ps
CPU time 10.75 seconds
Started Feb 07 01:44:16 PM PST 24
Finished Feb 07 01:44:28 PM PST 24
Peak memory 233884 kb
Host smart-70c4d337-a2e6-47f8-9f4c-542bb667acb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924361715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.924361715
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1380113799
Short name T1005
Test name
Test status
Simulation time 3807592827 ps
CPU time 8.95 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:44:38 PM PST 24
Peak memory 229968 kb
Host smart-3004498e-6565-46af-812a-8bdf2b36cb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380113799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1380113799
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.69515499
Short name T968
Test name
Test status
Simulation time 203490365 ps
CPU time 3.97 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:44:32 PM PST 24
Peak memory 221500 kb
Host smart-1aa101f6-b87b-467c-867c-7abeae65bca0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=69515499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direc
t.69515499
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.256661556
Short name T1078
Test name
Test status
Simulation time 25955255612 ps
CPU time 119.36 seconds
Started Feb 07 01:44:30 PM PST 24
Finished Feb 07 01:46:31 PM PST 24
Peak memory 249512 kb
Host smart-289052ed-d093-4fc2-82a5-2c5c4d7a7a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256661556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.256661556
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2368381614
Short name T775
Test name
Test status
Simulation time 46166443359 ps
CPU time 104.35 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:46:13 PM PST 24
Peak memory 216596 kb
Host smart-8c1879f6-6bc5-4434-b4a1-b115e3d671aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368381614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2368381614
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3058453050
Short name T283
Test name
Test status
Simulation time 2685439840 ps
CPU time 12.51 seconds
Started Feb 07 01:44:17 PM PST 24
Finished Feb 07 01:44:30 PM PST 24
Peak memory 216484 kb
Host smart-556e6171-a77c-4dcc-833b-1944fd8491ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058453050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3058453050
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1817670328
Short name T1
Test name
Test status
Simulation time 117887201 ps
CPU time 1.78 seconds
Started Feb 07 01:44:21 PM PST 24
Finished Feb 07 01:44:23 PM PST 24
Peak memory 216692 kb
Host smart-0567d5d0-d0b6-4bbb-81da-d88f84cf61e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817670328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1817670328
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2844331623
Short name T811
Test name
Test status
Simulation time 142196101 ps
CPU time 0.86 seconds
Started Feb 07 01:44:25 PM PST 24
Finished Feb 07 01:44:26 PM PST 24
Peak memory 206516 kb
Host smart-d7fa4955-6f0e-47ea-9ba5-c3717197383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844331623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2844331623
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2692769931
Short name T15
Test name
Test status
Simulation time 166812387 ps
CPU time 4 seconds
Started Feb 07 01:44:15 PM PST 24
Finished Feb 07 01:44:20 PM PST 24
Peak memory 234056 kb
Host smart-e468a7cb-1641-4f31-b3f4-413dbec18460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692769931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2692769931
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3464565574
Short name T294
Test name
Test status
Simulation time 12217990 ps
CPU time 0.75 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:44:40 PM PST 24
Peak memory 204988 kb
Host smart-16b08fda-114d-49a0-a796-941f67ad2fe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464565574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3464565574
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4112503451
Short name T13
Test name
Test status
Simulation time 349101996 ps
CPU time 2.5 seconds
Started Feb 07 01:44:26 PM PST 24
Finished Feb 07 01:44:29 PM PST 24
Peak memory 224744 kb
Host smart-b88e6b44-72f6-4a81-b5ed-8107e311169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112503451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4112503451
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3135472093
Short name T512
Test name
Test status
Simulation time 21787827 ps
CPU time 0.8 seconds
Started Feb 07 01:44:20 PM PST 24
Finished Feb 07 01:44:22 PM PST 24
Peak memory 206168 kb
Host smart-09bbade9-228e-45f1-b340-81a80fbca00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135472093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3135472093
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.71145992
Short name T165
Test name
Test status
Simulation time 11474182172 ps
CPU time 109.35 seconds
Started Feb 07 01:44:20 PM PST 24
Finished Feb 07 01:46:10 PM PST 24
Peak memory 265228 kb
Host smart-c5c05cfd-c3b7-4a1b-bfa4-b52e02de81c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71145992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.71145992
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.59201938
Short name T226
Test name
Test status
Simulation time 106515114577 ps
CPU time 209.97 seconds
Started Feb 07 01:44:21 PM PST 24
Finished Feb 07 01:47:52 PM PST 24
Peak memory 254784 kb
Host smart-658790a2-db25-423f-8deb-bf99c7115da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59201938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.59201938
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.85132716
Short name T558
Test name
Test status
Simulation time 898026405904 ps
CPU time 320.97 seconds
Started Feb 07 01:44:24 PM PST 24
Finished Feb 07 01:49:46 PM PST 24
Peak memory 252192 kb
Host smart-52191183-bf92-4a15-bc09-3e3caaf95f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85132716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.85132716
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3304237502
Short name T1112
Test name
Test status
Simulation time 3692452250 ps
CPU time 6.74 seconds
Started Feb 07 01:44:15 PM PST 24
Finished Feb 07 01:44:23 PM PST 24
Peak memory 233480 kb
Host smart-c2b49f47-01c9-4af0-a6f4-bc1008258805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304237502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3304237502
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1504913514
Short name T158
Test name
Test status
Simulation time 6065778221 ps
CPU time 13.41 seconds
Started Feb 07 01:44:19 PM PST 24
Finished Feb 07 01:44:34 PM PST 24
Peak memory 233040 kb
Host smart-d45f5d5f-64cf-454d-9d7e-9877d486b720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504913514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1504913514
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1090933251
Short name T1010
Test name
Test status
Simulation time 1286685163 ps
CPU time 6.55 seconds
Started Feb 07 01:44:15 PM PST 24
Finished Feb 07 01:44:22 PM PST 24
Peak memory 238484 kb
Host smart-39ce7ca0-faa3-4695-89b6-b6e09ca9692a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090933251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1090933251
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3389496059
Short name T693
Test name
Test status
Simulation time 14541878408 ps
CPU time 15.19 seconds
Started Feb 07 01:44:14 PM PST 24
Finished Feb 07 01:44:30 PM PST 24
Peak memory 234388 kb
Host smart-5f8b6268-ae3f-41db-b8a4-03510ab15fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389496059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3389496059
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3045601720
Short name T644
Test name
Test status
Simulation time 97031146 ps
CPU time 3.83 seconds
Started Feb 07 01:44:18 PM PST 24
Finished Feb 07 01:44:22 PM PST 24
Peak memory 222060 kb
Host smart-91b58c97-ebc9-4e48-b641-6eb706967601
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3045601720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3045601720
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2368593662
Short name T215
Test name
Test status
Simulation time 74169635933 ps
CPU time 136.91 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:46:47 PM PST 24
Peak memory 249480 kb
Host smart-a284321f-81a2-4645-aa38-4fe178502376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368593662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2368593662
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1959751934
Short name T686
Test name
Test status
Simulation time 8382134780 ps
CPU time 67.84 seconds
Started Feb 07 01:44:20 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 216608 kb
Host smart-52336e38-8435-4aac-81a5-b031d5fb4e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959751934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1959751934
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3571107242
Short name T714
Test name
Test status
Simulation time 4172613837 ps
CPU time 12.2 seconds
Started Feb 07 01:44:21 PM PST 24
Finished Feb 07 01:44:34 PM PST 24
Peak memory 216660 kb
Host smart-89482bf9-1e84-4c8a-ad34-26cd0165fa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571107242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3571107242
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.594930031
Short name T582
Test name
Test status
Simulation time 28312705 ps
CPU time 1.73 seconds
Started Feb 07 01:44:32 PM PST 24
Finished Feb 07 01:44:35 PM PST 24
Peak memory 208072 kb
Host smart-df54a7b3-3d1a-4772-8805-2bd3019b60fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594930031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.594930031
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.235048666
Short name T788
Test name
Test status
Simulation time 86281605 ps
CPU time 1.05 seconds
Started Feb 07 01:44:21 PM PST 24
Finished Feb 07 01:44:23 PM PST 24
Peak memory 206512 kb
Host smart-98eec8dd-c879-461c-af76-40614e2036f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235048666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.235048666
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4244698921
Short name T1098
Test name
Test status
Simulation time 40777214 ps
CPU time 2.13 seconds
Started Feb 07 01:44:24 PM PST 24
Finished Feb 07 01:44:27 PM PST 24
Peak memory 216932 kb
Host smart-51e9cd59-ba49-4009-8c68-d961aaf5245c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244698921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4244698921
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1728021593
Short name T937
Test name
Test status
Simulation time 159895025 ps
CPU time 0.69 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:44:31 PM PST 24
Peak memory 204988 kb
Host smart-69efde29-fd15-4da7-82b6-410e60555b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728021593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1728021593
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.671745498
Short name T167
Test name
Test status
Simulation time 370697496 ps
CPU time 3.39 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:44:39 PM PST 24
Peak memory 220748 kb
Host smart-f61fd341-8b25-44c3-9453-f348d500a525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671745498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.671745498
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1344264019
Short name T550
Test name
Test status
Simulation time 97610730 ps
CPU time 0.76 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:44:29 PM PST 24
Peak memory 205552 kb
Host smart-a97a9ad3-95e9-4ffa-b6ca-f80c58262348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344264019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1344264019
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.30776838
Short name T591
Test name
Test status
Simulation time 77930950211 ps
CPU time 192.09 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:47:43 PM PST 24
Peak memory 256044 kb
Host smart-312d991b-d8f1-41bd-95d1-e35bcf483f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30776838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.30776838
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3483124232
Short name T933
Test name
Test status
Simulation time 4358985107 ps
CPU time 33.97 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:45:05 PM PST 24
Peak memory 234928 kb
Host smart-d5e1f3b9-0388-4b48-b7e3-aecb425f9e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483124232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3483124232
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.798207967
Short name T6
Test name
Test status
Simulation time 26056049305 ps
CPU time 187.26 seconds
Started Feb 07 01:44:28 PM PST 24
Finished Feb 07 01:47:36 PM PST 24
Peak memory 241340 kb
Host smart-c0ee51ed-b264-4fe5-b443-0c644af2e88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798207967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.798207967
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3811849162
Short name T1033
Test name
Test status
Simulation time 1736676593 ps
CPU time 13.35 seconds
Started Feb 07 01:44:40 PM PST 24
Finished Feb 07 01:44:54 PM PST 24
Peak memory 235136 kb
Host smart-91c18100-745a-4242-b0cd-4468068cea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811849162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3811849162
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3319609038
Short name T750
Test name
Test status
Simulation time 1194140798 ps
CPU time 7.71 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:44:47 PM PST 24
Peak memory 233576 kb
Host smart-33fa464c-81a9-4e4d-85f3-976c047077d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319609038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3319609038
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.342172503
Short name T754
Test name
Test status
Simulation time 4255555819 ps
CPU time 9.62 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:44:38 PM PST 24
Peak memory 229528 kb
Host smart-a68ea7e0-5739-456d-9bd3-512bb296388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342172503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.342172503
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1943238524
Short name T192
Test name
Test status
Simulation time 1702787066 ps
CPU time 5.89 seconds
Started Feb 07 01:44:23 PM PST 24
Finished Feb 07 01:44:29 PM PST 24
Peak memory 233320 kb
Host smart-97a20bd9-bf27-465d-93fa-472b9ae6b56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943238524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1943238524
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2435474333
Short name T493
Test name
Test status
Simulation time 15273370782 ps
CPU time 12.72 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:44:48 PM PST 24
Peak memory 234160 kb
Host smart-247e9110-edc2-4f7e-ad9f-5bd15d5e70e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435474333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2435474333
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2589475924
Short name T438
Test name
Test status
Simulation time 512501114 ps
CPU time 3.12 seconds
Started Feb 07 01:44:30 PM PST 24
Finished Feb 07 01:44:34 PM PST 24
Peak memory 219008 kb
Host smart-f1738c7e-b421-49e9-9fca-f65807b520c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2589475924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2589475924
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.754349331
Short name T220
Test name
Test status
Simulation time 81333322120 ps
CPU time 237.1 seconds
Started Feb 07 01:44:31 PM PST 24
Finished Feb 07 01:48:29 PM PST 24
Peak memory 272008 kb
Host smart-bbf9e45d-bfcb-4379-a92c-ce1edbf679d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754349331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.754349331
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1724655755
Short name T837
Test name
Test status
Simulation time 10658956214 ps
CPU time 39.94 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:45:08 PM PST 24
Peak memory 216688 kb
Host smart-bc873f96-5e76-41e0-9a03-d3a5c3a1aec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724655755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1724655755
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.502202647
Short name T504
Test name
Test status
Simulation time 2072792435 ps
CPU time 4.51 seconds
Started Feb 07 01:44:40 PM PST 24
Finished Feb 07 01:44:45 PM PST 24
Peak memory 216304 kb
Host smart-c88a4113-cb15-4f41-8070-80f444fb588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502202647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.502202647
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1652265041
Short name T604
Test name
Test status
Simulation time 100126681 ps
CPU time 1.42 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:44:36 PM PST 24
Peak memory 207856 kb
Host smart-7eef2316-94aa-4006-87cf-fa4fa180e079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652265041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1652265041
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1103235765
Short name T769
Test name
Test status
Simulation time 85592605 ps
CPU time 0.79 seconds
Started Feb 07 01:44:23 PM PST 24
Finished Feb 07 01:44:24 PM PST 24
Peak memory 205436 kb
Host smart-2a5c63fb-90e4-4e01-8eab-34c95fbb1416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103235765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1103235765
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3992793522
Short name T1100
Test name
Test status
Simulation time 652251815 ps
CPU time 2.85 seconds
Started Feb 07 01:44:31 PM PST 24
Finished Feb 07 01:44:35 PM PST 24
Peak memory 233972 kb
Host smart-8ee61ba9-f9cc-4f7e-a0af-32a758f374b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992793522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3992793522
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3561553433
Short name T430
Test name
Test status
Simulation time 14155812 ps
CPU time 0.71 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:44:44 PM PST 24
Peak memory 205048 kb
Host smart-2cd97671-ce7d-4edb-b4e0-1c7a61de4037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561553433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3561553433
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1233884123
Short name T503
Test name
Test status
Simulation time 338274238 ps
CPU time 4.52 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:44:35 PM PST 24
Peak memory 220952 kb
Host smart-9df10405-2924-42cb-ba9f-01712db74e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233884123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1233884123
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1750416055
Short name T909
Test name
Test status
Simulation time 112442169 ps
CPU time 0.76 seconds
Started Feb 07 01:44:30 PM PST 24
Finished Feb 07 01:44:32 PM PST 24
Peak memory 206568 kb
Host smart-eb9b9eac-b5f4-4bce-bd3c-41e4a0bd0ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750416055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1750416055
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3560482071
Short name T56
Test name
Test status
Simulation time 3194170884 ps
CPU time 52.72 seconds
Started Feb 07 01:44:28 PM PST 24
Finished Feb 07 01:45:22 PM PST 24
Peak memory 252996 kb
Host smart-e95d70bf-41e0-4886-abe8-d80d667d8b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560482071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3560482071
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3146795049
Short name T919
Test name
Test status
Simulation time 109454825191 ps
CPU time 120.8 seconds
Started Feb 07 01:44:40 PM PST 24
Finished Feb 07 01:46:42 PM PST 24
Peak memory 250860 kb
Host smart-242bb049-60e3-4ce1-a152-a38d78b1685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146795049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3146795049
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3942694844
Short name T799
Test name
Test status
Simulation time 28392617793 ps
CPU time 98.81 seconds
Started Feb 07 01:44:23 PM PST 24
Finished Feb 07 01:46:03 PM PST 24
Peak memory 234312 kb
Host smart-d0f2c142-6179-4db5-b34b-c534af4eab74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942694844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3942694844
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1556100771
Short name T270
Test name
Test status
Simulation time 17343937461 ps
CPU time 29.31 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:45:04 PM PST 24
Peak memory 238532 kb
Host smart-6cf30b7d-0e18-41ec-ae83-297fbad2adc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556100771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1556100771
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.975288947
Short name T658
Test name
Test status
Simulation time 232939810 ps
CPU time 5.11 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:44:35 PM PST 24
Peak memory 233720 kb
Host smart-872117b4-4187-4b60-9740-e7d4b678bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975288947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.975288947
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1071014918
Short name T934
Test name
Test status
Simulation time 6546608323 ps
CPU time 23.53 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:44:59 PM PST 24
Peak memory 234000 kb
Host smart-db6c73c0-a8c4-452e-9223-a7e5eb062a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071014918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1071014918
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3994702243
Short name T852
Test name
Test status
Simulation time 6250490463 ps
CPU time 11.64 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:44:42 PM PST 24
Peak memory 234236 kb
Host smart-56a3ade1-7f1c-4586-8674-a4019af33e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994702243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3994702243
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1304044985
Short name T996
Test name
Test status
Simulation time 11195521959 ps
CPU time 11 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:44:46 PM PST 24
Peak memory 238076 kb
Host smart-12c28ebf-35b1-4f99-bf0d-4e6d3685ad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304044985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1304044985
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2229724874
Short name T506
Test name
Test status
Simulation time 1818641484 ps
CPU time 4.1 seconds
Started Feb 07 01:44:32 PM PST 24
Finished Feb 07 01:44:38 PM PST 24
Peak memory 216268 kb
Host smart-c8afa3ed-fa8a-43c9-8b39-7440708e4251
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2229724874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2229724874
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3758370819
Short name T702
Test name
Test status
Simulation time 55842832218 ps
CPU time 58.76 seconds
Started Feb 07 01:44:28 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 219028 kb
Host smart-4e327d53-ec24-4a12-9461-a8a8b90fa901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758370819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3758370819
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2341786883
Short name T683
Test name
Test status
Simulation time 29908414300 ps
CPU time 31.33 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:45:10 PM PST 24
Peak memory 216552 kb
Host smart-f507ef3d-d297-49ec-9351-14d873b0f14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341786883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2341786883
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3143073661
Short name T653
Test name
Test status
Simulation time 1006023506 ps
CPU time 10.92 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:44:41 PM PST 24
Peak memory 208676 kb
Host smart-8a4b10cb-eb02-4f03-9914-e2d6b6438754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143073661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3143073661
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.924158677
Short name T597
Test name
Test status
Simulation time 78810412 ps
CPU time 1.03 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:44:40 PM PST 24
Peak memory 206484 kb
Host smart-1e6e97ad-7695-4a5b-85cd-b30c0a1b1a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924158677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.924158677
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2153675167
Short name T973
Test name
Test status
Simulation time 1717287016 ps
CPU time 7.24 seconds
Started Feb 07 01:44:30 PM PST 24
Finished Feb 07 01:44:39 PM PST 24
Peak memory 234336 kb
Host smart-755f6f48-032c-4923-98fb-773b5d4081cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153675167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2153675167
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1829895750
Short name T289
Test name
Test status
Simulation time 39856264 ps
CPU time 0.69 seconds
Started Feb 07 01:44:30 PM PST 24
Finished Feb 07 01:44:32 PM PST 24
Peak memory 204476 kb
Host smart-bd5cab3c-328b-4ead-986f-800b248f2dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829895750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1829895750
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3680026391
Short name T1114
Test name
Test status
Simulation time 3585329934 ps
CPU time 7.52 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:44:43 PM PST 24
Peak memory 233760 kb
Host smart-e155a0f4-874a-44e8-8eb6-3386b4548214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680026391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3680026391
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3550520305
Short name T847
Test name
Test status
Simulation time 20686486 ps
CPU time 0.76 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:44:36 PM PST 24
Peak memory 205040 kb
Host smart-1772acd8-2e92-4ffc-ba3b-e8b53f4bc23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550520305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3550520305
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1305068942
Short name T1026
Test name
Test status
Simulation time 27990616959 ps
CPU time 65.14 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:45:40 PM PST 24
Peak memory 256328 kb
Host smart-f48915c1-b7cc-45c0-8fd4-2876c498337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305068942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1305068942
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.340346119
Short name T219
Test name
Test status
Simulation time 19942618575 ps
CPU time 57.5 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:45:33 PM PST 24
Peak memory 249516 kb
Host smart-e680ff5d-e9d4-4a9c-afd7-3bde25662c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340346119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.340346119
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3896197003
Short name T929
Test name
Test status
Simulation time 20028445953 ps
CPU time 30.34 seconds
Started Feb 07 01:44:30 PM PST 24
Finished Feb 07 01:45:02 PM PST 24
Peak memory 241132 kb
Host smart-aa17e6cd-e821-4d72-9fe0-46d457099cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896197003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3896197003
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.212009022
Short name T68
Test name
Test status
Simulation time 5906089795 ps
CPU time 6.46 seconds
Started Feb 07 01:44:27 PM PST 24
Finished Feb 07 01:44:35 PM PST 24
Peak memory 233120 kb
Host smart-14630626-b3f3-4b79-911b-b1e446e8e593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212009022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.212009022
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4029337495
Short name T806
Test name
Test status
Simulation time 1150482966 ps
CPU time 9.76 seconds
Started Feb 07 01:44:28 PM PST 24
Finished Feb 07 01:44:39 PM PST 24
Peak memory 234324 kb
Host smart-44879541-d5be-4dcf-b391-bbb3b16d8aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029337495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4029337495
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.289236761
Short name T161
Test name
Test status
Simulation time 207302084 ps
CPU time 4 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:44:47 PM PST 24
Peak memory 232964 kb
Host smart-2799d77f-eb65-482f-b891-27e2ce92600f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289236761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.289236761
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.450782206
Short name T189
Test name
Test status
Simulation time 3515176204 ps
CPU time 12.62 seconds
Started Feb 07 01:44:30 PM PST 24
Finished Feb 07 01:44:44 PM PST 24
Peak memory 218780 kb
Host smart-e0f729ea-bad6-42a4-a60b-094dfd35b11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450782206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.450782206
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.258265771
Short name T1070
Test name
Test status
Simulation time 2608795186 ps
CPU time 4.57 seconds
Started Feb 07 01:44:32 PM PST 24
Finished Feb 07 01:44:38 PM PST 24
Peak memory 220180 kb
Host smart-96e4b211-af69-46f7-b524-90bd73a491b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=258265771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.258265771
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1380319789
Short name T1011
Test name
Test status
Simulation time 443127498836 ps
CPU time 383.65 seconds
Started Feb 07 01:44:32 PM PST 24
Finished Feb 07 01:50:57 PM PST 24
Peak memory 265340 kb
Host smart-3b8e2f9d-74cd-441b-bdc3-0f800c132409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380319789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1380319789
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1554636912
Short name T1031
Test name
Test status
Simulation time 18608558543 ps
CPU time 20.68 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:44:51 PM PST 24
Peak memory 216536 kb
Host smart-b397b0d7-b1a1-44cf-acc1-1a470e57a5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554636912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1554636912
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2871719835
Short name T1105
Test name
Test status
Simulation time 402046937 ps
CPU time 1.95 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:44:45 PM PST 24
Peak memory 208572 kb
Host smart-f7d3a1cd-bbb2-4d62-a358-69b4232384b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871719835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2871719835
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1337650231
Short name T821
Test name
Test status
Simulation time 285196212 ps
CPU time 0.94 seconds
Started Feb 07 01:44:28 PM PST 24
Finished Feb 07 01:44:30 PM PST 24
Peak memory 206504 kb
Host smart-894a7292-3f06-44e2-9575-f2fd8bd6ec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337650231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1337650231
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.447333908
Short name T782
Test name
Test status
Simulation time 597986609 ps
CPU time 5.62 seconds
Started Feb 07 01:44:29 PM PST 24
Finished Feb 07 01:44:36 PM PST 24
Peak memory 219592 kb
Host smart-eadfab8a-1961-459e-835c-3e0527400403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447333908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.447333908
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.289893368
Short name T643
Test name
Test status
Simulation time 34285557 ps
CPU time 0.7 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:44:44 PM PST 24
Peak memory 204428 kb
Host smart-dccef98a-f6a6-469c-8462-300f49cc14f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289893368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.289893368
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.260092010
Short name T432
Test name
Test status
Simulation time 577810146 ps
CPU time 3.9 seconds
Started Feb 07 01:44:33 PM PST 24
Finished Feb 07 01:44:38 PM PST 24
Peak memory 217888 kb
Host smart-680a9141-3082-4d34-b856-141175d79adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260092010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.260092010
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3984365663
Short name T684
Test name
Test status
Simulation time 73105873 ps
CPU time 0.77 seconds
Started Feb 07 01:44:31 PM PST 24
Finished Feb 07 01:44:33 PM PST 24
Peak memory 205192 kb
Host smart-e5c00c43-718e-49ec-b847-b9277c6d3e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984365663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3984365663
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1185114871
Short name T557
Test name
Test status
Simulation time 152913955056 ps
CPU time 92.93 seconds
Started Feb 07 01:44:36 PM PST 24
Finished Feb 07 01:46:09 PM PST 24
Peak memory 254480 kb
Host smart-61a24685-68df-4043-8d1a-76fb86632885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185114871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1185114871
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.663281186
Short name T520
Test name
Test status
Simulation time 4117468178 ps
CPU time 24.28 seconds
Started Feb 07 01:44:43 PM PST 24
Finished Feb 07 01:45:08 PM PST 24
Peak memory 233900 kb
Host smart-801621d6-dab6-440a-8277-a964093c04db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663281186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.663281186
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3095759559
Short name T488
Test name
Test status
Simulation time 805447912 ps
CPU time 4.96 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:44:47 PM PST 24
Peak memory 233944 kb
Host smart-27c45270-2407-4668-9211-0f09d39f7fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095759559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3095759559
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1813086492
Short name T631
Test name
Test status
Simulation time 1116075967 ps
CPU time 10.09 seconds
Started Feb 07 01:44:35 PM PST 24
Finished Feb 07 01:44:46 PM PST 24
Peak memory 234644 kb
Host smart-784dc1f8-bd86-488b-921d-a53b9c76a3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813086492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1813086492
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1261939264
Short name T534
Test name
Test status
Simulation time 659327344 ps
CPU time 8.63 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:44:52 PM PST 24
Peak memory 226900 kb
Host smart-5adceb75-364f-4ff4-add5-9df13ace6faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261939264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1261939264
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2005456693
Short name T261
Test name
Test status
Simulation time 8877688376 ps
CPU time 12.38 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:44:56 PM PST 24
Peak memory 236556 kb
Host smart-3d6f0716-589d-4782-aad1-bbc5c1352692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005456693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2005456693
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1038582239
Short name T1097
Test name
Test status
Simulation time 239028907 ps
CPU time 3.93 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:44:47 PM PST 24
Peak memory 222676 kb
Host smart-544c4089-1686-4640-8d43-d7f6b9ef2456
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1038582239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1038582239
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.626822658
Short name T221
Test name
Test status
Simulation time 10438221607 ps
CPU time 126.87 seconds
Started Feb 07 01:44:31 PM PST 24
Finished Feb 07 01:46:39 PM PST 24
Peak memory 265716 kb
Host smart-ad35e914-4953-40aa-998a-91c7fe31e1b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626822658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.626822658
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1401024151
Short name T815
Test name
Test status
Simulation time 8126816735 ps
CPU time 31.88 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:45:11 PM PST 24
Peak memory 216256 kb
Host smart-1e53cd7a-1cf0-4138-a10d-30ac10220866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401024151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1401024151
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2154934132
Short name T65
Test name
Test status
Simulation time 1247242789 ps
CPU time 4.85 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:44:44 PM PST 24
Peak memory 208208 kb
Host smart-bf3c1f42-b85f-433e-a9d9-cc1cbb81b13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154934132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2154934132
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1083374252
Short name T619
Test name
Test status
Simulation time 245107645 ps
CPU time 1.4 seconds
Started Feb 07 01:44:43 PM PST 24
Finished Feb 07 01:44:46 PM PST 24
Peak memory 208516 kb
Host smart-eef7410f-0f8c-4ee7-beeb-d85c8bf8ec86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083374252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1083374252
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.452802112
Short name T691
Test name
Test status
Simulation time 32861077 ps
CPU time 0.9 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:44:40 PM PST 24
Peak memory 206312 kb
Host smart-3e9288e5-c9ad-48de-a66c-548bbe358b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452802112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.452802112
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3984144064
Short name T247
Test name
Test status
Simulation time 4570989263 ps
CPU time 20.38 seconds
Started Feb 07 01:44:31 PM PST 24
Finished Feb 07 01:44:53 PM PST 24
Peak memory 234912 kb
Host smart-37842e58-e56d-4f9f-9539-867ae4055605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984144064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3984144064
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2640511789
Short name T1068
Test name
Test status
Simulation time 18045256 ps
CPU time 0.76 seconds
Started Feb 07 01:42:34 PM PST 24
Finished Feb 07 01:42:35 PM PST 24
Peak memory 205032 kb
Host smart-b328afd7-77a5-4226-89de-2ed714a1c00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640511789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
640511789
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2847285848
Short name T468
Test name
Test status
Simulation time 118587486 ps
CPU time 2.25 seconds
Started Feb 07 01:42:40 PM PST 24
Finished Feb 07 01:42:43 PM PST 24
Peak memory 224700 kb
Host smart-a793df40-536f-480b-ab4b-7655214ee8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847285848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2847285848
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1205955346
Short name T561
Test name
Test status
Simulation time 176505886 ps
CPU time 0.82 seconds
Started Feb 07 01:42:33 PM PST 24
Finished Feb 07 01:42:34 PM PST 24
Peak memory 206244 kb
Host smart-84266275-72ab-47e6-badc-98073916097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205955346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1205955346
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3896721004
Short name T896
Test name
Test status
Simulation time 16036537772 ps
CPU time 38.93 seconds
Started Feb 07 01:42:48 PM PST 24
Finished Feb 07 01:43:28 PM PST 24
Peak memory 246448 kb
Host smart-ae700580-ec6a-45fb-b053-315fbd2e6268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896721004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3896721004
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.225252462
Short name T276
Test name
Test status
Simulation time 111950926649 ps
CPU time 178.73 seconds
Started Feb 07 01:42:40 PM PST 24
Finished Feb 07 01:45:40 PM PST 24
Peak memory 249784 kb
Host smart-0783be62-c468-4c9c-b8de-02a766419d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225252462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.225252462
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3956641918
Short name T559
Test name
Test status
Simulation time 81683977741 ps
CPU time 138.66 seconds
Started Feb 07 01:42:34 PM PST 24
Finished Feb 07 01:44:54 PM PST 24
Peak memory 255584 kb
Host smart-f2835e45-fc6a-4499-8c76-47df95ae67d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956641918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3956641918
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.730725673
Short name T680
Test name
Test status
Simulation time 7232839819 ps
CPU time 36.39 seconds
Started Feb 07 01:42:50 PM PST 24
Finished Feb 07 01:43:28 PM PST 24
Peak memory 233036 kb
Host smart-a2674525-5808-4ead-884b-3d373c372d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730725673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.730725673
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3446593694
Short name T174
Test name
Test status
Simulation time 372361345 ps
CPU time 2.47 seconds
Started Feb 07 01:42:39 PM PST 24
Finished Feb 07 01:42:42 PM PST 24
Peak memory 224648 kb
Host smart-046f6dcf-59e9-41ef-82e1-99e9163b4bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446593694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3446593694
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3596171849
Short name T642
Test name
Test status
Simulation time 51091151573 ps
CPU time 36.14 seconds
Started Feb 07 01:42:45 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 233080 kb
Host smart-ea77a6df-e0ec-47ea-8a72-7f75b805588d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596171849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3596171849
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2548432748
Short name T999
Test name
Test status
Simulation time 216469794 ps
CPU time 0.99 seconds
Started Feb 07 01:42:40 PM PST 24
Finished Feb 07 01:42:42 PM PST 24
Peak memory 217876 kb
Host smart-efa79f4f-6b7d-4346-935b-e273a10af9d8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548432748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2548432748
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.626934712
Short name T564
Test name
Test status
Simulation time 3205890174 ps
CPU time 12.74 seconds
Started Feb 07 01:42:37 PM PST 24
Finished Feb 07 01:42:50 PM PST 24
Peak memory 249268 kb
Host smart-36e7ff3c-daa4-4f7e-9718-8e92dd19d0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626934712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
626934712
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.714609953
Short name T982
Test name
Test status
Simulation time 8670179873 ps
CPU time 14.75 seconds
Started Feb 07 01:42:35 PM PST 24
Finished Feb 07 01:42:51 PM PST 24
Peak memory 235628 kb
Host smart-4b960837-c600-4a00-9cb7-c83012d9aded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714609953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.714609953
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.1166868791
Short name T1088
Test name
Test status
Simulation time 17173075 ps
CPU time 0.73 seconds
Started Feb 07 01:42:32 PM PST 24
Finished Feb 07 01:42:34 PM PST 24
Peak memory 216352 kb
Host smart-d22ec7dc-7aa6-4510-ba7c-9c06a31b756b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166868791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.1166868791
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1571594103
Short name T3
Test name
Test status
Simulation time 3960557728 ps
CPU time 5.25 seconds
Started Feb 07 01:42:34 PM PST 24
Finished Feb 07 01:42:40 PM PST 24
Peak memory 216780 kb
Host smart-b42df304-0cfb-4acf-83c4-4f84d30f16f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1571594103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1571594103
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.202031565
Short name T50
Test name
Test status
Simulation time 30521632 ps
CPU time 0.95 seconds
Started Feb 07 01:42:33 PM PST 24
Finished Feb 07 01:42:35 PM PST 24
Peak memory 234652 kb
Host smart-b3eb5d30-4465-45d7-8e55-4d318f3c0b43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202031565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.202031565
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.971355882
Short name T1073
Test name
Test status
Simulation time 15000109462 ps
CPU time 19.21 seconds
Started Feb 07 01:42:34 PM PST 24
Finished Feb 07 01:42:54 PM PST 24
Peak memory 216892 kb
Host smart-077bf3b6-0c0c-4214-945f-126919dab037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971355882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.971355882
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1347274190
Short name T568
Test name
Test status
Simulation time 18134116795 ps
CPU time 18.51 seconds
Started Feb 07 01:42:36 PM PST 24
Finished Feb 07 01:42:55 PM PST 24
Peak memory 216552 kb
Host smart-db0c7b0d-4247-46b3-8c04-06889f96fdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347274190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1347274190
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3944249275
Short name T547
Test name
Test status
Simulation time 38111142 ps
CPU time 1.24 seconds
Started Feb 07 01:42:39 PM PST 24
Finished Feb 07 01:42:41 PM PST 24
Peak memory 208224 kb
Host smart-3bd447be-e56c-42c9-989c-46cbef09bced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944249275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3944249275
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3361190150
Short name T715
Test name
Test status
Simulation time 81150483 ps
CPU time 0.92 seconds
Started Feb 07 01:42:36 PM PST 24
Finished Feb 07 01:42:38 PM PST 24
Peak memory 205488 kb
Host smart-67a3048c-c85d-41a4-8578-65e0e7aad41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361190150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3361190150
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2481105643
Short name T820
Test name
Test status
Simulation time 2483664595 ps
CPU time 4.13 seconds
Started Feb 07 01:42:33 PM PST 24
Finished Feb 07 01:42:38 PM PST 24
Peak memory 233992 kb
Host smart-b897a6e7-25d8-4031-b830-aafba3d9e922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481105643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2481105643
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1553751295
Short name T860
Test name
Test status
Simulation time 17294900 ps
CPU time 0.72 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:44:42 PM PST 24
Peak memory 204972 kb
Host smart-fd372b5b-9c17-4478-95d5-a25143c42f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553751295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1553751295
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3556962339
Short name T665
Test name
Test status
Simulation time 650221013 ps
CPU time 3.82 seconds
Started Feb 07 01:44:39 PM PST 24
Finished Feb 07 01:44:43 PM PST 24
Peak memory 218036 kb
Host smart-318a770c-305f-4b38-affc-2797d3fe73e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556962339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3556962339
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3802127786
Short name T936
Test name
Test status
Simulation time 27875256 ps
CPU time 0.77 seconds
Started Feb 07 01:44:31 PM PST 24
Finished Feb 07 01:44:33 PM PST 24
Peak memory 205540 kb
Host smart-82cbd967-1166-40ee-90e5-f4a1e803763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802127786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3802127786
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1018475127
Short name T540
Test name
Test status
Simulation time 46384697556 ps
CPU time 53.92 seconds
Started Feb 07 01:44:39 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 236060 kb
Host smart-285837c1-5f0b-48fd-863d-2a74445d40f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018475127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1018475127
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3505429658
Short name T1008
Test name
Test status
Simulation time 34903858309 ps
CPU time 145.15 seconds
Started Feb 07 01:44:46 PM PST 24
Finished Feb 07 01:47:12 PM PST 24
Peak memory 249544 kb
Host smart-feff20ef-ee22-4c30-8907-94004cd5b177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505429658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3505429658
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1627285834
Short name T772
Test name
Test status
Simulation time 7747561487 ps
CPU time 28.97 seconds
Started Feb 07 01:44:45 PM PST 24
Finished Feb 07 01:45:14 PM PST 24
Peak memory 247308 kb
Host smart-c38c9cb2-5140-4a22-aaac-43ed7196058e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627285834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1627285834
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.421857202
Short name T500
Test name
Test status
Simulation time 2460125426 ps
CPU time 9.43 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:44:44 PM PST 24
Peak memory 233724 kb
Host smart-433ea29c-3cd2-438b-a95e-a4a92b90ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421857202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.421857202
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2810696298
Short name T1014
Test name
Test status
Simulation time 1386412453 ps
CPU time 5.91 seconds
Started Feb 07 01:44:33 PM PST 24
Finished Feb 07 01:44:40 PM PST 24
Peak memory 217548 kb
Host smart-556a4f67-6bee-4ab3-92d3-23892991ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810696298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2810696298
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1147639348
Short name T510
Test name
Test status
Simulation time 104166553 ps
CPU time 2.31 seconds
Started Feb 07 01:44:34 PM PST 24
Finished Feb 07 01:44:37 PM PST 24
Peak memory 216704 kb
Host smart-9f1e9c6d-c056-4206-926e-cc8ca7c7106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147639348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1147639348
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1395062090
Short name T450
Test name
Test status
Simulation time 3012301513 ps
CPU time 4.94 seconds
Started Feb 07 01:44:31 PM PST 24
Finished Feb 07 01:44:37 PM PST 24
Peak memory 233220 kb
Host smart-6781a94f-33a5-46cf-9621-490949baa2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395062090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1395062090
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1521530758
Short name T522
Test name
Test status
Simulation time 121790591 ps
CPU time 3.51 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:44:42 PM PST 24
Peak memory 222212 kb
Host smart-05464ab1-5480-4d84-9222-4b3f1a7d0391
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1521530758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1521530758
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3951492000
Short name T723
Test name
Test status
Simulation time 113267243612 ps
CPU time 388.81 seconds
Started Feb 07 01:44:40 PM PST 24
Finished Feb 07 01:51:09 PM PST 24
Peak memory 249432 kb
Host smart-3a90c15a-28ad-4e13-ac18-817041da411f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951492000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3951492000
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3930911454
Short name T277
Test name
Test status
Simulation time 18755883269 ps
CPU time 40.1 seconds
Started Feb 07 01:44:39 PM PST 24
Finished Feb 07 01:45:20 PM PST 24
Peak memory 216668 kb
Host smart-7b287a0a-2406-4150-aeaa-1906362ef9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930911454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3930911454
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.140103516
Short name T435
Test name
Test status
Simulation time 14425842901 ps
CPU time 19.15 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:44:58 PM PST 24
Peak memory 216588 kb
Host smart-5ab8f280-1b45-4790-846a-057260d6ca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140103516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.140103516
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2236820715
Short name T898
Test name
Test status
Simulation time 362810095 ps
CPU time 4.63 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:44:46 PM PST 24
Peak memory 216892 kb
Host smart-928ee5a6-2058-40ae-b70c-f4cec3d5b2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236820715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2236820715
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3753159936
Short name T804
Test name
Test status
Simulation time 33532673 ps
CPU time 0.87 seconds
Started Feb 07 01:44:31 PM PST 24
Finished Feb 07 01:44:33 PM PST 24
Peak memory 205488 kb
Host smart-aabb0eff-e8b8-4b27-96dc-69e21d4fe5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753159936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3753159936
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1226092957
Short name T260
Test name
Test status
Simulation time 23084413258 ps
CPU time 23.33 seconds
Started Feb 07 01:44:33 PM PST 24
Finished Feb 07 01:44:58 PM PST 24
Peak memory 253124 kb
Host smart-4d5461e7-eb5e-40b4-a373-16cfdc2172f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226092957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1226092957
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.784978934
Short name T710
Test name
Test status
Simulation time 15666720 ps
CPU time 0.73 seconds
Started Feb 07 01:44:46 PM PST 24
Finished Feb 07 01:44:48 PM PST 24
Peak memory 205012 kb
Host smart-f3769b70-ad00-4fc4-b13a-a0fe8f807d3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784978934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.784978934
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2774285374
Short name T1109
Test name
Test status
Simulation time 3493676023 ps
CPU time 4.99 seconds
Started Feb 07 01:44:40 PM PST 24
Finished Feb 07 01:44:45 PM PST 24
Peak memory 233780 kb
Host smart-00b94bd4-94e2-4e50-9caa-99d88a129854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774285374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2774285374
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1529476272
Short name T41
Test name
Test status
Simulation time 13954637 ps
CPU time 0.78 seconds
Started Feb 07 01:44:39 PM PST 24
Finished Feb 07 01:44:41 PM PST 24
Peak memory 206256 kb
Host smart-1c856309-2ad3-42bd-94be-63f9b43752c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529476272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1529476272
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2095367502
Short name T848
Test name
Test status
Simulation time 24961588066 ps
CPU time 31.56 seconds
Started Feb 07 01:44:46 PM PST 24
Finished Feb 07 01:45:18 PM PST 24
Peak memory 240956 kb
Host smart-6383e6d9-d27a-49db-a210-ce5d786ea0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095367502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2095367502
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2805529476
Short name T1038
Test name
Test status
Simulation time 97459030930 ps
CPU time 149.45 seconds
Started Feb 07 01:44:50 PM PST 24
Finished Feb 07 01:47:20 PM PST 24
Peak memory 249280 kb
Host smart-4e13d6e5-278e-42a3-8dcb-2f5860a44332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805529476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2805529476
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.172696168
Short name T36
Test name
Test status
Simulation time 29039730342 ps
CPU time 198.34 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:48:02 PM PST 24
Peak memory 250592 kb
Host smart-d659b21b-8ad9-4b6d-b1e4-3a5151a28b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172696168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.172696168
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1386749898
Short name T677
Test name
Test status
Simulation time 7860136597 ps
CPU time 42.76 seconds
Started Feb 07 01:44:44 PM PST 24
Finished Feb 07 01:45:27 PM PST 24
Peak memory 245428 kb
Host smart-43102d30-4ba5-408f-82a8-376974f2657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386749898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1386749898
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2876576223
Short name T889
Test name
Test status
Simulation time 276871032 ps
CPU time 2.96 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:44:42 PM PST 24
Peak memory 217924 kb
Host smart-a820f4b8-46a4-4ec3-9adc-66eccdf3b4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876576223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2876576223
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2441685387
Short name T1029
Test name
Test status
Simulation time 11525730625 ps
CPU time 28.07 seconds
Started Feb 07 01:44:40 PM PST 24
Finished Feb 07 01:45:08 PM PST 24
Peak memory 231112 kb
Host smart-5e23e84c-d06c-476c-99b1-69991d83bfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441685387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2441685387
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2601135486
Short name T1096
Test name
Test status
Simulation time 1496108704 ps
CPU time 9.73 seconds
Started Feb 07 01:44:39 PM PST 24
Finished Feb 07 01:44:50 PM PST 24
Peak memory 235916 kb
Host smart-aa83ad19-591a-4d6c-84ed-d2004ad8593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601135486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2601135486
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1951998884
Short name T254
Test name
Test status
Simulation time 3720501484 ps
CPU time 12.58 seconds
Started Feb 07 01:44:44 PM PST 24
Finished Feb 07 01:44:57 PM PST 24
Peak memory 233752 kb
Host smart-d63b795b-9356-43b0-89a0-906d9664130a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951998884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1951998884
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1612942849
Short name T881
Test name
Test status
Simulation time 222629581 ps
CPU time 3.79 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:44:46 PM PST 24
Peak memory 222840 kb
Host smart-88323f42-2c10-41b3-998c-dc3afd03ed5f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1612942849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1612942849
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1719799673
Short name T232
Test name
Test status
Simulation time 39110788283 ps
CPU time 333.12 seconds
Started Feb 07 01:44:45 PM PST 24
Finished Feb 07 01:50:18 PM PST 24
Peak memory 279084 kb
Host smart-202c78af-d3bc-492e-b593-13844aed7223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719799673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1719799673
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2140803834
Short name T565
Test name
Test status
Simulation time 59338636527 ps
CPU time 50.38 seconds
Started Feb 07 01:44:43 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 216596 kb
Host smart-1ca90f0d-065a-4bca-902d-4341117b43d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140803834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2140803834
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.475469972
Short name T491
Test name
Test status
Simulation time 84580003 ps
CPU time 1.11 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:44:43 PM PST 24
Peak memory 205636 kb
Host smart-ac1cec7c-e514-465c-91b3-14c61992bd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475469972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.475469972
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3772933186
Short name T517
Test name
Test status
Simulation time 13608693 ps
CPU time 0.73 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:44:44 PM PST 24
Peak memory 205460 kb
Host smart-659677fd-b2db-40f4-bb30-50f32b5f140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772933186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3772933186
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.387369069
Short name T942
Test name
Test status
Simulation time 94770133 ps
CPU time 1.03 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:44:42 PM PST 24
Peak memory 206540 kb
Host smart-b0d96cb9-94a0-42b8-8e8b-e3031994df5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387369069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.387369069
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2528922514
Short name T496
Test name
Test status
Simulation time 375431790 ps
CPU time 5.28 seconds
Started Feb 07 01:44:38 PM PST 24
Finished Feb 07 01:44:45 PM PST 24
Peak memory 226452 kb
Host smart-21cb98f5-8f97-411a-8f1a-faf0d447e723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528922514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2528922514
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3342998805
Short name T789
Test name
Test status
Simulation time 45386347 ps
CPU time 0.71 seconds
Started Feb 07 01:44:46 PM PST 24
Finished Feb 07 01:44:48 PM PST 24
Peak memory 205380 kb
Host smart-fca76ae9-c47f-420d-a19a-7d3032ab6d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342998805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3342998805
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3835087361
Short name T947
Test name
Test status
Simulation time 1212387660 ps
CPU time 4.81 seconds
Started Feb 07 01:44:39 PM PST 24
Finished Feb 07 01:44:45 PM PST 24
Peak memory 233284 kb
Host smart-c8b77d0a-2192-4331-8031-cc9f43f7a814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835087361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3835087361
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1547875398
Short name T544
Test name
Test status
Simulation time 55727168 ps
CPU time 0.77 seconds
Started Feb 07 01:44:46 PM PST 24
Finished Feb 07 01:44:48 PM PST 24
Peak memory 205200 kb
Host smart-42833f4a-0224-4c89-ab47-2ff69ab1f58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547875398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1547875398
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.280606031
Short name T759
Test name
Test status
Simulation time 39122760850 ps
CPU time 194.65 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:47:58 PM PST 24
Peak memory 253316 kb
Host smart-3347d784-2b70-49ff-b9d5-f815eed91e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280606031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.280606031
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3995516727
Short name T190
Test name
Test status
Simulation time 177142415213 ps
CPU time 302.85 seconds
Started Feb 07 01:44:45 PM PST 24
Finished Feb 07 01:49:48 PM PST 24
Peak memory 239780 kb
Host smart-f6599704-9bc7-421c-8846-9e0cf7f3d61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995516727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3995516727
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.320029510
Short name T926
Test name
Test status
Simulation time 48641166779 ps
CPU time 368.53 seconds
Started Feb 07 01:44:40 PM PST 24
Finished Feb 07 01:50:50 PM PST 24
Peak memory 253468 kb
Host smart-502ac24d-70b1-4c41-a7fd-2b3159ac62b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320029510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.320029510
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1682067447
Short name T593
Test name
Test status
Simulation time 2387824425 ps
CPU time 11.1 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:44:53 PM PST 24
Peak memory 233100 kb
Host smart-6129b4fb-ea8b-4eac-a354-b84853322e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682067447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1682067447
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.850775194
Short name T243
Test name
Test status
Simulation time 1311002436 ps
CPU time 4.76 seconds
Started Feb 07 01:44:42 PM PST 24
Finished Feb 07 01:44:47 PM PST 24
Peak memory 233304 kb
Host smart-e6817848-e6ca-4e35-9f1a-bbef51bbd66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850775194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.850775194
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4182078039
Short name T742
Test name
Test status
Simulation time 731369322 ps
CPU time 8.13 seconds
Started Feb 07 01:44:39 PM PST 24
Finished Feb 07 01:44:48 PM PST 24
Peak memory 227492 kb
Host smart-55b90dca-0075-4e99-aaf6-f01c670a3739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182078039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4182078039
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3449347377
Short name T900
Test name
Test status
Simulation time 112631247 ps
CPU time 2.16 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:44:44 PM PST 24
Peak memory 217004 kb
Host smart-351acc55-cd91-4172-98ce-b2a5fb407240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449347377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3449347377
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3185041807
Short name T104
Test name
Test status
Simulation time 34912215 ps
CPU time 2.46 seconds
Started Feb 07 01:44:45 PM PST 24
Finished Feb 07 01:44:47 PM PST 24
Peak memory 232868 kb
Host smart-0f74e1e5-9aba-4861-be4d-9f36fc3c6314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185041807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3185041807
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3008058449
Short name T431
Test name
Test status
Simulation time 130549140 ps
CPU time 3.2 seconds
Started Feb 07 01:44:43 PM PST 24
Finished Feb 07 01:44:47 PM PST 24
Peak memory 216456 kb
Host smart-fcc5b266-747f-4f63-be60-e83146fe58c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3008058449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3008058449
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1425339128
Short name T893
Test name
Test status
Simulation time 144886032829 ps
CPU time 457.27 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:52:20 PM PST 24
Peak memory 271264 kb
Host smart-89b3ea8a-f9a3-4c39-9eca-c451fd14a10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425339128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1425339128
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4077292994
Short name T817
Test name
Test status
Simulation time 2198212261 ps
CPU time 24.5 seconds
Started Feb 07 01:44:39 PM PST 24
Finished Feb 07 01:45:05 PM PST 24
Peak memory 216632 kb
Host smart-de94904e-75fe-46fa-8e69-fb6d8ea3ef6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077292994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4077292994
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1070056053
Short name T803
Test name
Test status
Simulation time 1045111870 ps
CPU time 1.61 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:44:43 PM PST 24
Peak memory 206684 kb
Host smart-075790fe-1148-4817-a623-ddf7e035163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070056053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1070056053
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.62483440
Short name T590
Test name
Test status
Simulation time 84975382 ps
CPU time 1.94 seconds
Started Feb 07 01:44:40 PM PST 24
Finished Feb 07 01:44:43 PM PST 24
Peak memory 216472 kb
Host smart-066c6ef1-2447-47bb-ae7f-9295202fa64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62483440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.62483440
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3920880026
Short name T142
Test name
Test status
Simulation time 261807734 ps
CPU time 0.92 seconds
Started Feb 07 01:44:44 PM PST 24
Finished Feb 07 01:44:46 PM PST 24
Peak memory 206380 kb
Host smart-905b85a4-8be8-43af-bbc0-f6f9f95ed991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920880026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3920880026
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4195823621
Short name T969
Test name
Test status
Simulation time 3921432396 ps
CPU time 4.91 seconds
Started Feb 07 01:44:41 PM PST 24
Finished Feb 07 01:44:47 PM PST 24
Peak memory 234148 kb
Host smart-a76f7a28-3f6c-4ea1-9908-8a0aace1dbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195823621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4195823621
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3223737616
Short name T603
Test name
Test status
Simulation time 17818719 ps
CPU time 0.7 seconds
Started Feb 07 01:44:49 PM PST 24
Finished Feb 07 01:44:50 PM PST 24
Peak memory 205384 kb
Host smart-bef0ac4c-c69a-435c-993f-9108f320eddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223737616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3223737616
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4003006697
Short name T833
Test name
Test status
Simulation time 300862120 ps
CPU time 3.66 seconds
Started Feb 07 01:44:48 PM PST 24
Finished Feb 07 01:44:53 PM PST 24
Peak memory 224736 kb
Host smart-a5cdc4a7-4d9b-420c-a747-2bc0c0193638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003006697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4003006697
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3468164689
Short name T471
Test name
Test status
Simulation time 16364744 ps
CPU time 0.75 seconds
Started Feb 07 01:44:40 PM PST 24
Finished Feb 07 01:44:41 PM PST 24
Peak memory 205432 kb
Host smart-688e5651-04c4-4c3b-9932-caef66e37f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468164689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3468164689
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2164262251
Short name T212
Test name
Test status
Simulation time 265373095509 ps
CPU time 504.49 seconds
Started Feb 07 01:44:55 PM PST 24
Finished Feb 07 01:53:20 PM PST 24
Peak memory 282976 kb
Host smart-70cbf703-99bf-4ae6-b113-fbdf42f4d1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164262251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2164262251
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2961685468
Short name T1019
Test name
Test status
Simulation time 192085815704 ps
CPU time 239.91 seconds
Started Feb 07 01:44:50 PM PST 24
Finished Feb 07 01:48:51 PM PST 24
Peak memory 254560 kb
Host smart-b284d1f5-7297-4ebc-9d77-286644c88a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961685468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2961685468
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3344522421
Short name T255
Test name
Test status
Simulation time 2155883103 ps
CPU time 10.29 seconds
Started Feb 07 01:44:59 PM PST 24
Finished Feb 07 01:45:10 PM PST 24
Peak memory 231988 kb
Host smart-89f0b782-699b-486a-b787-4e101582b40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344522421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3344522421
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1721404528
Short name T240
Test name
Test status
Simulation time 3588442360 ps
CPU time 8.47 seconds
Started Feb 07 01:45:00 PM PST 24
Finished Feb 07 01:45:09 PM PST 24
Peak memory 233240 kb
Host smart-58e7bbc8-3203-4ab8-8d98-2b1f8181bf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721404528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1721404528
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1419363795
Short name T883
Test name
Test status
Simulation time 33540553334 ps
CPU time 26.05 seconds
Started Feb 07 01:44:51 PM PST 24
Finished Feb 07 01:45:18 PM PST 24
Peak memory 224828 kb
Host smart-acc19ddb-19d4-43c2-8870-b9f8813c1d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419363795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1419363795
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.105157601
Short name T1060
Test name
Test status
Simulation time 8158251709 ps
CPU time 25.1 seconds
Started Feb 07 01:44:53 PM PST 24
Finished Feb 07 01:45:19 PM PST 24
Peak memory 233108 kb
Host smart-a60cc375-b14a-4092-a997-4b4e8721b7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105157601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.105157601
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4242069270
Short name T35
Test name
Test status
Simulation time 15046196908 ps
CPU time 9.65 seconds
Started Feb 07 01:44:49 PM PST 24
Finished Feb 07 01:45:00 PM PST 24
Peak memory 241144 kb
Host smart-68bede7f-d075-4f2c-a49a-e12e74adbc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242069270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4242069270
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2922951168
Short name T526
Test name
Test status
Simulation time 148941089 ps
CPU time 3.23 seconds
Started Feb 07 01:44:52 PM PST 24
Finished Feb 07 01:44:56 PM PST 24
Peak memory 218876 kb
Host smart-44787929-262c-4b03-8bb7-7aa6b631b4e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2922951168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2922951168
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3026701539
Short name T144
Test name
Test status
Simulation time 27585406833 ps
CPU time 218.61 seconds
Started Feb 07 01:44:53 PM PST 24
Finished Feb 07 01:48:32 PM PST 24
Peak memory 265772 kb
Host smart-a504a70e-7b7f-4147-b16b-c970e80a35c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026701539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3026701539
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2565382353
Short name T720
Test name
Test status
Simulation time 17435899041 ps
CPU time 29.25 seconds
Started Feb 07 01:44:52 PM PST 24
Finished Feb 07 01:45:22 PM PST 24
Peak memory 216604 kb
Host smart-16621b2b-9f20-4c74-be30-4fb2a4ade895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565382353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2565382353
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3831314926
Short name T849
Test name
Test status
Simulation time 3885721245 ps
CPU time 12.49 seconds
Started Feb 07 01:44:49 PM PST 24
Finished Feb 07 01:45:02 PM PST 24
Peak memory 216564 kb
Host smart-af533609-0df0-47f3-a54f-8e48f7e887e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831314926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3831314926
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3411506041
Short name T981
Test name
Test status
Simulation time 67269979 ps
CPU time 0.97 seconds
Started Feb 07 01:44:54 PM PST 24
Finished Feb 07 01:44:56 PM PST 24
Peak memory 206480 kb
Host smart-67da553a-6972-4c9a-bca3-47cc016ec788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411506041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3411506041
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4066804462
Short name T740
Test name
Test status
Simulation time 106104358 ps
CPU time 0.77 seconds
Started Feb 07 01:44:52 PM PST 24
Finished Feb 07 01:44:54 PM PST 24
Peak memory 205424 kb
Host smart-61a0bc6b-a25d-47e1-8e8b-52279124b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066804462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4066804462
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1737078081
Short name T871
Test name
Test status
Simulation time 95853037 ps
CPU time 2.61 seconds
Started Feb 07 01:44:53 PM PST 24
Finished Feb 07 01:44:57 PM PST 24
Peak memory 232924 kb
Host smart-e0f0caf3-c425-4988-bde1-499db3544cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737078081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1737078081
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2195954722
Short name T538
Test name
Test status
Simulation time 45855296 ps
CPU time 0.7 seconds
Started Feb 07 01:44:54 PM PST 24
Finished Feb 07 01:44:55 PM PST 24
Peak memory 205016 kb
Host smart-87d06ba7-5100-454c-a435-1bfe960f0dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195954722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2195954722
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3594543151
Short name T725
Test name
Test status
Simulation time 1234784340 ps
CPU time 3.49 seconds
Started Feb 07 01:44:50 PM PST 24
Finished Feb 07 01:44:54 PM PST 24
Peak memory 233180 kb
Host smart-2ce396f1-b4ce-4751-ac73-261d48d57437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594543151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3594543151
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2949072941
Short name T553
Test name
Test status
Simulation time 46906161 ps
CPU time 0.72 seconds
Started Feb 07 01:44:48 PM PST 24
Finished Feb 07 01:44:49 PM PST 24
Peak memory 205164 kb
Host smart-15e0049d-d2e8-4709-a0cb-6132881bed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949072941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2949072941
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3560670612
Short name T566
Test name
Test status
Simulation time 2523099157 ps
CPU time 35.53 seconds
Started Feb 07 01:44:51 PM PST 24
Finished Feb 07 01:45:27 PM PST 24
Peak memory 237528 kb
Host smart-dcbc131d-70b6-46f7-a16c-7f29ed47f4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560670612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3560670612
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1847227259
Short name T1012
Test name
Test status
Simulation time 9600121372 ps
CPU time 118.36 seconds
Started Feb 07 01:44:54 PM PST 24
Finished Feb 07 01:46:53 PM PST 24
Peak memory 250492 kb
Host smart-0969ed6d-13c4-4aeb-875c-482540eb861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847227259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1847227259
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2367435262
Short name T605
Test name
Test status
Simulation time 6318415148 ps
CPU time 35.82 seconds
Started Feb 07 01:44:52 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 241312 kb
Host smart-de4ae79e-a336-42ae-a7df-c057e04cabb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367435262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2367435262
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2977935296
Short name T777
Test name
Test status
Simulation time 457971741 ps
CPU time 3.26 seconds
Started Feb 07 01:44:51 PM PST 24
Finished Feb 07 01:44:55 PM PST 24
Peak memory 216588 kb
Host smart-ca733dcb-a4e7-49fb-8f07-2e3fad90142a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977935296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2977935296
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2729929763
Short name T916
Test name
Test status
Simulation time 44456072767 ps
CPU time 36.82 seconds
Started Feb 07 01:44:58 PM PST 24
Finished Feb 07 01:45:35 PM PST 24
Peak memory 240504 kb
Host smart-48672fc6-7ce7-4d3f-b780-7c895a1fb6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729929763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2729929763
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3747192405
Short name T122
Test name
Test status
Simulation time 2967145927 ps
CPU time 5.32 seconds
Started Feb 07 01:44:55 PM PST 24
Finished Feb 07 01:45:01 PM PST 24
Peak memory 233332 kb
Host smart-d2553994-bb42-43c8-840e-2d6f855cec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747192405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3747192405
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4078242700
Short name T656
Test name
Test status
Simulation time 1489302288 ps
CPU time 5.33 seconds
Started Feb 07 01:44:55 PM PST 24
Finished Feb 07 01:45:01 PM PST 24
Peak memory 232644 kb
Host smart-42c369a7-705b-4712-aa6d-d63831198d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078242700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4078242700
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1821624642
Short name T549
Test name
Test status
Simulation time 2040873216 ps
CPU time 4.71 seconds
Started Feb 07 01:44:56 PM PST 24
Finished Feb 07 01:45:02 PM PST 24
Peak memory 220100 kb
Host smart-7d10fac1-83dc-419b-92bc-ac78c2ac2821
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1821624642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1821624642
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2717164713
Short name T64
Test name
Test status
Simulation time 393185036113 ps
CPU time 694.53 seconds
Started Feb 07 01:44:50 PM PST 24
Finished Feb 07 01:56:26 PM PST 24
Peak memory 272624 kb
Host smart-33edf44b-8d56-454c-ac87-30e2799c42b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717164713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2717164713
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2206505873
Short name T651
Test name
Test status
Simulation time 52119539548 ps
CPU time 61.89 seconds
Started Feb 07 01:44:48 PM PST 24
Finished Feb 07 01:45:50 PM PST 24
Peak memory 216668 kb
Host smart-84cbeac5-9dbd-4a49-a191-60a58872824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206505873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2206505873
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.152420710
Short name T1015
Test name
Test status
Simulation time 5887652167 ps
CPU time 7.75 seconds
Started Feb 07 01:44:59 PM PST 24
Finished Feb 07 01:45:08 PM PST 24
Peak memory 216648 kb
Host smart-fd674c63-d487-40d9-babf-085ed1822207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152420710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.152420710
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2506217168
Short name T925
Test name
Test status
Simulation time 71212751 ps
CPU time 1.04 seconds
Started Feb 07 01:44:50 PM PST 24
Finished Feb 07 01:44:52 PM PST 24
Peak memory 206580 kb
Host smart-819f4d59-262d-4d0f-b444-5cf4b75aaa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506217168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2506217168
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1212148616
Short name T672
Test name
Test status
Simulation time 363929913 ps
CPU time 0.81 seconds
Started Feb 07 01:44:53 PM PST 24
Finished Feb 07 01:44:55 PM PST 24
Peak memory 205464 kb
Host smart-7d8a0847-38e0-4479-8a5c-f0529c796492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212148616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1212148616
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4037352022
Short name T990
Test name
Test status
Simulation time 444957279 ps
CPU time 3.3 seconds
Started Feb 07 01:44:49 PM PST 24
Finished Feb 07 01:44:53 PM PST 24
Peak memory 237428 kb
Host smart-e435104c-8500-4e09-8ceb-6ff877865b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037352022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4037352022
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2569095656
Short name T287
Test name
Test status
Simulation time 52655220 ps
CPU time 0.72 seconds
Started Feb 07 01:45:01 PM PST 24
Finished Feb 07 01:45:03 PM PST 24
Peak memory 205020 kb
Host smart-d6a4c169-12e3-46b1-821f-129ebcd70f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569095656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2569095656
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1334055414
Short name T850
Test name
Test status
Simulation time 73105251 ps
CPU time 2.18 seconds
Started Feb 07 01:44:54 PM PST 24
Finished Feb 07 01:44:57 PM PST 24
Peak memory 216816 kb
Host smart-3c3d910e-8a75-4d0b-86d4-414a6233062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334055414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1334055414
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2801235239
Short name T1111
Test name
Test status
Simulation time 21057244 ps
CPU time 0.8 seconds
Started Feb 07 01:44:50 PM PST 24
Finished Feb 07 01:44:52 PM PST 24
Peak memory 206492 kb
Host smart-1f3fd7a4-a2c8-4898-89e4-d7232645468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801235239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2801235239
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2763503550
Short name T1034
Test name
Test status
Simulation time 4216328610 ps
CPU time 77.1 seconds
Started Feb 07 01:44:53 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 265776 kb
Host smart-316a5a04-20d3-4074-ac2f-952c67057dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763503550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2763503550
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3353708771
Short name T858
Test name
Test status
Simulation time 8211569848 ps
CPU time 82.12 seconds
Started Feb 07 01:44:55 PM PST 24
Finished Feb 07 01:46:17 PM PST 24
Peak memory 237184 kb
Host smart-73d588b9-35cc-4637-ae58-0c6b51cf1e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353708771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3353708771
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1133399187
Short name T931
Test name
Test status
Simulation time 5639639139 ps
CPU time 25.05 seconds
Started Feb 07 01:44:52 PM PST 24
Finished Feb 07 01:45:18 PM PST 24
Peak memory 236184 kb
Host smart-fca588aa-a3ff-4f6e-baa9-7d7d317ef8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133399187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1133399187
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1279538324
Short name T1061
Test name
Test status
Simulation time 1060254835 ps
CPU time 6.69 seconds
Started Feb 07 01:44:48 PM PST 24
Finished Feb 07 01:44:55 PM PST 24
Peak memory 234808 kb
Host smart-3bc2b603-d646-4001-9452-24557ccd2da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279538324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1279538324
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3550059299
Short name T168
Test name
Test status
Simulation time 161783107 ps
CPU time 2.9 seconds
Started Feb 07 01:44:50 PM PST 24
Finished Feb 07 01:44:54 PM PST 24
Peak memory 217600 kb
Host smart-38dc69d3-48ad-4c4d-8272-ea706c2d9c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550059299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3550059299
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3479552063
Short name T79
Test name
Test status
Simulation time 3502293147 ps
CPU time 17.79 seconds
Started Feb 07 01:44:54 PM PST 24
Finished Feb 07 01:45:12 PM PST 24
Peak memory 233052 kb
Host smart-1b6619ca-9c03-42b6-9071-3e79a15342cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479552063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3479552063
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3909686681
Short name T928
Test name
Test status
Simulation time 5372965454 ps
CPU time 20.29 seconds
Started Feb 07 01:44:50 PM PST 24
Finished Feb 07 01:45:11 PM PST 24
Peak memory 236544 kb
Host smart-79d062ab-faab-4878-bef8-ce42adfdd421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909686681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3909686681
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3957019339
Short name T457
Test name
Test status
Simulation time 5797623792 ps
CPU time 10.34 seconds
Started Feb 07 01:44:55 PM PST 24
Finished Feb 07 01:45:07 PM PST 24
Peak memory 233604 kb
Host smart-cb46f858-0e3d-4711-a14e-3010ada16d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957019339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3957019339
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3517046344
Short name T901
Test name
Test status
Simulation time 6643104493 ps
CPU time 6.86 seconds
Started Feb 07 01:44:49 PM PST 24
Finished Feb 07 01:44:57 PM PST 24
Peak memory 222440 kb
Host smart-ed799155-8e56-470a-a3ed-f077c48a32d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3517046344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3517046344
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2950563945
Short name T963
Test name
Test status
Simulation time 19460359324 ps
CPU time 81.01 seconds
Started Feb 07 01:44:50 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 249540 kb
Host smart-158aea38-e030-4666-ab33-c302c08dfe8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950563945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2950563945
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1538469220
Short name T1045
Test name
Test status
Simulation time 66678646410 ps
CPU time 17.51 seconds
Started Feb 07 01:45:03 PM PST 24
Finished Feb 07 01:45:22 PM PST 24
Peak memory 216580 kb
Host smart-a9b19af0-533c-446c-9187-9db85a27c6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538469220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1538469220
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3308214326
Short name T118
Test name
Test status
Simulation time 515354041 ps
CPU time 1.73 seconds
Started Feb 07 01:44:51 PM PST 24
Finished Feb 07 01:44:54 PM PST 24
Peak memory 208192 kb
Host smart-7f1b6af7-9a82-4dda-a2f0-958df1ebbf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308214326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3308214326
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1508789098
Short name T469
Test name
Test status
Simulation time 80312419 ps
CPU time 0.77 seconds
Started Feb 07 01:44:53 PM PST 24
Finished Feb 07 01:44:54 PM PST 24
Peak memory 205460 kb
Host smart-e9e09dff-047f-45e1-8d98-416b973bacca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508789098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1508789098
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.444953537
Short name T17
Test name
Test status
Simulation time 460661636 ps
CPU time 2.8 seconds
Started Feb 07 01:44:49 PM PST 24
Finished Feb 07 01:44:52 PM PST 24
Peak memory 224728 kb
Host smart-bb50250f-228f-4f78-97c7-43d3a436115e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444953537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.444953537
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1853079811
Short name T437
Test name
Test status
Simulation time 11190597 ps
CPU time 0.7 seconds
Started Feb 07 01:45:26 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 205096 kb
Host smart-eb4b42d8-6d59-4fdd-9654-0ab0b0bce821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853079811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1853079811
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2778135570
Short name T913
Test name
Test status
Simulation time 5000015853 ps
CPU time 7.03 seconds
Started Feb 07 01:45:07 PM PST 24
Finished Feb 07 01:45:18 PM PST 24
Peak memory 233504 kb
Host smart-53cad914-2989-4d7f-93ea-92ac27dbcd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778135570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2778135570
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4229314752
Short name T284
Test name
Test status
Simulation time 17597632 ps
CPU time 0.76 seconds
Started Feb 07 01:45:10 PM PST 24
Finished Feb 07 01:45:13 PM PST 24
Peak memory 205204 kb
Host smart-931ea82d-9cc1-4e1d-be70-74c1d47727cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229314752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4229314752
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.323249274
Short name T244
Test name
Test status
Simulation time 43623637682 ps
CPU time 206.74 seconds
Started Feb 07 01:45:11 PM PST 24
Finished Feb 07 01:48:40 PM PST 24
Peak memory 265960 kb
Host smart-b7eb4ae5-2b37-41c1-a6fe-3770febf48fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323249274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.323249274
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1741936303
Short name T729
Test name
Test status
Simulation time 1856758251 ps
CPU time 25.82 seconds
Started Feb 07 01:45:14 PM PST 24
Finished Feb 07 01:45:42 PM PST 24
Peak memory 221432 kb
Host smart-dd3850a0-d26f-4ff3-847d-d433a950fd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741936303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1741936303
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3680901357
Short name T1000
Test name
Test status
Simulation time 3748835748 ps
CPU time 53.14 seconds
Started Feb 07 01:45:02 PM PST 24
Finished Feb 07 01:45:57 PM PST 24
Peak memory 250464 kb
Host smart-6550d688-606c-4abe-ad84-0312a20fd680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680901357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3680901357
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.53034554
Short name T250
Test name
Test status
Simulation time 443355335 ps
CPU time 7.45 seconds
Started Feb 07 01:45:10 PM PST 24
Finished Feb 07 01:45:20 PM PST 24
Peak memory 234024 kb
Host smart-729f1254-5428-426d-ad07-d6155d243ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53034554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.53034554
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.177475004
Short name T188
Test name
Test status
Simulation time 2481575592 ps
CPU time 6.66 seconds
Started Feb 07 01:45:10 PM PST 24
Finished Feb 07 01:45:19 PM PST 24
Peak memory 219500 kb
Host smart-645a965c-1018-403f-b346-554183fc3693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177475004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.177475004
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.962025158
Short name T798
Test name
Test status
Simulation time 2100644712 ps
CPU time 15.23 seconds
Started Feb 07 01:45:00 PM PST 24
Finished Feb 07 01:45:17 PM PST 24
Peak memory 241136 kb
Host smart-45a12bbd-84b4-4159-a63d-ce775f482c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962025158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.962025158
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.402284182
Short name T211
Test name
Test status
Simulation time 1761096351 ps
CPU time 6.81 seconds
Started Feb 07 01:45:00 PM PST 24
Finished Feb 07 01:45:07 PM PST 24
Peak memory 217864 kb
Host smart-1090bd48-e141-4828-a615-7906437f56a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402284182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.402284182
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2580552007
Short name T717
Test name
Test status
Simulation time 6996773626 ps
CPU time 11.38 seconds
Started Feb 07 01:45:14 PM PST 24
Finished Feb 07 01:45:32 PM PST 24
Peak memory 233192 kb
Host smart-014c92fb-7aab-480d-ae5e-02e4ed3dbddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580552007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2580552007
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1372386275
Short name T617
Test name
Test status
Simulation time 838312388 ps
CPU time 5.23 seconds
Started Feb 07 01:45:12 PM PST 24
Finished Feb 07 01:45:19 PM PST 24
Peak memory 222872 kb
Host smart-dcb26fe9-0e7c-4d4d-9e5b-5bcf606b5767
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1372386275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1372386275
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3338288032
Short name T1059
Test name
Test status
Simulation time 10356130812 ps
CPU time 114.33 seconds
Started Feb 07 01:45:12 PM PST 24
Finished Feb 07 01:47:10 PM PST 24
Peak memory 249568 kb
Host smart-1130287a-460c-42eb-ac69-7d07b11e7fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338288032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3338288032
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1554545742
Short name T870
Test name
Test status
Simulation time 5399504165 ps
CPU time 72.76 seconds
Started Feb 07 01:45:14 PM PST 24
Finished Feb 07 01:46:34 PM PST 24
Peak memory 216608 kb
Host smart-45450ca2-8911-4ba0-8a8c-4e61c64ef82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554545742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1554545742
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3268200401
Short name T823
Test name
Test status
Simulation time 616326265 ps
CPU time 2.12 seconds
Started Feb 07 01:45:12 PM PST 24
Finished Feb 07 01:45:17 PM PST 24
Peak memory 206788 kb
Host smart-92b0fa14-3dc8-4319-be14-61bb4f92ad25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268200401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3268200401
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.771717221
Short name T987
Test name
Test status
Simulation time 200638473 ps
CPU time 4.64 seconds
Started Feb 07 01:45:12 PM PST 24
Finished Feb 07 01:45:17 PM PST 24
Peak memory 208584 kb
Host smart-9a88fc94-8b35-4128-b90f-8c58a07d27b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771717221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.771717221
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3322024393
Short name T578
Test name
Test status
Simulation time 318775796 ps
CPU time 1.07 seconds
Started Feb 07 01:45:02 PM PST 24
Finished Feb 07 01:45:05 PM PST 24
Peak memory 206520 kb
Host smart-0b61c832-d235-4a84-9cec-4cd01ce30d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322024393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3322024393
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2140415485
Short name T989
Test name
Test status
Simulation time 110574280 ps
CPU time 2.56 seconds
Started Feb 07 01:45:08 PM PST 24
Finished Feb 07 01:45:15 PM PST 24
Peak memory 232984 kb
Host smart-fec2e0f1-8049-4e6d-8d80-908256697684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140415485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2140415485
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.87744903
Short name T531
Test name
Test status
Simulation time 42422470 ps
CPU time 0.7 seconds
Started Feb 07 01:45:19 PM PST 24
Finished Feb 07 01:45:23 PM PST 24
Peak memory 205040 kb
Host smart-3cdbb883-f98a-4875-b24f-4dd8c215371c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87744903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.87744903
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2223787293
Short name T787
Test name
Test status
Simulation time 1730664624 ps
CPU time 4.16 seconds
Started Feb 07 01:45:12 PM PST 24
Finished Feb 07 01:45:18 PM PST 24
Peak memory 233800 kb
Host smart-f68b1356-2474-43ce-82b5-1694dbf7593e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223787293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2223787293
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3912953883
Short name T783
Test name
Test status
Simulation time 34385663 ps
CPU time 0.78 seconds
Started Feb 07 01:45:13 PM PST 24
Finished Feb 07 01:45:17 PM PST 24
Peak memory 206572 kb
Host smart-a8d8327f-e543-4074-9fc3-83c5c4226d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912953883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3912953883
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.871834888
Short name T757
Test name
Test status
Simulation time 39270075498 ps
CPU time 27.39 seconds
Started Feb 07 01:45:33 PM PST 24
Finished Feb 07 01:46:02 PM PST 24
Peak memory 221576 kb
Host smart-fec8e33e-7940-4511-9f39-dea9edc2703e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871834888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.871834888
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.850135558
Short name T609
Test name
Test status
Simulation time 263077551352 ps
CPU time 369.25 seconds
Started Feb 07 01:45:14 PM PST 24
Finished Feb 07 01:51:26 PM PST 24
Peak memory 262928 kb
Host smart-d9f60fc4-36fc-4d15-a4e9-11667c8640f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850135558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.850135558
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2198804456
Short name T674
Test name
Test status
Simulation time 6852022607 ps
CPU time 85.15 seconds
Started Feb 07 01:45:18 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 252440 kb
Host smart-143447ef-aa14-4046-ba48-2eb26df04fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198804456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2198804456
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3676389838
Short name T719
Test name
Test status
Simulation time 21619643656 ps
CPU time 27.04 seconds
Started Feb 07 01:45:16 PM PST 24
Finished Feb 07 01:45:48 PM PST 24
Peak memory 247412 kb
Host smart-d0a4a708-fe97-4c49-92d6-12c9f404a175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676389838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3676389838
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2525836051
Short name T159
Test name
Test status
Simulation time 726978282 ps
CPU time 3.39 seconds
Started Feb 07 01:45:10 PM PST 24
Finished Feb 07 01:45:16 PM PST 24
Peak memory 217956 kb
Host smart-673db83f-6380-4f48-82ca-67e5616526d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525836051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2525836051
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3182204385
Short name T944
Test name
Test status
Simulation time 1820599867 ps
CPU time 8.01 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:45:35 PM PST 24
Peak memory 236692 kb
Host smart-00b0302d-3343-4e39-8e2c-80172ca2eff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182204385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3182204385
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3552587130
Short name T298
Test name
Test status
Simulation time 16549394966 ps
CPU time 11.18 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:45:38 PM PST 24
Peak memory 240228 kb
Host smart-96a451dd-0b2e-4e7d-9100-463cae19156c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552587130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3552587130
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1658795217
Short name T856
Test name
Test status
Simulation time 4209241540 ps
CPU time 11.64 seconds
Started Feb 07 01:45:14 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 223112 kb
Host smart-95357cf2-b68e-4439-a896-f68006d25394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658795217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1658795217
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2775152977
Short name T716
Test name
Test status
Simulation time 1241770361 ps
CPU time 3.62 seconds
Started Feb 07 01:45:29 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 221076 kb
Host smart-a8d7a553-dffa-4224-b20a-e777e7ed4857
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2775152977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2775152977
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2713309539
Short name T225
Test name
Test status
Simulation time 160022808672 ps
CPU time 601.16 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:55:30 PM PST 24
Peak memory 286108 kb
Host smart-413d29a8-591e-4e9e-aa47-424b40f1413b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713309539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2713309539
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4238113104
Short name T575
Test name
Test status
Simulation time 2461675979 ps
CPU time 11.84 seconds
Started Feb 07 01:45:12 PM PST 24
Finished Feb 07 01:45:26 PM PST 24
Peak memory 216700 kb
Host smart-a40bb7a2-8084-496a-acc6-691d6ae24dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238113104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4238113104
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.368198082
Short name T611
Test name
Test status
Simulation time 2931329970 ps
CPU time 5.66 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:45:32 PM PST 24
Peak memory 216580 kb
Host smart-2b70d55b-3697-4d7c-90cd-da71d9d06009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368198082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.368198082
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1384000760
Short name T1075
Test name
Test status
Simulation time 41975742 ps
CPU time 1.18 seconds
Started Feb 07 01:45:15 PM PST 24
Finished Feb 07 01:45:22 PM PST 24
Peak memory 207696 kb
Host smart-f56c465f-0523-4005-92e2-618320d8ee8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384000760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1384000760
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.727763736
Short name T623
Test name
Test status
Simulation time 167446852 ps
CPU time 0.86 seconds
Started Feb 07 01:45:29 PM PST 24
Finished Feb 07 01:45:31 PM PST 24
Peak memory 206484 kb
Host smart-b8a0399a-513b-4d69-82fc-2bf2cbe679f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727763736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.727763736
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3821102069
Short name T851
Test name
Test status
Simulation time 358635559 ps
CPU time 3.99 seconds
Started Feb 07 01:45:15 PM PST 24
Finished Feb 07 01:45:25 PM PST 24
Peak memory 235896 kb
Host smart-6f9449db-2f10-4efd-a603-251162e01925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821102069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3821102069
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.328098724
Short name T440
Test name
Test status
Simulation time 37749236 ps
CPU time 0.72 seconds
Started Feb 07 01:45:24 PM PST 24
Finished Feb 07 01:45:27 PM PST 24
Peak memory 205024 kb
Host smart-e2a23644-9a43-4799-b053-aa7a7a2eee77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328098724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.328098724
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2702411308
Short name T33
Test name
Test status
Simulation time 853438898 ps
CPU time 5.3 seconds
Started Feb 07 01:45:13 PM PST 24
Finished Feb 07 01:45:21 PM PST 24
Peak memory 235560 kb
Host smart-d590ad01-4bcb-4b3f-8318-887cf83c6d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702411308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2702411308
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3183394241
Short name T678
Test name
Test status
Simulation time 15082398 ps
CPU time 0.77 seconds
Started Feb 07 01:45:10 PM PST 24
Finished Feb 07 01:45:14 PM PST 24
Peak memory 206496 kb
Host smart-a57ee74b-6f0c-4b7d-bbed-5ff60d5d9ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183394241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3183394241
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4022043404
Short name T698
Test name
Test status
Simulation time 65115574096 ps
CPU time 152.54 seconds
Started Feb 07 01:45:24 PM PST 24
Finished Feb 07 01:47:59 PM PST 24
Peak memory 257224 kb
Host smart-59a6f8b4-2e90-42f1-bf4b-10cc9c0eb9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022043404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4022043404
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2408613699
Short name T23
Test name
Test status
Simulation time 5297751378 ps
CPU time 53.25 seconds
Started Feb 07 01:45:23 PM PST 24
Finished Feb 07 01:46:18 PM PST 24
Peak memory 253468 kb
Host smart-afdf9cef-58ff-4c99-abed-473d89b97055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408613699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2408613699
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.4141916124
Short name T481
Test name
Test status
Simulation time 3526675186 ps
CPU time 50.51 seconds
Started Feb 07 01:45:18 PM PST 24
Finished Feb 07 01:46:13 PM PST 24
Peak memory 251560 kb
Host smart-4a46b496-0d79-4a1c-9e68-dfc52721d9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141916124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.4141916124
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2930690745
Short name T800
Test name
Test status
Simulation time 4271389649 ps
CPU time 6.3 seconds
Started Feb 07 01:45:15 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 233648 kb
Host smart-b822f91f-b4cd-4cde-b339-f79ac7a83e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930690745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2930690745
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.346604629
Short name T528
Test name
Test status
Simulation time 3521462338 ps
CPU time 10.75 seconds
Started Feb 07 01:45:15 PM PST 24
Finished Feb 07 01:45:32 PM PST 24
Peak memory 233872 kb
Host smart-3f862ceb-61f9-447c-b103-85e5abc31236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346604629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.346604629
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2757497939
Short name T162
Test name
Test status
Simulation time 23562579495 ps
CPU time 19.02 seconds
Started Feb 07 01:45:13 PM PST 24
Finished Feb 07 01:45:35 PM PST 24
Peak memory 240424 kb
Host smart-0332be01-7304-43ab-8f24-927123f1d6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757497939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2757497939
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.874215421
Short name T864
Test name
Test status
Simulation time 2571326284 ps
CPU time 11.29 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:45:38 PM PST 24
Peak memory 218800 kb
Host smart-631b7082-854e-4f7e-b25a-08ce30bbfa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874215421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.874215421
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2955641087
Short name T12
Test name
Test status
Simulation time 563277436 ps
CPU time 4.25 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:45:33 PM PST 24
Peak memory 216460 kb
Host smart-f0ab8894-1985-4f5c-b1e4-048dc83a3068
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2955641087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2955641087
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2410469104
Short name T588
Test name
Test status
Simulation time 45125867462 ps
CPU time 83.32 seconds
Started Feb 07 01:45:16 PM PST 24
Finished Feb 07 01:46:46 PM PST 24
Peak memory 216608 kb
Host smart-e87ce179-79a7-4222-acde-6e508a7072a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410469104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2410469104
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3517725779
Short name T1093
Test name
Test status
Simulation time 12203378034 ps
CPU time 8.68 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:45:39 PM PST 24
Peak memory 216520 kb
Host smart-597e1493-e675-4677-bfac-a79b8aa99618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517725779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3517725779
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3143376401
Short name T434
Test name
Test status
Simulation time 800202268 ps
CPU time 2.77 seconds
Started Feb 07 01:45:26 PM PST 24
Finished Feb 07 01:45:30 PM PST 24
Peak memory 217704 kb
Host smart-4e13a79f-23ab-4c04-915c-cc117c83a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143376401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3143376401
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1951230087
Short name T607
Test name
Test status
Simulation time 143737347 ps
CPU time 0.92 seconds
Started Feb 07 01:45:18 PM PST 24
Finished Feb 07 01:45:24 PM PST 24
Peak memory 205420 kb
Host smart-c321fed2-26eb-49b9-be8e-3f7b48ccd10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951230087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1951230087
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3121948505
Short name T599
Test name
Test status
Simulation time 242180096 ps
CPU time 2.34 seconds
Started Feb 07 01:45:11 PM PST 24
Finished Feb 07 01:45:15 PM PST 24
Peak memory 217624 kb
Host smart-ba1f428e-0853-4249-b66c-6f89b2362a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121948505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3121948505
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.647516958
Short name T739
Test name
Test status
Simulation time 12205337 ps
CPU time 0.73 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:45:30 PM PST 24
Peak memory 205064 kb
Host smart-0d9fe3f0-a80c-45b4-8ae3-df2da0a370d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647516958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.647516958
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1845886430
Short name T979
Test name
Test status
Simulation time 3762973773 ps
CPU time 6.71 seconds
Started Feb 07 01:45:24 PM PST 24
Finished Feb 07 01:45:33 PM PST 24
Peak memory 219560 kb
Host smart-091176bb-1ac0-4e1d-afd7-e615e0e8616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845886430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1845886430
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1561269921
Short name T613
Test name
Test status
Simulation time 64146744 ps
CPU time 0.76 seconds
Started Feb 07 01:45:24 PM PST 24
Finished Feb 07 01:45:27 PM PST 24
Peak memory 205552 kb
Host smart-d5324777-7955-4002-9348-22bcba3afd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561269921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1561269921
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.906771183
Short name T164
Test name
Test status
Simulation time 140358002206 ps
CPU time 126.41 seconds
Started Feb 07 01:45:24 PM PST 24
Finished Feb 07 01:47:33 PM PST 24
Peak memory 254796 kb
Host smart-f64b64ba-f894-4104-b00c-fcc82ebf58b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906771183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.906771183
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1968328407
Short name T888
Test name
Test status
Simulation time 32383980182 ps
CPU time 91.14 seconds
Started Feb 07 01:45:23 PM PST 24
Finished Feb 07 01:46:56 PM PST 24
Peak memory 249492 kb
Host smart-1068bea6-40e8-4ef2-a0b6-f59eab8e80d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968328407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1968328407
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3118094707
Short name T1071
Test name
Test status
Simulation time 1202720839 ps
CPU time 16.85 seconds
Started Feb 07 01:45:24 PM PST 24
Finished Feb 07 01:45:43 PM PST 24
Peak memory 246088 kb
Host smart-08a22a2c-721c-46ab-b0a0-65c048a28446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118094707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3118094707
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4108116672
Short name T606
Test name
Test status
Simulation time 2504934338 ps
CPU time 5.19 seconds
Started Feb 07 01:45:26 PM PST 24
Finished Feb 07 01:45:32 PM PST 24
Peak memory 221240 kb
Host smart-716c14f0-3abc-44f2-b2e7-992ff198ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108116672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4108116672
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.963814010
Short name T14
Test name
Test status
Simulation time 75261099324 ps
CPU time 44.93 seconds
Started Feb 07 01:45:29 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 240724 kb
Host smart-7e02a20d-f813-4e39-b691-8724cd50b8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963814010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.963814010
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2782091179
Short name T484
Test name
Test status
Simulation time 801325492 ps
CPU time 4.96 seconds
Started Feb 07 01:45:27 PM PST 24
Finished Feb 07 01:45:33 PM PST 24
Peak memory 233520 kb
Host smart-6065d604-29bb-4c2e-b28a-561f907a14af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782091179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2782091179
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3575868977
Short name T761
Test name
Test status
Simulation time 733725343 ps
CPU time 6.74 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:45:33 PM PST 24
Peak memory 232688 kb
Host smart-de171552-0b9f-41ba-9cef-ac188dc43eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575868977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3575868977
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3995338763
Short name T600
Test name
Test status
Simulation time 733230812 ps
CPU time 4.4 seconds
Started Feb 07 01:45:26 PM PST 24
Finished Feb 07 01:45:32 PM PST 24
Peak memory 222000 kb
Host smart-b340fc0e-891e-448d-8a12-4a79004765e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3995338763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3995338763
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1294446109
Short name T447
Test name
Test status
Simulation time 81924930 ps
CPU time 1.02 seconds
Started Feb 07 01:45:29 PM PST 24
Finished Feb 07 01:45:31 PM PST 24
Peak memory 206860 kb
Host smart-8fde0c2f-b1a4-439c-87ad-a918855e614d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294446109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1294446109
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1367140120
Short name T927
Test name
Test status
Simulation time 15726192432 ps
CPU time 46.22 seconds
Started Feb 07 01:45:19 PM PST 24
Finished Feb 07 01:46:09 PM PST 24
Peak memory 216576 kb
Host smart-badcdf61-9a39-452e-8413-a3738b71b542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367140120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1367140120
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1898583144
Short name T946
Test name
Test status
Simulation time 3318375331 ps
CPU time 3.49 seconds
Started Feb 07 01:45:16 PM PST 24
Finished Feb 07 01:45:25 PM PST 24
Peak memory 216680 kb
Host smart-e76e3421-7c22-49b0-aa33-783123755601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898583144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1898583144
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3379416414
Short name T536
Test name
Test status
Simulation time 345481598 ps
CPU time 1.45 seconds
Started Feb 07 01:45:20 PM PST 24
Finished Feb 07 01:45:24 PM PST 24
Peak memory 207960 kb
Host smart-e72d41a4-b5e1-42d2-ac2c-ad7ddfa64e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379416414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3379416414
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2984177771
Short name T425
Test name
Test status
Simulation time 103659956 ps
CPU time 0.84 seconds
Started Feb 07 01:45:22 PM PST 24
Finished Feb 07 01:45:24 PM PST 24
Peak memory 205408 kb
Host smart-63933004-f963-4ef7-ae6a-df6f8a3cef20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984177771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2984177771
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3338390252
Short name T1104
Test name
Test status
Simulation time 1104283310 ps
CPU time 3.91 seconds
Started Feb 07 01:45:22 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 219248 kb
Host smart-eef3e43c-c297-4aa3-91f3-2b9cfa6a95c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338390252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3338390252
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.734563710
Short name T598
Test name
Test status
Simulation time 16620413 ps
CPU time 0.7 seconds
Started Feb 07 01:42:50 PM PST 24
Finished Feb 07 01:42:52 PM PST 24
Peak memory 205304 kb
Host smart-c44a713f-007a-44cc-b740-a2f46a1179d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734563710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.734563710
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3151774502
Short name T532
Test name
Test status
Simulation time 86244456 ps
CPU time 2.86 seconds
Started Feb 07 01:42:40 PM PST 24
Finished Feb 07 01:42:43 PM PST 24
Peak memory 233736 kb
Host smart-4c749aa5-7a50-4628-9054-d37d9b4c08a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151774502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3151774502
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3900278638
Short name T766
Test name
Test status
Simulation time 21060155 ps
CPU time 0.78 seconds
Started Feb 07 01:42:38 PM PST 24
Finished Feb 07 01:42:39 PM PST 24
Peak memory 206296 kb
Host smart-1ba4012c-a4ee-4668-91cd-f26cbf802300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900278638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3900278638
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1418899361
Short name T29
Test name
Test status
Simulation time 15670036282 ps
CPU time 19.24 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:26 PM PST 24
Peak memory 241292 kb
Host smart-afa09e57-1d17-42bb-a927-5b26fd59e499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418899361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1418899361
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3161456741
Short name T169
Test name
Test status
Simulation time 1196698741 ps
CPU time 14.82 seconds
Started Feb 07 01:42:53 PM PST 24
Finished Feb 07 01:43:13 PM PST 24
Peak memory 233168 kb
Host smart-79a84fc5-71ac-4c3d-8089-3b1efc6d5b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161456741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3161456741
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3675990325
Short name T903
Test name
Test status
Simulation time 696133727349 ps
CPU time 289.11 seconds
Started Feb 07 01:42:53 PM PST 24
Finished Feb 07 01:47:47 PM PST 24
Peak memory 255964 kb
Host smart-0c3f5c5d-61e2-4b2a-8e30-50c881faa105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675990325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3675990325
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3478229007
Short name T130
Test name
Test status
Simulation time 11108158427 ps
CPU time 30.61 seconds
Started Feb 07 01:42:37 PM PST 24
Finished Feb 07 01:43:09 PM PST 24
Peak memory 240180 kb
Host smart-5726c448-efba-485c-9066-ca9faccb24b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478229007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3478229007
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1805767863
Short name T187
Test name
Test status
Simulation time 1521250052 ps
CPU time 6.74 seconds
Started Feb 07 01:42:32 PM PST 24
Finished Feb 07 01:42:39 PM PST 24
Peak memory 218640 kb
Host smart-f1560d79-85b5-4ab0-ac54-5e5cf510d665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805767863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1805767863
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3404413122
Short name T992
Test name
Test status
Simulation time 31176932639 ps
CPU time 45.7 seconds
Started Feb 07 01:42:40 PM PST 24
Finished Feb 07 01:43:26 PM PST 24
Peak memory 248884 kb
Host smart-84766245-baf9-4edc-bd96-33170539facd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404413122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3404413122
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.434928734
Short name T1048
Test name
Test status
Simulation time 118271726 ps
CPU time 1 seconds
Started Feb 07 01:42:35 PM PST 24
Finished Feb 07 01:42:36 PM PST 24
Peak memory 217868 kb
Host smart-4e4b067a-6d7d-4616-adc6-b5347ca65d20
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434928734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.434928734
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2337420809
Short name T810
Test name
Test status
Simulation time 356306813 ps
CPU time 3.65 seconds
Started Feb 07 01:42:34 PM PST 24
Finished Feb 07 01:42:38 PM PST 24
Peak memory 233016 kb
Host smart-d5f8eb68-a02b-4318-bff2-a485e20ae4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337420809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2337420809
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.641306041
Short name T814
Test name
Test status
Simulation time 4432756736 ps
CPU time 15.4 seconds
Started Feb 07 01:42:37 PM PST 24
Finished Feb 07 01:42:53 PM PST 24
Peak memory 233944 kb
Host smart-3b2f6c22-5f2f-4cdc-811e-83314658e173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641306041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.641306041
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2137512938
Short name T46
Test name
Test status
Simulation time 56022726 ps
CPU time 0.73 seconds
Started Feb 07 01:42:40 PM PST 24
Finished Feb 07 01:42:41 PM PST 24
Peak memory 216316 kb
Host smart-aab7cab2-44fa-48cd-a87e-82038b675c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137512938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2137512938
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1329312497
Short name T771
Test name
Test status
Simulation time 992309945 ps
CPU time 3.93 seconds
Started Feb 07 01:42:36 PM PST 24
Finished Feb 07 01:42:40 PM PST 24
Peak memory 219968 kb
Host smart-04a7d5c1-6d04-4ce4-a110-4bb86389d8d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1329312497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1329312497
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2943120983
Short name T51
Test name
Test status
Simulation time 1060231417 ps
CPU time 1.22 seconds
Started Feb 07 01:42:52 PM PST 24
Finished Feb 07 01:42:59 PM PST 24
Peak memory 235672 kb
Host smart-02fb8af4-54eb-4c6c-904e-66a39173c9a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943120983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2943120983
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.81069651
Short name T630
Test name
Test status
Simulation time 123272104036 ps
CPU time 432.59 seconds
Started Feb 07 01:43:00 PM PST 24
Finished Feb 07 01:50:19 PM PST 24
Peak memory 274180 kb
Host smart-9ba1208b-05d5-4930-9a22-01cede80a8e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81069651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_
all.81069651
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4108610285
Short name T539
Test name
Test status
Simulation time 2083108428 ps
CPU time 19.23 seconds
Started Feb 07 01:42:37 PM PST 24
Finished Feb 07 01:42:56 PM PST 24
Peak memory 216588 kb
Host smart-e6062270-4f4e-442c-b742-e28e2515f53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108610285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4108610285
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1923414225
Short name T972
Test name
Test status
Simulation time 20389199957 ps
CPU time 17.65 seconds
Started Feb 07 01:42:32 PM PST 24
Finished Feb 07 01:42:51 PM PST 24
Peak memory 216516 kb
Host smart-b911baa2-0ffc-4167-9031-e055b6862612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923414225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1923414225
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.745820437
Short name T805
Test name
Test status
Simulation time 73893796 ps
CPU time 1 seconds
Started Feb 07 01:42:37 PM PST 24
Finished Feb 07 01:42:38 PM PST 24
Peak memory 206496 kb
Host smart-31b8600f-a376-4095-b1b1-e7e08be1a7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745820437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.745820437
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.225232000
Short name T1082
Test name
Test status
Simulation time 359744729 ps
CPU time 0.98 seconds
Started Feb 07 01:42:32 PM PST 24
Finished Feb 07 01:42:34 PM PST 24
Peak memory 205884 kb
Host smart-a9367f39-bf21-49ac-85cc-36d286f19386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225232000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.225232000
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3521579988
Short name T556
Test name
Test status
Simulation time 2870110651 ps
CPU time 11.64 seconds
Started Feb 07 01:42:35 PM PST 24
Finished Feb 07 01:42:47 PM PST 24
Peak memory 239224 kb
Host smart-2f23cd35-25c2-46da-aafe-fc26c2574307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521579988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3521579988
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1446816472
Short name T834
Test name
Test status
Simulation time 36690655 ps
CPU time 0.71 seconds
Started Feb 07 01:45:23 PM PST 24
Finished Feb 07 01:45:24 PM PST 24
Peak memory 204496 kb
Host smart-21cae6ab-cb2d-4401-826a-830ca94196b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446816472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1446816472
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2119494668
Short name T173
Test name
Test status
Simulation time 5653119220 ps
CPU time 6.44 seconds
Started Feb 07 01:45:19 PM PST 24
Finished Feb 07 01:45:29 PM PST 24
Peak memory 224864 kb
Host smart-e08f507c-1149-4b58-bb85-39993181416a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119494668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2119494668
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3539461001
Short name T1004
Test name
Test status
Simulation time 60187352 ps
CPU time 0.73 seconds
Started Feb 07 01:45:21 PM PST 24
Finished Feb 07 01:45:24 PM PST 24
Peak memory 205220 kb
Host smart-601aff17-e558-4d45-8abb-1d862822a96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539461001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3539461001
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1074632699
Short name T1056
Test name
Test status
Simulation time 49617990654 ps
CPU time 210.74 seconds
Started Feb 07 01:45:19 PM PST 24
Finished Feb 07 01:48:53 PM PST 24
Peak memory 265676 kb
Host smart-255eda93-5ef2-4aa4-ab93-67e1252cc607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074632699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1074632699
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3663660027
Short name T699
Test name
Test status
Simulation time 25556654021 ps
CPU time 93.08 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:47:00 PM PST 24
Peak memory 240184 kb
Host smart-10463047-439e-4f37-90ac-b6c6d8bec41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663660027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3663660027
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.726585939
Short name T502
Test name
Test status
Simulation time 8138235277 ps
CPU time 94.42 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:47:01 PM PST 24
Peak memory 253608 kb
Host smart-8bbff7c7-f9e4-4713-a26f-c1de1f58a8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726585939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.726585939
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.794716237
Short name T809
Test name
Test status
Simulation time 7489086699 ps
CPU time 16.25 seconds
Started Feb 07 01:45:23 PM PST 24
Finished Feb 07 01:45:40 PM PST 24
Peak memory 244212 kb
Host smart-2efa8847-76bf-4b8d-94d1-548c84c51c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794716237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.794716237
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4112989060
Short name T141
Test name
Test status
Simulation time 1963042356 ps
CPU time 8.09 seconds
Started Feb 07 01:45:17 PM PST 24
Finished Feb 07 01:45:31 PM PST 24
Peak memory 219308 kb
Host smart-6d959f37-5707-4b01-956f-f30cd0462099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112989060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4112989060
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3803948678
Short name T958
Test name
Test status
Simulation time 610619877 ps
CPU time 6.04 seconds
Started Feb 07 01:45:14 PM PST 24
Finished Feb 07 01:45:27 PM PST 24
Peak memory 224268 kb
Host smart-54af55f0-e31b-4445-8a1f-621cddbc8f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803948678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3803948678
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1244245984
Short name T957
Test name
Test status
Simulation time 22314655924 ps
CPU time 17.43 seconds
Started Feb 07 01:45:20 PM PST 24
Finished Feb 07 01:45:40 PM PST 24
Peak memory 233688 kb
Host smart-175b8f77-d117-403e-a40e-e3dd6460c2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244245984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1244245984
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4139431985
Short name T537
Test name
Test status
Simulation time 705128966 ps
CPU time 3.19 seconds
Started Feb 07 01:45:22 PM PST 24
Finished Feb 07 01:45:26 PM PST 24
Peak memory 217012 kb
Host smart-46c3201d-ba2b-4a5a-987d-2b33fd902257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139431985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4139431985
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2668184276
Short name T129
Test name
Test status
Simulation time 2821572479 ps
CPU time 4.13 seconds
Started Feb 07 01:45:33 PM PST 24
Finished Feb 07 01:45:39 PM PST 24
Peak memory 222228 kb
Host smart-1e6bd84e-4fa8-4ca8-87e7-452271593db3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2668184276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2668184276
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2669757070
Short name T205
Test name
Test status
Simulation time 27628256670 ps
CPU time 86.81 seconds
Started Feb 07 01:45:20 PM PST 24
Finished Feb 07 01:46:50 PM PST 24
Peak memory 263232 kb
Host smart-66cfc229-f826-4113-b014-7bf54766d2d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669757070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2669757070
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.639917085
Short name T1057
Test name
Test status
Simulation time 20304380632 ps
CPU time 36.41 seconds
Started Feb 07 01:45:14 PM PST 24
Finished Feb 07 01:45:56 PM PST 24
Peak memory 216604 kb
Host smart-d6308afd-854d-47e7-9114-2ecc07e2bc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639917085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.639917085
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2870504907
Short name T293
Test name
Test status
Simulation time 2006611426 ps
CPU time 7.96 seconds
Started Feb 07 01:45:27 PM PST 24
Finished Feb 07 01:45:37 PM PST 24
Peak memory 208128 kb
Host smart-e21f2d57-768f-4766-8ebc-1d351bf6847a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870504907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2870504907
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3626920504
Short name T688
Test name
Test status
Simulation time 24863467 ps
CPU time 1.44 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 216676 kb
Host smart-6489afea-20a2-4318-acda-30efc08d1dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626920504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3626920504
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3477175094
Short name T1002
Test name
Test status
Simulation time 120776242 ps
CPU time 0.85 seconds
Started Feb 07 01:45:22 PM PST 24
Finished Feb 07 01:45:24 PM PST 24
Peak memory 205484 kb
Host smart-17c3abc8-99c8-44e5-9831-52e31f5f4891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477175094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3477175094
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3078161144
Short name T151
Test name
Test status
Simulation time 131102541 ps
CPU time 2.99 seconds
Started Feb 07 01:45:18 PM PST 24
Finished Feb 07 01:45:26 PM PST 24
Peak memory 232808 kb
Host smart-78424627-11f3-4c9d-8178-bd1031baa8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078161144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3078161144
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2768548888
Short name T581
Test name
Test status
Simulation time 33942804 ps
CPU time 0.72 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:45:30 PM PST 24
Peak memory 204964 kb
Host smart-aad70e08-392b-4bfa-9de3-3e48df82d9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768548888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2768548888
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2552279514
Short name T945
Test name
Test status
Simulation time 349370026 ps
CPU time 3.07 seconds
Started Feb 07 01:45:23 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 219392 kb
Host smart-031d7890-0992-4264-a465-1caaf63998d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552279514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2552279514
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1516789677
Short name T1043
Test name
Test status
Simulation time 14570900 ps
CPU time 0.73 seconds
Started Feb 07 01:45:29 PM PST 24
Finished Feb 07 01:45:31 PM PST 24
Peak memory 205524 kb
Host smart-7143c50b-011b-4ddf-acdf-007efd58e03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516789677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1516789677
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3001644363
Short name T156
Test name
Test status
Simulation time 8714715571 ps
CPU time 43.46 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 249460 kb
Host smart-63309f5b-9878-44da-95fa-18e0bb4c3624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001644363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3001644363
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.244791282
Short name T155
Test name
Test status
Simulation time 71909716340 ps
CPU time 523.01 seconds
Started Feb 07 01:45:26 PM PST 24
Finished Feb 07 01:54:10 PM PST 24
Peak memory 252104 kb
Host smart-873a8d4a-f4eb-413c-9bec-12eae49e2d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244791282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.244791282
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3656104023
Short name T855
Test name
Test status
Simulation time 50333259145 ps
CPU time 117.77 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:47:34 PM PST 24
Peak memory 252136 kb
Host smart-44fd420c-8eda-4e64-8f94-c5e533cd2610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656104023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3656104023
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.106966854
Short name T1084
Test name
Test status
Simulation time 774521734 ps
CPU time 12.05 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:45:41 PM PST 24
Peak memory 240940 kb
Host smart-852e1511-2493-4a09-9256-d37cc3efbc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106966854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.106966854
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4009965020
Short name T876
Test name
Test status
Simulation time 627692997 ps
CPU time 4.15 seconds
Started Feb 07 01:45:29 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 232956 kb
Host smart-d97054c5-1281-46c4-8d85-da3c170c21a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009965020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4009965020
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.131232838
Short name T959
Test name
Test status
Simulation time 9375029738 ps
CPU time 18.05 seconds
Started Feb 07 01:45:24 PM PST 24
Finished Feb 07 01:45:44 PM PST 24
Peak memory 248436 kb
Host smart-56543ed1-1166-4259-ae3c-fe17e091a55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131232838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.131232838
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3546171683
Short name T1087
Test name
Test status
Simulation time 739876257 ps
CPU time 3.4 seconds
Started Feb 07 01:45:33 PM PST 24
Finished Feb 07 01:45:38 PM PST 24
Peak memory 218040 kb
Host smart-3c2ff313-e038-4566-80e2-a4ec8f6071aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546171683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3546171683
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4141429508
Short name T180
Test name
Test status
Simulation time 8548168831 ps
CPU time 11.9 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:45:41 PM PST 24
Peak memory 233148 kb
Host smart-88ad4438-504c-4cd5-b707-d30246394f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141429508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4141429508
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.431899431
Short name T827
Test name
Test status
Simulation time 1101872344 ps
CPU time 4.35 seconds
Started Feb 07 01:45:29 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 222056 kb
Host smart-10097b9e-8378-4f02-a74f-1834070708b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=431899431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.431899431
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4087110662
Short name T792
Test name
Test status
Simulation time 8485426749 ps
CPU time 70.77 seconds
Started Feb 07 01:45:36 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 236304 kb
Host smart-1f728e70-af9e-4af6-b5a6-aa8f1bba0739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087110662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4087110662
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.393063072
Short name T596
Test name
Test status
Simulation time 15231017841 ps
CPU time 10.79 seconds
Started Feb 07 01:45:29 PM PST 24
Finished Feb 07 01:45:41 PM PST 24
Peak memory 216380 kb
Host smart-58f0939d-85a6-4397-b53e-880fe198d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393063072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.393063072
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1626735709
Short name T878
Test name
Test status
Simulation time 83750381 ps
CPU time 1.4 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:45:30 PM PST 24
Peak memory 208300 kb
Host smart-75dc8d7c-6463-4406-b680-4f8e990abfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626735709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1626735709
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.573463857
Short name T452
Test name
Test status
Simulation time 15060297 ps
CPU time 0.72 seconds
Started Feb 07 01:45:33 PM PST 24
Finished Feb 07 01:45:35 PM PST 24
Peak memory 205432 kb
Host smart-37e18274-800a-47a5-bc2d-4cc15a5e25d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573463857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.573463857
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1877536080
Short name T34
Test name
Test status
Simulation time 1256967618 ps
CPU time 8.9 seconds
Started Feb 07 01:45:24 PM PST 24
Finished Feb 07 01:45:35 PM PST 24
Peak memory 240572 kb
Host smart-4b1f7bf5-989a-44ca-aece-58abe132b3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877536080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1877536080
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4254848957
Short name T910
Test name
Test status
Simulation time 30037611 ps
CPU time 0.73 seconds
Started Feb 07 01:45:35 PM PST 24
Finished Feb 07 01:45:37 PM PST 24
Peak memory 205336 kb
Host smart-ae4c59f8-a9af-403e-aec9-614fd16c2714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254848957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4254848957
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1967702735
Short name T624
Test name
Test status
Simulation time 1524179167 ps
CPU time 3.62 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:45:35 PM PST 24
Peak memory 233452 kb
Host smart-850859b1-4219-476e-a3cf-a09db45e69bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967702735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1967702735
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2256399413
Short name T828
Test name
Test status
Simulation time 20882828 ps
CPU time 0.75 seconds
Started Feb 07 01:45:36 PM PST 24
Finished Feb 07 01:45:38 PM PST 24
Peak memory 205260 kb
Host smart-901074af-d8f4-4b5e-b9e3-712d6a0f8100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256399413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2256399413
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1863121227
Short name T1055
Test name
Test status
Simulation time 681242357587 ps
CPU time 325.47 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:50:56 PM PST 24
Peak memory 265840 kb
Host smart-8aa9dc7b-d13c-41b8-90f4-3ec2070e8045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863121227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1863121227
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3567754794
Short name T920
Test name
Test status
Simulation time 6652505589 ps
CPU time 47.22 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 235272 kb
Host smart-e7a15234-ccf2-4ded-a5c5-db09717b8fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567754794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3567754794
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1054012502
Short name T1086
Test name
Test status
Simulation time 6702828896 ps
CPU time 64.05 seconds
Started Feb 07 01:45:27 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 240980 kb
Host smart-c7c0087e-d7df-41b5-9162-31646a9f033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054012502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1054012502
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4218899556
Short name T1030
Test name
Test status
Simulation time 2733660994 ps
CPU time 32.07 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:46:06 PM PST 24
Peak memory 251228 kb
Host smart-8c7fbc6e-de1a-4ab9-8be7-23fe958cb651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218899556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4218899556
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.880825710
Short name T300
Test name
Test status
Simulation time 235903016 ps
CPU time 2.36 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:45:31 PM PST 24
Peak memory 217148 kb
Host smart-d336165d-d199-40fe-9491-c737320bacf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880825710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.880825710
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1315996638
Short name T752
Test name
Test status
Simulation time 13211401162 ps
CPU time 9.67 seconds
Started Feb 07 01:45:36 PM PST 24
Finished Feb 07 01:45:47 PM PST 24
Peak memory 224864 kb
Host smart-90128aa3-1a56-4f60-a8d1-18aed5f4c0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315996638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1315996638
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1020085131
Short name T199
Test name
Test status
Simulation time 2187025489 ps
CPU time 9.57 seconds
Started Feb 07 01:45:26 PM PST 24
Finished Feb 07 01:45:37 PM PST 24
Peak memory 235560 kb
Host smart-ddefc7a7-ed86-4ec8-8ff0-4fa882f895e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020085131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1020085131
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.988898381
Short name T436
Test name
Test status
Simulation time 105801285 ps
CPU time 2.47 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:45:36 PM PST 24
Peak memory 224708 kb
Host smart-7562bc8f-a66a-4f1a-9fdf-9d58d81ce470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988898381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.988898381
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3689429249
Short name T474
Test name
Test status
Simulation time 18031090082 ps
CPU time 6.03 seconds
Started Feb 07 01:45:36 PM PST 24
Finished Feb 07 01:45:44 PM PST 24
Peak memory 222960 kb
Host smart-c4107fb8-8e3f-499d-8c9d-6531f4bb7cd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3689429249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3689429249
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.63040203
Short name T875
Test name
Test status
Simulation time 7720800982 ps
CPU time 66.19 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 216568 kb
Host smart-f1ba7bcf-a791-4371-a0e0-770b003a6e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63040203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.63040203
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2125457305
Short name T650
Test name
Test status
Simulation time 19634462679 ps
CPU time 30.59 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:46:02 PM PST 24
Peak memory 216612 kb
Host smart-32e23db9-d47b-47db-8345-27786b19854f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125457305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2125457305
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3574588727
Short name T1006
Test name
Test status
Simulation time 411398246 ps
CPU time 9.56 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:45:43 PM PST 24
Peak memory 216496 kb
Host smart-371ca6ef-867b-4c11-8a8a-d630065bbcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574588727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3574588727
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.640725816
Short name T552
Test name
Test status
Simulation time 309630315 ps
CPU time 1.05 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:45:28 PM PST 24
Peak memory 206464 kb
Host smart-7efad59b-4f9e-459e-8912-c1c87a199a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640725816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.640725816
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2989440122
Short name T1053
Test name
Test status
Simulation time 29550648753 ps
CPU time 19.88 seconds
Started Feb 07 01:45:25 PM PST 24
Finished Feb 07 01:45:46 PM PST 24
Peak memory 224860 kb
Host smart-a69208a8-411f-429a-8c05-cf4e99102f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989440122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2989440122
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1886639998
Short name T697
Test name
Test status
Simulation time 26728411 ps
CPU time 0.71 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 204472 kb
Host smart-7fbd622f-704d-4151-87c8-81e77653a962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886639998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1886639998
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1818266335
Short name T577
Test name
Test status
Simulation time 1691728573 ps
CPU time 8.24 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:45:39 PM PST 24
Peak memory 219292 kb
Host smart-ecb52494-f682-4928-ba5e-50208f9aad66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818266335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1818266335
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.225710431
Short name T867
Test name
Test status
Simulation time 68406875 ps
CPU time 0.78 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 206192 kb
Host smart-04ed6058-2a10-4bb1-8596-5a2373467a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225710431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.225710431
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3246190071
Short name T201
Test name
Test status
Simulation time 44868869179 ps
CPU time 228.07 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:49:19 PM PST 24
Peak memory 265756 kb
Host smart-edb5c056-6c3b-4e96-a3f2-aa3a23168d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246190071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3246190071
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2702585439
Short name T543
Test name
Test status
Simulation time 2742629331 ps
CPU time 46.28 seconds
Started Feb 07 01:45:36 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 237688 kb
Host smart-3ccf463b-1152-4ea2-b0e5-8c50b7c397fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702585439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2702585439
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2725270652
Short name T816
Test name
Test status
Simulation time 7665805783 ps
CPU time 76.38 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:46:47 PM PST 24
Peak memory 250248 kb
Host smart-82499fd1-daf3-4f0d-b4ca-7eadaa86ee71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725270652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2725270652
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4204817695
Short name T444
Test name
Test status
Simulation time 732679912 ps
CPU time 12.58 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:45:44 PM PST 24
Peak memory 241096 kb
Host smart-a470c88e-c37a-4f45-a8a9-e17c529a78ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204817695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4204817695
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1003615464
Short name T303
Test name
Test status
Simulation time 822971252 ps
CPU time 4.48 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 233936 kb
Host smart-73b7d2b7-60b4-406a-963e-a99788d55811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003615464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1003615464
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1313439264
Short name T923
Test name
Test status
Simulation time 5423494180 ps
CPU time 12.66 seconds
Started Feb 07 01:45:33 PM PST 24
Finished Feb 07 01:45:47 PM PST 24
Peak memory 224836 kb
Host smart-602765e6-d42d-4af5-9aec-0d1d980f90f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313439264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1313439264
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2512149330
Short name T533
Test name
Test status
Simulation time 3361300333 ps
CPU time 10.49 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:45:41 PM PST 24
Peak memory 241172 kb
Host smart-c3b1ef28-6fd0-4f1f-b36c-ebd9ee31c3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512149330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2512149330
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1824609507
Short name T622
Test name
Test status
Simulation time 7331504476 ps
CPU time 19.82 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:45:49 PM PST 24
Peak memory 233384 kb
Host smart-e78396ce-e228-485b-b151-3305dc88a652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824609507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1824609507
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1493949290
Short name T842
Test name
Test status
Simulation time 610894077 ps
CPU time 4.13 seconds
Started Feb 07 01:45:31 PM PST 24
Finished Feb 07 01:45:36 PM PST 24
Peak memory 218900 kb
Host smart-77c70288-df55-4583-a44a-3a808bef9268
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1493949290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1493949290
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.676770156
Short name T966
Test name
Test status
Simulation time 23211285981 ps
CPU time 159.28 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:48:10 PM PST 24
Peak memory 236300 kb
Host smart-ae4dda4b-fcb2-4d88-9512-fcab6af8f13e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676770156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.676770156
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.952775524
Short name T705
Test name
Test status
Simulation time 1924883589 ps
CPU time 24.69 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:45:56 PM PST 24
Peak memory 216480 kb
Host smart-729b7b82-f28d-463e-af38-7073165e1d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952775524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.952775524
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2344568570
Short name T426
Test name
Test status
Simulation time 500086456 ps
CPU time 1.46 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:45:32 PM PST 24
Peak memory 206748 kb
Host smart-bbb75eb3-af12-4ff1-b55d-f314e55208e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344568570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2344568570
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2931385098
Short name T967
Test name
Test status
Simulation time 430103100 ps
CPU time 8.71 seconds
Started Feb 07 01:45:24 PM PST 24
Finished Feb 07 01:45:35 PM PST 24
Peak memory 216744 kb
Host smart-ae7991d0-d365-48c6-b392-2b737e2b8b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931385098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2931385098
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3470370076
Short name T795
Test name
Test status
Simulation time 168011673 ps
CPU time 0.73 seconds
Started Feb 07 01:45:35 PM PST 24
Finished Feb 07 01:45:37 PM PST 24
Peak memory 205488 kb
Host smart-d2c92cad-3beb-4b45-83d2-08fd66c8ce3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470370076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3470370076
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3429110335
Short name T874
Test name
Test status
Simulation time 494907102 ps
CPU time 8.08 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:45:41 PM PST 24
Peak memory 233320 kb
Host smart-24f4af3c-8ce5-4aac-b41d-77d81fae2523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429110335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3429110335
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.61731983
Short name T612
Test name
Test status
Simulation time 19576966 ps
CPU time 0.7 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:45:36 PM PST 24
Peak memory 205356 kb
Host smart-237b853a-fab5-4184-b9b6-a87eaa80eebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61731983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.61731983
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2797436281
Short name T826
Test name
Test status
Simulation time 221169587 ps
CPU time 2.32 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:45:35 PM PST 24
Peak memory 216764 kb
Host smart-a28cad25-151f-4872-974a-b1f419c93210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797436281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2797436281
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.450461857
Short name T632
Test name
Test status
Simulation time 13618654 ps
CPU time 0.8 seconds
Started Feb 07 01:45:33 PM PST 24
Finished Feb 07 01:45:36 PM PST 24
Peak memory 206488 kb
Host smart-e2ec5782-3cbb-4af3-9008-212ebd37d742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450461857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.450461857
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.837034232
Short name T666
Test name
Test status
Simulation time 2615226163 ps
CPU time 33.52 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:46:07 PM PST 24
Peak memory 240568 kb
Host smart-1c6d11dc-b50f-45b2-b030-b5753ff582ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837034232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.837034232
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3103374477
Short name T760
Test name
Test status
Simulation time 15455397629 ps
CPU time 83.73 seconds
Started Feb 07 01:45:46 PM PST 24
Finished Feb 07 01:47:15 PM PST 24
Peak memory 249324 kb
Host smart-4be82d50-d202-4473-94ab-d99c4031fa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103374477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3103374477
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.184021374
Short name T475
Test name
Test status
Simulation time 7805037026 ps
CPU time 101.49 seconds
Started Feb 07 01:45:46 PM PST 24
Finished Feb 07 01:47:33 PM PST 24
Peak memory 251436 kb
Host smart-9e2fdb7b-d402-40ba-8d1b-e7221cc2f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184021374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.184021374
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2045139018
Short name T518
Test name
Test status
Simulation time 6244325561 ps
CPU time 23.86 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:46:00 PM PST 24
Peak memory 224824 kb
Host smart-f21c1ecb-2eac-4e5d-acdc-9d7705518491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045139018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2045139018
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2112318087
Short name T902
Test name
Test status
Simulation time 14181619107 ps
CPU time 13.81 seconds
Started Feb 07 01:45:46 PM PST 24
Finished Feb 07 01:46:06 PM PST 24
Peak memory 222288 kb
Host smart-b8ea4166-837e-472b-abd9-71b7455540c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112318087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2112318087
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2033990902
Short name T153
Test name
Test status
Simulation time 3713659919 ps
CPU time 13.53 seconds
Started Feb 07 01:45:33 PM PST 24
Finished Feb 07 01:45:48 PM PST 24
Peak memory 232640 kb
Host smart-0f58f16d-76c4-4792-9d1e-4a9ad50bcee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033990902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2033990902
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.816322335
Short name T932
Test name
Test status
Simulation time 2545177377 ps
CPU time 8.93 seconds
Started Feb 07 01:45:43 PM PST 24
Finished Feb 07 01:45:54 PM PST 24
Peak memory 233088 kb
Host smart-81c6532d-e7f7-4e04-a3a4-f873f139b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816322335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.816322335
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3057464386
Short name T150
Test name
Test status
Simulation time 1316014381 ps
CPU time 6.66 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:45:36 PM PST 24
Peak memory 216660 kb
Host smart-d4333c4a-3d8a-4740-8ece-86b1e351b733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057464386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3057464386
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2745912558
Short name T703
Test name
Test status
Simulation time 5691133274 ps
CPU time 5.35 seconds
Started Feb 07 01:45:33 PM PST 24
Finished Feb 07 01:45:40 PM PST 24
Peak memory 219128 kb
Host smart-2a5c65c4-5d3a-4a40-9a43-9e5d23830a5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2745912558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2745912558
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.347410942
Short name T551
Test name
Test status
Simulation time 158982789 ps
CPU time 0.91 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 206572 kb
Host smart-c7645e4f-901b-4186-8b6e-6128a29bea13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347410942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.347410942
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1740154522
Short name T997
Test name
Test status
Simulation time 7950214446 ps
CPU time 31.72 seconds
Started Feb 07 01:45:28 PM PST 24
Finished Feb 07 01:46:01 PM PST 24
Peak memory 216568 kb
Host smart-bba393fb-ae43-4954-a365-27de2c0331d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740154522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1740154522
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3522983130
Short name T302
Test name
Test status
Simulation time 1120055312 ps
CPU time 6.76 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:45:38 PM PST 24
Peak memory 216384 kb
Host smart-b451cde1-9e0e-4a87-9f30-b1c83c61b2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522983130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3522983130
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2444108047
Short name T868
Test name
Test status
Simulation time 326850900 ps
CPU time 4.14 seconds
Started Feb 07 01:45:29 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 208960 kb
Host smart-8197921b-e704-4c8a-ab8f-bd5d745c85bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444108047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2444108047
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.436240708
Short name T120
Test name
Test status
Simulation time 39072523 ps
CPU time 0.71 seconds
Started Feb 07 01:45:30 PM PST 24
Finished Feb 07 01:45:32 PM PST 24
Peak memory 205500 kb
Host smart-55090f49-63d9-474e-8adb-95814a4de78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436240708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.436240708
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.654842785
Short name T765
Test name
Test status
Simulation time 20023174780 ps
CPU time 18.26 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:45:51 PM PST 24
Peak memory 238956 kb
Host smart-52d3e193-bd37-4e93-8398-b12bfb596a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654842785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.654842785
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1795476494
Short name T580
Test name
Test status
Simulation time 40861872 ps
CPU time 0.66 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:45:37 PM PST 24
Peak memory 205120 kb
Host smart-1eeecf02-1291-4177-b8ea-9539e384211b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795476494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1795476494
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.849499452
Short name T899
Test name
Test status
Simulation time 280422113 ps
CPU time 4.98 seconds
Started Feb 07 01:45:46 PM PST 24
Finished Feb 07 01:45:57 PM PST 24
Peak memory 233448 kb
Host smart-02fcbf9d-a1e2-4879-a61a-caf8f8522290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849499452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.849499452
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2170237186
Short name T501
Test name
Test status
Simulation time 24295743 ps
CPU time 0.77 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:45:37 PM PST 24
Peak memory 206268 kb
Host smart-bc3ba319-7499-4eda-a739-d6dfed26b29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170237186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2170237186
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.726569178
Short name T200
Test name
Test status
Simulation time 18110453642 ps
CPU time 77.89 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:46:54 PM PST 24
Peak memory 256732 kb
Host smart-6340f032-e1aa-4a09-adb4-ea60b2807287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726569178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.726569178
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1399029705
Short name T1074
Test name
Test status
Simulation time 68347760391 ps
CPU time 134.81 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:47:51 PM PST 24
Peak memory 239180 kb
Host smart-7a02a883-4141-4da1-9efa-b087ae2d2db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399029705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1399029705
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3995962445
Short name T498
Test name
Test status
Simulation time 6740993969 ps
CPU time 15.03 seconds
Started Feb 07 01:45:35 PM PST 24
Finished Feb 07 01:45:52 PM PST 24
Peak memory 233192 kb
Host smart-2e29ac0b-f288-4ead-b1cf-4d358930f41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995962445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3995962445
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1319301731
Short name T907
Test name
Test status
Simulation time 1056638862 ps
CPU time 6.97 seconds
Started Feb 07 01:45:44 PM PST 24
Finished Feb 07 01:45:52 PM PST 24
Peak memory 232920 kb
Host smart-148e6471-d283-443f-937c-7c2d527df13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319301731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1319301731
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.901632567
Short name T908
Test name
Test status
Simulation time 1157106871 ps
CPU time 6.53 seconds
Started Feb 07 01:45:35 PM PST 24
Finished Feb 07 01:45:43 PM PST 24
Peak memory 234040 kb
Host smart-d4369d5e-8b7e-4832-9dc4-8fac2757661e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901632567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.901632567
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3546764763
Short name T626
Test name
Test status
Simulation time 313892724 ps
CPU time 2.87 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:45:38 PM PST 24
Peak memory 218996 kb
Host smart-50b5b273-5262-4772-9de7-631423da6671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546764763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3546764763
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1485942465
Short name T241
Test name
Test status
Simulation time 1257462561 ps
CPU time 3.86 seconds
Started Feb 07 01:45:33 PM PST 24
Finished Feb 07 01:45:38 PM PST 24
Peak memory 233428 kb
Host smart-159ea2df-f705-4107-a2da-9d9575320333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485942465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1485942465
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4158768913
Short name T657
Test name
Test status
Simulation time 4096151040 ps
CPU time 9.08 seconds
Started Feb 07 01:45:46 PM PST 24
Finished Feb 07 01:46:01 PM PST 24
Peak memory 235800 kb
Host smart-df17edb2-5d5f-4801-be68-7c51e83208c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158768913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4158768913
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3024712073
Short name T922
Test name
Test status
Simulation time 27877733678 ps
CPU time 6.35 seconds
Started Feb 07 01:45:45 PM PST 24
Finished Feb 07 01:45:55 PM PST 24
Peak memory 218808 kb
Host smart-c680d4b2-5a16-43a4-9499-2ed47078dc23
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3024712073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3024712073
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3760460126
Short name T514
Test name
Test status
Simulation time 200601904 ps
CPU time 1.04 seconds
Started Feb 07 01:45:33 PM PST 24
Finished Feb 07 01:45:36 PM PST 24
Peak memory 206604 kb
Host smart-d3599942-ec8f-46ca-978c-20e250c868b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760460126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3760460126
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.995222849
Short name T140
Test name
Test status
Simulation time 8535588061 ps
CPU time 127.02 seconds
Started Feb 07 01:45:43 PM PST 24
Finished Feb 07 01:47:52 PM PST 24
Peak memory 216580 kb
Host smart-607c68aa-db3e-47d5-98b8-b2da3234a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995222849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.995222849
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1478911571
Short name T555
Test name
Test status
Simulation time 7708546316 ps
CPU time 24.39 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:46:01 PM PST 24
Peak memory 216604 kb
Host smart-e6a8c8b5-ae6c-4573-a4ed-5eff3121757e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478911571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1478911571
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.454342244
Short name T652
Test name
Test status
Simulation time 106276113 ps
CPU time 0.94 seconds
Started Feb 07 01:45:45 PM PST 24
Finished Feb 07 01:45:50 PM PST 24
Peak memory 206576 kb
Host smart-212edd91-4778-4990-9bba-51f1e6621544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454342244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.454342244
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.4076439292
Short name T770
Test name
Test status
Simulation time 33554622 ps
CPU time 0.85 seconds
Started Feb 07 01:45:45 PM PST 24
Finished Feb 07 01:45:50 PM PST 24
Peak memory 205312 kb
Host smart-21b0a55b-e5f1-4cf1-ac7e-c9f68a6dd4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076439292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4076439292
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.502220781
Short name T676
Test name
Test status
Simulation time 6784872844 ps
CPU time 21.35 seconds
Started Feb 07 01:45:45 PM PST 24
Finished Feb 07 01:46:10 PM PST 24
Peak memory 233960 kb
Host smart-c6c83a83-1da2-4973-9667-fb7bd6b8f9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502220781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.502220781
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3040148688
Short name T718
Test name
Test status
Simulation time 21668187 ps
CPU time 0.71 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:45:34 PM PST 24
Peak memory 204456 kb
Host smart-e447a582-ce42-4408-979b-6066cc61deb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040148688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3040148688
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4143556312
Short name T262
Test name
Test status
Simulation time 1337318904 ps
CPU time 4.93 seconds
Started Feb 07 01:45:43 PM PST 24
Finished Feb 07 01:45:50 PM PST 24
Peak memory 224768 kb
Host smart-7f25004a-7c52-4505-ba46-0b52530d39a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143556312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4143556312
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1870073614
Short name T560
Test name
Test status
Simulation time 26016834 ps
CPU time 0.76 seconds
Started Feb 07 01:45:45 PM PST 24
Finished Feb 07 01:45:50 PM PST 24
Peak memory 206516 kb
Host smart-498fe9b4-f83f-4803-9dce-b616c472fe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870073614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1870073614
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.264644175
Short name T202
Test name
Test status
Simulation time 8775545995 ps
CPU time 44.6 seconds
Started Feb 07 01:45:37 PM PST 24
Finished Feb 07 01:46:23 PM PST 24
Peak memory 249728 kb
Host smart-37c16354-361d-4c4f-b49c-9a13650319db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264644175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.264644175
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3421399256
Short name T146
Test name
Test status
Simulation time 10474328582 ps
CPU time 120.9 seconds
Started Feb 07 01:45:43 PM PST 24
Finished Feb 07 01:47:46 PM PST 24
Peak memory 250640 kb
Host smart-b2afcd81-8871-4813-9092-79610875a5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421399256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3421399256
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1347556936
Short name T914
Test name
Test status
Simulation time 3020387911 ps
CPU time 11.2 seconds
Started Feb 07 01:45:35 PM PST 24
Finished Feb 07 01:45:48 PM PST 24
Peak memory 233928 kb
Host smart-373f594d-eb17-47a2-88d7-d3e85342a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347556936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1347556936
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2821938343
Short name T625
Test name
Test status
Simulation time 948412157 ps
CPU time 6.69 seconds
Started Feb 07 01:45:35 PM PST 24
Finished Feb 07 01:45:44 PM PST 24
Peak memory 233376 kb
Host smart-4d1589f1-50e3-46fc-ad5c-c9d403b6c157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821938343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2821938343
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3259512872
Short name T464
Test name
Test status
Simulation time 15678157367 ps
CPU time 39.65 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:46:16 PM PST 24
Peak memory 234516 kb
Host smart-a1d02abe-efd7-41bf-9e6d-019e499676af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259512872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3259512872
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1711906871
Short name T1052
Test name
Test status
Simulation time 471256183 ps
CPU time 4.35 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:45:40 PM PST 24
Peak memory 217992 kb
Host smart-3b82bf39-ab8f-49c9-a51f-6e122b55f35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711906871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1711906871
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2699232560
Short name T890
Test name
Test status
Simulation time 17791648520 ps
CPU time 27.51 seconds
Started Feb 07 01:45:32 PM PST 24
Finished Feb 07 01:46:00 PM PST 24
Peak memory 233952 kb
Host smart-86b25557-69ad-48a0-8c13-62b25fccbfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699232560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2699232560
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4126575236
Short name T16
Test name
Test status
Simulation time 279995346 ps
CPU time 3.6 seconds
Started Feb 07 01:45:38 PM PST 24
Finished Feb 07 01:45:43 PM PST 24
Peak memory 222688 kb
Host smart-ddcf7a5a-48d7-4ff4-8693-d715c8b523a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4126575236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4126575236
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3077314396
Short name T80
Test name
Test status
Simulation time 288223851416 ps
CPU time 411.8 seconds
Started Feb 07 01:45:31 PM PST 24
Finished Feb 07 01:52:24 PM PST 24
Peak memory 272736 kb
Host smart-f48e9ebd-c79d-470a-a1ee-dc6d9a941d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077314396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3077314396
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1595276972
Short name T1062
Test name
Test status
Simulation time 2130959151 ps
CPU time 27.68 seconds
Started Feb 07 01:45:46 PM PST 24
Finished Feb 07 01:46:19 PM PST 24
Peak memory 216216 kb
Host smart-52f3dbf6-14c7-471c-b6ce-ff7daf392746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595276972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1595276972
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.15871445
Short name T912
Test name
Test status
Simulation time 9087093281 ps
CPU time 14.08 seconds
Started Feb 07 01:45:38 PM PST 24
Finished Feb 07 01:45:53 PM PST 24
Peak memory 216572 kb
Host smart-4c6afb64-ef80-4a98-a998-c758fc57620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15871445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.15871445
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.372320699
Short name T962
Test name
Test status
Simulation time 374914619 ps
CPU time 4.17 seconds
Started Feb 07 01:45:40 PM PST 24
Finished Feb 07 01:45:45 PM PST 24
Peak memory 208344 kb
Host smart-b30c5cb1-0bf7-4f7f-8738-ca221cd3daca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372320699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.372320699
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3551006520
Short name T840
Test name
Test status
Simulation time 70707703 ps
CPU time 0.77 seconds
Started Feb 07 01:45:35 PM PST 24
Finished Feb 07 01:45:38 PM PST 24
Peak memory 205480 kb
Host smart-23f6b301-4fdd-4f1c-8dec-fa4706bd30c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551006520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3551006520
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4261914244
Short name T554
Test name
Test status
Simulation time 16632236989 ps
CPU time 15.58 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:45:52 PM PST 24
Peak memory 233744 kb
Host smart-e46ab2ac-ac6a-4c68-928b-378347d10094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261914244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4261914244
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.977087946
Short name T1036
Test name
Test status
Simulation time 18525373 ps
CPU time 0.71 seconds
Started Feb 07 01:45:48 PM PST 24
Finished Feb 07 01:45:52 PM PST 24
Peak memory 204480 kb
Host smart-995f3447-37a4-4435-81f3-e23fcf5de3a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977087946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.977087946
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3459602738
Short name T445
Test name
Test status
Simulation time 873754516 ps
CPU time 4.73 seconds
Started Feb 07 01:45:49 PM PST 24
Finished Feb 07 01:45:56 PM PST 24
Peak memory 224784 kb
Host smart-7892543a-dd72-4158-b8ff-5a26d4227d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459602738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3459602738
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3192417238
Short name T53
Test name
Test status
Simulation time 101786186 ps
CPU time 0.77 seconds
Started Feb 07 01:45:41 PM PST 24
Finished Feb 07 01:45:42 PM PST 24
Peak memory 205232 kb
Host smart-57750289-aff1-4d8d-8c79-01abf154eecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192417238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3192417238
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3569866828
Short name T627
Test name
Test status
Simulation time 23676276732 ps
CPU time 121.62 seconds
Started Feb 07 01:45:59 PM PST 24
Finished Feb 07 01:48:02 PM PST 24
Peak memory 241260 kb
Host smart-da7165bb-83c1-4b8a-a218-7364bc08b543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569866828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3569866828
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2231931307
Short name T279
Test name
Test status
Simulation time 6738439068 ps
CPU time 56.85 seconds
Started Feb 07 01:45:47 PM PST 24
Finished Feb 07 01:46:49 PM PST 24
Peak memory 249264 kb
Host smart-b058a6b1-bed7-419b-b0da-36af8c521a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231931307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2231931307
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2382822475
Short name T713
Test name
Test status
Simulation time 3857413751 ps
CPU time 23.41 seconds
Started Feb 07 01:45:47 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 245756 kb
Host smart-841a6e74-a081-45cd-bb46-5578f25a87e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382822475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2382822475
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1092524799
Short name T530
Test name
Test status
Simulation time 175444322 ps
CPU time 3.23 seconds
Started Feb 07 01:45:55 PM PST 24
Finished Feb 07 01:46:00 PM PST 24
Peak memory 234004 kb
Host smart-96b9d630-8781-45d3-9b02-1abf1f42aea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092524799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1092524799
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3918404381
Short name T615
Test name
Test status
Simulation time 603327921 ps
CPU time 6.08 seconds
Started Feb 07 01:45:46 PM PST 24
Finished Feb 07 01:45:58 PM PST 24
Peak memory 232904 kb
Host smart-b93b94ab-e176-45e6-9b9e-97909d62cb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918404381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3918404381
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1064366417
Short name T177
Test name
Test status
Simulation time 5405347511 ps
CPU time 8.3 seconds
Started Feb 07 01:45:40 PM PST 24
Finished Feb 07 01:45:49 PM PST 24
Peak memory 217984 kb
Host smart-d4b30d9d-6a9a-4cbd-9b4e-8d20a4849ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064366417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1064366417
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.837598704
Short name T824
Test name
Test status
Simulation time 1581364679 ps
CPU time 7.3 seconds
Started Feb 07 01:45:44 PM PST 24
Finished Feb 07 01:45:53 PM PST 24
Peak memory 234288 kb
Host smart-68dfa262-bdc2-4260-aab8-0b08e3e67319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837598704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.837598704
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2706412955
Short name T499
Test name
Test status
Simulation time 1014701496 ps
CPU time 4.99 seconds
Started Feb 07 01:45:51 PM PST 24
Finished Feb 07 01:46:00 PM PST 24
Peak memory 216508 kb
Host smart-0415830f-01cc-4670-beba-43a19d393114
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2706412955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2706412955
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2710100681
Short name T633
Test name
Test status
Simulation time 14677493550 ps
CPU time 117.74 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:47:34 PM PST 24
Peak memory 219356 kb
Host smart-d7de231a-c661-4514-a537-74565799a91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710100681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2710100681
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1514142780
Short name T682
Test name
Test status
Simulation time 2523032585 ps
CPU time 13.6 seconds
Started Feb 07 01:45:34 PM PST 24
Finished Feb 07 01:45:50 PM PST 24
Peak memory 216592 kb
Host smart-2a27bbd7-64d3-4b7c-8469-71994d13a2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514142780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1514142780
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2369152480
Short name T1046
Test name
Test status
Simulation time 69023970 ps
CPU time 1.5 seconds
Started Feb 07 01:45:41 PM PST 24
Finished Feb 07 01:45:43 PM PST 24
Peak memory 208288 kb
Host smart-2e6b2f7f-eb9f-4f10-a0a9-f85bc05ca8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369152480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2369152480
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.70302575
Short name T773
Test name
Test status
Simulation time 167984647 ps
CPU time 0.92 seconds
Started Feb 07 01:45:41 PM PST 24
Finished Feb 07 01:45:43 PM PST 24
Peak memory 205468 kb
Host smart-d9e63f30-1e57-426b-abe5-de01f22621ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70302575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.70302575
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2635975756
Short name T78
Test name
Test status
Simulation time 5154760360 ps
CPU time 11.05 seconds
Started Feb 07 01:45:50 PM PST 24
Finished Feb 07 01:46:03 PM PST 24
Peak memory 238608 kb
Host smart-9339d61d-cb7a-4c79-b139-12b3ef08cdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635975756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2635975756
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.358864144
Short name T822
Test name
Test status
Simulation time 177068840 ps
CPU time 0.72 seconds
Started Feb 07 01:45:54 PM PST 24
Finished Feb 07 01:45:56 PM PST 24
Peak memory 204468 kb
Host smart-1f47ef13-e76f-47d6-b1be-54335665bd80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358864144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.358864144
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.868459173
Short name T866
Test name
Test status
Simulation time 33133122 ps
CPU time 2.55 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:46:04 PM PST 24
Peak memory 233140 kb
Host smart-8f40d218-5c58-4086-b1f6-0f350adb841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868459173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.868459173
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2340649061
Short name T428
Test name
Test status
Simulation time 14277422 ps
CPU time 0.77 seconds
Started Feb 07 01:45:48 PM PST 24
Finished Feb 07 01:45:53 PM PST 24
Peak memory 206232 kb
Host smart-95dc724a-0ca6-44bf-92bb-a67dc3140893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340649061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2340649061
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1723233934
Short name T608
Test name
Test status
Simulation time 23360451227 ps
CPU time 113.86 seconds
Started Feb 07 01:45:59 PM PST 24
Finished Feb 07 01:47:54 PM PST 24
Peak memory 251584 kb
Host smart-8f1bfb5d-3a78-4890-bb3c-2d7012ad180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723233934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1723233934
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2865949481
Short name T546
Test name
Test status
Simulation time 18620917988 ps
CPU time 65.96 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:47:08 PM PST 24
Peak memory 234244 kb
Host smart-9293c617-b3c9-4ae8-8fa0-532a73957e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865949481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2865949481
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2595201135
Short name T831
Test name
Test status
Simulation time 44219892442 ps
CPU time 70.28 seconds
Started Feb 07 01:45:54 PM PST 24
Finished Feb 07 01:47:06 PM PST 24
Peak memory 253264 kb
Host smart-8e7ce9e8-d8ac-4ebd-9419-58fbcfa19a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595201135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2595201135
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3334898158
Short name T157
Test name
Test status
Simulation time 21058065159 ps
CPU time 19.7 seconds
Started Feb 07 01:45:49 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 233840 kb
Host smart-0792c87f-7f44-45cc-b264-0460964d312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334898158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3334898158
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.15466936
Short name T246
Test name
Test status
Simulation time 9980342472 ps
CPU time 14.48 seconds
Started Feb 07 01:45:47 PM PST 24
Finished Feb 07 01:46:06 PM PST 24
Peak memory 239432 kb
Host smart-a9d74746-5080-4525-986f-911d5d428f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15466936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.15466936
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3460276023
Short name T731
Test name
Test status
Simulation time 12981261661 ps
CPU time 15.66 seconds
Started Feb 07 01:45:48 PM PST 24
Finished Feb 07 01:46:07 PM PST 24
Peak memory 238060 kb
Host smart-ce4ccb5c-5803-436f-9232-cf284ee30eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460276023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3460276023
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4062287403
Short name T696
Test name
Test status
Simulation time 1744935924 ps
CPU time 7.2 seconds
Started Feb 07 01:45:48 PM PST 24
Finished Feb 07 01:45:59 PM PST 24
Peak memory 256232 kb
Host smart-24b4d2a0-c287-4234-ac35-1fbacc1fae46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062287403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4062287403
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3617126965
Short name T895
Test name
Test status
Simulation time 273898519 ps
CPU time 3.37 seconds
Started Feb 07 01:45:53 PM PST 24
Finished Feb 07 01:45:59 PM PST 24
Peak memory 222012 kb
Host smart-03d1dab5-4c26-4819-9bc6-9ee459479cea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3617126965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3617126965
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3855039323
Short name T213
Test name
Test status
Simulation time 52540293747 ps
CPU time 382.31 seconds
Started Feb 07 01:45:56 PM PST 24
Finished Feb 07 01:52:20 PM PST 24
Peak memory 265244 kb
Host smart-ec042087-a9ac-4f83-a01c-fd560eae2c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855039323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3855039323
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4226405616
Short name T271
Test name
Test status
Simulation time 26557434507 ps
CPU time 93.81 seconds
Started Feb 07 01:45:47 PM PST 24
Finished Feb 07 01:47:26 PM PST 24
Peak memory 216660 kb
Host smart-0d136b4f-f289-4e50-a1a4-4e1ecbda0fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226405616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4226405616
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1749502290
Short name T19
Test name
Test status
Simulation time 7828799333 ps
CPU time 24.01 seconds
Started Feb 07 01:45:50 PM PST 24
Finished Feb 07 01:46:17 PM PST 24
Peak memory 216596 kb
Host smart-db273213-768f-4686-9d9c-451735aad846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749502290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1749502290
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.4272908211
Short name T455
Test name
Test status
Simulation time 181500341 ps
CPU time 5.52 seconds
Started Feb 07 01:45:52 PM PST 24
Finished Feb 07 01:46:01 PM PST 24
Peak memory 216464 kb
Host smart-a52c317b-ace5-431c-a61c-0d057eaa8ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272908211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.4272908211
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3668486900
Short name T734
Test name
Test status
Simulation time 132231632 ps
CPU time 1.05 seconds
Started Feb 07 01:45:48 PM PST 24
Finished Feb 07 01:45:53 PM PST 24
Peak memory 206488 kb
Host smart-671fd1c9-6a4a-4a77-91b3-2007391740f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668486900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3668486900
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.567937998
Short name T675
Test name
Test status
Simulation time 474813828 ps
CPU time 6.54 seconds
Started Feb 07 01:46:02 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 240664 kb
Host smart-f07f263c-63bb-461a-8fa2-373ebe114e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567937998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.567937998
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3806169116
Short name T977
Test name
Test status
Simulation time 17382313 ps
CPU time 0.72 seconds
Started Feb 07 01:45:59 PM PST 24
Finished Feb 07 01:46:01 PM PST 24
Peak memory 204424 kb
Host smart-69fc90be-29f4-419c-80fd-11854c8780c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806169116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3806169116
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2055056084
Short name T103
Test name
Test status
Simulation time 2515161598 ps
CPU time 6.34 seconds
Started Feb 07 01:46:01 PM PST 24
Finished Feb 07 01:46:10 PM PST 24
Peak memory 233168 kb
Host smart-3e544bd4-1622-43b1-ab63-90f9371eb63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055056084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2055056084
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1327279873
Short name T774
Test name
Test status
Simulation time 37148159 ps
CPU time 0.77 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:46:03 PM PST 24
Peak memory 206292 kb
Host smart-dd997dcd-f578-4dc4-959f-52b05d7c315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327279873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1327279873
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1568187550
Short name T768
Test name
Test status
Simulation time 107193778956 ps
CPU time 145.4 seconds
Started Feb 07 01:45:58 PM PST 24
Finished Feb 07 01:48:24 PM PST 24
Peak memory 253416 kb
Host smart-5b83ebf8-fdd6-4d5f-b331-d2096fe1483b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568187550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1568187550
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1061537067
Short name T149
Test name
Test status
Simulation time 44361174206 ps
CPU time 59.12 seconds
Started Feb 07 01:45:58 PM PST 24
Finished Feb 07 01:46:58 PM PST 24
Peak memory 252972 kb
Host smart-e30a5ece-e8fb-49f9-99fc-6401d099eaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061537067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1061537067
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4243052538
Short name T621
Test name
Test status
Simulation time 186742948814 ps
CPU time 342.21 seconds
Started Feb 07 01:46:04 PM PST 24
Finished Feb 07 01:51:47 PM PST 24
Peak memory 257544 kb
Host smart-0d28a10a-7330-4ede-b848-92337f7dae94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243052538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4243052538
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4087665588
Short name T131
Test name
Test status
Simulation time 1459752178 ps
CPU time 13.39 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 237128 kb
Host smart-71e4a50e-6fd1-431c-a7bc-7144fceaf3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087665588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4087665588
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1864302821
Short name T838
Test name
Test status
Simulation time 9099239758 ps
CPU time 9.5 seconds
Started Feb 07 01:45:57 PM PST 24
Finished Feb 07 01:46:08 PM PST 24
Peak memory 220764 kb
Host smart-3f1728bb-28e2-4353-a21c-2e6ed3c1dd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864302821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1864302821
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2709242803
Short name T265
Test name
Test status
Simulation time 17358909622 ps
CPU time 45.41 seconds
Started Feb 07 01:46:05 PM PST 24
Finished Feb 07 01:46:52 PM PST 24
Peak memory 238784 kb
Host smart-6aa40eb8-fca6-4ac5-976f-03e99bf69cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709242803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2709242803
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.129192792
Short name T1106
Test name
Test status
Simulation time 1741450829 ps
CPU time 8.94 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:18 PM PST 24
Peak memory 224780 kb
Host smart-96817de8-4c2b-4c17-9e53-103f176b0841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129192792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.129192792
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1815569455
Short name T701
Test name
Test status
Simulation time 3856776910 ps
CPU time 9.73 seconds
Started Feb 07 01:46:01 PM PST 24
Finished Feb 07 01:46:13 PM PST 24
Peak memory 237628 kb
Host smart-de4d93d2-f802-4afc-8c1f-4cc2e329c81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815569455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1815569455
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1884176994
Short name T1107
Test name
Test status
Simulation time 1593898863 ps
CPU time 4.59 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:46:06 PM PST 24
Peak memory 222704 kb
Host smart-e22f987e-bb58-442b-af9f-b8931931ddb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1884176994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1884176994
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3349328007
Short name T1037
Test name
Test status
Simulation time 149048844916 ps
CPU time 269.39 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:50:30 PM PST 24
Peak memory 241420 kb
Host smart-3e1d7dc2-364c-4156-8bea-dadc0fedc5cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349328007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3349328007
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2972428944
Short name T659
Test name
Test status
Simulation time 3458158329 ps
CPU time 31.08 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:46:32 PM PST 24
Peak memory 216580 kb
Host smart-11ea5aec-1c73-45a1-9fd0-b9343a4a7ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972428944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2972428944
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.881682185
Short name T830
Test name
Test status
Simulation time 3751534250 ps
CPU time 11.95 seconds
Started Feb 07 01:46:02 PM PST 24
Finished Feb 07 01:46:17 PM PST 24
Peak memory 217248 kb
Host smart-a1fa6671-28b3-4e35-b9e0-ab687ea0fdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881682185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.881682185
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.256333287
Short name T585
Test name
Test status
Simulation time 54394885 ps
CPU time 1.28 seconds
Started Feb 07 01:46:01 PM PST 24
Finished Feb 07 01:46:04 PM PST 24
Peak memory 216524 kb
Host smart-b640fa3e-323e-4377-84a2-8d1434a6e041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256333287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.256333287
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3038378355
Short name T692
Test name
Test status
Simulation time 97682521 ps
CPU time 1.04 seconds
Started Feb 07 01:46:03 PM PST 24
Finished Feb 07 01:46:06 PM PST 24
Peak memory 206508 kb
Host smart-10982fda-62d4-4bc3-bf67-95f4fcf6236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038378355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3038378355
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1276708750
Short name T709
Test name
Test status
Simulation time 1674819453 ps
CPU time 8.52 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:18 PM PST 24
Peak memory 241076 kb
Host smart-6cda339d-cc8b-40d5-91d3-8469948e05b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276708750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1276708750
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2182330819
Short name T485
Test name
Test status
Simulation time 41508646 ps
CPU time 0.69 seconds
Started Feb 07 01:43:00 PM PST 24
Finished Feb 07 01:43:07 PM PST 24
Peak memory 204924 kb
Host smart-64333360-ff5d-4187-a696-ec65451577a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182330819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
182330819
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4088444512
Short name T721
Test name
Test status
Simulation time 8407003771 ps
CPU time 6.08 seconds
Started Feb 07 01:42:53 PM PST 24
Finished Feb 07 01:43:04 PM PST 24
Peak memory 235460 kb
Host smart-9fe0f846-63c3-4f11-9c50-80c6eb248133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088444512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4088444512
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4107892566
Short name T8
Test name
Test status
Simulation time 41237976 ps
CPU time 0.79 seconds
Started Feb 07 01:42:50 PM PST 24
Finished Feb 07 01:42:52 PM PST 24
Peak memory 206244 kb
Host smart-bd7e13ad-e52f-43cf-a770-e9c791f68ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107892566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4107892566
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.595665995
Short name T685
Test name
Test status
Simulation time 30469964160 ps
CPU time 72.24 seconds
Started Feb 07 01:42:59 PM PST 24
Finished Feb 07 01:44:19 PM PST 24
Peak memory 249500 kb
Host smart-b302af06-bf8e-4f70-b179-5ad825bd3cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595665995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.595665995
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.428750973
Short name T869
Test name
Test status
Simulation time 27317629663 ps
CPU time 215.08 seconds
Started Feb 07 01:42:49 PM PST 24
Finished Feb 07 01:46:25 PM PST 24
Peak memory 238652 kb
Host smart-767406e5-2a7c-4881-a755-32f2a5133b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428750973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.428750973
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2920087379
Short name T251
Test name
Test status
Simulation time 6985589902 ps
CPU time 95.21 seconds
Started Feb 07 01:43:00 PM PST 24
Finished Feb 07 01:44:42 PM PST 24
Peak memory 264072 kb
Host smart-6d1cbed9-8b59-4e53-9372-6d2b2819f359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920087379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2920087379
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3785581479
Short name T748
Test name
Test status
Simulation time 36387128083 ps
CPU time 40.66 seconds
Started Feb 07 01:42:52 PM PST 24
Finished Feb 07 01:43:38 PM PST 24
Peak memory 240980 kb
Host smart-209d15cd-d81f-4c50-9cc9-b445f817bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785581479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3785581479
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1847001729
Short name T819
Test name
Test status
Simulation time 117671148 ps
CPU time 2.77 seconds
Started Feb 07 01:42:52 PM PST 24
Finished Feb 07 01:42:57 PM PST 24
Peak memory 233848 kb
Host smart-d8345c49-f0e0-4d21-9327-23da7121c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847001729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1847001729
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2930038984
Short name T668
Test name
Test status
Simulation time 25787291248 ps
CPU time 7.58 seconds
Started Feb 07 01:43:03 PM PST 24
Finished Feb 07 01:43:15 PM PST 24
Peak memory 228200 kb
Host smart-d04d4900-3544-4fe4-ac42-234c3cfc4cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930038984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2930038984
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1302260490
Short name T454
Test name
Test status
Simulation time 18455263 ps
CPU time 1.03 seconds
Started Feb 07 01:43:01 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 216636 kb
Host smart-c96b5e7f-0dc8-4e2a-8a5b-4404ef0d70a6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302260490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1302260490
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2608481719
Short name T872
Test name
Test status
Simulation time 1303161165 ps
CPU time 5.04 seconds
Started Feb 07 01:42:55 PM PST 24
Finished Feb 07 01:43:09 PM PST 24
Peak memory 233664 kb
Host smart-dea2d743-11d8-403e-8215-d5b7d2ed7b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608481719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2608481719
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3214927658
Short name T863
Test name
Test status
Simulation time 11350043357 ps
CPU time 26.75 seconds
Started Feb 07 01:42:52 PM PST 24
Finished Feb 07 01:43:21 PM PST 24
Peak memory 224828 kb
Host smart-4883c200-71b4-43dd-ab7a-ac8a9023b5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214927658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3214927658
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.1842495236
Short name T747
Test name
Test status
Simulation time 35169741 ps
CPU time 0.73 seconds
Started Feb 07 01:42:56 PM PST 24
Finished Feb 07 01:43:04 PM PST 24
Peak memory 216336 kb
Host smart-a5b25d33-1bfb-4069-ad59-a82dd4711c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842495236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1842495236
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1830623347
Short name T645
Test name
Test status
Simulation time 585291859 ps
CPU time 3.94 seconds
Started Feb 07 01:42:52 PM PST 24
Finished Feb 07 01:42:58 PM PST 24
Peak memory 222200 kb
Host smart-ffb12082-9b9e-4fcd-879d-89a6eed885de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1830623347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1830623347
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.453417090
Short name T297
Test name
Test status
Simulation time 1344686692 ps
CPU time 1.15 seconds
Started Feb 07 01:42:52 PM PST 24
Finished Feb 07 01:42:55 PM PST 24
Peak memory 206508 kb
Host smart-261e883b-5b6a-4b3b-b3da-7e1ac04c8fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453417090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.453417090
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1279551021
Short name T18
Test name
Test status
Simulation time 2089264324 ps
CPU time 29.09 seconds
Started Feb 07 01:42:53 PM PST 24
Finished Feb 07 01:43:27 PM PST 24
Peak memory 216680 kb
Host smart-592cb291-20fd-4e36-8fcf-dcc08b057860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279551021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1279551021
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1778857983
Short name T470
Test name
Test status
Simulation time 4625983679 ps
CPU time 15.12 seconds
Started Feb 07 01:42:59 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 216680 kb
Host smart-6114403d-a20f-465a-94d7-c0fffdcc1145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778857983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1778857983
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.104605489
Short name T602
Test name
Test status
Simulation time 981063928 ps
CPU time 9.08 seconds
Started Feb 07 01:42:52 PM PST 24
Finished Feb 07 01:43:03 PM PST 24
Peak memory 216540 kb
Host smart-279f8009-70d2-47c9-bd84-ced152eff458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104605489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.104605489
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1475400184
Short name T755
Test name
Test status
Simulation time 56708242 ps
CPU time 0.86 seconds
Started Feb 07 01:42:50 PM PST 24
Finished Feb 07 01:42:52 PM PST 24
Peak memory 205484 kb
Host smart-99b6635f-1501-412f-95f9-bfb7e6f7ac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475400184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1475400184
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2619786626
Short name T1054
Test name
Test status
Simulation time 287524537 ps
CPU time 5.2 seconds
Started Feb 07 01:42:51 PM PST 24
Finished Feb 07 01:42:59 PM PST 24
Peak memory 240144 kb
Host smart-e18aeb39-4176-43de-9a36-b5e622d53a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619786626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2619786626
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2411907146
Short name T955
Test name
Test status
Simulation time 16609526 ps
CPU time 0.76 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 205040 kb
Host smart-189813ed-d728-48fb-b802-e8f5e6c64c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411907146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
411907146
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1298554111
Short name T119
Test name
Test status
Simulation time 1236747260 ps
CPU time 3.59 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:11 PM PST 24
Peak memory 224776 kb
Host smart-6a9d39d2-9e4b-4e03-a737-a71ed9015ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298554111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1298554111
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.492150843
Short name T964
Test name
Test status
Simulation time 159215633 ps
CPU time 0.74 seconds
Started Feb 07 01:42:50 PM PST 24
Finished Feb 07 01:42:52 PM PST 24
Peak memory 205528 kb
Host smart-0f0e2473-fa57-45d3-b227-77a8aead8b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492150843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.492150843
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1708139685
Short name T1024
Test name
Test status
Simulation time 7515126546 ps
CPU time 56.91 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:44:04 PM PST 24
Peak memory 247208 kb
Host smart-2c7f0eab-0f70-4cf4-8e0b-46ffb477687e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708139685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1708139685
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1862461981
Short name T694
Test name
Test status
Simulation time 13598384070 ps
CPU time 114.22 seconds
Started Feb 07 01:43:04 PM PST 24
Finished Feb 07 01:45:04 PM PST 24
Peak memory 251972 kb
Host smart-290263d3-c189-49c1-b983-bb8c657aea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862461981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1862461981
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3554385107
Short name T1022
Test name
Test status
Simulation time 52133032565 ps
CPU time 328.44 seconds
Started Feb 07 01:43:03 PM PST 24
Finished Feb 07 01:48:36 PM PST 24
Peak memory 254660 kb
Host smart-dc1f953c-23f3-4ae5-8992-3d84cc3f6a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554385107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3554385107
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3677364869
Short name T935
Test name
Test status
Simulation time 8813167823 ps
CPU time 49.19 seconds
Started Feb 07 01:43:03 PM PST 24
Finished Feb 07 01:43:56 PM PST 24
Peak memory 240824 kb
Host smart-b4cf7236-b625-4425-a147-1900ffe1a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677364869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3677364869
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4032528684
Short name T482
Test name
Test status
Simulation time 599878351 ps
CPU time 4.1 seconds
Started Feb 07 01:42:55 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 217848 kb
Host smart-cfabe31c-e8eb-4f14-a256-b584cbbe845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032528684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4032528684
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2386509972
Short name T726
Test name
Test status
Simulation time 420378293 ps
CPU time 5.9 seconds
Started Feb 07 01:43:05 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 216800 kb
Host smart-b004db60-ece7-4b61-b050-b5977ac77864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386509972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2386509972
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.450803236
Short name T1047
Test name
Test status
Simulation time 15816530 ps
CPU time 0.98 seconds
Started Feb 07 01:42:53 PM PST 24
Finished Feb 07 01:42:59 PM PST 24
Peak memory 217856 kb
Host smart-a99a90f2-51f6-43b7-a944-78e866818363
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450803236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.450803236
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.807770393
Short name T1094
Test name
Test status
Simulation time 1462912918 ps
CPU time 9.41 seconds
Started Feb 07 01:42:48 PM PST 24
Finished Feb 07 01:42:58 PM PST 24
Peak memory 219100 kb
Host smart-0628ed4e-ed11-4808-8693-113bebac69b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807770393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
807770393
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.910688007
Short name T253
Test name
Test status
Simulation time 22812487714 ps
CPU time 25.62 seconds
Started Feb 07 01:42:50 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 219568 kb
Host smart-56ed3409-76d7-4360-bd70-c293de5053a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910688007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.910688007
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.72913203
Short name T862
Test name
Test status
Simulation time 19711936 ps
CPU time 0.76 seconds
Started Feb 07 01:42:53 PM PST 24
Finished Feb 07 01:42:59 PM PST 24
Peak memory 216364 kb
Host smart-817ddf97-b694-42e4-bac1-8d050c2f26b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72913203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.72913203
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2382397985
Short name T786
Test name
Test status
Simulation time 70225092 ps
CPU time 2.95 seconds
Started Feb 07 01:43:03 PM PST 24
Finished Feb 07 01:43:10 PM PST 24
Peak memory 220064 kb
Host smart-73cf2920-fd06-4187-b674-cae0e95fbd22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2382397985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2382397985
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1662526870
Short name T1066
Test name
Test status
Simulation time 126708467 ps
CPU time 1.09 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 206584 kb
Host smart-66a61b47-1586-4b1c-8a2a-b4e7729ac8e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662526870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1662526870
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3682334247
Short name T983
Test name
Test status
Simulation time 1505124121 ps
CPU time 19.56 seconds
Started Feb 07 01:42:52 PM PST 24
Finished Feb 07 01:43:14 PM PST 24
Peak memory 216344 kb
Host smart-d1e88171-3f22-446a-b18e-6cb49fc24c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682334247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3682334247
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2652359859
Short name T1069
Test name
Test status
Simulation time 3497225139 ps
CPU time 5.25 seconds
Started Feb 07 01:42:49 PM PST 24
Finished Feb 07 01:42:55 PM PST 24
Peak memory 216628 kb
Host smart-3dfc8c20-85a4-421d-900a-f0fe4aeeac5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652359859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2652359859
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3533768053
Short name T1064
Test name
Test status
Simulation time 196785273 ps
CPU time 3.3 seconds
Started Feb 07 01:43:01 PM PST 24
Finished Feb 07 01:43:10 PM PST 24
Peak memory 216656 kb
Host smart-f2347cf7-9dbe-4288-9bb8-364b7bd6a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533768053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3533768053
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3962445368
Short name T749
Test name
Test status
Simulation time 42621391 ps
CPU time 0.81 seconds
Started Feb 07 01:42:51 PM PST 24
Finished Feb 07 01:42:54 PM PST 24
Peak memory 205428 kb
Host smart-31a4957e-d73c-4c94-b27b-b09ae428194e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962445368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3962445368
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.583662155
Short name T570
Test name
Test status
Simulation time 71226149 ps
CPU time 2.77 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:10 PM PST 24
Peak memory 224760 kb
Host smart-2ac05dc4-d722-4293-92cd-c42920d2f924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583662155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.583662155
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2695730651
Short name T1090
Test name
Test status
Simulation time 13433651 ps
CPU time 0.74 seconds
Started Feb 07 01:43:00 PM PST 24
Finished Feb 07 01:43:07 PM PST 24
Peak memory 204428 kb
Host smart-bd30366e-edcb-4093-83d2-e7abb607884f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695730651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
695730651
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4256815338
Short name T841
Test name
Test status
Simulation time 1600472952 ps
CPU time 6.87 seconds
Started Feb 07 01:43:01 PM PST 24
Finished Feb 07 01:43:14 PM PST 24
Peak memory 236544 kb
Host smart-5c3cde80-f67a-46cb-ac8f-45e72ed3ea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256815338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4256815338
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3978241695
Short name T911
Test name
Test status
Simulation time 21501855 ps
CPU time 0.82 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 206232 kb
Host smart-ba9b998c-f44b-4e20-b3c4-175c38054a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978241695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3978241695
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.512811136
Short name T259
Test name
Test status
Simulation time 2913790817 ps
CPU time 34.85 seconds
Started Feb 07 01:43:00 PM PST 24
Finished Feb 07 01:43:41 PM PST 24
Peak memory 235120 kb
Host smart-f13a0b5f-be48-4ba2-9433-fbee7d8cb8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512811136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.512811136
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1726185658
Short name T722
Test name
Test status
Simulation time 33203318643 ps
CPU time 76.82 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:44:24 PM PST 24
Peak memory 238812 kb
Host smart-ac300cea-a5e8-4213-a10c-06086e6d1633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726185658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1726185658
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1825483498
Short name T208
Test name
Test status
Simulation time 152031400149 ps
CPU time 318.81 seconds
Started Feb 07 01:43:01 PM PST 24
Finished Feb 07 01:48:25 PM PST 24
Peak memory 239732 kb
Host smart-c454083a-fd8e-4122-98fa-186853f61d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825483498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1825483498
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1234581459
Short name T248
Test name
Test status
Simulation time 4616512165 ps
CPU time 15.4 seconds
Started Feb 07 01:43:01 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 234852 kb
Host smart-45d60ecf-59a0-4ea7-9964-1911c775e515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234581459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1234581459
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1924231753
Short name T494
Test name
Test status
Simulation time 304287732 ps
CPU time 3.13 seconds
Started Feb 07 01:43:05 PM PST 24
Finished Feb 07 01:43:13 PM PST 24
Peak memory 233112 kb
Host smart-9f4bd9ef-c8a8-4523-8d29-2908cc858670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924231753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1924231753
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.4009180075
Short name T1001
Test name
Test status
Simulation time 24157201321 ps
CPU time 20.56 seconds
Started Feb 07 01:43:05 PM PST 24
Finished Feb 07 01:43:31 PM PST 24
Peak memory 238136 kb
Host smart-b786f148-0e5f-4548-856c-cdfbcf120750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009180075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.4009180075
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.924767362
Short name T26
Test name
Test status
Simulation time 25185980 ps
CPU time 1.04 seconds
Started Feb 07 01:43:00 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 216628 kb
Host smart-ed8ace4d-9715-454b-b79a-5f8bdc00a8d2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924767362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.924767362
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2288554460
Short name T571
Test name
Test status
Simulation time 5518749718 ps
CPU time 5.69 seconds
Started Feb 07 01:43:04 PM PST 24
Finished Feb 07 01:43:15 PM PST 24
Peak memory 216692 kb
Host smart-52e947f5-0bfa-4193-97df-89ed5c6837d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288554460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2288554460
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.2775164342
Short name T956
Test name
Test status
Simulation time 41528374 ps
CPU time 0.73 seconds
Started Feb 07 01:43:03 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 216364 kb
Host smart-4f851269-5216-4273-93fa-b2009656a415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775164342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2775164342
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3664154480
Short name T886
Test name
Test status
Simulation time 1168913936 ps
CPU time 4.02 seconds
Started Feb 07 01:43:06 PM PST 24
Finished Feb 07 01:43:14 PM PST 24
Peak memory 222024 kb
Host smart-bc209304-4387-4e19-aa63-b6a828e2a5ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3664154480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3664154480
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2972902958
Short name T223
Test name
Test status
Simulation time 506083231298 ps
CPU time 489.65 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:51:17 PM PST 24
Peak memory 290236 kb
Host smart-f7f746ff-20a0-4966-ac49-4344cd815230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972902958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2972902958
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1643660395
Short name T461
Test name
Test status
Simulation time 50900609593 ps
CPU time 150.49 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:45:41 PM PST 24
Peak memory 216680 kb
Host smart-d7e3837a-7051-4edc-afa0-68e8e0cdd9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643660395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1643660395
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1888307945
Short name T853
Test name
Test status
Simulation time 18694476821 ps
CPU time 18.54 seconds
Started Feb 07 01:43:08 PM PST 24
Finished Feb 07 01:43:29 PM PST 24
Peak memory 216568 kb
Host smart-e24d39a4-50e8-4107-9100-5e2ef5b56c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888307945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1888307945
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2927746715
Short name T882
Test name
Test status
Simulation time 23696528 ps
CPU time 0.83 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 206032 kb
Host smart-295a21cb-c5ab-44df-8457-12e2c9e4e2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927746715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2927746715
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3841752812
Short name T54
Test name
Test status
Simulation time 23625965 ps
CPU time 0.76 seconds
Started Feb 07 01:43:01 PM PST 24
Finished Feb 07 01:43:07 PM PST 24
Peak memory 205480 kb
Host smart-4fec713f-cc10-42ac-8c36-e121ff1bbb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841752812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3841752812
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.672220629
Short name T1102
Test name
Test status
Simulation time 18824973769 ps
CPU time 15.08 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 227372 kb
Host smart-fad9ae8f-2a98-4a21-aa52-cc73b53d219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672220629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.672220629
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2731789869
Short name T2
Test name
Test status
Simulation time 90493938 ps
CPU time 0.72 seconds
Started Feb 07 01:43:14 PM PST 24
Finished Feb 07 01:43:15 PM PST 24
Peak memory 204392 kb
Host smart-b875a21f-797c-4177-9534-91d9d3f02e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731789869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
731789869
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4007177014
Short name T662
Test name
Test status
Simulation time 6462416609 ps
CPU time 4.65 seconds
Started Feb 07 01:43:09 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 218764 kb
Host smart-93ba61c0-410d-4310-bb28-bfd7ad22d213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007177014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4007177014
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3091932950
Short name T887
Test name
Test status
Simulation time 43516466 ps
CPU time 0.72 seconds
Started Feb 07 01:43:08 PM PST 24
Finished Feb 07 01:43:12 PM PST 24
Peak memory 205208 kb
Host smart-2f9fb11c-6902-4c09-8aba-1aa932345bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091932950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3091932950
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1528838070
Short name T1044
Test name
Test status
Simulation time 10361064330 ps
CPU time 38.42 seconds
Started Feb 07 01:43:20 PM PST 24
Finished Feb 07 01:44:00 PM PST 24
Peak memory 241152 kb
Host smart-203c905b-731c-496e-943c-e752800eb9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528838070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1528838070
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.989528720
Short name T1099
Test name
Test status
Simulation time 55017952185 ps
CPU time 251.06 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:47:21 PM PST 24
Peak memory 256300 kb
Host smart-4e8750b0-c362-40b3-b6ea-d7f4b6b2d6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989528720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.989528720
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.755075322
Short name T216
Test name
Test status
Simulation time 27707166558 ps
CPU time 147.94 seconds
Started Feb 07 01:43:09 PM PST 24
Finished Feb 07 01:45:39 PM PST 24
Peak memory 257736 kb
Host smart-d3ee9fe1-e295-4823-ad3e-3f9ac61b1f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755075322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
755075322
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2357363211
Short name T589
Test name
Test status
Simulation time 41199916685 ps
CPU time 29.22 seconds
Started Feb 07 01:43:05 PM PST 24
Finished Feb 07 01:43:39 PM PST 24
Peak memory 238908 kb
Host smart-a7483be1-cc15-4dea-83bc-21b667986df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357363211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2357363211
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.352329965
Short name T152
Test name
Test status
Simulation time 9132868465 ps
CPU time 8 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:15 PM PST 24
Peak memory 234040 kb
Host smart-5b010521-4227-40d9-b093-2cfddfe00b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352329965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.352329965
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3307168463
Short name T728
Test name
Test status
Simulation time 1391101736 ps
CPU time 9.03 seconds
Started Feb 07 01:43:11 PM PST 24
Finished Feb 07 01:43:21 PM PST 24
Peak memory 236016 kb
Host smart-f792b5b4-41bc-4dc1-b83d-98344e58d49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307168463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3307168463
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.570545673
Short name T467
Test name
Test status
Simulation time 71348056 ps
CPU time 1.04 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 216632 kb
Host smart-60a3f161-d18b-47b0-8883-f404ff4d1710
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570545673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.570545673
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2656082162
Short name T224
Test name
Test status
Simulation time 883036926 ps
CPU time 7.1 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:43:17 PM PST 24
Peak memory 233556 kb
Host smart-3bd10437-17f8-41a9-a4ce-ad0641470bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656082162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2656082162
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2326334014
Short name T5
Test name
Test status
Simulation time 31485702486 ps
CPU time 23.46 seconds
Started Feb 07 01:43:06 PM PST 24
Finished Feb 07 01:43:34 PM PST 24
Peak memory 236264 kb
Host smart-cc923fec-db62-48b8-b614-234090ccc476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326334014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2326334014
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.3866253238
Short name T758
Test name
Test status
Simulation time 17284004 ps
CPU time 0.74 seconds
Started Feb 07 01:43:09 PM PST 24
Finished Feb 07 01:43:12 PM PST 24
Peak memory 216280 kb
Host smart-b9138315-eaed-4e87-b2a8-86203852360c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866253238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3866253238
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.452968803
Short name T790
Test name
Test status
Simulation time 1250901000 ps
CPU time 3.49 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:43:14 PM PST 24
Peak memory 220312 kb
Host smart-1a80bf37-bb7d-49e7-a1d6-e5df0ce1c7d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=452968803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.452968803
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1787195860
Short name T258
Test name
Test status
Simulation time 2789231790 ps
CPU time 43.62 seconds
Started Feb 07 01:43:09 PM PST 24
Finished Feb 07 01:43:55 PM PST 24
Peak memory 254876 kb
Host smart-a1cf2793-00ff-4366-b508-fc4c1d082244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787195860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1787195860
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1402322709
Short name T950
Test name
Test status
Simulation time 3313731270 ps
CPU time 16.92 seconds
Started Feb 07 01:43:01 PM PST 24
Finished Feb 07 01:43:23 PM PST 24
Peak memory 216632 kb
Host smart-974b9321-bef8-443f-a7a1-d6276a1ca7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402322709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1402322709
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1619992395
Short name T545
Test name
Test status
Simulation time 496804757 ps
CPU time 2.03 seconds
Started Feb 07 01:43:02 PM PST 24
Finished Feb 07 01:43:09 PM PST 24
Peak memory 206716 kb
Host smart-d8e8024e-7fc4-4e91-b5c3-16847318a8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619992395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1619992395
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1250751398
Short name T746
Test name
Test status
Simulation time 304272802 ps
CPU time 3.88 seconds
Started Feb 07 01:43:03 PM PST 24
Finished Feb 07 01:43:11 PM PST 24
Peak memory 216468 kb
Host smart-4e867769-a6b7-4c4a-b9bc-9dfa785c312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250751398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1250751398
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1263333788
Short name T574
Test name
Test status
Simulation time 354651763 ps
CPU time 0.82 seconds
Started Feb 07 01:43:04 PM PST 24
Finished Feb 07 01:43:10 PM PST 24
Peak memory 206548 kb
Host smart-67a17fc0-6b5e-4b15-baa0-37a87b8c68f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263333788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1263333788
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3224068632
Short name T641
Test name
Test status
Simulation time 2497120600 ps
CPU time 10.35 seconds
Started Feb 07 01:43:14 PM PST 24
Finished Feb 07 01:43:25 PM PST 24
Peak memory 220124 kb
Host smart-4b1744d8-a9a7-4e23-9322-89a48d1d40dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224068632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3224068632
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1863201453
Short name T794
Test name
Test status
Simulation time 35581465 ps
CPU time 0.73 seconds
Started Feb 07 01:43:06 PM PST 24
Finished Feb 07 01:43:11 PM PST 24
Peak memory 205032 kb
Host smart-5cc442d1-fc5e-473e-be5c-09af19af5b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863201453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
863201453
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3835323310
Short name T483
Test name
Test status
Simulation time 1054996692 ps
CPU time 4.01 seconds
Started Feb 07 01:43:11 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 224708 kb
Host smart-7ec276ad-5732-4f5c-a17e-9e02bcb35146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835323310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3835323310
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2551718540
Short name T433
Test name
Test status
Simulation time 18462292 ps
CPU time 0.81 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:43:11 PM PST 24
Peak memory 205160 kb
Host smart-babe3a2f-f516-4e4a-b95e-54c2e6de7afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551718540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2551718540
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4162332787
Short name T1018
Test name
Test status
Simulation time 6346120149 ps
CPU time 54.05 seconds
Started Feb 07 01:43:06 PM PST 24
Finished Feb 07 01:44:04 PM PST 24
Peak memory 265820 kb
Host smart-34cbf1e1-a25f-48d7-b896-5d08d5d7f131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162332787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4162332787
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3757775932
Short name T654
Test name
Test status
Simulation time 327812377330 ps
CPU time 372.67 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:49:23 PM PST 24
Peak memory 255092 kb
Host smart-96a72038-f29a-4927-a6c4-d4bf097c1258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757775932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3757775932
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.503444181
Short name T222
Test name
Test status
Simulation time 14208305091 ps
CPU time 59.11 seconds
Started Feb 07 01:43:11 PM PST 24
Finished Feb 07 01:44:11 PM PST 24
Peak memory 251200 kb
Host smart-0e6c59ae-a93c-476a-9675-83638c821da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503444181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
503444181
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3876101214
Short name T296
Test name
Test status
Simulation time 18789756065 ps
CPU time 42.27 seconds
Started Feb 07 01:43:12 PM PST 24
Finished Feb 07 01:43:55 PM PST 24
Peak memory 245916 kb
Host smart-6ead7e9f-b960-4899-bba7-16c05b35f015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876101214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3876101214
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2673038478
Short name T1095
Test name
Test status
Simulation time 2576473846 ps
CPU time 6.71 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:43:17 PM PST 24
Peak memory 233764 kb
Host smart-fa682d5f-138e-4d55-a4a2-dc827ceefc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673038478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2673038478
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3890456114
Short name T707
Test name
Test status
Simulation time 4250529491 ps
CPU time 4.07 seconds
Started Feb 07 01:43:10 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 234236 kb
Host smart-7d346b97-f71a-4a41-8b70-0ccf6a4d74e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890456114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3890456114
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2363664128
Short name T423
Test name
Test status
Simulation time 26930723 ps
CPU time 1.08 seconds
Started Feb 07 01:43:14 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 216588 kb
Host smart-610fbe37-70b9-4528-a239-a6addc980f52
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363664128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2363664128
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2556813381
Short name T634
Test name
Test status
Simulation time 3916526941 ps
CPU time 17.32 seconds
Started Feb 07 01:43:06 PM PST 24
Finished Feb 07 01:43:27 PM PST 24
Peak memory 239136 kb
Host smart-51772f24-d9cb-4ded-8f3c-044e8e8edf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556813381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2556813381
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.550928038
Short name T689
Test name
Test status
Simulation time 712391136 ps
CPU time 6.52 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:43:17 PM PST 24
Peak memory 220612 kb
Host smart-fa17d588-cece-4c6e-9373-e1c39f3d8bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550928038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.550928038
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.3876813486
Short name T829
Test name
Test status
Simulation time 17078779 ps
CPU time 0.73 seconds
Started Feb 07 01:43:10 PM PST 24
Finished Feb 07 01:43:12 PM PST 24
Peak memory 216280 kb
Host smart-0b0b3cb6-91f8-42d8-b9e7-280ecbcce66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876813486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.3876813486
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.782270749
Short name T1110
Test name
Test status
Simulation time 13012070030 ps
CPU time 5.56 seconds
Started Feb 07 01:43:08 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 222376 kb
Host smart-aee6b808-462c-4e21-a2fa-8c50cdda4834
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=782270749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.782270749
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1050757224
Short name T1023
Test name
Test status
Simulation time 45635660 ps
CPU time 1.09 seconds
Started Feb 07 01:43:11 PM PST 24
Finished Feb 07 01:43:13 PM PST 24
Peak memory 206416 kb
Host smart-a4c3512b-7850-4550-bf92-0708436da60b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050757224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1050757224
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.300648802
Short name T60
Test name
Test status
Simulation time 392850914 ps
CPU time 7.15 seconds
Started Feb 07 01:43:14 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 216420 kb
Host smart-a7a96391-8c75-4ecd-b5a3-0555bc4ce8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300648802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.300648802
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.362556323
Short name T741
Test name
Test status
Simulation time 3276146650 ps
CPU time 3.34 seconds
Started Feb 07 01:43:07 PM PST 24
Finished Feb 07 01:43:14 PM PST 24
Peak memory 208096 kb
Host smart-82c8d77d-915b-4a96-b4bf-67a6ccafca97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362556323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.362556323
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1928614197
Short name T563
Test name
Test status
Simulation time 47561647 ps
CPU time 1.59 seconds
Started Feb 07 01:43:10 PM PST 24
Finished Feb 07 01:43:13 PM PST 24
Peak memory 208476 kb
Host smart-d49ebba6-8098-41a6-bc89-436dd4b0c29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928614197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1928614197
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.569933768
Short name T993
Test name
Test status
Simulation time 113397313 ps
CPU time 0.86 seconds
Started Feb 07 01:43:09 PM PST 24
Finished Feb 07 01:43:12 PM PST 24
Peak memory 205488 kb
Host smart-198f7abf-a314-4926-bf1d-2f0a11bb36b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569933768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.569933768
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2260238730
Short name T846
Test name
Test status
Simulation time 44394108912 ps
CPU time 17.98 seconds
Started Feb 07 01:43:08 PM PST 24
Finished Feb 07 01:43:29 PM PST 24
Peak memory 228924 kb
Host smart-a6092ea4-bbeb-408a-88a3-17880527c5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260238730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2260238730
Directory /workspace/9.spi_device_upload/latest
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