Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8305894	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7243885

1

T1

16984

T2

1

T3

16345

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10779851	1			T1	7455		T2	41		T3	9469
values[0x0]	2383070	1			T1	6908		T3	6666		T4	464
values[0x1]	2386858	1			T1	7192		T3	6653		T4	427

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5940177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9609602

1

T1

18121

T2

15

T3

18028

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58090	1			T1	91		T3	57		T8	1
valid_sources[0x01]	59559	1			T1	98		T3	84		T9	2
valid_sources[0x02]	60486	1			T1	82		T2	2		T3	65
valid_sources[0x03]	61737	1			T1	61		T3	134		T5	6
valid_sources[0x04]	61677	1			T1	99		T3	62		T5	12
valid_sources[0x05]	56696	1			T1	100		T3	105		T8	2
valid_sources[0x06]	59454	1			T1	108		T3	82		T5	3
valid_sources[0x07]	59902	1			T1	115		T3	78		T9	4
valid_sources[0x08]	60761	1			T1	109		T3	84		T5	2
valid_sources[0x09]	66001	1			T1	157		T3	53		T5	12
valid_sources[0x0a]	58897	1			T1	20		T3	97		T5	5
valid_sources[0x0b]	63354	1			T1	99		T3	57		T7	1
valid_sources[0x0c]	59475	1			T1	84		T3	81		T5	6
valid_sources[0x0d]	58557	1			T1	83		T3	110		T9	3
valid_sources[0x0e]	71146	1			T1	141		T3	84		T5	3
valid_sources[0x0f]	61538	1			T1	44		T3	67		T8	7
valid_sources[0x10]	59019	1			T1	73		T3	77		T8	3
valid_sources[0x11]	59511	1			T1	39		T3	73		T5	13
valid_sources[0x12]	59168	1			T1	77		T3	88		T5	1
valid_sources[0x13]	62497	1			T1	63		T3	63		T5	4
valid_sources[0x14]	61555	1			T1	83		T3	94		T5	1
valid_sources[0x15]	61800	1			T1	127		T3	68		T8	1
valid_sources[0x16]	57911	1			T1	116		T2	1		T3	81
valid_sources[0x17]	60774	1			T1	60		T3	78		T8	4
valid_sources[0x18]	61140	1			T1	92		T3	110		T5	1
valid_sources[0x19]	60191	1			T1	37		T3	95		T5	2
valid_sources[0x1a]	63323	1			T1	44		T3	92		T5	7
valid_sources[0x1b]	58459	1			T1	87		T3	86		T5	4
valid_sources[0x1c]	59095	1			T1	32		T2	1		T3	59
valid_sources[0x1d]	60528	1			T1	86		T3	92		T5	2
valid_sources[0x1e]	58760	1			T1	111		T2	1		T3	102
valid_sources[0x1f]	61891	1			T1	45		T3	72		T5	3
valid_sources[0x20]	66650	1			T1	77		T3	65		T5	1
valid_sources[0x21]	57591	1			T1	53		T3	98		T8	2
valid_sources[0x22]	62864	1			T1	97		T2	4		T3	93
valid_sources[0x23]	58887	1			T1	93		T3	109		T8	3
valid_sources[0x24]	56705	1			T1	109		T3	62		T5	2
valid_sources[0x25]	64129	1			T1	60		T2	2		T3	75
valid_sources[0x26]	59683	1			T1	45		T3	90		T5	5
valid_sources[0x27]	57515	1			T1	81		T2	1		T3	83
valid_sources[0x28]	61743	1			T1	161		T3	101		T5	13
valid_sources[0x29]	58019	1			T1	107		T3	71		T8	2
valid_sources[0x2a]	58421	1			T1	58		T3	106		T8	10
valid_sources[0x2b]	56965	1			T1	109		T3	104		T5	13
valid_sources[0x2c]	66439	1			T1	98		T3	102		T8	2
valid_sources[0x2d]	59713	1			T1	101		T3	27		T5	2
valid_sources[0x2e]	57582	1			T1	152		T3	78		T5	12
valid_sources[0x2f]	69747	1			T1	61		T3	64		T5	3
valid_sources[0x30]	58740	1			T1	90		T3	98		T5	11
valid_sources[0x31]	57236	1			T1	97		T3	55		T5	1
valid_sources[0x32]	61048	1			T1	50		T3	69		T8	4
valid_sources[0x33]	67884	1			T1	64		T3	184		T5	1
valid_sources[0x34]	64135	1			T1	101		T3	41		T5	5
valid_sources[0x35]	60614	1			T1	43		T3	66		T5	12
valid_sources[0x36]	59235	1			T1	72		T3	65		T5	10
valid_sources[0x37]	55976	1			T1	94		T3	129		T8	1
valid_sources[0x38]	59504	1			T1	42		T3	84		T5	2
valid_sources[0x39]	60681	1			T1	57		T2	1		T3	117
valid_sources[0x3a]	61355	1			T1	28		T3	107		T5	1
valid_sources[0x3b]	64155	1			T1	126		T3	132		T5	5
valid_sources[0x3c]	55450	1			T1	103		T3	103		T5	4
valid_sources[0x3d]	59340	1			T1	139		T3	65		T9	1
valid_sources[0x3e]	62659	1			T1	78		T3	88		T8	19
valid_sources[0x3f]	69058	1			T1	58		T3	114		T5	3
valid_sources[0x40]	58868	1			T1	103		T3	71		T5	4
valid_sources[0x41]	69616	1			T1	100		T3	89		T5	3
valid_sources[0x42]	60982	1			T1	25		T3	120		T5	11
valid_sources[0x43]	58187	1			T1	70		T3	120		T5	3
valid_sources[0x44]	63392	1			T1	74		T3	172		T8	8
valid_sources[0x45]	60313	1			T1	72		T3	71		T5	9
valid_sources[0x46]	58444	1			T1	53		T3	84		T5	3
valid_sources[0x47]	59926	1			T1	172		T3	94		T5	17
valid_sources[0x48]	58866	1			T1	139		T3	119		T9	4
valid_sources[0x49]	59775	1			T1	120		T2	1		T3	88
valid_sources[0x4a]	60608	1			T1	37		T3	87		T5	10
valid_sources[0x4b]	57398	1			T1	102		T3	82		T5	2
valid_sources[0x4c]	67025	1			T1	81		T3	46		T5	1
valid_sources[0x4d]	59487	1			T1	26		T3	68		T5	5
valid_sources[0x4e]	60172	1			T1	123		T3	129		T7	454
valid_sources[0x4f]	57902	1			T1	94		T3	98		T5	15
valid_sources[0x50]	57791	1			T1	138		T3	165		T5	2
valid_sources[0x51]	62416	1			T1	55		T3	67		T5	8
valid_sources[0x52]	58845	1			T1	121		T3	84		T5	11
valid_sources[0x53]	60082	1			T1	72		T3	92		T5	4
valid_sources[0x54]	60903	1			T1	16		T3	114		T5	5
valid_sources[0x55]	58203	1			T1	97		T3	109		T5	4
valid_sources[0x56]	59673	1			T1	107		T3	138		T5	11
valid_sources[0x57]	58522	1			T1	165		T2	1		T3	136
valid_sources[0x58]	61196	1			T1	57		T3	91		T5	8
valid_sources[0x59]	63349	1			T1	25		T3	100		T5	18
valid_sources[0x5a]	61254	1			T1	27		T3	63		T5	4
valid_sources[0x5b]	58050	1			T1	75		T3	61		T5	4
valid_sources[0x5c]	62567	1			T1	85		T3	97		T9	1
valid_sources[0x5d]	64741	1			T1	93		T3	131		T5	3
valid_sources[0x5e]	61097	1			T1	84		T3	88		T5	1
valid_sources[0x5f]	59215	1			T1	112		T3	103		T9	4
valid_sources[0x60]	62729	1			T1	152		T3	73		T8	10
valid_sources[0x61]	60619	1			T1	71		T3	88		T5	4
valid_sources[0x62]	66320	1			T1	28		T3	101		T5	26
valid_sources[0x63]	62285	1			T1	33		T3	77		T9	1
valid_sources[0x64]	57491	1			T1	84		T3	61		T5	1
valid_sources[0x65]	55970	1			T1	41		T3	80		T5	1
valid_sources[0x66]	55053	1			T1	54		T3	83		T5	3
valid_sources[0x67]	59168	1			T1	82		T3	51		T5	3
valid_sources[0x68]	56857	1			T1	37		T3	105		T5	1
valid_sources[0x69]	56979	1			T1	161		T3	80		T9	5
valid_sources[0x6a]	57986	1			T1	51		T3	75		T5	9
valid_sources[0x6b]	64057	1			T1	84		T3	165		T8	3
valid_sources[0x6c]	57549	1			T1	30		T3	81		T8	7
valid_sources[0x6d]	61172	1			T1	66		T3	150		T5	2
valid_sources[0x6e]	59688	1			T1	99		T3	79		T9	2
valid_sources[0x6f]	60958	1			T1	32		T3	120		T5	1
valid_sources[0x70]	59875	1			T1	163		T3	139		T5	6
valid_sources[0x71]	59913	1			T1	121		T2	1		T3	103
valid_sources[0x72]	58203	1			T1	39		T2	2		T3	98
valid_sources[0x73]	57207	1			T1	38		T3	45		T5	3
valid_sources[0x74]	58181	1			T1	36		T3	75		T9	2
valid_sources[0x75]	62167	1			T1	61		T3	79		T8	4
valid_sources[0x76]	59325	1			T1	140		T2	2		T3	38
valid_sources[0x77]	57846	1			T1	108		T2	3		T3	74
valid_sources[0x78]	59656	1			T1	100		T3	91		T5	1
valid_sources[0x79]	62468	1			T1	73		T3	103		T5	3
valid_sources[0x7a]	59380	1			T1	145		T2	2		T3	101
valid_sources[0x7b]	63277	1			T1	106		T3	82		T5	8
valid_sources[0x7c]	61469	1			T1	105		T3	118		T5	4
valid_sources[0x7d]	59300	1			T1	67		T3	93		T4	912
valid_sources[0x7e]	68907	1			T1	94		T3	107		T5	11
valid_sources[0x7f]	58201	1			T1	70		T3	104		T5	11
valid_sources[0x80]	58156	1			T1	187		T3	78		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2880952

1

T1

3248

T2

1

T3

3504

values[0x0]

all_enables

biggest_size

2191239

1

T1

6761

T3

6436

T4

464

values[0x1]

all_enables

biggest_size

2171694

1

T1

6975

T3

6405

T4

425