Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

8334618

1

T1

4571

T2

40

T3

6443

full_word

7243450

1

T1

16984

T2

1

T3

16345

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	15577698	1			T1	21555		T2	41		T3	22788
auto[TlIntgErrCmd]	122	1			T73	13		T77	12		T78	10
auto[TlIntgErrData]	133	1			T73	6		T77	9		T78	13
auto[TlIntgErrBoth]	115	1			T73	11		T77	9		T78	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10782889

1

T1

7455

T2

41

T3

9469

auto[1]

4795179

1

T1

14100

T3

13319

T4

891

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7901577	1			T1	4207		T2	40		T3	5965
auto[TlIntgErrNone]	partial	auto[1]	432707	1			T1	364		T3	478		T4	2
auto[TlIntgErrNone]	full_word	auto[0]	2881145	1			T1	3248		T2	1		T3	3504
auto[TlIntgErrNone]	full_word	auto[1]	4362269	1			T1	13736		T3	12841		T4	889
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T73	7		T77	5		T78	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T73	5		T77	5		T78	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T77	1		T78	1		T211	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T73	1		T77	1		T78	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T73	5		T77	3		T78	9
auto[TlIntgErrData]	partial	auto[1]	59	1			T73	1		T77	6		T78	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T212	1		T210	2		T213	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T90	1		T211	1		T214	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T73	4		T77	2		T78	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T73	7		T77	5		T78	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T90	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T77	2		T78	1		T215	1