Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	606133507	67158	0	0
DepthKnown_A	606133507	606008658	0	0
RvalidKnown_A	606133507	606008658	0	0
WreadyKnown_A	606133507	606008658	0	0
gen_passthru_fifo.paramCheckPass	1099	1099	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	67158	0	0
T1	280166	598	0	0
T2	1464	0	0	0
T3	402035	384	0	0
T4	28034	0	0	0
T5	39133	0	0	0
T6	1134	0	0	0
T7	30225	0	0	0
T8	348271	0	0	0
T9	21874	0	0	0
T10	332922	0	0	0
T11	0	265	0	0
T22	0	284	0	0
T23	0	64	0	0
T24	0	128	0	0
T25	0	96	0	0
T26	0	289	0	0
T27	0	546	0	0
T28	0	399	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1099	1099	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	606133507	157793	0	0
DepthKnown_A	606133507	606008658	0	0
RvalidKnown_A	606133507	606008658	0	0
WreadyKnown_A	606133507	606008658	0	0
gen_passthru_fifo.paramCheckPass	1099	1099	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	157793	0	0
T1	280166	598	0	0
T2	1464	0	0	0
T3	402035	1920	0	0
T4	28034	0	0	0
T5	39133	0	0	0
T6	1134	0	0	0
T7	30225	0	0	0
T8	348271	0	0	0
T9	21874	0	0	0
T10	332922	0	0	0
T11	0	1224	0	0
T22	0	1290	0	0
T23	0	64	0	0
T24	0	558	0	0
T25	0	96	0	0
T26	0	1301	0	0
T27	0	2558	0	0
T28	0	399	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1099	1099	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	606133507	13955460	0	0
DepthKnown_A	606133507	606008658	0	0
RvalidKnown_A	606133507	606008658	0	0
WreadyKnown_A	606133507	606008658	0	0
gen_passthru_fifo.paramCheckPass	1099	1099	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	13955460	0	0
T1	280166	9505	0	0
T2	1464	41	0	0
T3	402035	15946	0	0
T4	28034	80	0	0
T5	39133	143	0	0
T6	1134	5	0	0
T7	30225	110	0	0
T8	348271	68	0	0
T9	21874	87	0	0
T10	332922	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1099	1099	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	606133507	29206422	0	0
DepthKnown_A	606133507	606008658	0	0
RvalidKnown_A	606133507	606008658	0	0
WreadyKnown_A	606133507	606008658	0	0
gen_passthru_fifo.paramCheckPass	1099	1099	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	29206422	0	0
T1	280166	9309	0	0
T2	1464	41	0	0
T3	402035	57646	0	0
T4	28034	80	0	0
T5	39133	569	0	0
T6	1134	16	0	0
T7	30225	110	0	0
T8	348271	68	0	0
T9	21874	87	0	0
T10	332922	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606133507	606008658	0	0
T1	280166	280111	0	0
T2	1464	1368	0	0
T3	402035	401982	0	0
T4	28034	27983	0	0
T5	39133	39039	0	0
T6	1134	1060	0	0
T7	30225	30150	0	0
T8	348271	348204	0	0
T9	21874	21806	0	0
T10	332922	332823	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1099	1099	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0