Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5313 |
0 |
0 |
T73 |
29504 |
1 |
0 |
0 |
T74 |
11619 |
224 |
0 |
0 |
T75 |
10055 |
96 |
0 |
0 |
T76 |
11399 |
272 |
0 |
0 |
T77 |
87190 |
4 |
0 |
0 |
T78 |
100625 |
2 |
0 |
0 |
T80 |
9974 |
121 |
0 |
0 |
T81 |
13497 |
357 |
0 |
0 |
T82 |
2537 |
64 |
0 |
0 |
T85 |
2636 |
115 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2903 |
0 |
0 |
T78 |
100625 |
93 |
0 |
0 |
T94 |
83321 |
525 |
0 |
0 |
T96 |
10171 |
11 |
0 |
0 |
T99 |
242002 |
444 |
0 |
0 |
T121 |
7638 |
5 |
0 |
0 |
T122 |
86846 |
546 |
0 |
0 |
T123 |
19633 |
60 |
0 |
0 |
T124 |
6838 |
10 |
0 |
0 |
T125 |
8118 |
14 |
0 |
0 |
T126 |
35052 |
49 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2989 |
0 |
0 |
T78 |
100625 |
117 |
0 |
0 |
T94 |
83321 |
549 |
0 |
0 |
T96 |
10171 |
18 |
0 |
0 |
T99 |
242002 |
500 |
0 |
0 |
T121 |
7638 |
6 |
0 |
0 |
T122 |
86846 |
505 |
0 |
0 |
T123 |
19633 |
111 |
0 |
0 |
T124 |
6838 |
6 |
0 |
0 |
T125 |
8118 |
11 |
0 |
0 |
T126 |
35052 |
46 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
3531 |
0 |
0 |
T78 |
100625 |
222 |
0 |
0 |
T94 |
83321 |
538 |
0 |
0 |
T96 |
10171 |
27 |
0 |
0 |
T99 |
242002 |
361 |
0 |
0 |
T121 |
7638 |
15 |
0 |
0 |
T122 |
86846 |
559 |
0 |
0 |
T123 |
19633 |
70 |
0 |
0 |
T124 |
6838 |
4 |
0 |
0 |
T125 |
8118 |
56 |
0 |
0 |
T126 |
35052 |
100 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
9229 |
0 |
0 |
T78 |
100625 |
1987 |
0 |
0 |
T94 |
83321 |
530 |
0 |
0 |
T96 |
10171 |
122 |
0 |
0 |
T99 |
242002 |
441 |
0 |
0 |
T121 |
7638 |
154 |
0 |
0 |
T122 |
86846 |
540 |
0 |
0 |
T123 |
19633 |
47 |
0 |
0 |
T124 |
6838 |
28 |
0 |
0 |
T125 |
8118 |
12 |
0 |
0 |
T126 |
35052 |
744 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
8840 |
0 |
0 |
T78 |
100625 |
1509 |
0 |
0 |
T94 |
83321 |
517 |
0 |
0 |
T96 |
10171 |
144 |
0 |
0 |
T99 |
242002 |
360 |
0 |
0 |
T121 |
7638 |
112 |
0 |
0 |
T122 |
86846 |
500 |
0 |
0 |
T123 |
19633 |
49 |
0 |
0 |
T124 |
6838 |
7 |
0 |
0 |
T125 |
8118 |
29 |
0 |
0 |
T126 |
35052 |
661 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
8754 |
0 |
0 |
T78 |
100625 |
1927 |
0 |
0 |
T94 |
83321 |
553 |
0 |
0 |
T96 |
10171 |
19 |
0 |
0 |
T99 |
242002 |
345 |
0 |
0 |
T121 |
7638 |
13 |
0 |
0 |
T122 |
86846 |
500 |
0 |
0 |
T123 |
19633 |
64 |
0 |
0 |
T124 |
6838 |
71 |
0 |
0 |
T125 |
8118 |
12 |
0 |
0 |
T126 |
35052 |
788 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
8176 |
0 |
0 |
T78 |
100625 |
1757 |
0 |
0 |
T94 |
83321 |
498 |
0 |
0 |
T96 |
10171 |
129 |
0 |
0 |
T99 |
242002 |
377 |
0 |
0 |
T121 |
7638 |
12 |
0 |
0 |
T122 |
86846 |
562 |
0 |
0 |
T123 |
19633 |
11 |
0 |
0 |
T124 |
6838 |
4 |
0 |
0 |
T125 |
8118 |
10 |
0 |
0 |
T126 |
35052 |
755 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
8774 |
0 |
0 |
T78 |
100625 |
1416 |
0 |
0 |
T94 |
83321 |
525 |
0 |
0 |
T96 |
10171 |
217 |
0 |
0 |
T99 |
242002 |
404 |
0 |
0 |
T121 |
7638 |
8 |
0 |
0 |
T122 |
86846 |
467 |
0 |
0 |
T123 |
19633 |
50 |
0 |
0 |
T124 |
6838 |
35 |
0 |
0 |
T125 |
8118 |
36 |
0 |
0 |
T126 |
35052 |
920 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
8356 |
0 |
0 |
T78 |
100625 |
1082 |
0 |
0 |
T94 |
83321 |
575 |
0 |
0 |
T96 |
10171 |
14 |
0 |
0 |
T99 |
242002 |
421 |
0 |
0 |
T121 |
7638 |
235 |
0 |
0 |
T122 |
86846 |
540 |
0 |
0 |
T123 |
19633 |
66 |
0 |
0 |
T124 |
6838 |
65 |
0 |
0 |
T125 |
8118 |
14 |
0 |
0 |
T126 |
35052 |
411 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
8465 |
0 |
0 |
T78 |
100625 |
1485 |
0 |
0 |
T94 |
83321 |
556 |
0 |
0 |
T96 |
10171 |
167 |
0 |
0 |
T99 |
242002 |
347 |
0 |
0 |
T121 |
7638 |
149 |
0 |
0 |
T122 |
86846 |
579 |
0 |
0 |
T123 |
19633 |
74 |
0 |
0 |
T124 |
6838 |
2 |
0 |
0 |
T125 |
8118 |
18 |
0 |
0 |
T126 |
35052 |
595 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
8948 |
0 |
0 |
T78 |
100625 |
2113 |
0 |
0 |
T94 |
83321 |
551 |
0 |
0 |
T96 |
10171 |
156 |
0 |
0 |
T99 |
242002 |
419 |
0 |
0 |
T121 |
7638 |
102 |
0 |
0 |
T122 |
86846 |
546 |
0 |
0 |
T123 |
19633 |
62 |
0 |
0 |
T124 |
6838 |
19 |
0 |
0 |
T125 |
8118 |
6 |
0 |
0 |
T126 |
35052 |
633 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5129 |
0 |
0 |
T78 |
100625 |
836 |
0 |
0 |
T94 |
83321 |
494 |
0 |
0 |
T96 |
10171 |
106 |
0 |
0 |
T99 |
242002 |
445 |
0 |
0 |
T121 |
7638 |
14 |
0 |
0 |
T122 |
86846 |
477 |
0 |
0 |
T123 |
19633 |
79 |
0 |
0 |
T124 |
6838 |
6 |
0 |
0 |
T125 |
8118 |
19 |
0 |
0 |
T126 |
35052 |
257 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
4834 |
0 |
0 |
T78 |
100625 |
865 |
0 |
0 |
T94 |
83321 |
499 |
0 |
0 |
T96 |
10171 |
48 |
0 |
0 |
T99 |
242002 |
424 |
0 |
0 |
T121 |
7638 |
67 |
0 |
0 |
T122 |
86846 |
586 |
0 |
0 |
T123 |
19633 |
51 |
0 |
0 |
T124 |
6838 |
9 |
0 |
0 |
T125 |
8118 |
40 |
0 |
0 |
T126 |
35052 |
205 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5182 |
0 |
0 |
T78 |
100625 |
702 |
0 |
0 |
T94 |
83321 |
539 |
0 |
0 |
T96 |
10171 |
109 |
0 |
0 |
T99 |
242002 |
337 |
0 |
0 |
T121 |
7638 |
57 |
0 |
0 |
T122 |
86846 |
551 |
0 |
0 |
T123 |
19633 |
77 |
0 |
0 |
T124 |
6838 |
14 |
0 |
0 |
T125 |
8118 |
18 |
0 |
0 |
T126 |
35052 |
309 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5395 |
0 |
0 |
T78 |
100625 |
665 |
0 |
0 |
T94 |
83321 |
440 |
0 |
0 |
T96 |
10171 |
134 |
0 |
0 |
T99 |
242002 |
387 |
0 |
0 |
T121 |
7638 |
13 |
0 |
0 |
T122 |
86846 |
548 |
0 |
0 |
T123 |
19633 |
62 |
0 |
0 |
T124 |
6838 |
24 |
0 |
0 |
T125 |
8118 |
45 |
0 |
0 |
T126 |
35052 |
243 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5477 |
0 |
0 |
T78 |
100625 |
954 |
0 |
0 |
T94 |
83321 |
571 |
0 |
0 |
T96 |
10171 |
110 |
0 |
0 |
T99 |
242002 |
391 |
0 |
0 |
T121 |
7638 |
13 |
0 |
0 |
T122 |
86846 |
499 |
0 |
0 |
T123 |
19633 |
102 |
0 |
0 |
T124 |
6838 |
5 |
0 |
0 |
T125 |
8118 |
65 |
0 |
0 |
T126 |
35052 |
232 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5004 |
0 |
0 |
T78 |
100625 |
585 |
0 |
0 |
T94 |
83321 |
578 |
0 |
0 |
T96 |
10171 |
65 |
0 |
0 |
T99 |
242002 |
408 |
0 |
0 |
T121 |
7638 |
55 |
0 |
0 |
T122 |
86846 |
556 |
0 |
0 |
T123 |
19633 |
43 |
0 |
0 |
T124 |
6838 |
35 |
0 |
0 |
T125 |
8118 |
15 |
0 |
0 |
T126 |
35052 |
331 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5358 |
0 |
0 |
T78 |
100625 |
790 |
0 |
0 |
T94 |
83321 |
467 |
0 |
0 |
T96 |
10171 |
68 |
0 |
0 |
T99 |
242002 |
441 |
0 |
0 |
T121 |
7638 |
47 |
0 |
0 |
T122 |
86846 |
535 |
0 |
0 |
T123 |
19633 |
59 |
0 |
0 |
T124 |
6838 |
64 |
0 |
0 |
T125 |
8118 |
19 |
0 |
0 |
T126 |
35052 |
314 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5288 |
0 |
0 |
T78 |
100625 |
825 |
0 |
0 |
T94 |
83321 |
507 |
0 |
0 |
T96 |
10171 |
67 |
0 |
0 |
T99 |
242002 |
370 |
0 |
0 |
T121 |
7638 |
59 |
0 |
0 |
T122 |
86846 |
547 |
0 |
0 |
T123 |
19633 |
75 |
0 |
0 |
T124 |
6838 |
16 |
0 |
0 |
T125 |
8118 |
31 |
0 |
0 |
T126 |
35052 |
362 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5152 |
0 |
0 |
T78 |
100625 |
784 |
0 |
0 |
T94 |
83321 |
526 |
0 |
0 |
T96 |
10171 |
108 |
0 |
0 |
T99 |
242002 |
346 |
0 |
0 |
T121 |
7638 |
96 |
0 |
0 |
T122 |
86846 |
497 |
0 |
0 |
T123 |
19633 |
74 |
0 |
0 |
T124 |
6838 |
16 |
0 |
0 |
T125 |
8118 |
5 |
0 |
0 |
T126 |
35052 |
334 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5177 |
0 |
0 |
T78 |
100625 |
976 |
0 |
0 |
T94 |
83321 |
546 |
0 |
0 |
T96 |
10171 |
57 |
0 |
0 |
T99 |
242002 |
413 |
0 |
0 |
T121 |
7638 |
140 |
0 |
0 |
T122 |
86846 |
538 |
0 |
0 |
T123 |
19633 |
21 |
0 |
0 |
T124 |
6838 |
15 |
0 |
0 |
T125 |
8118 |
16 |
0 |
0 |
T126 |
35052 |
203 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5292 |
0 |
0 |
T78 |
100625 |
727 |
0 |
0 |
T94 |
83321 |
494 |
0 |
0 |
T96 |
10171 |
43 |
0 |
0 |
T99 |
242002 |
433 |
0 |
0 |
T121 |
7638 |
7 |
0 |
0 |
T122 |
86846 |
512 |
0 |
0 |
T123 |
19633 |
76 |
0 |
0 |
T124 |
6838 |
16 |
0 |
0 |
T126 |
35052 |
316 |
0 |
0 |
T127 |
4565 |
3 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5388 |
0 |
0 |
T78 |
100625 |
843 |
0 |
0 |
T94 |
83321 |
546 |
0 |
0 |
T96 |
10171 |
92 |
0 |
0 |
T99 |
242002 |
414 |
0 |
0 |
T121 |
7638 |
48 |
0 |
0 |
T122 |
86846 |
528 |
0 |
0 |
T123 |
19633 |
31 |
0 |
0 |
T124 |
6838 |
20 |
0 |
0 |
T125 |
8118 |
10 |
0 |
0 |
T126 |
35052 |
290 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5100 |
0 |
0 |
T78 |
100625 |
881 |
0 |
0 |
T94 |
83321 |
506 |
0 |
0 |
T96 |
10171 |
85 |
0 |
0 |
T99 |
242002 |
365 |
0 |
0 |
T121 |
7638 |
51 |
0 |
0 |
T122 |
86846 |
524 |
0 |
0 |
T123 |
19633 |
62 |
0 |
0 |
T124 |
6838 |
54 |
0 |
0 |
T125 |
8118 |
24 |
0 |
0 |
T126 |
35052 |
146 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
4921 |
0 |
0 |
T78 |
100625 |
656 |
0 |
0 |
T94 |
83321 |
487 |
0 |
0 |
T96 |
10171 |
100 |
0 |
0 |
T99 |
242002 |
458 |
0 |
0 |
T121 |
7638 |
44 |
0 |
0 |
T122 |
86846 |
561 |
0 |
0 |
T123 |
19633 |
41 |
0 |
0 |
T124 |
6838 |
24 |
0 |
0 |
T125 |
8118 |
28 |
0 |
0 |
T126 |
35052 |
138 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5570 |
0 |
0 |
T78 |
100625 |
931 |
0 |
0 |
T94 |
83321 |
489 |
0 |
0 |
T96 |
10171 |
58 |
0 |
0 |
T99 |
242002 |
484 |
0 |
0 |
T121 |
7638 |
42 |
0 |
0 |
T122 |
86846 |
532 |
0 |
0 |
T123 |
19633 |
77 |
0 |
0 |
T124 |
6838 |
33 |
0 |
0 |
T125 |
8118 |
13 |
0 |
0 |
T126 |
35052 |
302 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5021 |
0 |
0 |
T78 |
100625 |
735 |
0 |
0 |
T94 |
83321 |
528 |
0 |
0 |
T96 |
10171 |
64 |
0 |
0 |
T99 |
242002 |
377 |
0 |
0 |
T121 |
7638 |
14 |
0 |
0 |
T122 |
86846 |
579 |
0 |
0 |
T123 |
19633 |
81 |
0 |
0 |
T124 |
6838 |
27 |
0 |
0 |
T125 |
8118 |
41 |
0 |
0 |
T126 |
35052 |
336 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5221 |
0 |
0 |
T78 |
100625 |
528 |
0 |
0 |
T94 |
83321 |
500 |
0 |
0 |
T96 |
10171 |
88 |
0 |
0 |
T99 |
242002 |
382 |
0 |
0 |
T121 |
7638 |
46 |
0 |
0 |
T122 |
86846 |
532 |
0 |
0 |
T123 |
19633 |
89 |
0 |
0 |
T124 |
6838 |
24 |
0 |
0 |
T125 |
8118 |
6 |
0 |
0 |
T126 |
35052 |
344 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
4880 |
0 |
0 |
T78 |
100625 |
588 |
0 |
0 |
T94 |
83321 |
522 |
0 |
0 |
T96 |
10171 |
93 |
0 |
0 |
T99 |
242002 |
404 |
0 |
0 |
T121 |
7638 |
96 |
0 |
0 |
T122 |
86846 |
560 |
0 |
0 |
T123 |
19633 |
66 |
0 |
0 |
T125 |
8118 |
25 |
0 |
0 |
T126 |
35052 |
317 |
0 |
0 |
T128 |
7058 |
23 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5287 |
0 |
0 |
T78 |
100625 |
720 |
0 |
0 |
T94 |
83321 |
517 |
0 |
0 |
T96 |
10171 |
103 |
0 |
0 |
T99 |
242002 |
360 |
0 |
0 |
T121 |
7638 |
54 |
0 |
0 |
T122 |
86846 |
557 |
0 |
0 |
T123 |
19633 |
83 |
0 |
0 |
T124 |
6838 |
68 |
0 |
0 |
T125 |
8118 |
13 |
0 |
0 |
T126 |
35052 |
165 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
4952 |
0 |
0 |
T78 |
100625 |
692 |
0 |
0 |
T94 |
83321 |
488 |
0 |
0 |
T96 |
10171 |
87 |
0 |
0 |
T99 |
242002 |
361 |
0 |
0 |
T121 |
7638 |
84 |
0 |
0 |
T122 |
86846 |
479 |
0 |
0 |
T123 |
19633 |
44 |
0 |
0 |
T124 |
6838 |
22 |
0 |
0 |
T125 |
8118 |
30 |
0 |
0 |
T126 |
35052 |
360 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5208 |
0 |
0 |
T78 |
100625 |
630 |
0 |
0 |
T94 |
83321 |
452 |
0 |
0 |
T96 |
10171 |
49 |
0 |
0 |
T99 |
242002 |
393 |
0 |
0 |
T121 |
7638 |
47 |
0 |
0 |
T122 |
86846 |
521 |
0 |
0 |
T123 |
19633 |
84 |
0 |
0 |
T124 |
6838 |
28 |
0 |
0 |
T125 |
8118 |
16 |
0 |
0 |
T126 |
35052 |
434 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5216 |
0 |
0 |
T78 |
100625 |
631 |
0 |
0 |
T91 |
15482 |
4 |
0 |
0 |
T94 |
83321 |
531 |
0 |
0 |
T96 |
10171 |
126 |
0 |
0 |
T99 |
242002 |
368 |
0 |
0 |
T121 |
7638 |
61 |
0 |
0 |
T122 |
86846 |
540 |
0 |
0 |
T123 |
19633 |
55 |
0 |
0 |
T124 |
6838 |
8 |
0 |
0 |
T125 |
8118 |
5 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
4859 |
0 |
0 |
T78 |
100625 |
849 |
0 |
0 |
T94 |
83321 |
415 |
0 |
0 |
T96 |
10171 |
55 |
0 |
0 |
T99 |
242002 |
388 |
0 |
0 |
T121 |
7638 |
39 |
0 |
0 |
T122 |
86846 |
588 |
0 |
0 |
T123 |
19633 |
66 |
0 |
0 |
T124 |
6838 |
3 |
0 |
0 |
T126 |
35052 |
182 |
0 |
0 |
T128 |
7058 |
5 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
5106 |
0 |
0 |
T78 |
100625 |
840 |
0 |
0 |
T94 |
83321 |
481 |
0 |
0 |
T96 |
10171 |
110 |
0 |
0 |
T99 |
242002 |
358 |
0 |
0 |
T121 |
7638 |
92 |
0 |
0 |
T122 |
86846 |
546 |
0 |
0 |
T123 |
19633 |
72 |
0 |
0 |
T124 |
6838 |
7 |
0 |
0 |
T125 |
8118 |
25 |
0 |
0 |
T126 |
35052 |
248 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2995 |
0 |
0 |
T78 |
100625 |
187 |
0 |
0 |
T94 |
83321 |
511 |
0 |
0 |
T96 |
10171 |
6 |
0 |
0 |
T99 |
242002 |
348 |
0 |
0 |
T121 |
7638 |
14 |
0 |
0 |
T122 |
86846 |
515 |
0 |
0 |
T123 |
19633 |
67 |
0 |
0 |
T124 |
6838 |
43 |
0 |
0 |
T125 |
8118 |
39 |
0 |
0 |
T126 |
35052 |
57 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
3173 |
0 |
0 |
T78 |
100625 |
163 |
0 |
0 |
T94 |
83321 |
559 |
0 |
0 |
T96 |
10171 |
30 |
0 |
0 |
T99 |
242002 |
406 |
0 |
0 |
T121 |
7638 |
16 |
0 |
0 |
T122 |
86846 |
511 |
0 |
0 |
T123 |
19633 |
61 |
0 |
0 |
T125 |
8118 |
16 |
0 |
0 |
T126 |
35052 |
55 |
0 |
0 |
T128 |
7058 |
20 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
3059 |
0 |
0 |
T78 |
100625 |
201 |
0 |
0 |
T94 |
83321 |
464 |
0 |
0 |
T96 |
10171 |
18 |
0 |
0 |
T99 |
242002 |
434 |
0 |
0 |
T121 |
7638 |
14 |
0 |
0 |
T122 |
86846 |
533 |
0 |
0 |
T123 |
19633 |
84 |
0 |
0 |
T125 |
8118 |
24 |
0 |
0 |
T126 |
35052 |
63 |
0 |
0 |
T128 |
7058 |
5 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
3064 |
0 |
0 |
T78 |
100625 |
130 |
0 |
0 |
T94 |
83321 |
482 |
0 |
0 |
T96 |
10171 |
17 |
0 |
0 |
T99 |
242002 |
351 |
0 |
0 |
T121 |
7638 |
4 |
0 |
0 |
T122 |
86846 |
548 |
0 |
0 |
T123 |
19633 |
79 |
0 |
0 |
T124 |
6838 |
26 |
0 |
0 |
T125 |
8118 |
6 |
0 |
0 |
T126 |
35052 |
68 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
3532 |
0 |
0 |
T78 |
100625 |
207 |
0 |
0 |
T94 |
83321 |
558 |
0 |
0 |
T96 |
10171 |
50 |
0 |
0 |
T99 |
242002 |
415 |
0 |
0 |
T121 |
7638 |
23 |
0 |
0 |
T122 |
86846 |
592 |
0 |
0 |
T123 |
19633 |
122 |
0 |
0 |
T124 |
6838 |
18 |
0 |
0 |
T125 |
8118 |
18 |
0 |
0 |
T126 |
35052 |
51 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
4603 |
0 |
0 |
T11 |
133645 |
114 |
0 |
0 |
T15 |
34180 |
0 |
0 |
0 |
T16 |
302937 |
0 |
0 |
0 |
T22 |
802609 |
0 |
0 |
0 |
T23 |
112765 |
0 |
0 |
0 |
T24 |
117824 |
0 |
0 |
0 |
T27 |
0 |
16 |
0 |
0 |
T36 |
39901 |
0 |
0 |
0 |
T37 |
77707 |
0 |
0 |
0 |
T43 |
836 |
0 |
0 |
0 |
T44 |
856 |
0 |
0 |
0 |
T129 |
0 |
26 |
0 |
0 |
T130 |
0 |
41 |
0 |
0 |
T131 |
0 |
72 |
0 |
0 |
T132 |
0 |
34 |
0 |
0 |
T133 |
0 |
10 |
0 |
0 |
T134 |
0 |
24 |
0 |
0 |
T135 |
0 |
7 |
0 |
0 |
T136 |
0 |
10 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
3102 |
0 |
0 |
T78 |
100625 |
182 |
0 |
0 |
T94 |
83321 |
526 |
0 |
0 |
T96 |
10171 |
10 |
0 |
0 |
T99 |
242002 |
363 |
0 |
0 |
T121 |
7638 |
8 |
0 |
0 |
T122 |
86846 |
559 |
0 |
0 |
T123 |
19633 |
80 |
0 |
0 |
T124 |
6838 |
28 |
0 |
0 |
T125 |
8118 |
17 |
0 |
0 |
T126 |
35052 |
45 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2959 |
0 |
0 |
T78 |
100625 |
189 |
0 |
0 |
T94 |
83321 |
518 |
0 |
0 |
T96 |
10171 |
19 |
0 |
0 |
T99 |
242002 |
405 |
0 |
0 |
T121 |
7638 |
21 |
0 |
0 |
T122 |
86846 |
441 |
0 |
0 |
T123 |
19633 |
28 |
0 |
0 |
T124 |
6838 |
48 |
0 |
0 |
T125 |
8118 |
18 |
0 |
0 |
T126 |
35052 |
55 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2885 |
0 |
0 |
T78 |
100625 |
112 |
0 |
0 |
T94 |
83321 |
463 |
0 |
0 |
T96 |
10171 |
15 |
0 |
0 |
T99 |
242002 |
438 |
0 |
0 |
T121 |
7638 |
8 |
0 |
0 |
T122 |
86846 |
551 |
0 |
0 |
T123 |
19633 |
53 |
0 |
0 |
T124 |
6838 |
4 |
0 |
0 |
T125 |
8118 |
25 |
0 |
0 |
T126 |
35052 |
36 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2887 |
0 |
0 |
T78 |
100625 |
107 |
0 |
0 |
T94 |
83321 |
513 |
0 |
0 |
T96 |
10171 |
12 |
0 |
0 |
T99 |
242002 |
377 |
0 |
0 |
T121 |
7638 |
14 |
0 |
0 |
T122 |
86846 |
520 |
0 |
0 |
T123 |
19633 |
55 |
0 |
0 |
T124 |
6838 |
32 |
0 |
0 |
T125 |
8118 |
41 |
0 |
0 |
T126 |
35052 |
28 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2911 |
0 |
0 |
T78 |
100625 |
114 |
0 |
0 |
T94 |
83321 |
519 |
0 |
0 |
T96 |
10171 |
9 |
0 |
0 |
T99 |
242002 |
344 |
0 |
0 |
T121 |
7638 |
12 |
0 |
0 |
T122 |
86846 |
508 |
0 |
0 |
T123 |
19633 |
126 |
0 |
0 |
T124 |
6838 |
6 |
0 |
0 |
T125 |
8118 |
48 |
0 |
0 |
T126 |
35052 |
49 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2964 |
0 |
0 |
T78 |
100625 |
88 |
0 |
0 |
T94 |
83321 |
532 |
0 |
0 |
T96 |
10171 |
8 |
0 |
0 |
T99 |
242002 |
432 |
0 |
0 |
T121 |
7638 |
8 |
0 |
0 |
T122 |
86846 |
504 |
0 |
0 |
T123 |
19633 |
92 |
0 |
0 |
T124 |
6838 |
24 |
0 |
0 |
T125 |
8118 |
32 |
0 |
0 |
T126 |
35052 |
47 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
3510 |
0 |
0 |
T78 |
100625 |
233 |
0 |
0 |
T91 |
15482 |
5 |
0 |
0 |
T94 |
83321 |
476 |
0 |
0 |
T96 |
10171 |
35 |
0 |
0 |
T99 |
242002 |
433 |
0 |
0 |
T121 |
7638 |
20 |
0 |
0 |
T122 |
86846 |
559 |
0 |
0 |
T123 |
19633 |
86 |
0 |
0 |
T124 |
6838 |
32 |
0 |
0 |
T125 |
8118 |
8 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2948 |
0 |
0 |
T78 |
100625 |
100 |
0 |
0 |
T94 |
83321 |
513 |
0 |
0 |
T96 |
10171 |
19 |
0 |
0 |
T99 |
242002 |
373 |
0 |
0 |
T121 |
7638 |
15 |
0 |
0 |
T122 |
86846 |
523 |
0 |
0 |
T123 |
19633 |
52 |
0 |
0 |
T124 |
6838 |
36 |
0 |
0 |
T125 |
8118 |
15 |
0 |
0 |
T126 |
35052 |
55 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
3538 |
0 |
0 |
T78 |
100625 |
341 |
0 |
0 |
T94 |
83321 |
427 |
0 |
0 |
T96 |
10171 |
21 |
0 |
0 |
T99 |
242002 |
357 |
0 |
0 |
T121 |
7638 |
13 |
0 |
0 |
T122 |
86846 |
548 |
0 |
0 |
T123 |
19633 |
24 |
0 |
0 |
T124 |
6838 |
4 |
0 |
0 |
T125 |
8118 |
31 |
0 |
0 |
T126 |
35052 |
153 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
3180 |
0 |
0 |
T78 |
100625 |
176 |
0 |
0 |
T94 |
83321 |
525 |
0 |
0 |
T96 |
10171 |
23 |
0 |
0 |
T99 |
242002 |
455 |
0 |
0 |
T121 |
7638 |
13 |
0 |
0 |
T122 |
86846 |
546 |
0 |
0 |
T123 |
19633 |
66 |
0 |
0 |
T124 |
6838 |
9 |
0 |
0 |
T125 |
8118 |
1 |
0 |
0 |
T126 |
35052 |
47 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2932 |
0 |
0 |
T78 |
100625 |
105 |
0 |
0 |
T94 |
83321 |
505 |
0 |
0 |
T96 |
10171 |
12 |
0 |
0 |
T99 |
242002 |
487 |
0 |
0 |
T121 |
7638 |
13 |
0 |
0 |
T122 |
86846 |
540 |
0 |
0 |
T123 |
19633 |
46 |
0 |
0 |
T124 |
6838 |
18 |
0 |
0 |
T125 |
8118 |
17 |
0 |
0 |
T126 |
35052 |
41 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2815 |
0 |
0 |
T78 |
100625 |
77 |
0 |
0 |
T94 |
83321 |
493 |
0 |
0 |
T96 |
10171 |
13 |
0 |
0 |
T99 |
242002 |
414 |
0 |
0 |
T121 |
7638 |
3 |
0 |
0 |
T122 |
86846 |
556 |
0 |
0 |
T123 |
19633 |
31 |
0 |
0 |
T124 |
6838 |
10 |
0 |
0 |
T125 |
8118 |
44 |
0 |
0 |
T126 |
35052 |
39 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
3070 |
0 |
0 |
T78 |
100625 |
111 |
0 |
0 |
T94 |
83321 |
522 |
0 |
0 |
T96 |
10171 |
12 |
0 |
0 |
T99 |
242002 |
421 |
0 |
0 |
T121 |
7638 |
8 |
0 |
0 |
T122 |
86846 |
489 |
0 |
0 |
T123 |
19633 |
62 |
0 |
0 |
T124 |
6838 |
19 |
0 |
0 |
T125 |
8118 |
25 |
0 |
0 |
T126 |
35052 |
47 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2936 |
0 |
0 |
T78 |
100625 |
102 |
0 |
0 |
T94 |
83321 |
512 |
0 |
0 |
T96 |
10171 |
5 |
0 |
0 |
T99 |
242002 |
415 |
0 |
0 |
T121 |
7638 |
8 |
0 |
0 |
T122 |
86846 |
492 |
0 |
0 |
T123 |
19633 |
62 |
0 |
0 |
T124 |
6838 |
47 |
0 |
0 |
T125 |
8118 |
7 |
0 |
0 |
T126 |
35052 |
52 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2990 |
0 |
0 |
T78 |
100625 |
115 |
0 |
0 |
T94 |
83321 |
524 |
0 |
0 |
T96 |
10171 |
10 |
0 |
0 |
T99 |
242002 |
393 |
0 |
0 |
T121 |
7638 |
9 |
0 |
0 |
T122 |
86846 |
524 |
0 |
0 |
T123 |
19633 |
70 |
0 |
0 |
T124 |
6838 |
49 |
0 |
0 |
T125 |
8118 |
29 |
0 |
0 |
T126 |
35052 |
33 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
606133507 |
2884 |
0 |
0 |
T78 |
100625 |
88 |
0 |
0 |
T94 |
83321 |
568 |
0 |
0 |
T96 |
10171 |
16 |
0 |
0 |
T99 |
242002 |
379 |
0 |
0 |
T121 |
7638 |
1 |
0 |
0 |
T122 |
86846 |
526 |
0 |
0 |
T123 |
19633 |
74 |
0 |
0 |
T124 |
6838 |
13 |
0 |
0 |
T125 |
8118 |
27 |
0 |
0 |
T126 |
35052 |
32 |
0 |
0 |