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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 98.50 94.91 98.60 89.36 97.30 96.40 98.14


Total test records in report: 1099
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T1015 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.444709556 Feb 18 12:29:01 PM PST 24 Feb 18 12:29:07 PM PST 24 219215835 ps
T1016 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.110506299 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:39 PM PST 24 137778799 ps
T102 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4274937154 Feb 18 12:29:12 PM PST 24 Feb 18 12:29:16 PM PST 24 62159170 ps
T126 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3292890144 Feb 18 12:28:42 PM PST 24 Feb 18 12:28:52 PM PST 24 368982327 ps
T128 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.435703081 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:46 PM PST 24 121702861 ps
T1017 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.314273776 Feb 18 12:28:34 PM PST 24 Feb 18 12:28:37 PM PST 24 21736402 ps
T1018 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.484640370 Feb 18 12:28:54 PM PST 24 Feb 18 12:29:02 PM PST 24 163680686 ps
T208 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1122871943 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:45 PM PST 24 604568494 ps
T103 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3500129231 Feb 18 12:28:57 PM PST 24 Feb 18 12:29:05 PM PST 24 80640161 ps
T127 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4202191497 Feb 18 12:28:28 PM PST 24 Feb 18 12:28:34 PM PST 24 95121960 ps
T1019 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3108593286 Feb 18 12:28:57 PM PST 24 Feb 18 12:29:04 PM PST 24 24092165 ps
T92 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.411249681 Feb 18 12:28:18 PM PST 24 Feb 18 12:28:27 PM PST 24 47633850 ps
T105 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4116641061 Feb 18 12:28:50 PM PST 24 Feb 18 12:28:55 PM PST 24 437583639 ps
T1020 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2988845543 Feb 18 12:28:49 PM PST 24 Feb 18 12:28:54 PM PST 24 145205360 ps
T1021 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.950281026 Feb 18 12:28:38 PM PST 24 Feb 18 12:28:41 PM PST 24 295094919 ps
T1022 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1777361556 Feb 18 12:28:50 PM PST 24 Feb 18 12:28:59 PM PST 24 104318353 ps
T1023 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3573880275 Feb 18 12:28:38 PM PST 24 Feb 18 12:28:43 PM PST 24 138928824 ps
T1024 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1660587284 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:50 PM PST 24 112487489 ps
T1025 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1497626206 Feb 18 12:28:57 PM PST 24 Feb 18 12:29:05 PM PST 24 46464101 ps
T1026 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1416784294 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:51 PM PST 24 148524915 ps
T1027 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1489017459 Feb 18 12:29:00 PM PST 24 Feb 18 12:29:06 PM PST 24 16839372 ps
T1028 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4258003622 Feb 18 12:28:33 PM PST 24 Feb 18 12:28:41 PM PST 24 813671400 ps
T1029 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4069872974 Feb 18 12:29:12 PM PST 24 Feb 18 12:29:15 PM PST 24 146935976 ps
T1030 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2039144 Feb 18 12:28:44 PM PST 24 Feb 18 12:28:49 PM PST 24 299387807 ps
T1031 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2229340963 Feb 18 12:28:34 PM PST 24 Feb 18 12:28:36 PM PST 24 35921091 ps
T1032 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.560083722 Feb 18 12:28:38 PM PST 24 Feb 18 12:28:42 PM PST 24 129995495 ps
T1033 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1374144468 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:39 PM PST 24 42881868 ps
T1034 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1724444052 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:46 PM PST 24 147644701 ps
T207 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.767309795 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:41 PM PST 24 41280397 ps
T1035 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2768141727 Feb 18 12:28:52 PM PST 24 Feb 18 12:28:56 PM PST 24 52729287 ps
T93 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1607094787 Feb 18 12:33:14 PM PST 24 Feb 18 12:33:19 PM PST 24 677508493 ps
T1036 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1495665241 Feb 18 12:28:34 PM PST 24 Feb 18 12:28:41 PM PST 24 386559188 ps
T1037 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.141349289 Feb 18 12:28:49 PM PST 24 Feb 18 12:28:52 PM PST 24 28142923 ps
T1038 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1341541151 Feb 18 12:28:46 PM PST 24 Feb 18 12:28:50 PM PST 24 27685108 ps
T1039 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3787130583 Feb 18 12:28:42 PM PST 24 Feb 18 12:28:47 PM PST 24 94185352 ps
T212 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.99095073 Feb 18 12:28:58 PM PST 24 Feb 18 12:29:10 PM PST 24 405531971 ps
T1040 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2857077958 Feb 18 12:28:51 PM PST 24 Feb 18 12:28:55 PM PST 24 130777830 ps
T1041 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.695331101 Feb 18 12:28:49 PM PST 24 Feb 18 12:29:26 PM PST 24 2235202483 ps
T1042 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4012395347 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:38 PM PST 24 29318082 ps
T1043 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2887145092 Feb 18 12:28:48 PM PST 24 Feb 18 12:28:52 PM PST 24 656965454 ps
T1044 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2847513613 Feb 18 12:28:45 PM PST 24 Feb 18 12:28:49 PM PST 24 177580828 ps
T1045 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1528086024 Feb 18 12:28:46 PM PST 24 Feb 18 12:29:07 PM PST 24 602392624 ps
T1046 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.784596259 Feb 18 12:28:46 PM PST 24 Feb 18 12:28:50 PM PST 24 22477196 ps
T1047 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3453371533 Feb 18 12:28:58 PM PST 24 Feb 18 12:29:05 PM PST 24 20053414 ps
T1048 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.115385644 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:39 PM PST 24 81613873 ps
T1049 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1336432251 Feb 18 12:28:38 PM PST 24 Feb 18 12:28:41 PM PST 24 15263370 ps
T1050 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3388122293 Feb 18 12:28:39 PM PST 24 Feb 18 12:28:48 PM PST 24 196422345 ps
T1051 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3664852452 Feb 18 12:29:10 PM PST 24 Feb 18 12:29:15 PM PST 24 2060654319 ps
T1052 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3522770018 Feb 18 12:28:40 PM PST 24 Feb 18 12:29:10 PM PST 24 2589982492 ps
T1053 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.533345390 Feb 18 12:28:51 PM PST 24 Feb 18 12:28:54 PM PST 24 15366441 ps
T1054 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.984815748 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:45 PM PST 24 132150479 ps
T1055 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.116451145 Feb 18 12:29:00 PM PST 24 Feb 18 12:29:06 PM PST 24 18911143 ps
T209 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2917072725 Feb 18 12:28:33 PM PST 24 Feb 18 12:28:49 PM PST 24 638020594 ps
T1056 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1265065362 Feb 18 12:28:51 PM PST 24 Feb 18 12:28:56 PM PST 24 31116102 ps
T210 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3911415392 Feb 18 12:28:56 PM PST 24 Feb 18 12:29:27 PM PST 24 6884190601 ps
T1057 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3258338501 Feb 18 12:28:47 PM PST 24 Feb 18 12:28:50 PM PST 24 91525281 ps
T1058 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3938835824 Feb 18 12:29:03 PM PST 24 Feb 18 12:29:21 PM PST 24 213252407 ps
T1059 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3987262737 Feb 18 12:28:53 PM PST 24 Feb 18 12:28:57 PM PST 24 17854720 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.371642394 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:46 PM PST 24 52746190 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1400338721 Feb 18 12:28:52 PM PST 24 Feb 18 12:28:57 PM PST 24 161955320 ps
T1062 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1719775843 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:49 PM PST 24 400419493 ps
T1063 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2821407522 Feb 18 12:28:45 PM PST 24 Feb 18 12:28:51 PM PST 24 343179643 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.140882751 Feb 18 12:28:42 PM PST 24 Feb 18 12:28:46 PM PST 24 14876027 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2272721088 Feb 18 12:28:33 PM PST 24 Feb 18 12:28:38 PM PST 24 277643580 ps
T1066 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2349190514 Feb 18 12:28:54 PM PST 24 Feb 18 12:28:58 PM PST 24 48987603 ps
T1067 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1642825401 Feb 18 12:28:49 PM PST 24 Feb 18 12:29:10 PM PST 24 604429208 ps
T1068 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1565812421 Feb 18 12:29:01 PM PST 24 Feb 18 12:29:08 PM PST 24 81249670 ps
T1069 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3729752667 Feb 18 12:28:42 PM PST 24 Feb 18 12:28:50 PM PST 24 151488297 ps
T1070 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.70156389 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:41 PM PST 24 121295578 ps
T1071 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2983635880 Feb 18 12:29:01 PM PST 24 Feb 18 12:29:10 PM PST 24 185673954 ps
T1072 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1355214465 Feb 18 12:28:51 PM PST 24 Feb 18 12:29:01 PM PST 24 12494914 ps
T1073 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.701539569 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:40 PM PST 24 796484895 ps
T1074 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.770825503 Feb 18 12:28:38 PM PST 24 Feb 18 12:28:41 PM PST 24 17597139 ps
T1075 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1043986190 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:39 PM PST 24 35092478 ps
T1076 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2195685535 Feb 18 12:29:01 PM PST 24 Feb 18 12:29:07 PM PST 24 33747616 ps
T1077 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2629219654 Feb 18 12:28:55 PM PST 24 Feb 18 12:29:02 PM PST 24 28467388 ps
T1078 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2502253821 Feb 18 12:28:48 PM PST 24 Feb 18 12:28:55 PM PST 24 475833712 ps
T1079 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.66624184 Feb 18 12:28:28 PM PST 24 Feb 18 12:29:11 PM PST 24 21406200607 ps
T1080 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.968708163 Feb 18 12:28:43 PM PST 24 Feb 18 12:28:48 PM PST 24 50291048 ps
T1081 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3468610881 Feb 18 12:28:38 PM PST 24 Feb 18 12:28:42 PM PST 24 47342255 ps
T1082 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.359514615 Feb 18 12:28:35 PM PST 24 Feb 18 12:28:39 PM PST 24 49303375 ps
T1083 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3451149490 Feb 18 12:28:51 PM PST 24 Feb 18 12:28:53 PM PST 24 20570917 ps
T1084 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2405762503 Feb 18 12:28:53 PM PST 24 Feb 18 12:28:58 PM PST 24 55305243 ps
T1085 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.114798983 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:50 PM PST 24 1188880499 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3574454159 Feb 18 12:28:38 PM PST 24 Feb 18 12:28:43 PM PST 24 49763595 ps
T1087 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1862731564 Feb 18 12:28:50 PM PST 24 Feb 18 12:28:54 PM PST 24 32067363 ps
T1088 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.248898112 Feb 18 12:28:53 PM PST 24 Feb 18 12:28:59 PM PST 24 275061362 ps
T213 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3141468700 Feb 18 12:28:43 PM PST 24 Feb 18 12:29:01 PM PST 24 744441097 ps
T1089 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4034152498 Feb 18 12:28:37 PM PST 24 Feb 18 12:28:42 PM PST 24 167095894 ps
T1090 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1961800138 Feb 18 12:28:44 PM PST 24 Feb 18 12:28:48 PM PST 24 39074864 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1971479437 Feb 18 12:28:44 PM PST 24 Feb 18 12:28:55 PM PST 24 243257666 ps
T1092 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3474268559 Feb 18 12:28:38 PM PST 24 Feb 18 12:29:04 PM PST 24 958194436 ps
T1093 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1363160259 Feb 18 12:28:55 PM PST 24 Feb 18 12:29:01 PM PST 24 280649916 ps
T1094 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.508161619 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:45 PM PST 24 277608610 ps
T1095 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3304019192 Feb 18 12:28:49 PM PST 24 Feb 18 12:28:53 PM PST 24 20546064 ps
T1096 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1218361670 Feb 18 12:28:55 PM PST 24 Feb 18 12:29:01 PM PST 24 12518567 ps
T1097 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2616711646 Feb 18 12:29:16 PM PST 24 Feb 18 12:29:20 PM PST 24 18087610 ps
T1098 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.802594857 Feb 18 12:28:56 PM PST 24 Feb 18 12:29:02 PM PST 24 46690002 ps
T1099 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3520982484 Feb 18 12:28:48 PM PST 24 Feb 18 12:28:53 PM PST 24 1029211507 ps

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2240436210
Short name T1
Test name
Test status
Simulation time 14745811164 ps
CPU time 63.41 seconds
Started Feb 18 02:14:18 PM PST 24
Finished Feb 18 02:16:16 PM PST 24
Peak memory 254700 kb
Host smart-d0c39bfd-0e35-47a9-9fa1-b7dfd2035221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240436210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2240436210
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1568272475
Short name T11
Test name
Test status
Simulation time 1113706647651 ps
CPU time 886.69 seconds
Started Feb 18 02:13:57 PM PST 24
Finished Feb 18 02:29:23 PM PST 24
Peak memory 265380 kb
Host smart-ede88708-9306-45be-82c2-c0cb780eff34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568272475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1568272475
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1042178311
Short name T29
Test name
Test status
Simulation time 21101566598 ps
CPU time 335.49 seconds
Started Feb 18 02:15:37 PM PST 24
Finished Feb 18 02:21:52 PM PST 24
Peak memory 305960 kb
Host smart-a90e7184-23ab-4415-9b67-67288ba315b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042178311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1042178311
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1432845054
Short name T78
Test name
Test status
Simulation time 1037365048 ps
CPU time 20.99 seconds
Started Feb 18 12:28:29 PM PST 24
Finished Feb 18 12:28:54 PM PST 24
Peak memory 214452 kb
Host smart-193f7f56-d081-4baa-8a49-09b473fdc949
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432845054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1432845054
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3539765831
Short name T171
Test name
Test status
Simulation time 71152319313 ps
CPU time 349.12 seconds
Started Feb 18 02:15:01 PM PST 24
Finished Feb 18 02:21:33 PM PST 24
Peak memory 281740 kb
Host smart-fe1f77f1-e3e8-4f04-be49-4d1b88b9c64f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539765831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3539765831
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3958827116
Short name T305
Test name
Test status
Simulation time 26798075 ps
CPU time 0.73 seconds
Started Feb 18 02:12:09 PM PST 24
Finished Feb 18 02:12:43 PM PST 24
Peak memory 216008 kb
Host smart-1c9addf1-0664-47a9-8f59-2f16a2e00983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958827116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3958827116
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3901031164
Short name T58
Test name
Test status
Simulation time 294413489134 ps
CPU time 1055.57 seconds
Started Feb 18 02:15:15 PM PST 24
Finished Feb 18 02:33:29 PM PST 24
Peak memory 298588 kb
Host smart-b5490ba8-a6d3-4252-84ee-2272d07a6936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901031164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3901031164
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1829178152
Short name T76
Test name
Test status
Simulation time 456043087 ps
CPU time 7.75 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:55 PM PST 24
Peak memory 218868 kb
Host smart-600f1d44-68d9-4118-acca-9d96dd52e07d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829178152 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1829178152
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.898110741
Short name T39
Test name
Test status
Simulation time 2653424846 ps
CPU time 17.42 seconds
Started Feb 18 02:15:07 PM PST 24
Finished Feb 18 02:16:05 PM PST 24
Peak memory 240096 kb
Host smart-b7bf94e1-a75e-4733-a6f7-ef9d433120d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898110741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.898110741
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2400092432
Short name T27
Test name
Test status
Simulation time 12732760284 ps
CPU time 136.5 seconds
Started Feb 18 02:12:17 PM PST 24
Finished Feb 18 02:15:07 PM PST 24
Peak memory 265436 kb
Host smart-63b3bdf3-9629-48ee-8e75-15b197383678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400092432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2400092432
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4218980486
Short name T6
Test name
Test status
Simulation time 11369890 ps
CPU time 0.7 seconds
Started Feb 18 02:15:44 PM PST 24
Finished Feb 18 02:16:23 PM PST 24
Peak memory 204688 kb
Host smart-650dae85-00fa-4b2a-9895-bd60ab6dd977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218980486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4218980486
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4269170225
Short name T179
Test name
Test status
Simulation time 277320743801 ps
CPU time 557.86 seconds
Started Feb 18 02:14:11 PM PST 24
Finished Feb 18 02:24:10 PM PST 24
Peak memory 281812 kb
Host smart-fc7bdfa2-9405-4b44-b622-c430b5888407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269170225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4269170225
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1121249629
Short name T32
Test name
Test status
Simulation time 82314534325 ps
CPU time 639.11 seconds
Started Feb 18 02:13:07 PM PST 24
Finished Feb 18 02:24:31 PM PST 24
Peak memory 273212 kb
Host smart-bee76cf8-b51c-4224-a691-09579baba3d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121249629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1121249629
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2548516407
Short name T96
Test name
Test status
Simulation time 203451677 ps
CPU time 2.63 seconds
Started Feb 18 12:28:57 PM PST 24
Finished Feb 18 12:29:05 PM PST 24
Peak memory 214672 kb
Host smart-7aee1142-804c-4cc4-b4c0-32387cb6eaf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548516407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2548516407
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.498405381
Short name T178
Test name
Test status
Simulation time 73567303329 ps
CPU time 510.87 seconds
Started Feb 18 02:14:14 PM PST 24
Finished Feb 18 02:23:27 PM PST 24
Peak memory 252544 kb
Host smart-9d957738-bab1-4a70-bf49-e2aa0c81ffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498405381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.498405381
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1631134543
Short name T571
Test name
Test status
Simulation time 26326714 ps
CPU time 1.04 seconds
Started Feb 18 02:13:04 PM PST 24
Finished Feb 18 02:13:44 PM PST 24
Peak memory 216308 kb
Host smart-81491d27-3fd5-4d7a-a879-d8aef3ba0208
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631134543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1631134543
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3579009424
Short name T192
Test name
Test status
Simulation time 211921218384 ps
CPU time 545.27 seconds
Started Feb 18 02:13:56 PM PST 24
Finished Feb 18 02:23:47 PM PST 24
Peak memory 273424 kb
Host smart-564f8d60-8c58-48bc-90b7-1636a63c5388
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579009424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3579009424
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3007783902
Short name T50
Test name
Test status
Simulation time 81608005 ps
CPU time 1.03 seconds
Started Feb 18 02:12:14 PM PST 24
Finished Feb 18 02:12:48 PM PST 24
Peak memory 235396 kb
Host smart-4d57b604-fd07-4233-8341-7ac75131f6e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007783902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3007783902
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2960509494
Short name T146
Test name
Test status
Simulation time 511569062644 ps
CPU time 968.29 seconds
Started Feb 18 02:14:40 PM PST 24
Finished Feb 18 02:31:38 PM PST 24
Peak memory 285676 kb
Host smart-0ef4c09d-26b9-4614-bebe-64bccd780216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960509494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2960509494
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.589755598
Short name T182
Test name
Test status
Simulation time 29067932428 ps
CPU time 412.65 seconds
Started Feb 18 02:13:32 PM PST 24
Finished Feb 18 02:21:12 PM PST 24
Peak memory 281808 kb
Host smart-9d410a8a-7d12-436e-b194-6c09ff8e4525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589755598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.589755598
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3231424847
Short name T66
Test name
Test status
Simulation time 76286316331 ps
CPU time 282.85 seconds
Started Feb 18 02:12:28 PM PST 24
Finished Feb 18 02:17:50 PM PST 24
Peak memory 249580 kb
Host smart-582531e2-8341-4072-9405-b41b9f3970c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231424847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3231424847
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.260977090
Short name T187
Test name
Test status
Simulation time 193838493919 ps
CPU time 435.7 seconds
Started Feb 18 02:13:55 PM PST 24
Finished Feb 18 02:21:58 PM PST 24
Peak memory 273056 kb
Host smart-4a01f53a-5116-49d0-a8ef-8c75404b1392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260977090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.260977090
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1143702130
Short name T159
Test name
Test status
Simulation time 33196019374 ps
CPU time 290.47 seconds
Started Feb 18 02:15:39 PM PST 24
Finished Feb 18 02:21:09 PM PST 24
Peak memory 256856 kb
Host smart-77959f45-3eed-4d30-a4a6-2a603a8e94f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143702130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1143702130
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.411249681
Short name T92
Test name
Test status
Simulation time 47633850 ps
CPU time 3.03 seconds
Started Feb 18 12:28:18 PM PST 24
Finished Feb 18 12:28:27 PM PST 24
Peak memory 214648 kb
Host smart-1bc6eb64-b338-47fb-af5f-c777c84761d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411249681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.411249681
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2559497281
Short name T12
Test name
Test status
Simulation time 15206620010 ps
CPU time 49.23 seconds
Started Feb 18 02:13:38 PM PST 24
Finished Feb 18 02:15:08 PM PST 24
Peak memory 251376 kb
Host smart-93312fd7-4e1a-4429-b342-4e451185f594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559497281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2559497281
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3911415392
Short name T210
Test name
Test status
Simulation time 6884190601 ps
CPU time 21.98 seconds
Started Feb 18 12:28:56 PM PST 24
Finished Feb 18 12:29:27 PM PST 24
Peak memory 214740 kb
Host smart-6a32eaa0-f9b9-4ac0-bbba-290188b9339f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911415392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3911415392
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.772993878
Short name T252
Test name
Test status
Simulation time 11486963073 ps
CPU time 26.59 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:15:53 PM PST 24
Peak memory 224344 kb
Host smart-6b93eca2-f983-4d8c-8df8-a63d761c6956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772993878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.772993878
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1327138272
Short name T68
Test name
Test status
Simulation time 26073897092 ps
CPU time 158.86 seconds
Started Feb 18 02:16:17 PM PST 24
Finished Feb 18 02:19:25 PM PST 24
Peak memory 273644 kb
Host smart-39c46c3a-3722-4ff4-b282-44b9c6143b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327138272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1327138272
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1264994525
Short name T134
Test name
Test status
Simulation time 86371744610 ps
CPU time 412.23 seconds
Started Feb 18 02:12:39 PM PST 24
Finished Feb 18 02:20:13 PM PST 24
Peak memory 281812 kb
Host smart-c3e36ced-a4ee-43d4-8f48-960901e31baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264994525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1264994525
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3457935840
Short name T90
Test name
Test status
Simulation time 1157565252 ps
CPU time 12.48 seconds
Started Feb 18 12:28:41 PM PST 24
Finished Feb 18 12:28:57 PM PST 24
Peak memory 214576 kb
Host smart-312dc7cb-cfae-4bf0-9574-64bf25a66b60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457935840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3457935840
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.633925020
Short name T190
Test name
Test status
Simulation time 28087389067 ps
CPU time 145.47 seconds
Started Feb 18 02:12:21 PM PST 24
Finished Feb 18 02:15:21 PM PST 24
Peak memory 266232 kb
Host smart-03c102eb-ff1a-481a-9c67-3b3eefb5f955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633925020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
633925020
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3937556515
Short name T359
Test name
Test status
Simulation time 941848050 ps
CPU time 16.73 seconds
Started Feb 18 02:13:07 PM PST 24
Finished Feb 18 02:14:05 PM PST 24
Peak memory 224228 kb
Host smart-04cd7781-4522-4e9b-8e37-063cae0fbf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937556515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3937556515
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.297066593
Short name T223
Test name
Test status
Simulation time 67410058537 ps
CPU time 80.9 seconds
Started Feb 18 02:13:14 PM PST 24
Finished Feb 18 02:15:16 PM PST 24
Peak memory 224364 kb
Host smart-2869ff65-b957-4429-bbb0-881cb062a558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297066593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.297066593
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4000691672
Short name T163
Test name
Test status
Simulation time 30036826523 ps
CPU time 121.9 seconds
Started Feb 18 02:13:37 PM PST 24
Finished Feb 18 02:16:25 PM PST 24
Peak memory 240500 kb
Host smart-622fc0c8-89d9-4a05-95be-2866e431463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000691672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4000691672
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4258003622
Short name T1028
Test name
Test status
Simulation time 813671400 ps
CPU time 6.07 seconds
Started Feb 18 12:28:33 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 219528 kb
Host smart-1a1ea454-0792-4c93-8273-b86866c1e4a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258003622 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4258003622
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3183171576
Short name T65
Test name
Test status
Simulation time 19119694 ps
CPU time 1.15 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:47 PM PST 24
Peak memory 206476 kb
Host smart-07b2bc5d-c7b1-4247-a996-d58e82875a25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183171576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3183171576
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.910076414
Short name T81
Test name
Test status
Simulation time 539976299 ps
CPU time 10.21 seconds
Started Feb 18 12:28:29 PM PST 24
Finished Feb 18 12:28:44 PM PST 24
Peak memory 219640 kb
Host smart-c25d673d-b46d-418b-8d96-16a02febfbdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910076414 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.910076414
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.679607870
Short name T101
Test name
Test status
Simulation time 7957769676 ps
CPU time 15.39 seconds
Started Feb 18 12:28:42 PM PST 24
Finished Feb 18 12:29:00 PM PST 24
Peak memory 214704 kb
Host smart-6a10558c-448f-46dd-aa32-b112a8060e28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679607870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.679607870
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.66624184
Short name T1079
Test name
Test status
Simulation time 21406200607 ps
CPU time 38.12 seconds
Started Feb 18 12:28:28 PM PST 24
Finished Feb 18 12:29:11 PM PST 24
Peak memory 206304 kb
Host smart-3f1ce99f-e5e4-449e-836d-3c6e2f71d95c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66624184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
bit_bash.66624184
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1421609392
Short name T992
Test name
Test status
Simulation time 316311716 ps
CPU time 2.36 seconds
Started Feb 18 12:28:44 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 214680 kb
Host smart-c03506ed-ead4-41f4-8a19-d46114a5bfa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421609392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
421609392
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.140882751
Short name T1064
Test name
Test status
Simulation time 14876027 ps
CPU time 0.73 seconds
Started Feb 18 12:28:42 PM PST 24
Finished Feb 18 12:28:46 PM PST 24
Peak memory 202392 kb
Host smart-a33941a0-99e9-4473-a0b7-80e27ed8dcd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140882751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.140882751
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3468610881
Short name T1081
Test name
Test status
Simulation time 47342255 ps
CPU time 2.04 seconds
Started Feb 18 12:28:38 PM PST 24
Finished Feb 18 12:28:42 PM PST 24
Peak memory 214672 kb
Host smart-912cb85f-4c84-49ee-85bc-6b8a65d50bfe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468610881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3468610881
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4012395347
Short name T1042
Test name
Test status
Simulation time 29318082 ps
CPU time 0.66 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:38 PM PST 24
Peak memory 202736 kb
Host smart-57a2ffd8-1ca8-4ec5-9b2a-cac3ea1ea22f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012395347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4012395347
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1416784294
Short name T1026
Test name
Test status
Simulation time 148524915 ps
CPU time 1.8 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:51 PM PST 24
Peak memory 206380 kb
Host smart-ab9d1002-c63f-4f85-8ddc-e4581ce08a3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416784294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1416784294
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3044854179
Short name T73
Test name
Test status
Simulation time 1229426742 ps
CPU time 18.27 seconds
Started Feb 18 12:28:35 PM PST 24
Finished Feb 18 12:28:55 PM PST 24
Peak memory 214524 kb
Host smart-57350c20-34c2-4b1d-a6af-6f55fe6bedc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044854179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3044854179
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1971479437
Short name T1091
Test name
Test status
Simulation time 243257666 ps
CPU time 7.47 seconds
Started Feb 18 12:28:44 PM PST 24
Finished Feb 18 12:28:55 PM PST 24
Peak memory 206468 kb
Host smart-2a24c891-026d-445b-9d40-bd4b058fd02f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971479437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1971479437
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3522770018
Short name T1052
Test name
Test status
Simulation time 2589982492 ps
CPU time 26.03 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:29:10 PM PST 24
Peak memory 206516 kb
Host smart-556cf2e0-4c3c-4206-abdb-c4425e112ac2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522770018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3522770018
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.835670732
Short name T64
Test name
Test status
Simulation time 94056095 ps
CPU time 1.41 seconds
Started Feb 18 12:28:28 PM PST 24
Finished Feb 18 12:28:34 PM PST 24
Peak memory 206272 kb
Host smart-b8123491-2309-490d-aec3-be53ea1cdd3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835670732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.835670732
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2272721088
Short name T1065
Test name
Test status
Simulation time 277643580 ps
CPU time 2.59 seconds
Started Feb 18 12:28:33 PM PST 24
Finished Feb 18 12:28:38 PM PST 24
Peak memory 206416 kb
Host smart-39a76273-c297-400e-9fd8-421ff242500e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272721088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
272721088
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3145788829
Short name T988
Test name
Test status
Simulation time 48926292 ps
CPU time 0.69 seconds
Started Feb 18 12:28:39 PM PST 24
Finished Feb 18 12:28:43 PM PST 24
Peak memory 202720 kb
Host smart-6cc9a243-48a1-4dbf-9560-c22d229bb414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145788829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
145788829
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4083794794
Short name T104
Test name
Test status
Simulation time 58081070 ps
CPU time 2.23 seconds
Started Feb 18 12:28:24 PM PST 24
Finished Feb 18 12:28:32 PM PST 24
Peak memory 214720 kb
Host smart-2418acc1-f81a-4bd8-908c-cb96bb31db76
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083794794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4083794794
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2229340963
Short name T1031
Test name
Test status
Simulation time 35921091 ps
CPU time 0.62 seconds
Started Feb 18 12:28:34 PM PST 24
Finished Feb 18 12:28:36 PM PST 24
Peak memory 202712 kb
Host smart-4f250cf5-aa79-4e1d-83fb-9ce9bc371d10
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229340963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2229340963
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3574454159
Short name T1086
Test name
Test status
Simulation time 49763595 ps
CPU time 2.82 seconds
Started Feb 18 12:28:38 PM PST 24
Finished Feb 18 12:28:43 PM PST 24
Peak memory 214648 kb
Host smart-ff4273b6-edb8-488c-82d1-085a518cb71a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574454159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3574454159
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2753702574
Short name T88
Test name
Test status
Simulation time 36793255 ps
CPU time 2.6 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:49 PM PST 24
Peak memory 214728 kb
Host smart-737875b2-38a1-4aba-8880-687924fbf533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753702574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
753702574
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2917072725
Short name T209
Test name
Test status
Simulation time 638020594 ps
CPU time 13.73 seconds
Started Feb 18 12:28:33 PM PST 24
Finished Feb 18 12:28:49 PM PST 24
Peak memory 215048 kb
Host smart-f7011696-c926-41e7-81ba-7fa62d6a68cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917072725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2917072725
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2821407522
Short name T1063
Test name
Test status
Simulation time 343179643 ps
CPU time 2.82 seconds
Started Feb 18 12:28:45 PM PST 24
Finished Feb 18 12:28:51 PM PST 24
Peak memory 216784 kb
Host smart-78f7ba76-856c-4189-ab1e-0565360f6a5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821407522 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2821407522
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.508161619
Short name T1094
Test name
Test status
Simulation time 277608610 ps
CPU time 2.03 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:45 PM PST 24
Peak memory 206476 kb
Host smart-49a2d46b-c721-4282-9a0b-cba00a67b1c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508161619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.508161619
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2847513613
Short name T1044
Test name
Test status
Simulation time 177580828 ps
CPU time 0.68 seconds
Started Feb 18 12:28:45 PM PST 24
Finished Feb 18 12:28:49 PM PST 24
Peak memory 202704 kb
Host smart-e09def46-3fad-4f14-9132-99ed2a8ebc40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847513613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2847513613
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1565812421
Short name T1068
Test name
Test status
Simulation time 81249670 ps
CPU time 1.91 seconds
Started Feb 18 12:29:01 PM PST 24
Finished Feb 18 12:29:08 PM PST 24
Peak memory 214708 kb
Host smart-aa9e9458-3d68-499d-b59e-a6ad1b8b9b50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565812421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1565812421
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.984815748
Short name T1054
Test name
Test status
Simulation time 132150479 ps
CPU time 2.19 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:45 PM PST 24
Peak memory 214892 kb
Host smart-dfb15004-11f9-4d58-af17-ad40b18b5072
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984815748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.984815748
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1719775843
Short name T1062
Test name
Test status
Simulation time 400419493 ps
CPU time 5.93 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:49 PM PST 24
Peak memory 214652 kb
Host smart-cc6dd5e6-07d2-4d60-9606-e4f087853530
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719775843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1719775843
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3388122293
Short name T1050
Test name
Test status
Simulation time 196422345 ps
CPU time 5.76 seconds
Started Feb 18 12:28:39 PM PST 24
Finished Feb 18 12:28:48 PM PST 24
Peak memory 218408 kb
Host smart-ecbac4a6-44d7-4ec9-be85-8677bbfc2035
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388122293 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3388122293
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.950281026
Short name T1021
Test name
Test status
Simulation time 295094919 ps
CPU time 1.35 seconds
Started Feb 18 12:28:38 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 206460 kb
Host smart-16aaaddc-ffa9-4a45-ba24-5be64f123f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950281026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.950281026
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1336432251
Short name T1049
Test name
Test status
Simulation time 15263370 ps
CPU time 0.7 seconds
Started Feb 18 12:28:38 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 202416 kb
Host smart-92bd8231-0b73-4883-9cc4-95eaa0a1b5a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336432251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1336432251
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1363160259
Short name T1093
Test name
Test status
Simulation time 280649916 ps
CPU time 2.93 seconds
Started Feb 18 12:28:55 PM PST 24
Finished Feb 18 12:29:01 PM PST 24
Peak memory 214752 kb
Host smart-f8f9ae73-f89d-44ef-a878-f73f043d857f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363160259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1363160259
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1862731564
Short name T1087
Test name
Test status
Simulation time 32067363 ps
CPU time 2.1 seconds
Started Feb 18 12:28:50 PM PST 24
Finished Feb 18 12:28:54 PM PST 24
Peak memory 214908 kb
Host smart-ad94360a-52ac-4638-931b-95e82bb5d1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862731564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1862731564
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3141468700
Short name T213
Test name
Test status
Simulation time 744441097 ps
CPU time 15.13 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:29:01 PM PST 24
Peak memory 222824 kb
Host smart-c3bd927b-539b-4317-ae52-b1debccbf29d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141468700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3141468700
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3304019192
Short name T1095
Test name
Test status
Simulation time 20546064 ps
CPU time 1.37 seconds
Started Feb 18 12:28:49 PM PST 24
Finished Feb 18 12:28:53 PM PST 24
Peak memory 206468 kb
Host smart-dd799715-808a-4792-856f-36d1b62bc73c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304019192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3304019192
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.110506299
Short name T1016
Test name
Test status
Simulation time 137778799 ps
CPU time 0.76 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:39 PM PST 24
Peak memory 202408 kb
Host smart-483e7920-d8bc-4450-b8d5-05c6d8977f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110506299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.110506299
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4034152498
Short name T1089
Test name
Test status
Simulation time 167095894 ps
CPU time 2.83 seconds
Started Feb 18 12:28:37 PM PST 24
Finished Feb 18 12:28:42 PM PST 24
Peak memory 206244 kb
Host smart-79994c48-f33a-4644-a404-cd5006930ce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034152498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4034152498
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3589829363
Short name T80
Test name
Test status
Simulation time 415700108 ps
CPU time 3.01 seconds
Started Feb 18 12:29:26 PM PST 24
Finished Feb 18 12:29:30 PM PST 24
Peak memory 214792 kb
Host smart-e1aa5f69-9290-4139-9e8c-113b9fedc624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589829363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3589829363
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1497626206
Short name T1025
Test name
Test status
Simulation time 46464101 ps
CPU time 3.19 seconds
Started Feb 18 12:28:57 PM PST 24
Finished Feb 18 12:29:05 PM PST 24
Peak memory 216260 kb
Host smart-28754f9f-53b3-4b14-a47d-ef4b43037392
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497626206 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1497626206
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2022823676
Short name T97
Test name
Test status
Simulation time 51734909 ps
CPU time 1.39 seconds
Started Feb 18 12:28:54 PM PST 24
Finished Feb 18 12:29:00 PM PST 24
Peak memory 206488 kb
Host smart-e4ff6eca-baf2-416f-bb1e-def9d67aea7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022823676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2022823676
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3258338501
Short name T1057
Test name
Test status
Simulation time 91525281 ps
CPU time 0.7 seconds
Started Feb 18 12:28:47 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 202392 kb
Host smart-b121649e-357f-4106-a72e-1ce36fbb8bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258338501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3258338501
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.701539569
Short name T1073
Test name
Test status
Simulation time 796484895 ps
CPU time 2.9 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:40 PM PST 24
Peak memory 206244 kb
Host smart-219cafeb-746e-48b1-a02e-26dcfd764e88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701539569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.701539569
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2737942436
Short name T85
Test name
Test status
Simulation time 109955282 ps
CPU time 2.06 seconds
Started Feb 18 12:28:50 PM PST 24
Finished Feb 18 12:28:54 PM PST 24
Peak memory 214800 kb
Host smart-f408568d-cd55-408b-8e9e-f819632e68a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737942436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2737942436
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4238745347
Short name T211
Test name
Test status
Simulation time 672377553 ps
CPU time 6.39 seconds
Started Feb 18 12:28:37 PM PST 24
Finished Feb 18 12:28:46 PM PST 24
Peak memory 214632 kb
Host smart-e0540bbd-389a-4017-ae5c-3ca3bb332bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238745347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4238745347
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2999256760
Short name T87
Test name
Test status
Simulation time 385288745 ps
CPU time 7.1 seconds
Started Feb 18 12:29:12 PM PST 24
Finished Feb 18 12:29:20 PM PST 24
Peak memory 219416 kb
Host smart-a52206ac-e1a0-4ec3-825c-1ecc7e74688e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999256760 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2999256760
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1265065362
Short name T1056
Test name
Test status
Simulation time 31116102 ps
CPU time 1.94 seconds
Started Feb 18 12:28:51 PM PST 24
Finished Feb 18 12:28:56 PM PST 24
Peak memory 206464 kb
Host smart-1aac1409-ccb2-4246-86c8-3f7d34f48b1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265065362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1265065362
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1891523562
Short name T1014
Test name
Test status
Simulation time 19468843 ps
CPU time 0.78 seconds
Started Feb 18 12:28:53 PM PST 24
Finished Feb 18 12:29:00 PM PST 24
Peak memory 202396 kb
Host smart-1782a380-5eea-4a9a-8e1e-3723852be05e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891523562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1891523562
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.330786810
Short name T123
Test name
Test status
Simulation time 400685758 ps
CPU time 4.05 seconds
Started Feb 18 12:28:55 PM PST 24
Finished Feb 18 12:29:04 PM PST 24
Peak memory 206440 kb
Host smart-367040e8-c15e-405e-86be-a6ed2004d510
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330786810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.330786810
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1495665241
Short name T1036
Test name
Test status
Simulation time 386559188 ps
CPU time 4.8 seconds
Started Feb 18 12:28:34 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 215912 kb
Host smart-fd06dd93-2b9f-4b4c-89b1-7780d52faf06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495665241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1495665241
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2629219654
Short name T1077
Test name
Test status
Simulation time 28467388 ps
CPU time 1.83 seconds
Started Feb 18 12:28:55 PM PST 24
Finished Feb 18 12:29:02 PM PST 24
Peak memory 206552 kb
Host smart-87b14af6-68f5-4d8b-8a68-5d080f1371be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629219654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2629219654
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3453371533
Short name T1047
Test name
Test status
Simulation time 20053414 ps
CPU time 0.75 seconds
Started Feb 18 12:28:58 PM PST 24
Finished Feb 18 12:29:05 PM PST 24
Peak memory 202392 kb
Host smart-bcf26958-4de7-45d5-a784-3fc209a82e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453371533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3453371533
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1326814841
Short name T990
Test name
Test status
Simulation time 1134706775 ps
CPU time 1.75 seconds
Started Feb 18 12:28:46 PM PST 24
Finished Feb 18 12:28:51 PM PST 24
Peak memory 214628 kb
Host smart-75ef72be-b2c4-41d6-8dd6-f6effcde457f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326814841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1326814841
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4228558673
Short name T89
Test name
Test status
Simulation time 211501591 ps
CPU time 2.9 seconds
Started Feb 18 12:28:58 PM PST 24
Finished Feb 18 12:29:07 PM PST 24
Peak memory 214800 kb
Host smart-991c13a6-ab19-4b5d-9c6e-4be53bc8ec51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228558673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4228558673
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2752548885
Short name T215
Test name
Test status
Simulation time 1151462543 ps
CPU time 8.11 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:52 PM PST 24
Peak memory 214660 kb
Host smart-0a81e7f0-4aae-4f0e-8ba7-83644be9fe1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752548885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2752548885
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3794939110
Short name T84
Test name
Test status
Simulation time 80350786 ps
CPU time 5.62 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:53 PM PST 24
Peak memory 218992 kb
Host smart-78e8c10e-ec80-434a-866d-5d101fa9baf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794939110 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3794939110
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3713821350
Short name T998
Test name
Test status
Simulation time 13220460 ps
CPU time 0.69 seconds
Started Feb 18 12:29:12 PM PST 24
Finished Feb 18 12:29:14 PM PST 24
Peak memory 202708 kb
Host smart-1d28f102-35c3-4579-8409-6a7f0286bdf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713821350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3713821350
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1221333951
Short name T1005
Test name
Test status
Simulation time 56503539 ps
CPU time 3.35 seconds
Started Feb 18 12:28:57 PM PST 24
Finished Feb 18 12:29:05 PM PST 24
Peak memory 214688 kb
Host smart-3c376b7f-5756-435b-b265-eecba676e261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221333951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1221333951
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1607094787
Short name T93
Test name
Test status
Simulation time 677508493 ps
CPU time 3.47 seconds
Started Feb 18 12:33:14 PM PST 24
Finished Feb 18 12:33:19 PM PST 24
Peak memory 215032 kb
Host smart-efb012f1-6e64-4d80-a2e6-43c604133e0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607094787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1607094787
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1122871943
Short name T208
Test name
Test status
Simulation time 604568494 ps
CPU time 7.44 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:45 PM PST 24
Peak memory 214712 kb
Host smart-b1aba879-a02e-4ac1-95c8-a01881540134
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122871943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1122871943
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1724444052
Short name T1034
Test name
Test status
Simulation time 147644701 ps
CPU time 2.02 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:46 PM PST 24
Peak memory 206408 kb
Host smart-a94b187d-f687-41c9-b1f8-1907fcf0136e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724444052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1724444052
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3463278461
Short name T1006
Test name
Test status
Simulation time 56742376 ps
CPU time 0.7 seconds
Started Feb 18 12:29:10 PM PST 24
Finished Feb 18 12:29:11 PM PST 24
Peak memory 202568 kb
Host smart-70436198-19ef-499d-b393-83fcb7c7d7eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463278461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3463278461
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.435703081
Short name T128
Test name
Test status
Simulation time 121702861 ps
CPU time 1.82 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:46 PM PST 24
Peak memory 214396 kb
Host smart-84504679-7e36-453e-88ed-02b4876a2e1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435703081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.435703081
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3833177192
Short name T74
Test name
Test status
Simulation time 116221528 ps
CPU time 3.58 seconds
Started Feb 18 12:29:12 PM PST 24
Finished Feb 18 12:29:17 PM PST 24
Peak memory 214820 kb
Host smart-dad7c7a4-5f28-4e8a-956c-65f97cd321f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833177192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3833177192
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1528086024
Short name T1045
Test name
Test status
Simulation time 602392624 ps
CPU time 17.76 seconds
Started Feb 18 12:28:46 PM PST 24
Finished Feb 18 12:29:07 PM PST 24
Peak memory 214396 kb
Host smart-049701dc-a45f-4e40-a825-325a191f7d44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528086024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1528086024
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4274937154
Short name T102
Test name
Test status
Simulation time 62159170 ps
CPU time 2.01 seconds
Started Feb 18 12:29:12 PM PST 24
Finished Feb 18 12:29:16 PM PST 24
Peak memory 206468 kb
Host smart-5a6c1216-3ced-4130-afa7-40669d0bbe80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274937154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4274937154
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1218361670
Short name T1096
Test name
Test status
Simulation time 12518567 ps
CPU time 0.75 seconds
Started Feb 18 12:28:55 PM PST 24
Finished Feb 18 12:29:01 PM PST 24
Peak memory 202484 kb
Host smart-e845165b-83bf-4f8a-a447-0d97dfc5df82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218361670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1218361670
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2988845543
Short name T1020
Test name
Test status
Simulation time 145205360 ps
CPU time 3.06 seconds
Started Feb 18 12:28:49 PM PST 24
Finished Feb 18 12:28:54 PM PST 24
Peak memory 206360 kb
Host smart-b60a73ad-86d1-4431-b1d6-2d82fcfaa998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988845543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2988845543
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4036121687
Short name T91
Test name
Test status
Simulation time 645165752 ps
CPU time 3.84 seconds
Started Feb 18 12:28:50 PM PST 24
Finished Feb 18 12:28:56 PM PST 24
Peak memory 214976 kb
Host smart-d6cbfe5e-0a68-43c5-8811-ff74aa7651d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036121687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4036121687
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3938835824
Short name T1058
Test name
Test status
Simulation time 213252407 ps
CPU time 13.16 seconds
Started Feb 18 12:29:03 PM PST 24
Finished Feb 18 12:29:21 PM PST 24
Peak memory 214736 kb
Host smart-0a79693d-7208-4026-bb98-a353a9f77e99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938835824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3938835824
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4116641061
Short name T105
Test name
Test status
Simulation time 437583639 ps
CPU time 2.46 seconds
Started Feb 18 12:28:50 PM PST 24
Finished Feb 18 12:28:55 PM PST 24
Peak memory 206424 kb
Host smart-b352d460-08c0-4703-a86a-ddfe3b9fae84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116641061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4116641061
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1043986190
Short name T1075
Test name
Test status
Simulation time 35092478 ps
CPU time 0.7 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:39 PM PST 24
Peak memory 202708 kb
Host smart-e4a67522-0cbf-4099-9539-edf98fa335ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043986190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1043986190
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2502253821
Short name T1078
Test name
Test status
Simulation time 475833712 ps
CPU time 4.55 seconds
Started Feb 18 12:28:48 PM PST 24
Finished Feb 18 12:28:55 PM PST 24
Peak memory 206308 kb
Host smart-8708b5da-2e56-4ac3-9113-7b17eb991580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502253821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2502253821
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2983635880
Short name T1071
Test name
Test status
Simulation time 185673954 ps
CPU time 3.22 seconds
Started Feb 18 12:29:01 PM PST 24
Finished Feb 18 12:29:10 PM PST 24
Peak memory 214832 kb
Host smart-c988f62c-e79b-44a6-aa15-50fee472e152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983635880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2983635880
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.99095073
Short name T212
Test name
Test status
Simulation time 405531971 ps
CPU time 6.43 seconds
Started Feb 18 12:28:58 PM PST 24
Finished Feb 18 12:29:10 PM PST 24
Peak memory 214620 kb
Host smart-d927d1f3-92a9-4a3d-bfa0-b7d83f11a45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99095073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_
tl_intg_err.99095073
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3474268559
Short name T1092
Test name
Test status
Simulation time 958194436 ps
CPU time 24.29 seconds
Started Feb 18 12:28:38 PM PST 24
Finished Feb 18 12:29:04 PM PST 24
Peak memory 214632 kb
Host smart-c4b2474c-49cb-4fdc-8504-c2ac7b30b529
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474268559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3474268559
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.695331101
Short name T1041
Test name
Test status
Simulation time 2235202483 ps
CPU time 34.9 seconds
Started Feb 18 12:28:49 PM PST 24
Finished Feb 18 12:29:26 PM PST 24
Peak memory 206480 kb
Host smart-93c1f35d-3608-448a-a788-e416e9c5e8a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695331101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.695331101
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.359514615
Short name T1082
Test name
Test status
Simulation time 49303375 ps
CPU time 1.43 seconds
Started Feb 18 12:28:35 PM PST 24
Finished Feb 18 12:28:39 PM PST 24
Peak memory 206288 kb
Host smart-c75b1e42-ce73-4ec3-a5e0-ca6ab83f8618
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359514615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.359514615
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3729752667
Short name T1069
Test name
Test status
Simulation time 151488297 ps
CPU time 5.5 seconds
Started Feb 18 12:28:42 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 219636 kb
Host smart-6f824fff-58ea-4d3d-949c-3de053f5ade6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729752667 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3729752667
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.560083722
Short name T1032
Test name
Test status
Simulation time 129995495 ps
CPU time 2.12 seconds
Started Feb 18 12:28:38 PM PST 24
Finished Feb 18 12:28:42 PM PST 24
Peak memory 214700 kb
Host smart-a6b84ae6-e5ca-43bb-bb8d-36f400764eab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560083722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.560083722
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.425048655
Short name T989
Test name
Test status
Simulation time 28698577 ps
CPU time 0.71 seconds
Started Feb 18 12:28:42 PM PST 24
Finished Feb 18 12:28:45 PM PST 24
Peak memory 202400 kb
Host smart-12d18b71-fe16-4dbb-a255-9c3fe5aefe21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425048655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.425048655
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1336287086
Short name T95
Test name
Test status
Simulation time 36571808 ps
CPU time 1.27 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:45 PM PST 24
Peak memory 214584 kb
Host smart-e31acd90-0fc4-42a4-8636-a9c52c498f02
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336287086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1336287086
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.468836760
Short name T1004
Test name
Test status
Simulation time 12726787 ps
CPU time 0.67 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:47 PM PST 24
Peak memory 202688 kb
Host smart-106b9f81-8766-426b-9f97-bb8f2cf26287
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468836760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.468836760
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3490125046
Short name T991
Test name
Test status
Simulation time 108491887 ps
CPU time 2.53 seconds
Started Feb 18 12:28:53 PM PST 24
Finished Feb 18 12:29:02 PM PST 24
Peak memory 206576 kb
Host smart-8557f945-2c43-4e0b-8241-c777dd74de61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490125046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3490125046
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3573880275
Short name T1023
Test name
Test status
Simulation time 138928824 ps
CPU time 2.61 seconds
Started Feb 18 12:28:38 PM PST 24
Finished Feb 18 12:28:43 PM PST 24
Peak memory 215960 kb
Host smart-b0fd23ee-c061-45ef-8865-db0e4d2114c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573880275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
573880275
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2616711646
Short name T1097
Test name
Test status
Simulation time 18087610 ps
CPU time 0.79 seconds
Started Feb 18 12:29:16 PM PST 24
Finished Feb 18 12:29:20 PM PST 24
Peak memory 202424 kb
Host smart-bc5f1ce5-c75b-4557-90ce-9f34703d596a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616711646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2616711646
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3108593286
Short name T1019
Test name
Test status
Simulation time 24092165 ps
CPU time 0.71 seconds
Started Feb 18 12:28:57 PM PST 24
Finished Feb 18 12:29:04 PM PST 24
Peak memory 202508 kb
Host smart-81886df5-da47-4700-a36c-85209a9962a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108593286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3108593286
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1289769881
Short name T1012
Test name
Test status
Simulation time 37020168 ps
CPU time 0.77 seconds
Started Feb 18 12:28:56 PM PST 24
Finished Feb 18 12:29:02 PM PST 24
Peak memory 202484 kb
Host smart-cca55693-f327-4fec-807c-1ebb0c5f49f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289769881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1289769881
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1622946229
Short name T1001
Test name
Test status
Simulation time 12330471 ps
CPU time 0.68 seconds
Started Feb 18 12:28:47 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 202384 kb
Host smart-7d7c4337-bcd1-41b9-bc5f-54120702a2e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622946229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1622946229
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1341541151
Short name T1038
Test name
Test status
Simulation time 27685108 ps
CPU time 0.74 seconds
Started Feb 18 12:28:46 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 202380 kb
Host smart-77a60983-e30e-471e-a357-d054b148a4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341541151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1341541151
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1683670066
Short name T1003
Test name
Test status
Simulation time 12449050 ps
CPU time 0.67 seconds
Started Feb 18 12:28:41 PM PST 24
Finished Feb 18 12:28:45 PM PST 24
Peak memory 202424 kb
Host smart-da84fb89-f9f5-4091-a011-d6644d829ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683670066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1683670066
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3500912683
Short name T997
Test name
Test status
Simulation time 34172025 ps
CPU time 0.73 seconds
Started Feb 18 12:28:52 PM PST 24
Finished Feb 18 12:28:56 PM PST 24
Peak memory 202484 kb
Host smart-5ac2f2d4-6815-4b66-b47e-822df0ad0469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500912683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3500912683
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.802594857
Short name T1098
Test name
Test status
Simulation time 46690002 ps
CPU time 0.78 seconds
Started Feb 18 12:28:56 PM PST 24
Finished Feb 18 12:29:02 PM PST 24
Peak memory 202804 kb
Host smart-b0eda492-de6f-43c7-90e7-9388f85e5e6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802594857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.802594857
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.444709556
Short name T1015
Test name
Test status
Simulation time 219215835 ps
CPU time 0.73 seconds
Started Feb 18 12:29:01 PM PST 24
Finished Feb 18 12:29:07 PM PST 24
Peak memory 202392 kb
Host smart-c70aefe9-d8a9-455c-8bec-4bd5dbb70848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444709556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.444709556
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1103232217
Short name T986
Test name
Test status
Simulation time 107344541 ps
CPU time 0.72 seconds
Started Feb 18 12:28:41 PM PST 24
Finished Feb 18 12:28:45 PM PST 24
Peak memory 202660 kb
Host smart-35903545-2fc7-44ce-8c23-b73ce4cd41be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103232217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1103232217
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2184767540
Short name T122
Test name
Test status
Simulation time 3340368910 ps
CPU time 18.38 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:29:02 PM PST 24
Peak memory 214744 kb
Host smart-2feb6426-7722-429f-ad0c-74b3f2fb9c36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184767540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2184767540
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2965658431
Short name T99
Test name
Test status
Simulation time 5041655871 ps
CPU time 35.96 seconds
Started Feb 18 12:28:52 PM PST 24
Finished Feb 18 12:29:31 PM PST 24
Peak memory 206564 kb
Host smart-9d712fe9-014f-4c5b-8453-d3123e6d79d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965658431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2965658431
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3500129231
Short name T103
Test name
Test status
Simulation time 80640161 ps
CPU time 1.45 seconds
Started Feb 18 12:28:57 PM PST 24
Finished Feb 18 12:29:05 PM PST 24
Peak memory 206512 kb
Host smart-9dc5f8ae-8d3a-4ee7-9364-58d70bb7f626
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500129231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3500129231
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4202191497
Short name T127
Test name
Test status
Simulation time 95121960 ps
CPU time 1.35 seconds
Started Feb 18 12:28:28 PM PST 24
Finished Feb 18 12:28:34 PM PST 24
Peak memory 206432 kb
Host smart-c7c7bce8-8508-41c2-b9cd-cd4d80507bdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202191497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
202191497
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1374144468
Short name T1033
Test name
Test status
Simulation time 42881868 ps
CPU time 0.73 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:39 PM PST 24
Peak memory 202384 kb
Host smart-7e068933-105d-4e11-b9fc-875c1720200e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374144468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
374144468
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.778989362
Short name T98
Test name
Test status
Simulation time 24726936 ps
CPU time 1.63 seconds
Started Feb 18 12:28:48 PM PST 24
Finished Feb 18 12:28:52 PM PST 24
Peak memory 214488 kb
Host smart-7b7c8c75-e4ec-4d4c-ac35-66e222bbb79d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778989362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.778989362
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1328193694
Short name T1010
Test name
Test status
Simulation time 10267364 ps
CPU time 0.66 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:44 PM PST 24
Peak memory 202372 kb
Host smart-840cd250-f7bf-4239-a203-bdbc841ce68f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328193694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1328193694
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4089742196
Short name T124
Test name
Test status
Simulation time 142473107 ps
CPU time 1.8 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:51 PM PST 24
Peak memory 206284 kb
Host smart-9b7ea335-96a8-4b86-8dd4-e4228af5a137
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089742196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4089742196
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.371642394
Short name T1060
Test name
Test status
Simulation time 52746190 ps
CPU time 3.64 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:46 PM PST 24
Peak memory 214940 kb
Host smart-b7323974-6dbc-4f20-a35d-79f6e65c81cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371642394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.371642394
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1766527501
Short name T214
Test name
Test status
Simulation time 206709319 ps
CPU time 12.78 seconds
Started Feb 18 12:28:47 PM PST 24
Finished Feb 18 12:29:02 PM PST 24
Peak memory 214684 kb
Host smart-0f396f48-cd0d-429b-8895-8545716e4c82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766527501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1766527501
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1341343864
Short name T993
Test name
Test status
Simulation time 24185852 ps
CPU time 0.72 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:39 PM PST 24
Peak memory 202564 kb
Host smart-43eececb-b92c-420b-b700-d3f505779a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341343864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1341343864
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.609319793
Short name T999
Test name
Test status
Simulation time 43370419 ps
CPU time 0.68 seconds
Started Feb 18 12:28:51 PM PST 24
Finished Feb 18 12:28:53 PM PST 24
Peak memory 202712 kb
Host smart-041e3d1f-3e66-4929-821a-9f39fe81e0b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609319793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.609319793
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1591963516
Short name T1002
Test name
Test status
Simulation time 48402831 ps
CPU time 0.75 seconds
Started Feb 18 12:29:11 PM PST 24
Finished Feb 18 12:29:13 PM PST 24
Peak memory 202420 kb
Host smart-efc1341b-9b8b-4e9d-85fc-cada1ab1f2dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591963516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1591963516
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3987262737
Short name T1059
Test name
Test status
Simulation time 17854720 ps
CPU time 0.75 seconds
Started Feb 18 12:28:53 PM PST 24
Finished Feb 18 12:28:57 PM PST 24
Peak memory 202384 kb
Host smart-ac456d34-4310-4820-a92c-ec175c5ec2f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987262737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3987262737
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1355214465
Short name T1072
Test name
Test status
Simulation time 12494914 ps
CPU time 0.69 seconds
Started Feb 18 12:28:51 PM PST 24
Finished Feb 18 12:29:01 PM PST 24
Peak memory 202380 kb
Host smart-31e6798b-1922-4d8a-8df2-39a2675c040a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355214465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1355214465
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3451149490
Short name T1083
Test name
Test status
Simulation time 20570917 ps
CPU time 0.77 seconds
Started Feb 18 12:28:51 PM PST 24
Finished Feb 18 12:28:53 PM PST 24
Peak memory 202400 kb
Host smart-e204a5a0-c4d3-4277-b9c8-3b871f73e7b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451149490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3451149490
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2768141727
Short name T1035
Test name
Test status
Simulation time 52729287 ps
CPU time 0.71 seconds
Started Feb 18 12:28:52 PM PST 24
Finished Feb 18 12:28:56 PM PST 24
Peak memory 202700 kb
Host smart-7e1508ca-19ee-4fd0-9fe6-43ee40809e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768141727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2768141727
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2349190514
Short name T1066
Test name
Test status
Simulation time 48987603 ps
CPU time 0.72 seconds
Started Feb 18 12:28:54 PM PST 24
Finished Feb 18 12:28:58 PM PST 24
Peak memory 202384 kb
Host smart-eb609b97-6de7-4a13-8194-c05f8018ab3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349190514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2349190514
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2857077958
Short name T1040
Test name
Test status
Simulation time 130777830 ps
CPU time 0.7 seconds
Started Feb 18 12:28:51 PM PST 24
Finished Feb 18 12:28:55 PM PST 24
Peak memory 202412 kb
Host smart-9d2635b1-ef07-4809-aa81-26015aa9f4cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857077958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2857077958
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.297408764
Short name T1009
Test name
Test status
Simulation time 71393631 ps
CPU time 0.71 seconds
Started Feb 18 12:28:53 PM PST 24
Finished Feb 18 12:28:57 PM PST 24
Peak memory 202400 kb
Host smart-a9564e96-9e6f-4d0c-8ce7-80fc9c7b04e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297408764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.297408764
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3657814079
Short name T94
Test name
Test status
Simulation time 3471778465 ps
CPU time 18.42 seconds
Started Feb 18 12:28:33 PM PST 24
Finished Feb 18 12:28:54 PM PST 24
Peak memory 206568 kb
Host smart-9d94f550-1556-4229-a97f-1ed8be9c8486
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657814079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3657814079
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.9777618
Short name T1011
Test name
Test status
Simulation time 195202209 ps
CPU time 12.16 seconds
Started Feb 18 12:28:47 PM PST 24
Finished Feb 18 12:29:02 PM PST 24
Peak memory 205984 kb
Host smart-be8a3a68-f354-40f4-ae72-90cefc51fdb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9777618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_b
it_bash.9777618
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2838373668
Short name T63
Test name
Test status
Simulation time 27889754 ps
CPU time 1.32 seconds
Started Feb 18 12:28:38 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 206456 kb
Host smart-34527479-a873-48f4-8bcb-39182fdf095a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838373668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2838373668
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1400338721
Short name T1061
Test name
Test status
Simulation time 161955320 ps
CPU time 1.47 seconds
Started Feb 18 12:28:52 PM PST 24
Finished Feb 18 12:28:57 PM PST 24
Peak memory 206456 kb
Host smart-9ffb3e9f-d94a-4868-b324-d170aa4e8878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400338721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
400338721
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.770825503
Short name T1074
Test name
Test status
Simulation time 17597139 ps
CPU time 0.72 seconds
Started Feb 18 12:28:38 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 202720 kb
Host smart-e0329ee5-433b-42ca-9d68-9c8ffd51b64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770825503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.770825503
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3811257808
Short name T100
Test name
Test status
Simulation time 87142494 ps
CPU time 1.61 seconds
Started Feb 18 12:28:44 PM PST 24
Finished Feb 18 12:28:49 PM PST 24
Peak memory 214676 kb
Host smart-08eb6c31-7959-4909-a241-d55df5a43785
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811257808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3811257808
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1647783759
Short name T995
Test name
Test status
Simulation time 29273342 ps
CPU time 0.68 seconds
Started Feb 18 12:28:49 PM PST 24
Finished Feb 18 12:28:52 PM PST 24
Peak memory 202360 kb
Host smart-490527f9-ed60-4bb3-8136-f94cc1f2fa04
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647783759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1647783759
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4069872974
Short name T1029
Test name
Test status
Simulation time 146935976 ps
CPU time 1.82 seconds
Started Feb 18 12:29:12 PM PST 24
Finished Feb 18 12:29:15 PM PST 24
Peak memory 214676 kb
Host smart-0e2fc182-fb2b-40d2-a222-17c74035b0b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069872974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4069872974
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2117686180
Short name T83
Test name
Test status
Simulation time 1368663072 ps
CPU time 3.03 seconds
Started Feb 18 12:28:49 PM PST 24
Finished Feb 18 12:28:54 PM PST 24
Peak memory 214872 kb
Host smart-3e413ae7-19d7-4a96-9b86-b3936f26d53d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117686180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
117686180
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1777361556
Short name T1022
Test name
Test status
Simulation time 104318353 ps
CPU time 6.73 seconds
Started Feb 18 12:28:50 PM PST 24
Finished Feb 18 12:28:59 PM PST 24
Peak memory 214664 kb
Host smart-4c67f254-f57b-4ccb-875c-313a09095505
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777361556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1777361556
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.533345390
Short name T1053
Test name
Test status
Simulation time 15366441 ps
CPU time 0.71 seconds
Started Feb 18 12:28:51 PM PST 24
Finished Feb 18 12:28:54 PM PST 24
Peak memory 202400 kb
Host smart-5757f5fe-872d-409f-931b-ee3e09ac840a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533345390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.533345390
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.576962113
Short name T987
Test name
Test status
Simulation time 11143041 ps
CPU time 0.73 seconds
Started Feb 18 12:29:01 PM PST 24
Finished Feb 18 12:29:07 PM PST 24
Peak memory 202716 kb
Host smart-d85e3bb4-cdfa-4990-86b9-cf20b4c3de0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576962113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.576962113
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2405762503
Short name T1084
Test name
Test status
Simulation time 55305243 ps
CPU time 0.74 seconds
Started Feb 18 12:28:53 PM PST 24
Finished Feb 18 12:28:58 PM PST 24
Peak memory 202388 kb
Host smart-fd2dd32a-d48f-4108-a094-f7b1a8fa3ac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405762503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2405762503
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2344003871
Short name T985
Test name
Test status
Simulation time 16615787 ps
CPU time 0.74 seconds
Started Feb 18 12:29:02 PM PST 24
Finished Feb 18 12:29:08 PM PST 24
Peak memory 202440 kb
Host smart-9de42d0e-3f86-41da-ab74-dd918d9b2234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344003871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2344003871
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.116451145
Short name T1055
Test name
Test status
Simulation time 18911143 ps
CPU time 0.73 seconds
Started Feb 18 12:29:00 PM PST 24
Finished Feb 18 12:29:06 PM PST 24
Peak memory 202400 kb
Host smart-8db20aca-ebc7-4a5d-821c-2d3d6a9abded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116451145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.116451145
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2195685535
Short name T1076
Test name
Test status
Simulation time 33747616 ps
CPU time 0.69 seconds
Started Feb 18 12:29:01 PM PST 24
Finished Feb 18 12:29:07 PM PST 24
Peak memory 202388 kb
Host smart-6ce20222-68d5-4788-8968-1cf2e338b260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195685535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2195685535
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1489017459
Short name T1027
Test name
Test status
Simulation time 16839372 ps
CPU time 0.72 seconds
Started Feb 18 12:29:00 PM PST 24
Finished Feb 18 12:29:06 PM PST 24
Peak memory 202696 kb
Host smart-cd4e9a02-db1f-489e-9da1-aa54f65e8247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489017459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1489017459
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.115385644
Short name T1048
Test name
Test status
Simulation time 81613873 ps
CPU time 0.72 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:39 PM PST 24
Peak memory 202416 kb
Host smart-2e643ab3-5ffb-45fc-a5db-de563053a2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115385644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.115385644
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2093584064
Short name T1008
Test name
Test status
Simulation time 13476579 ps
CPU time 0.78 seconds
Started Feb 18 12:28:47 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 202408 kb
Host smart-73c23019-6c06-4148-a266-b61bafc1e542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093584064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2093584064
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.968708163
Short name T1080
Test name
Test status
Simulation time 50291048 ps
CPU time 0.74 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:48 PM PST 24
Peak memory 202732 kb
Host smart-4be88d3f-a98b-47ba-b201-7a2ea2dbc4e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968708163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.968708163
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1665125052
Short name T75
Test name
Test status
Simulation time 209511662 ps
CPU time 2.91 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:47 PM PST 24
Peak memory 216492 kb
Host smart-18a1a71f-3bd9-494c-9abb-b24a8789d48c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665125052 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1665125052
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.248898112
Short name T1088
Test name
Test status
Simulation time 275061362 ps
CPU time 2 seconds
Started Feb 18 12:28:53 PM PST 24
Finished Feb 18 12:28:59 PM PST 24
Peak memory 206504 kb
Host smart-2aa59212-5e62-4aae-9317-24504d32e1b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248898112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.248898112
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1961800138
Short name T1090
Test name
Test status
Simulation time 39074864 ps
CPU time 0.7 seconds
Started Feb 18 12:28:44 PM PST 24
Finished Feb 18 12:28:48 PM PST 24
Peak memory 202740 kb
Host smart-8c6298d8-6c48-4c4f-8acf-6c08ddc145f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961800138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
961800138
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1208245052
Short name T996
Test name
Test status
Simulation time 245108465 ps
CPU time 3.56 seconds
Started Feb 18 12:28:49 PM PST 24
Finished Feb 18 12:28:55 PM PST 24
Peak memory 214688 kb
Host smart-1f91e52b-b03d-4d68-9d70-eeed0051d3ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208245052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1208245052
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2039144
Short name T1030
Test name
Test status
Simulation time 299387807 ps
CPU time 1.47 seconds
Started Feb 18 12:28:44 PM PST 24
Finished Feb 18 12:28:49 PM PST 24
Peak memory 215828 kb
Host smart-d5713304-5d76-4aa4-8203-3f25a9541bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2039144
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3292890144
Short name T126
Test name
Test status
Simulation time 368982327 ps
CPU time 7.71 seconds
Started Feb 18 12:28:42 PM PST 24
Finished Feb 18 12:28:52 PM PST 24
Peak memory 214644 kb
Host smart-28a284a0-0c60-4a24-8640-814b6e8e65e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292890144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3292890144
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4115940293
Short name T86
Test name
Test status
Simulation time 88937101 ps
CPU time 3.36 seconds
Started Feb 18 12:29:04 PM PST 24
Finished Feb 18 12:29:11 PM PST 24
Peak memory 218672 kb
Host smart-4cc2b90d-d710-4a68-9a82-ce51d97f9975
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115940293 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4115940293
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1807523894
Short name T1000
Test name
Test status
Simulation time 56661195 ps
CPU time 1.32 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:48 PM PST 24
Peak memory 206432 kb
Host smart-0d5dd96a-5bf3-4fbe-819a-4d4cf588277d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807523894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
807523894
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.314273776
Short name T1017
Test name
Test status
Simulation time 21736402 ps
CPU time 0.71 seconds
Started Feb 18 12:28:34 PM PST 24
Finished Feb 18 12:28:37 PM PST 24
Peak memory 202348 kb
Host smart-fbc88256-bff2-4228-92cc-ee497aa6d4f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314273776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.314273776
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2887145092
Short name T1043
Test name
Test status
Simulation time 656965454 ps
CPU time 1.96 seconds
Started Feb 18 12:28:48 PM PST 24
Finished Feb 18 12:28:52 PM PST 24
Peak memory 206456 kb
Host smart-2fa1ec4a-82b0-40bc-95c2-bd8259623697
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887145092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2887145092
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.767309795
Short name T207
Test name
Test status
Simulation time 41280397 ps
CPU time 2.86 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 214792 kb
Host smart-101ddc41-8215-4946-92e2-e2b2818762cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767309795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.767309795
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2879267430
Short name T77
Test name
Test status
Simulation time 889704857 ps
CPU time 19.81 seconds
Started Feb 18 12:28:54 PM PST 24
Finished Feb 18 12:29:19 PM PST 24
Peak memory 215108 kb
Host smart-25336cac-1182-47ea-a6a4-ee7e309b2952
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879267430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2879267430
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.70156389
Short name T1070
Test name
Test status
Simulation time 121295578 ps
CPU time 3.07 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 216404 kb
Host smart-c01b3f77-5743-4fe5-9506-20929fa8b29a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70156389 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.70156389
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3787130583
Short name T1039
Test name
Test status
Simulation time 94185352 ps
CPU time 1.95 seconds
Started Feb 18 12:28:42 PM PST 24
Finished Feb 18 12:28:47 PM PST 24
Peak memory 214652 kb
Host smart-780ab347-681d-4e79-a72f-202b5ed9c9c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787130583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
787130583
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2116537652
Short name T1007
Test name
Test status
Simulation time 57365059 ps
CPU time 0.76 seconds
Started Feb 18 12:28:45 PM PST 24
Finished Feb 18 12:28:49 PM PST 24
Peak memory 202408 kb
Host smart-6607cd3e-f5d4-43c3-9fc1-a6d31936277b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116537652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
116537652
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4279325866
Short name T125
Test name
Test status
Simulation time 84590969 ps
CPU time 2 seconds
Started Feb 18 12:28:48 PM PST 24
Finished Feb 18 12:28:52 PM PST 24
Peak memory 206220 kb
Host smart-ed783c08-f4e6-48e5-a599-41d23560d79f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279325866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4279325866
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3520982484
Short name T1099
Test name
Test status
Simulation time 1029211507 ps
CPU time 2.75 seconds
Started Feb 18 12:28:48 PM PST 24
Finished Feb 18 12:28:53 PM PST 24
Peak memory 214812 kb
Host smart-2a885f2e-1a51-45b5-8a7e-2b369d1bf556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520982484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
520982484
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.114798983
Short name T1085
Test name
Test status
Simulation time 1188880499 ps
CPU time 7.08 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 214676 kb
Host smart-309d9e35-e98f-44d7-b744-77037d3b845b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114798983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.114798983
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.784596259
Short name T1046
Test name
Test status
Simulation time 22477196 ps
CPU time 1.25 seconds
Started Feb 18 12:28:46 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 206424 kb
Host smart-b032c1a9-02d1-477d-a5d4-a24e244a6f13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784596259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.784596259
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3813115856
Short name T1013
Test name
Test status
Simulation time 45042202 ps
CPU time 0.73 seconds
Started Feb 18 12:28:50 PM PST 24
Finished Feb 18 12:28:53 PM PST 24
Peak memory 202720 kb
Host smart-325bb45e-883b-4919-a8c2-212f71470066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813115856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
813115856
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.445559198
Short name T994
Test name
Test status
Simulation time 758351236 ps
CPU time 4.28 seconds
Started Feb 18 12:28:46 PM PST 24
Finished Feb 18 12:28:53 PM PST 24
Peak memory 206208 kb
Host smart-1f49dbad-c630-49a8-8bd1-c3fd031e2431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445559198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.445559198
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2952041868
Short name T82
Test name
Test status
Simulation time 26457171 ps
CPU time 1.74 seconds
Started Feb 18 12:29:10 PM PST 24
Finished Feb 18 12:29:13 PM PST 24
Peak memory 214796 kb
Host smart-9e09d862-f8ee-47f6-b364-bcb119658831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952041868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
952041868
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1642825401
Short name T1067
Test name
Test status
Simulation time 604429208 ps
CPU time 18.84 seconds
Started Feb 18 12:28:49 PM PST 24
Finished Feb 18 12:29:10 PM PST 24
Peak memory 214684 kb
Host smart-a0c3f5e2-259c-405d-b1b5-cb6a70a29362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642825401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1642825401
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2008701692
Short name T121
Test name
Test status
Simulation time 77961340 ps
CPU time 1.91 seconds
Started Feb 18 12:28:45 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 214304 kb
Host smart-30725acc-7ad7-40a8-9709-6b1604628285
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008701692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
008701692
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.141349289
Short name T1037
Test name
Test status
Simulation time 28142923 ps
CPU time 0.72 seconds
Started Feb 18 12:28:49 PM PST 24
Finished Feb 18 12:28:52 PM PST 24
Peak memory 202720 kb
Host smart-a7841eca-db7e-4bf7-8d1e-43644a5ed25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141349289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.141349289
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3664852452
Short name T1051
Test name
Test status
Simulation time 2060654319 ps
CPU time 4.29 seconds
Started Feb 18 12:29:10 PM PST 24
Finished Feb 18 12:29:15 PM PST 24
Peak memory 206332 kb
Host smart-3f7d30e8-3d84-46dc-995e-fd2ce8b5fc6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664852452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3664852452
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.484640370
Short name T1018
Test name
Test status
Simulation time 163680686 ps
CPU time 4.77 seconds
Started Feb 18 12:28:54 PM PST 24
Finished Feb 18 12:29:02 PM PST 24
Peak memory 214768 kb
Host smart-c5cc74fd-62b4-47c2-abad-b9ceb70f7281
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484640370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.484640370
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1660587284
Short name T1024
Test name
Test status
Simulation time 112487489 ps
CPU time 6.55 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 214632 kb
Host smart-c1919184-a187-473c-96bc-3fb9debd7068
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660587284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1660587284
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3687742027
Short name T621
Test name
Test status
Simulation time 12606652 ps
CPU time 0.69 seconds
Started Feb 18 02:12:14 PM PST 24
Finished Feb 18 02:12:47 PM PST 24
Peak memory 204716 kb
Host smart-ee007f0f-818a-4014-9fb6-6382cfe0ea2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687742027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
687742027
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1593908811
Short name T561
Test name
Test status
Simulation time 23044478162 ps
CPU time 6.59 seconds
Started Feb 18 02:12:13 PM PST 24
Finished Feb 18 02:12:53 PM PST 24
Peak memory 233588 kb
Host smart-b676abc1-f258-474d-b947-767a25e5460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593908811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1593908811
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4194341248
Short name T616
Test name
Test status
Simulation time 18781913 ps
CPU time 0.85 seconds
Started Feb 18 02:12:08 PM PST 24
Finished Feb 18 02:12:43 PM PST 24
Peak memory 205836 kb
Host smart-6d45a0e8-4a89-476d-bc3b-64fe637f21b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194341248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4194341248
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3216525588
Short name T440
Test name
Test status
Simulation time 23874846401 ps
CPU time 70.03 seconds
Started Feb 18 02:12:14 PM PST 24
Finished Feb 18 02:13:57 PM PST 24
Peak memory 251232 kb
Host smart-b71ec197-04a7-434a-8737-ba2425f083c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216525588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3216525588
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.574945859
Short name T743
Test name
Test status
Simulation time 3309637661 ps
CPU time 41.3 seconds
Started Feb 18 02:12:15 PM PST 24
Finished Feb 18 02:13:30 PM PST 24
Peak memory 235776 kb
Host smart-72a1379f-add0-41c5-9f4d-d3f8ed1296be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574945859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.574945859
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1956466996
Short name T696
Test name
Test status
Simulation time 4716225130 ps
CPU time 34.87 seconds
Started Feb 18 02:12:22 PM PST 24
Finished Feb 18 02:13:31 PM PST 24
Peak memory 239216 kb
Host smart-7d5971e2-a2a3-4f65-859f-d5833d803e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956466996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1956466996
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1900210338
Short name T814
Test name
Test status
Simulation time 2986614150 ps
CPU time 10.16 seconds
Started Feb 18 02:12:22 PM PST 24
Finished Feb 18 02:13:08 PM PST 24
Peak memory 217900 kb
Host smart-b12efaa5-d4ea-46d7-836d-ab5f0e527771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900210338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1900210338
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2672965766
Short name T686
Test name
Test status
Simulation time 3165856888 ps
CPU time 5.78 seconds
Started Feb 18 02:12:20 PM PST 24
Finished Feb 18 02:13:00 PM PST 24
Peak memory 232836 kb
Host smart-e486cf2b-2a49-4a34-90b2-6685822ee6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672965766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2672965766
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2399027086
Short name T831
Test name
Test status
Simulation time 29838800 ps
CPU time 1.01 seconds
Started Feb 18 02:12:14 PM PST 24
Finished Feb 18 02:12:49 PM PST 24
Peak memory 217528 kb
Host smart-173147ee-c5ac-4714-93e9-c72e0f18af95
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399027086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2399027086
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4020937575
Short name T486
Test name
Test status
Simulation time 208885893 ps
CPU time 2.88 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:13:04 PM PST 24
Peak memory 233008 kb
Host smart-66d995c3-deee-499d-b49e-b010d1339156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020937575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4020937575
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1778913167
Short name T910
Test name
Test status
Simulation time 2179306236 ps
CPU time 7.36 seconds
Started Feb 18 02:12:22 PM PST 24
Finished Feb 18 02:13:05 PM PST 24
Peak memory 223660 kb
Host smart-6c0b4007-64ae-4f06-9c1a-0e72490ea557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778913167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1778913167
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2670981559
Short name T332
Test name
Test status
Simulation time 343481016 ps
CPU time 3.44 seconds
Started Feb 18 02:12:17 PM PST 24
Finished Feb 18 02:12:53 PM PST 24
Peak memory 221468 kb
Host smart-431a783d-2ebc-49b3-a54e-c6907e488d73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2670981559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2670981559
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.547668107
Short name T298
Test name
Test status
Simulation time 42206469916 ps
CPU time 173.17 seconds
Started Feb 18 02:12:22 PM PST 24
Finished Feb 18 02:15:49 PM PST 24
Peak memory 249160 kb
Host smart-b3eb40c2-ed73-409d-8049-3a459bfa9b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547668107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.547668107
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.710289707
Short name T892
Test name
Test status
Simulation time 17150033988 ps
CPU time 56.19 seconds
Started Feb 18 02:12:05 PM PST 24
Finished Feb 18 02:13:35 PM PST 24
Peak memory 216224 kb
Host smart-e63bcff9-4971-4ddc-8fb4-05545b19ab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710289707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.710289707
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2227693623
Short name T289
Test name
Test status
Simulation time 1210669820 ps
CPU time 3.26 seconds
Started Feb 18 02:12:09 PM PST 24
Finished Feb 18 02:12:46 PM PST 24
Peak memory 207852 kb
Host smart-109a4dee-5dc6-4d9b-850c-8111df523316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227693623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2227693623
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1736416358
Short name T870
Test name
Test status
Simulation time 2458152974 ps
CPU time 4.16 seconds
Started Feb 18 02:12:16 PM PST 24
Finished Feb 18 02:12:55 PM PST 24
Peak memory 216380 kb
Host smart-5ec12e0e-4040-449a-b2e0-ed4b9e01ab18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736416358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1736416358
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3042277463
Short name T928
Test name
Test status
Simulation time 61861092 ps
CPU time 0.92 seconds
Started Feb 18 02:12:16 PM PST 24
Finished Feb 18 02:12:52 PM PST 24
Peak memory 205432 kb
Host smart-c7c98d68-0410-4857-9322-7d9fa52d64e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042277463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3042277463
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2608299115
Short name T964
Test name
Test status
Simulation time 3739514329 ps
CPU time 8.94 seconds
Started Feb 18 02:12:16 PM PST 24
Finished Feb 18 02:13:00 PM PST 24
Peak memory 219340 kb
Host smart-f61b8859-0ff1-415a-b2c1-4f63697df2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608299115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2608299115
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.927338831
Short name T563
Test name
Test status
Simulation time 40136905 ps
CPU time 0.68 seconds
Started Feb 18 02:12:30 PM PST 24
Finished Feb 18 02:13:11 PM PST 24
Peak memory 204708 kb
Host smart-8656af1f-90bf-4a49-b2c5-974e4388a7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927338831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.927338831
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.35277109
Short name T4
Test name
Test status
Simulation time 4004957464 ps
CPU time 3.66 seconds
Started Feb 18 02:12:22 PM PST 24
Finished Feb 18 02:13:02 PM PST 24
Peak memory 218784 kb
Host smart-09aa8d78-b2de-480a-8415-93ffb55d8bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35277109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.35277109
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.313982639
Short name T435
Test name
Test status
Simulation time 12538899 ps
CPU time 0.75 seconds
Started Feb 18 02:12:24 PM PST 24
Finished Feb 18 02:13:00 PM PST 24
Peak memory 204736 kb
Host smart-25f06335-0ca3-4793-9fcb-0a4fcd7b86dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313982639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.313982639
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3682899999
Short name T642
Test name
Test status
Simulation time 30997448454 ps
CPU time 83.56 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:14:25 PM PST 24
Peak memory 257152 kb
Host smart-ca84ac61-5561-4b6e-8f7a-95ad7da46c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682899999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3682899999
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2209659027
Short name T220
Test name
Test status
Simulation time 104794994766 ps
CPU time 305.18 seconds
Started Feb 18 02:12:24 PM PST 24
Finished Feb 18 02:18:05 PM PST 24
Peak memory 255976 kb
Host smart-067f19ae-d6d1-42bd-9fd0-e27013ad25fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209659027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2209659027
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2869251664
Short name T819
Test name
Test status
Simulation time 172538274435 ps
CPU time 243.23 seconds
Started Feb 18 02:12:29 PM PST 24
Finished Feb 18 02:17:12 PM PST 24
Peak memory 251404 kb
Host smart-030c6b9f-7d88-4a84-9a17-a5e183ed4f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869251664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2869251664
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3957195562
Short name T774
Test name
Test status
Simulation time 560084633 ps
CPU time 6.93 seconds
Started Feb 18 02:12:20 PM PST 24
Finished Feb 18 02:13:01 PM PST 24
Peak memory 224144 kb
Host smart-17001c43-6900-4326-a7c6-3d8cac8fd507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957195562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3957195562
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3962881307
Short name T694
Test name
Test status
Simulation time 566098314 ps
CPU time 5.2 seconds
Started Feb 18 02:12:16 PM PST 24
Finished Feb 18 02:12:57 PM PST 24
Peak memory 233032 kb
Host smart-9bba64e9-df6f-4924-aaa2-53973b9055bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962881307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3962881307
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2837863723
Short name T929
Test name
Test status
Simulation time 63695733355 ps
CPU time 40.76 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:13:42 PM PST 24
Peak memory 240672 kb
Host smart-4b9c7a56-4806-46fd-95d9-5e6df4ee827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837863723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2837863723
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3406659118
Short name T617
Test name
Test status
Simulation time 64242406 ps
CPU time 1.08 seconds
Started Feb 18 02:12:16 PM PST 24
Finished Feb 18 02:12:50 PM PST 24
Peak memory 216312 kb
Host smart-b54fb32b-051d-4711-ae12-39476ae3651f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406659118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3406659118
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.410681822
Short name T668
Test name
Test status
Simulation time 138902185 ps
CPU time 2.41 seconds
Started Feb 18 02:12:22 PM PST 24
Finished Feb 18 02:12:59 PM PST 24
Peak memory 216124 kb
Host smart-66c9e1fb-608e-439a-8dbb-eb07d9027a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410681822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
410681822
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2561312370
Short name T915
Test name
Test status
Simulation time 21959435235 ps
CPU time 9 seconds
Started Feb 18 02:12:23 PM PST 24
Finished Feb 18 02:13:08 PM PST 24
Peak memory 217420 kb
Host smart-38f158d8-d875-4b16-ae31-8022cb61441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561312370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2561312370
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.79781466
Short name T480
Test name
Test status
Simulation time 18769795 ps
CPU time 0.75 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:13:02 PM PST 24
Peak memory 216012 kb
Host smart-eacfd581-c120-458a-9709-e6a65d0792dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79781466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.79781466
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.90891839
Short name T744
Test name
Test status
Simulation time 211690136 ps
CPU time 3.93 seconds
Started Feb 18 02:12:23 PM PST 24
Finished Feb 18 02:13:02 PM PST 24
Peak memory 222108 kb
Host smart-97720f55-942d-422b-b8dd-04b0c9709f47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=90891839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct
.90891839
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2536048112
Short name T52
Test name
Test status
Simulation time 110080298 ps
CPU time 1.17 seconds
Started Feb 18 02:12:28 PM PST 24
Finished Feb 18 02:13:08 PM PST 24
Peak memory 235304 kb
Host smart-aadce85f-b585-4836-b969-63f735b2dac3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536048112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2536048112
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.684731240
Short name T712
Test name
Test status
Simulation time 3392554067 ps
CPU time 26.95 seconds
Started Feb 18 02:12:13 PM PST 24
Finished Feb 18 02:13:14 PM PST 24
Peak memory 216220 kb
Host smart-0e249126-4643-44b2-a303-24e46e068f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684731240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.684731240
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.276930592
Short name T883
Test name
Test status
Simulation time 3671176045 ps
CPU time 16.62 seconds
Started Feb 18 02:12:23 PM PST 24
Finished Feb 18 02:13:15 PM PST 24
Peak memory 216184 kb
Host smart-e3234200-df87-4f67-bdc4-a40e3dc4db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276930592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.276930592
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3189880214
Short name T520
Test name
Test status
Simulation time 24626263 ps
CPU time 0.95 seconds
Started Feb 18 02:12:15 PM PST 24
Finished Feb 18 02:12:50 PM PST 24
Peak memory 206384 kb
Host smart-22d69dbc-ec9e-441c-a4e0-cb334196d5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189880214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3189880214
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2575347146
Short name T895
Test name
Test status
Simulation time 70017785 ps
CPU time 0.76 seconds
Started Feb 18 02:12:16 PM PST 24
Finished Feb 18 02:12:50 PM PST 24
Peak memory 205040 kb
Host smart-0a782ab7-f745-4159-8e52-7a740dbfec03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575347146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2575347146
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.6295919
Short name T248
Test name
Test status
Simulation time 14238947153 ps
CPU time 26.24 seconds
Started Feb 18 02:12:23 PM PST 24
Finished Feb 18 02:13:24 PM PST 24
Peak memory 250544 kb
Host smart-fba83a8a-cadb-4ea1-a43a-328e148b01b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6295919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.6295919
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1505913665
Short name T535
Test name
Test status
Simulation time 27750712 ps
CPU time 0.72 seconds
Started Feb 18 02:13:07 PM PST 24
Finished Feb 18 02:13:47 PM PST 24
Peak memory 204148 kb
Host smart-5b713796-070d-4bf6-9b36-654bf682f6be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505913665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1505913665
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2414468192
Short name T553
Test name
Test status
Simulation time 819296684 ps
CPU time 3.2 seconds
Started Feb 18 02:13:07 PM PST 24
Finished Feb 18 02:13:49 PM PST 24
Peak memory 233412 kb
Host smart-0d5556c3-6b56-436b-94fd-821a3f9d569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414468192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2414468192
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3774585976
Short name T750
Test name
Test status
Simulation time 17990484 ps
CPU time 0.78 seconds
Started Feb 18 02:13:01 PM PST 24
Finished Feb 18 02:13:41 PM PST 24
Peak memory 205168 kb
Host smart-44630e5a-5da8-4afb-9bda-13763ae150a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774585976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3774585976
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3390442664
Short name T110
Test name
Test status
Simulation time 132357156295 ps
CPU time 205.52 seconds
Started Feb 18 02:13:06 PM PST 24
Finished Feb 18 02:17:12 PM PST 24
Peak memory 249024 kb
Host smart-ae227b9b-aab3-4dd3-87c7-ed7b17aacd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390442664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3390442664
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2332853540
Short name T360
Test name
Test status
Simulation time 1683294547 ps
CPU time 5.86 seconds
Started Feb 18 02:12:59 PM PST 24
Finished Feb 18 02:13:44 PM PST 24
Peak memory 217076 kb
Host smart-0c2a0d67-95c4-496e-8f07-fcf26bf444e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332853540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2332853540
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3433435600
Short name T420
Test name
Test status
Simulation time 80927789658 ps
CPU time 31.86 seconds
Started Feb 18 02:13:11 PM PST 24
Finished Feb 18 02:14:20 PM PST 24
Peak memory 247204 kb
Host smart-c4c42bb4-14d5-4eed-a544-4afc19ab9ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433435600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3433435600
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.888447189
Short name T153
Test name
Test status
Simulation time 746146434 ps
CPU time 2.9 seconds
Started Feb 18 02:13:11 PM PST 24
Finished Feb 18 02:13:51 PM PST 24
Peak memory 217520 kb
Host smart-bcdb5236-c9bc-4187-bb8f-d1bc531b4ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888447189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.888447189
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2608479745
Short name T140
Test name
Test status
Simulation time 3653822018 ps
CPU time 9.51 seconds
Started Feb 18 02:13:02 PM PST 24
Finished Feb 18 02:13:50 PM PST 24
Peak memory 233136 kb
Host smart-a151a547-4df9-4b08-9e26-0df1421d88a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608479745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2608479745
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.503369240
Short name T442
Test name
Test status
Simulation time 47804449 ps
CPU time 0.73 seconds
Started Feb 18 02:13:05 PM PST 24
Finished Feb 18 02:13:45 PM PST 24
Peak memory 215944 kb
Host smart-a77be99a-b145-4d6e-b4c1-ab3c45eb4db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503369240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.503369240
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3703442959
Short name T909
Test name
Test status
Simulation time 814194451 ps
CPU time 4 seconds
Started Feb 18 02:13:11 PM PST 24
Finished Feb 18 02:13:52 PM PST 24
Peak memory 222068 kb
Host smart-478de7cc-1cb8-4e1c-aae3-8367dbcc89e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3703442959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3703442959
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1302720595
Short name T343
Test name
Test status
Simulation time 56153107 ps
CPU time 0.99 seconds
Started Feb 18 02:13:05 PM PST 24
Finished Feb 18 02:13:46 PM PST 24
Peak memory 206084 kb
Host smart-97f32808-a972-4bd8-b500-b8f8da9aade6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302720595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1302720595
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3297596645
Short name T742
Test name
Test status
Simulation time 35555429308 ps
CPU time 91.99 seconds
Started Feb 18 02:13:02 PM PST 24
Finished Feb 18 02:15:39 PM PST 24
Peak memory 216376 kb
Host smart-d100c565-e88f-49be-a806-4eaf15fe80d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297596645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3297596645
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4235357763
Short name T690
Test name
Test status
Simulation time 477812602 ps
CPU time 1.64 seconds
Started Feb 18 02:13:06 PM PST 24
Finished Feb 18 02:13:46 PM PST 24
Peak memory 206396 kb
Host smart-4ca74551-0408-459b-94a9-5787bd0bf5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235357763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4235357763
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2578459643
Short name T591
Test name
Test status
Simulation time 153547130 ps
CPU time 2.5 seconds
Started Feb 18 02:13:07 PM PST 24
Finished Feb 18 02:13:50 PM PST 24
Peak memory 216336 kb
Host smart-023699c1-0142-420a-a07c-6c99d926d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578459643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2578459643
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2852256837
Short name T472
Test name
Test status
Simulation time 160275520 ps
CPU time 0.89 seconds
Started Feb 18 02:13:11 PM PST 24
Finished Feb 18 02:13:49 PM PST 24
Peak memory 204920 kb
Host smart-a625070a-b2ed-4f2a-a9ca-33cc6bcee693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852256837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2852256837
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1667855247
Short name T850
Test name
Test status
Simulation time 9991159002 ps
CPU time 29.78 seconds
Started Feb 18 02:13:09 PM PST 24
Finished Feb 18 02:14:25 PM PST 24
Peak memory 237088 kb
Host smart-216d46dc-268a-4aae-8fac-4fbf1264da9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667855247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1667855247
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3203860103
Short name T942
Test name
Test status
Simulation time 22085796 ps
CPU time 0.68 seconds
Started Feb 18 02:13:10 PM PST 24
Finished Feb 18 02:13:50 PM PST 24
Peak memory 204148 kb
Host smart-8773a4d8-78cb-42f4-b631-7a9c4d999f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203860103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3203860103
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2600675135
Short name T521
Test name
Test status
Simulation time 7414833655 ps
CPU time 6.7 seconds
Started Feb 18 02:13:12 PM PST 24
Finished Feb 18 02:14:19 PM PST 24
Peak memory 224360 kb
Host smart-ddfe0a2c-c06b-482a-9221-7e12c83e4200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600675135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2600675135
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1765917731
Short name T2
Test name
Test status
Simulation time 15113243 ps
CPU time 0.74 seconds
Started Feb 18 02:13:07 PM PST 24
Finished Feb 18 02:13:55 PM PST 24
Peak memory 204792 kb
Host smart-02885582-c85b-4db3-a85e-5eed02d9e099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765917731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1765917731
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1248067313
Short name T736
Test name
Test status
Simulation time 2771361865 ps
CPU time 54.41 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:58 PM PST 24
Peak memory 253060 kb
Host smart-7e0d9363-bea2-4189-89aa-710c84ab772a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248067313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1248067313
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3921512352
Short name T177
Test name
Test status
Simulation time 102839227967 ps
CPU time 778.38 seconds
Started Feb 18 02:13:05 PM PST 24
Finished Feb 18 02:26:49 PM PST 24
Peak memory 260680 kb
Host smart-df050477-b931-4bbd-b3fb-9688eabea12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921512352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3921512352
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1701279780
Short name T411
Test name
Test status
Simulation time 3331182721 ps
CPU time 59.39 seconds
Started Feb 18 02:13:07 PM PST 24
Finished Feb 18 02:14:46 PM PST 24
Peak memory 254748 kb
Host smart-c1f0c34d-d189-4b3e-87e5-e77b2f4376b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701279780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1701279780
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2943237654
Short name T755
Test name
Test status
Simulation time 898639705 ps
CPU time 12.5 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:17 PM PST 24
Peak memory 236064 kb
Host smart-0ec9549f-670c-4cf8-9154-f28858bfc866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943237654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2943237654
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2293153776
Short name T667
Test name
Test status
Simulation time 12616639320 ps
CPU time 11.65 seconds
Started Feb 18 02:13:11 PM PST 24
Finished Feb 18 02:14:01 PM PST 24
Peak memory 224308 kb
Host smart-78afb27e-31da-4e31-b945-0654b9be318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293153776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2293153776
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3138446912
Short name T405
Test name
Test status
Simulation time 14649674681 ps
CPU time 28.69 seconds
Started Feb 18 02:13:08 PM PST 24
Finished Feb 18 02:14:14 PM PST 24
Peak memory 240688 kb
Host smart-662c560d-e6e9-4db3-a648-2f0a2575d87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138446912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3138446912
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2102259610
Short name T781
Test name
Test status
Simulation time 54720521 ps
CPU time 1.02 seconds
Started Feb 18 02:13:02 PM PST 24
Finished Feb 18 02:13:42 PM PST 24
Peak memory 216228 kb
Host smart-e3f92699-2c1e-4bea-92d7-510cc4b84dcd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102259610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2102259610
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3029252958
Short name T334
Test name
Test status
Simulation time 327587506 ps
CPU time 3.38 seconds
Started Feb 18 02:13:12 PM PST 24
Finished Feb 18 02:14:06 PM PST 24
Peak memory 232476 kb
Host smart-92b4497b-4c8b-4903-8b8f-b0b7d98819a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029252958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3029252958
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.722151636
Short name T705
Test name
Test status
Simulation time 55701222 ps
CPU time 2.34 seconds
Started Feb 18 02:13:06 PM PST 24
Finished Feb 18 02:13:47 PM PST 24
Peak memory 216108 kb
Host smart-e2242b83-4b34-449e-ad1c-9fd61dd3883c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722151636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.722151636
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3250155365
Short name T983
Test name
Test status
Simulation time 34055492 ps
CPU time 0.69 seconds
Started Feb 18 02:13:01 PM PST 24
Finished Feb 18 02:13:40 PM PST 24
Peak memory 215936 kb
Host smart-595906a2-d7ff-4b31-8d0d-5f10c106e3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250155365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3250155365
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.505646273
Short name T522
Test name
Test status
Simulation time 194317627 ps
CPU time 3.66 seconds
Started Feb 18 02:13:18 PM PST 24
Finished Feb 18 02:14:01 PM PST 24
Peak memory 219628 kb
Host smart-8d2d24e8-4eaf-43db-a519-19435658446b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=505646273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.505646273
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1588728873
Short name T654
Test name
Test status
Simulation time 5077220175 ps
CPU time 68.97 seconds
Started Feb 18 02:13:08 PM PST 24
Finished Feb 18 02:14:55 PM PST 24
Peak memory 216164 kb
Host smart-9ec64010-91de-4c84-8859-7d4bd5f1a483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588728873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1588728873
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1919909995
Short name T386
Test name
Test status
Simulation time 5622848193 ps
CPU time 14.81 seconds
Started Feb 18 02:13:07 PM PST 24
Finished Feb 18 02:14:01 PM PST 24
Peak memory 216124 kb
Host smart-2908bd31-6de5-487f-9010-36658c93dd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919909995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1919909995
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1437795349
Short name T372
Test name
Test status
Simulation time 48879345 ps
CPU time 1.3 seconds
Started Feb 18 02:12:59 PM PST 24
Finished Feb 18 02:13:41 PM PST 24
Peak memory 216084 kb
Host smart-6f878a6f-2c5c-477e-8f26-606c614d043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437795349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1437795349
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1095861321
Short name T704
Test name
Test status
Simulation time 308277977 ps
CPU time 0.95 seconds
Started Feb 18 02:13:07 PM PST 24
Finished Feb 18 02:13:53 PM PST 24
Peak memory 205080 kb
Host smart-d53f2eb1-66a6-475c-8359-458708a8fb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095861321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1095861321
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.75241581
Short name T337
Test name
Test status
Simulation time 573064905 ps
CPU time 4.85 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:08 PM PST 24
Peak memory 216052 kb
Host smart-22794e73-c7b2-4ca2-bc82-98f1835619d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75241581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.75241581
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1129556852
Short name T446
Test name
Test status
Simulation time 61007321 ps
CPU time 0.7 seconds
Started Feb 18 02:13:14 PM PST 24
Finished Feb 18 02:14:01 PM PST 24
Peak memory 205052 kb
Host smart-73e61bb5-2950-4126-9e9f-c454a7c928e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129556852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1129556852
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1482912319
Short name T38
Test name
Test status
Simulation time 1946428510 ps
CPU time 6.61 seconds
Started Feb 18 02:13:15 PM PST 24
Finished Feb 18 02:14:00 PM PST 24
Peak memory 234104 kb
Host smart-4b5880f5-c3d5-46df-9888-8502ea5472d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482912319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1482912319
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2438357517
Short name T547
Test name
Test status
Simulation time 17065450 ps
CPU time 0.76 seconds
Started Feb 18 02:13:22 PM PST 24
Finished Feb 18 02:14:04 PM PST 24
Peak memory 206208 kb
Host smart-dd43398b-d201-4d67-be14-af707322c449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438357517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2438357517
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2020525834
Short name T923
Test name
Test status
Simulation time 34508075694 ps
CPU time 203.6 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:17:28 PM PST 24
Peak memory 256168 kb
Host smart-0a4659c3-91f5-462f-8b06-785c82592c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020525834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2020525834
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2824112212
Short name T195
Test name
Test status
Simulation time 151798719456 ps
CPU time 508.35 seconds
Started Feb 18 02:13:17 PM PST 24
Finished Feb 18 02:22:31 PM PST 24
Peak memory 269260 kb
Host smart-f0b60f3f-521f-4bfd-8c25-dcdf29b01506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824112212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2824112212
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4218618755
Short name T709
Test name
Test status
Simulation time 5413123837 ps
CPU time 27.11 seconds
Started Feb 18 02:13:14 PM PST 24
Finished Feb 18 02:14:22 PM PST 24
Peak memory 240584 kb
Host smart-5f28473e-c67b-47e7-a584-0e3d00e249dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218618755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4218618755
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2015788034
Short name T601
Test name
Test status
Simulation time 1529510286 ps
CPU time 4.31 seconds
Started Feb 18 02:13:12 PM PST 24
Finished Feb 18 02:14:05 PM PST 24
Peak memory 216932 kb
Host smart-bd749659-9a77-46cf-8f81-5ab1795c97a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015788034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2015788034
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.856175343
Short name T733
Test name
Test status
Simulation time 1683962570 ps
CPU time 10.92 seconds
Started Feb 18 02:13:11 PM PST 24
Finished Feb 18 02:14:02 PM PST 24
Peak memory 232392 kb
Host smart-8e14f0a0-006c-4cdc-a5af-09deb187bd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856175343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.856175343
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1385040984
Short name T979
Test name
Test status
Simulation time 25697648 ps
CPU time 1.12 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:05 PM PST 24
Peak memory 216264 kb
Host smart-ba140015-0f6e-44fb-8acb-a3e779f6199d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385040984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1385040984
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1359400519
Short name T760
Test name
Test status
Simulation time 161788691 ps
CPU time 2.77 seconds
Started Feb 18 02:13:18 PM PST 24
Finished Feb 18 02:14:01 PM PST 24
Peak memory 233088 kb
Host smart-3df022c0-222c-41ab-b186-6e33ce83e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359400519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1359400519
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.796597794
Short name T562
Test name
Test status
Simulation time 2344932730 ps
CPU time 9.36 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:14 PM PST 24
Peak memory 233020 kb
Host smart-51c67e1b-a1c0-4823-9d35-1493804be2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796597794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.796597794
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3574261294
Short name T59
Test name
Test status
Simulation time 18109373 ps
CPU time 0.76 seconds
Started Feb 18 02:13:07 PM PST 24
Finished Feb 18 02:13:52 PM PST 24
Peak memory 216008 kb
Host smart-4bf211ef-d96a-46bc-a65b-058b3658c91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574261294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3574261294
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4055342758
Short name T345
Test name
Test status
Simulation time 9621017034 ps
CPU time 5.53 seconds
Started Feb 18 02:13:14 PM PST 24
Finished Feb 18 02:13:57 PM PST 24
Peak memory 222340 kb
Host smart-b30b1488-5d29-4073-9f82-d6de6bb9c9a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4055342758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4055342758
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.800915229
Short name T255
Test name
Test status
Simulation time 7060886962 ps
CPU time 57.41 seconds
Started Feb 18 02:13:19 PM PST 24
Finished Feb 18 02:14:54 PM PST 24
Peak memory 236852 kb
Host smart-57c24597-3242-4144-b046-04b63185b4de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800915229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.800915229
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3228518949
Short name T851
Test name
Test status
Simulation time 16451699659 ps
CPU time 69.21 seconds
Started Feb 18 02:13:12 PM PST 24
Finished Feb 18 02:15:12 PM PST 24
Peak memory 216160 kb
Host smart-b67f0184-748f-4753-ab55-a1686b424f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228518949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3228518949
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2801114460
Short name T431
Test name
Test status
Simulation time 1245543858 ps
CPU time 7.39 seconds
Started Feb 18 02:13:12 PM PST 24
Finished Feb 18 02:14:00 PM PST 24
Peak memory 207884 kb
Host smart-5882eb71-3713-4e26-9f6b-035b0be82441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801114460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2801114460
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2887221015
Short name T579
Test name
Test status
Simulation time 665337215 ps
CPU time 1.43 seconds
Started Feb 18 02:13:08 PM PST 24
Finished Feb 18 02:13:49 PM PST 24
Peak memory 216028 kb
Host smart-0c38de15-5504-48ca-ac71-d48f37774c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887221015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2887221015
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2069335685
Short name T548
Test name
Test status
Simulation time 39380615 ps
CPU time 0.88 seconds
Started Feb 18 02:13:17 PM PST 24
Finished Feb 18 02:13:58 PM PST 24
Peak memory 205424 kb
Host smart-0e6e9d60-0515-4f41-bb9a-a220b9ffc7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069335685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2069335685
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.694181774
Short name T802
Test name
Test status
Simulation time 1403978856 ps
CPU time 11.2 seconds
Started Feb 18 02:13:28 PM PST 24
Finished Feb 18 02:14:20 PM PST 24
Peak memory 240288 kb
Host smart-590110e7-8c7d-4405-9504-ea5ac507e9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694181774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.694181774
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3932224443
Short name T558
Test name
Test status
Simulation time 16810508 ps
CPU time 0.76 seconds
Started Feb 18 02:13:16 PM PST 24
Finished Feb 18 02:13:58 PM PST 24
Peak memory 204708 kb
Host smart-d193c46c-c57f-49f2-a72d-fb66daae6269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932224443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3932224443
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1177719301
Short name T566
Test name
Test status
Simulation time 1672030538 ps
CPU time 4.97 seconds
Started Feb 18 02:13:18 PM PST 24
Finished Feb 18 02:14:02 PM PST 24
Peak memory 233028 kb
Host smart-da2f794a-b0f0-49b6-82bd-481207445ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177719301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1177719301
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4003572522
Short name T42
Test name
Test status
Simulation time 21145220 ps
CPU time 0.79 seconds
Started Feb 18 02:13:14 PM PST 24
Finished Feb 18 02:14:06 PM PST 24
Peak memory 206192 kb
Host smart-7193a05f-4691-43a2-bf97-f646bb465e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003572522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4003572522
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2826079256
Short name T378
Test name
Test status
Simulation time 16707885804 ps
CPU time 83.42 seconds
Started Feb 18 02:13:16 PM PST 24
Finished Feb 18 02:15:16 PM PST 24
Peak memory 236912 kb
Host smart-ed4d0509-f705-491b-913f-bed1c788a325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826079256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2826079256
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.519132014
Short name T366
Test name
Test status
Simulation time 26289797889 ps
CPU time 183.31 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:17:17 PM PST 24
Peak memory 249036 kb
Host smart-4e0e9e93-70f6-4858-9974-593547f25b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519132014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.519132014
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3872931823
Short name T432
Test name
Test status
Simulation time 3293517702 ps
CPU time 58.06 seconds
Started Feb 18 02:13:16 PM PST 24
Finished Feb 18 02:14:52 PM PST 24
Peak memory 249072 kb
Host smart-ec7903bd-8a5d-4f41-af37-2cc4437c27c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872931823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3872931823
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1057623826
Short name T227
Test name
Test status
Simulation time 6114727458 ps
CPU time 23.07 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:27 PM PST 24
Peak memory 224292 kb
Host smart-01678471-b4ec-41e6-be07-391f5e720b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057623826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1057623826
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2832193563
Short name T751
Test name
Test status
Simulation time 227734320 ps
CPU time 3.01 seconds
Started Feb 18 02:13:44 PM PST 24
Finished Feb 18 02:14:28 PM PST 24
Peak memory 217168 kb
Host smart-3d20ef99-c264-41e9-be4f-334501ca89f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832193563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2832193563
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3140704360
Short name T507
Test name
Test status
Simulation time 8534914164 ps
CPU time 27.25 seconds
Started Feb 18 02:13:16 PM PST 24
Finished Feb 18 02:14:20 PM PST 24
Peak memory 233612 kb
Host smart-e00b4d55-e147-47b1-9e3a-bbddd2c75516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140704360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3140704360
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2951328544
Short name T658
Test name
Test status
Simulation time 45408729 ps
CPU time 1.02 seconds
Started Feb 18 02:13:28 PM PST 24
Finished Feb 18 02:14:09 PM PST 24
Peak memory 217528 kb
Host smart-fa530717-05dd-41ea-b334-88513a68fd19
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951328544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2951328544
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2300933594
Short name T165
Test name
Test status
Simulation time 1127509896 ps
CPU time 11.03 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:21 PM PST 24
Peak memory 231220 kb
Host smart-4fdc4ec7-1b40-443c-8926-6a84610e5275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300933594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2300933594
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2759130951
Short name T778
Test name
Test status
Simulation time 4552512371 ps
CPU time 15.64 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:21 PM PST 24
Peak memory 228552 kb
Host smart-8e6ab69d-fe68-4c60-b022-b3c5a1fdcc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759130951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2759130951
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1378630446
Short name T735
Test name
Test status
Simulation time 44323731 ps
CPU time 0.73 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:05 PM PST 24
Peak memory 216000 kb
Host smart-116d8b24-035c-4352-8041-5fb662752f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378630446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1378630446
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1499671445
Short name T806
Test name
Test status
Simulation time 947448527 ps
CPU time 4.21 seconds
Started Feb 18 02:13:19 PM PST 24
Finished Feb 18 02:14:01 PM PST 24
Peak memory 222432 kb
Host smart-e4297336-264d-48ff-bece-7b80f099c4b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1499671445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1499671445
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.496638567
Short name T152
Test name
Test status
Simulation time 47825660063 ps
CPU time 369.08 seconds
Started Feb 18 02:13:23 PM PST 24
Finished Feb 18 02:20:10 PM PST 24
Peak memory 257212 kb
Host smart-fcfbf61e-a588-4b10-91f8-c9b0b86270c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496638567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.496638567
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3720248440
Short name T939
Test name
Test status
Simulation time 19122499796 ps
CPU time 41.16 seconds
Started Feb 18 02:13:23 PM PST 24
Finished Feb 18 02:14:44 PM PST 24
Peak memory 216220 kb
Host smart-32363765-4391-42f6-9c86-dcae4deced88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720248440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3720248440
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.369242953
Short name T813
Test name
Test status
Simulation time 5044857848 ps
CPU time 4.1 seconds
Started Feb 18 02:13:18 PM PST 24
Finished Feb 18 02:14:01 PM PST 24
Peak memory 216200 kb
Host smart-c7162fff-b4c2-41a8-9604-55af5f2c3181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369242953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.369242953
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1772261542
Short name T655
Test name
Test status
Simulation time 328219450 ps
CPU time 13.31 seconds
Started Feb 18 02:13:21 PM PST 24
Finished Feb 18 02:14:16 PM PST 24
Peak memory 208312 kb
Host smart-bf6578f2-8eb7-4209-adf5-11b951942d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772261542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1772261542
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.484059966
Short name T752
Test name
Test status
Simulation time 72864764 ps
CPU time 0.78 seconds
Started Feb 18 02:13:23 PM PST 24
Finished Feb 18 02:14:01 PM PST 24
Peak memory 204996 kb
Host smart-95478abe-7b41-4b82-a30f-a4c5c2be55cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484059966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.484059966
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2266384028
Short name T379
Test name
Test status
Simulation time 2551625951 ps
CPU time 13.9 seconds
Started Feb 18 02:13:17 PM PST 24
Finished Feb 18 02:14:16 PM PST 24
Peak memory 236264 kb
Host smart-f0913748-6c0d-45fd-a854-101b1ecec5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266384028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2266384028
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3487059691
Short name T875
Test name
Test status
Simulation time 15090670 ps
CPU time 0.73 seconds
Started Feb 18 02:14:24 PM PST 24
Finished Feb 18 02:15:18 PM PST 24
Peak memory 204700 kb
Host smart-9a8d8f1c-9277-4df9-8f8c-ac4cc13e1cfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487059691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3487059691
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3424182308
Short name T864
Test name
Test status
Simulation time 1663277233 ps
CPU time 4.53 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:10 PM PST 24
Peak memory 217488 kb
Host smart-edb73d2d-028c-471f-b0cd-9ab0c1cf84c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424182308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3424182308
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.843337843
Short name T764
Test name
Test status
Simulation time 45324464 ps
CPU time 0.78 seconds
Started Feb 18 02:13:20 PM PST 24
Finished Feb 18 02:14:01 PM PST 24
Peak memory 205836 kb
Host smart-8c133ecb-4c0d-4168-a722-fe9bee097705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843337843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.843337843
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1116432774
Short name T28
Test name
Test status
Simulation time 12390728912 ps
CPU time 72.15 seconds
Started Feb 18 02:13:27 PM PST 24
Finished Feb 18 02:15:21 PM PST 24
Peak memory 249964 kb
Host smart-90b54b07-4050-48db-bdc3-ab0e290f8458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116432774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1116432774
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2010111199
Short name T106
Test name
Test status
Simulation time 100566777077 ps
CPU time 174.91 seconds
Started Feb 18 02:13:23 PM PST 24
Finished Feb 18 02:16:58 PM PST 24
Peak memory 256636 kb
Host smart-b0d9c02c-28eb-45b2-8b04-1acb323ec6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010111199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2010111199
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2436697537
Short name T41
Test name
Test status
Simulation time 1148405652 ps
CPU time 13.01 seconds
Started Feb 18 02:13:25 PM PST 24
Finished Feb 18 02:14:26 PM PST 24
Peak memory 238472 kb
Host smart-44677a5d-c4e6-45f0-82aa-419062064511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436697537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2436697537
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.272757855
Short name T162
Test name
Test status
Simulation time 228144198 ps
CPU time 3.1 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:14:41 PM PST 24
Peak memory 233280 kb
Host smart-285ae794-c816-42dc-9eee-a83da61eac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272757855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.272757855
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2553261844
Short name T466
Test name
Test status
Simulation time 905590715 ps
CPU time 4.93 seconds
Started Feb 18 02:13:30 PM PST 24
Finished Feb 18 02:14:17 PM PST 24
Peak memory 233396 kb
Host smart-33f974c9-a2f7-4abc-9320-24f54a9fc63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553261844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2553261844
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2243215414
Short name T692
Test name
Test status
Simulation time 47715545 ps
CPU time 1.01 seconds
Started Feb 18 02:13:23 PM PST 24
Finished Feb 18 02:14:03 PM PST 24
Peak memory 216316 kb
Host smart-90deecdc-9ec1-4d39-808c-5978cb59e3ce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243215414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2243215414
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.251192858
Short name T782
Test name
Test status
Simulation time 7731427452 ps
CPU time 22.21 seconds
Started Feb 18 02:13:26 PM PST 24
Finished Feb 18 02:14:28 PM PST 24
Peak memory 239380 kb
Host smart-ffb391f7-8f7b-4cfa-9c40-3be01a1416cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251192858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.251192858
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2540385617
Short name T848
Test name
Test status
Simulation time 3187804393 ps
CPU time 5.96 seconds
Started Feb 18 02:13:40 PM PST 24
Finished Feb 18 02:14:30 PM PST 24
Peak memory 227632 kb
Host smart-82cb9be7-e1ce-4104-b986-bfa0cd11aa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540385617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2540385617
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1593044031
Short name T702
Test name
Test status
Simulation time 43113448 ps
CPU time 0.72 seconds
Started Feb 18 02:14:26 PM PST 24
Finished Feb 18 02:15:20 PM PST 24
Peak memory 215984 kb
Host smart-cfc5f7c3-ff9f-4e5d-b260-5a8fa181e61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593044031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1593044031
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3600688996
Short name T341
Test name
Test status
Simulation time 2320012694 ps
CPU time 5.76 seconds
Started Feb 18 02:13:38 PM PST 24
Finished Feb 18 02:14:22 PM PST 24
Peak memory 218628 kb
Host smart-5cded702-cbce-4a2b-b787-ab103359738a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3600688996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3600688996
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1437413485
Short name T637
Test name
Test status
Simulation time 27293755227 ps
CPU time 119.66 seconds
Started Feb 18 02:13:25 PM PST 24
Finished Feb 18 02:16:05 PM PST 24
Peak memory 254548 kb
Host smart-25d2fee2-e986-4f45-8878-d182512295f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437413485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1437413485
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2804819220
Short name T749
Test name
Test status
Simulation time 585400837 ps
CPU time 8.48 seconds
Started Feb 18 02:13:26 PM PST 24
Finished Feb 18 02:14:26 PM PST 24
Peak memory 216076 kb
Host smart-25a1ce73-6575-43e5-9cc9-f21e200c33a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804819220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2804819220
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3900677609
Short name T266
Test name
Test status
Simulation time 1273744946 ps
CPU time 8.51 seconds
Started Feb 18 02:13:25 PM PST 24
Finished Feb 18 02:14:14 PM PST 24
Peak memory 207636 kb
Host smart-6a2d0af9-c36a-4687-aa4e-d502c73c2b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900677609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3900677609
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1435327570
Short name T857
Test name
Test status
Simulation time 506938095 ps
CPU time 2.46 seconds
Started Feb 18 02:13:23 PM PST 24
Finished Feb 18 02:14:07 PM PST 24
Peak memory 216052 kb
Host smart-e81b13e0-4400-4cc5-aec2-a6f45de816c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435327570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1435327570
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3540639086
Short name T416
Test name
Test status
Simulation time 27406337 ps
CPU time 0.83 seconds
Started Feb 18 02:13:28 PM PST 24
Finished Feb 18 02:14:09 PM PST 24
Peak memory 205148 kb
Host smart-cb7cd11c-33ad-4488-ad39-9b803a69e01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540639086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3540639086
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1497552786
Short name T494
Test name
Test status
Simulation time 445932406 ps
CPU time 6.07 seconds
Started Feb 18 02:13:39 PM PST 24
Finished Feb 18 02:14:25 PM PST 24
Peak memory 235828 kb
Host smart-4057d930-f930-49fc-80bb-526c8ec77b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497552786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1497552786
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.316193665
Short name T44
Test name
Test status
Simulation time 35758711 ps
CPU time 0.69 seconds
Started Feb 18 02:13:35 PM PST 24
Finished Feb 18 02:14:17 PM PST 24
Peak memory 204724 kb
Host smart-414dce28-c3a7-4273-8cc7-fe23a69d40ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316193665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.316193665
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.90117048
Short name T789
Test name
Test status
Simulation time 139557265 ps
CPU time 2.4 seconds
Started Feb 18 02:13:33 PM PST 24
Finished Feb 18 02:14:15 PM PST 24
Peak memory 233588 kb
Host smart-4655eb9b-2b7d-49b1-aae5-5e7d33e5de10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90117048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.90117048
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1235301609
Short name T474
Test name
Test status
Simulation time 19401342 ps
CPU time 0.78 seconds
Started Feb 18 02:13:25 PM PST 24
Finished Feb 18 02:14:11 PM PST 24
Peak memory 204716 kb
Host smart-6ae3c9f9-3b8a-4176-87c8-3a15d54b900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235301609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1235301609
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3908816001
Short name T347
Test name
Test status
Simulation time 36595933287 ps
CPU time 179.18 seconds
Started Feb 18 02:13:31 PM PST 24
Finished Feb 18 02:17:18 PM PST 24
Peak memory 257132 kb
Host smart-0070f8c0-20fe-48a7-8187-03cda77d9848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908816001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3908816001
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1045869183
Short name T676
Test name
Test status
Simulation time 3390062891 ps
CPU time 58.33 seconds
Started Feb 18 02:13:32 PM PST 24
Finished Feb 18 02:15:11 PM PST 24
Peak memory 238124 kb
Host smart-500fba4b-1435-4a6f-b629-03f0f2935774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045869183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1045869183
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3879586119
Short name T845
Test name
Test status
Simulation time 34285871968 ps
CPU time 84.91 seconds
Started Feb 18 02:13:31 PM PST 24
Finished Feb 18 02:15:44 PM PST 24
Peak memory 252420 kb
Host smart-73a5b31e-8278-47b0-a99c-e653b0de4c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879586119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3879586119
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1908158736
Short name T552
Test name
Test status
Simulation time 7547831365 ps
CPU time 15.74 seconds
Started Feb 18 02:13:32 PM PST 24
Finished Feb 18 02:14:28 PM PST 24
Peak memory 247204 kb
Host smart-57c6f8ee-c987-40b2-a8d5-c90fea79f7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908158736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1908158736
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.773976294
Short name T364
Test name
Test status
Simulation time 154664862 ps
CPU time 4.76 seconds
Started Feb 18 02:13:28 PM PST 24
Finished Feb 18 02:14:23 PM PST 24
Peak memory 232960 kb
Host smart-e84ebcd0-e088-4d31-8a0c-9d82a38c0877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773976294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.773976294
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3743136711
Short name T353
Test name
Test status
Simulation time 3304869743 ps
CPU time 17.01 seconds
Started Feb 18 02:13:29 PM PST 24
Finished Feb 18 02:14:33 PM PST 24
Peak memory 238988 kb
Host smart-946fd86e-b091-4f9f-aa61-4c2aa9833fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743136711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3743136711
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3638777794
Short name T304
Test name
Test status
Simulation time 46916095 ps
CPU time 1.01 seconds
Started Feb 18 02:13:25 PM PST 24
Finished Feb 18 02:14:07 PM PST 24
Peak memory 216308 kb
Host smart-40f75002-48a0-43fb-9646-856e30804ad0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638777794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3638777794
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2449477839
Short name T357
Test name
Test status
Simulation time 2326599129 ps
CPU time 11.46 seconds
Started Feb 18 02:13:25 PM PST 24
Finished Feb 18 02:14:15 PM PST 24
Peak memory 235184 kb
Host smart-5faa7974-623c-4fc7-955f-7939e1d1421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449477839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2449477839
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.1973571496
Short name T693
Test name
Test status
Simulation time 71484018 ps
CPU time 0.71 seconds
Started Feb 18 02:13:23 PM PST 24
Finished Feb 18 02:14:03 PM PST 24
Peak memory 216012 kb
Host smart-50c66987-9d9f-4460-9dc4-6739a2018c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973571496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.1973571496
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.445855138
Short name T629
Test name
Test status
Simulation time 789565706 ps
CPU time 5.07 seconds
Started Feb 18 02:13:31 PM PST 24
Finished Feb 18 02:14:24 PM PST 24
Peak memory 219396 kb
Host smart-0906fd29-14a4-4902-ae95-66a1df785b49
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=445855138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.445855138
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2963886753
Short name T463
Test name
Test status
Simulation time 33589065570 ps
CPU time 211.03 seconds
Started Feb 18 02:13:35 PM PST 24
Finished Feb 18 02:17:50 PM PST 24
Peak memory 253412 kb
Host smart-e8525869-8f7a-46e8-a581-27d478734033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963886753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2963886753
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3568303527
Short name T724
Test name
Test status
Simulation time 4518837150 ps
CPU time 34.25 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:39 PM PST 24
Peak memory 216220 kb
Host smart-6aac3041-5ef8-4d71-b27d-755605978cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568303527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3568303527
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1403581196
Short name T856
Test name
Test status
Simulation time 13544845325 ps
CPU time 32.93 seconds
Started Feb 18 02:13:30 PM PST 24
Finished Feb 18 02:14:43 PM PST 24
Peak memory 216172 kb
Host smart-91f1bae8-e863-4eb6-a53f-df004033bc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403581196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1403581196
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3510574761
Short name T647
Test name
Test status
Simulation time 523129000 ps
CPU time 2.55 seconds
Started Feb 18 02:13:22 PM PST 24
Finished Feb 18 02:14:05 PM PST 24
Peak memory 216260 kb
Host smart-7335e526-412b-4cdb-829d-dcba737ff23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510574761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3510574761
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.709400489
Short name T949
Test name
Test status
Simulation time 171854449 ps
CPU time 1.17 seconds
Started Feb 18 02:13:24 PM PST 24
Finished Feb 18 02:14:12 PM PST 24
Peak memory 206104 kb
Host smart-b638d023-26c7-49a6-aea2-d402588be73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709400489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.709400489
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1590723297
Short name T920
Test name
Test status
Simulation time 1141103404 ps
CPU time 9.09 seconds
Started Feb 18 02:13:37 PM PST 24
Finished Feb 18 02:14:30 PM PST 24
Peak memory 235924 kb
Host smart-a0084ea3-2de1-4d09-9e3f-e2ec6b3f0db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590723297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1590723297
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3759585348
Short name T280
Test name
Test status
Simulation time 52886544 ps
CPU time 0.7 seconds
Started Feb 18 02:13:32 PM PST 24
Finished Feb 18 02:14:14 PM PST 24
Peak memory 204156 kb
Host smart-dcf8a410-97e5-46c9-8fa8-330ca2fef7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759585348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3759585348
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4089354877
Short name T550
Test name
Test status
Simulation time 4085701476 ps
CPU time 4.77 seconds
Started Feb 18 02:13:39 PM PST 24
Finished Feb 18 02:14:24 PM PST 24
Peak memory 224344 kb
Host smart-0c422f05-c26c-44a7-9617-7b7f82f9c1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089354877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4089354877
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.478605088
Short name T560
Test name
Test status
Simulation time 65811811 ps
CPU time 0.73 seconds
Started Feb 18 02:13:30 PM PST 24
Finished Feb 18 02:14:13 PM PST 24
Peak memory 204824 kb
Host smart-02b192a1-b1b0-4d2a-91cc-76c4454cd6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478605088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.478605088
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.651071558
Short name T622
Test name
Test status
Simulation time 1537269275 ps
CPU time 10.64 seconds
Started Feb 18 02:13:32 PM PST 24
Finished Feb 18 02:14:24 PM PST 24
Peak memory 232372 kb
Host smart-82ed9dfc-5f7a-4a71-84e0-4cf3afcd3339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651071558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.651071558
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1098358128
Short name T421
Test name
Test status
Simulation time 86181105357 ps
CPU time 142.23 seconds
Started Feb 18 02:13:34 PM PST 24
Finished Feb 18 02:16:38 PM PST 24
Peak memory 249052 kb
Host smart-8e94df86-6441-4115-929a-b58d62c451cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098358128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1098358128
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4032154369
Short name T503
Test name
Test status
Simulation time 28463594264 ps
CPU time 225.89 seconds
Started Feb 18 02:13:32 PM PST 24
Finished Feb 18 02:17:57 PM PST 24
Peak memory 248672 kb
Host smart-4d083b53-d2af-4932-b8ec-2368bd96d2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032154369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4032154369
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2726196569
Short name T482
Test name
Test status
Simulation time 2046917640 ps
CPU time 8.81 seconds
Started Feb 18 02:13:33 PM PST 24
Finished Feb 18 02:14:33 PM PST 24
Peak memory 235708 kb
Host smart-a8ce8e36-a14b-424d-aa6e-80241e774750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726196569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2726196569
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3536672987
Short name T841
Test name
Test status
Simulation time 1437041654 ps
CPU time 7.69 seconds
Started Feb 18 02:13:36 PM PST 24
Finished Feb 18 02:14:25 PM PST 24
Peak memory 224204 kb
Host smart-8e4a1e1e-0875-4152-84e0-19ecba3799d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536672987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3536672987
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3424383491
Short name T842
Test name
Test status
Simulation time 26857997179 ps
CPU time 24.74 seconds
Started Feb 18 02:13:35 PM PST 24
Finished Feb 18 02:14:41 PM PST 24
Peak memory 232524 kb
Host smart-20a0907e-3b4d-40a9-91af-fc42f64d3af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424383491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3424383491
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2733684009
Short name T393
Test name
Test status
Simulation time 176521053 ps
CPU time 1.07 seconds
Started Feb 18 02:13:31 PM PST 24
Finished Feb 18 02:14:20 PM PST 24
Peak memory 216304 kb
Host smart-09df4c79-5b1d-47e7-a94e-69d6d790a236
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733684009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2733684009
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3692517579
Short name T825
Test name
Test status
Simulation time 1299550614 ps
CPU time 5.9 seconds
Started Feb 18 02:13:30 PM PST 24
Finished Feb 18 02:14:15 PM PST 24
Peak memory 216648 kb
Host smart-1c436c24-059c-48cf-8b21-28ed60637a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692517579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3692517579
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1322159990
Short name T634
Test name
Test status
Simulation time 25932598247 ps
CPU time 17.62 seconds
Started Feb 18 02:13:30 PM PST 24
Finished Feb 18 02:14:30 PM PST 24
Peak memory 233004 kb
Host smart-35caef7a-6a39-4dc6-bdfe-f62e4d843594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322159990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1322159990
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.206487066
Short name T45
Test name
Test status
Simulation time 17821291 ps
CPU time 0.71 seconds
Started Feb 18 02:13:35 PM PST 24
Finished Feb 18 02:14:15 PM PST 24
Peak memory 216012 kb
Host smart-e23f919d-2ca5-4d97-8848-4d7ceb9d6700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206487066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.206487066
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2760896793
Short name T652
Test name
Test status
Simulation time 3923213938 ps
CPU time 6.35 seconds
Started Feb 18 02:13:30 PM PST 24
Finished Feb 18 02:14:24 PM PST 24
Peak memory 221772 kb
Host smart-bb1da7cf-a499-4631-8511-d7e474cabc74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2760896793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2760896793
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2633109413
Short name T278
Test name
Test status
Simulation time 3689362414 ps
CPU time 17.61 seconds
Started Feb 18 02:13:32 PM PST 24
Finished Feb 18 02:14:29 PM PST 24
Peak memory 216164 kb
Host smart-ce3388a4-9fe8-4cf4-a510-d9c873576cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633109413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2633109413
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4147571691
Short name T315
Test name
Test status
Simulation time 2530331769 ps
CPU time 9.65 seconds
Started Feb 18 02:13:32 PM PST 24
Finished Feb 18 02:14:24 PM PST 24
Peak memory 216696 kb
Host smart-680b4c6b-42e4-4a3e-995d-c19346406a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147571691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4147571691
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3842932562
Short name T855
Test name
Test status
Simulation time 85312876 ps
CPU time 2.08 seconds
Started Feb 18 02:13:31 PM PST 24
Finished Feb 18 02:14:21 PM PST 24
Peak memory 216008 kb
Host smart-838bdee7-0d88-4b1d-a737-bc7858674042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842932562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3842932562
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2154671254
Short name T530
Test name
Test status
Simulation time 597326632 ps
CPU time 1.16 seconds
Started Feb 18 02:13:33 PM PST 24
Finished Feb 18 02:14:27 PM PST 24
Peak memory 206128 kb
Host smart-968ff6db-dc38-40b9-9bf6-6909dab0e046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154671254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2154671254
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.557198484
Short name T777
Test name
Test status
Simulation time 2873445422 ps
CPU time 5.61 seconds
Started Feb 18 02:13:31 PM PST 24
Finished Feb 18 02:14:19 PM PST 24
Peak memory 236024 kb
Host smart-c566fd78-7115-489e-8073-2a60154b9c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557198484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.557198484
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3618752813
Short name T675
Test name
Test status
Simulation time 13043089 ps
CPU time 0.7 seconds
Started Feb 18 02:13:33 PM PST 24
Finished Feb 18 02:14:13 PM PST 24
Peak memory 205072 kb
Host smart-c9413015-34a4-429e-b60b-19ee65e4e971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618752813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3618752813
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.819327991
Short name T880
Test name
Test status
Simulation time 141894387 ps
CPU time 3.28 seconds
Started Feb 18 02:13:38 PM PST 24
Finished Feb 18 02:14:23 PM PST 24
Peak memory 219472 kb
Host smart-259914b2-b763-4701-b293-d979fdfdda3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819327991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.819327991
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3167384154
Short name T13
Test name
Test status
Simulation time 34666183 ps
CPU time 0.78 seconds
Started Feb 18 02:13:30 PM PST 24
Finished Feb 18 02:14:11 PM PST 24
Peak memory 205812 kb
Host smart-bf1eba43-cb53-42d4-b1f2-d4eba4b57278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167384154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3167384154
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.792941340
Short name T228
Test name
Test status
Simulation time 4745604184 ps
CPU time 27.04 seconds
Started Feb 18 02:13:34 PM PST 24
Finished Feb 18 02:14:43 PM PST 24
Peak memory 234972 kb
Host smart-b16679d7-6107-4874-9925-738c43de7000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792941340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.792941340
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3436838609
Short name T143
Test name
Test status
Simulation time 60225456681 ps
CPU time 229.56 seconds
Started Feb 18 02:13:42 PM PST 24
Finished Feb 18 02:18:11 PM PST 24
Peak memory 266736 kb
Host smart-0147e228-2fd6-4f30-b138-266e6e84ebfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436838609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3436838609
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2839598448
Short name T499
Test name
Test status
Simulation time 9633201466 ps
CPU time 24.46 seconds
Started Feb 18 02:13:41 PM PST 24
Finished Feb 18 02:14:47 PM PST 24
Peak memory 232472 kb
Host smart-91fe9da3-e524-4a21-bf60-d6915a23eae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839598448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2839598448
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1546713702
Short name T262
Test name
Test status
Simulation time 28760552438 ps
CPU time 13 seconds
Started Feb 18 02:13:40 PM PST 24
Finished Feb 18 02:14:42 PM PST 24
Peak memory 233072 kb
Host smart-6168f63f-2d5c-42ea-8892-a16667939ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546713702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1546713702
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1881115085
Short name T397
Test name
Test status
Simulation time 6682972785 ps
CPU time 19.12 seconds
Started Feb 18 02:13:34 PM PST 24
Finished Feb 18 02:14:35 PM PST 24
Peak memory 242136 kb
Host smart-b146b962-61c9-4332-a90e-9aaba6fa0e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881115085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1881115085
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1339308812
Short name T20
Test name
Test status
Simulation time 14738215 ps
CPU time 1.04 seconds
Started Feb 18 02:13:33 PM PST 24
Finished Feb 18 02:14:13 PM PST 24
Peak memory 216312 kb
Host smart-b3ebebec-6153-4baf-b1c7-e4e2f5036cb2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339308812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1339308812
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2956588953
Short name T488
Test name
Test status
Simulation time 59106744523 ps
CPU time 40.3 seconds
Started Feb 18 02:13:31 PM PST 24
Finished Feb 18 02:14:52 PM PST 24
Peak memory 248972 kb
Host smart-e6a2df55-85a9-4045-9351-80f7925a996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956588953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2956588953
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.560897875
Short name T381
Test name
Test status
Simulation time 1874146296 ps
CPU time 5.79 seconds
Started Feb 18 02:13:37 PM PST 24
Finished Feb 18 02:14:23 PM PST 24
Peak memory 224184 kb
Host smart-4ff38d44-287f-41f7-b07a-784a476517ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560897875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.560897875
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.4033547998
Short name T956
Test name
Test status
Simulation time 18645822 ps
CPU time 0.73 seconds
Started Feb 18 02:13:35 PM PST 24
Finished Feb 18 02:14:17 PM PST 24
Peak memory 216012 kb
Host smart-6d8d2692-b605-44a8-a6e9-6c31ef79a8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033547998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.4033547998
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1115200077
Short name T117
Test name
Test status
Simulation time 1383465673 ps
CPU time 3.83 seconds
Started Feb 18 02:13:41 PM PST 24
Finished Feb 18 02:14:24 PM PST 24
Peak memory 222200 kb
Host smart-6a9662be-da41-4e2f-a2c5-b47f30778a44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1115200077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1115200077
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2456590826
Short name T800
Test name
Test status
Simulation time 17001819635 ps
CPU time 70.13 seconds
Started Feb 18 02:13:34 PM PST 24
Finished Feb 18 02:15:26 PM PST 24
Peak memory 216308 kb
Host smart-082ed4cf-fa35-4e3a-9e15-97e68e324972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456590826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2456590826
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4241257867
Short name T628
Test name
Test status
Simulation time 2336439829 ps
CPU time 4.65 seconds
Started Feb 18 02:13:33 PM PST 24
Finished Feb 18 02:14:17 PM PST 24
Peak memory 216120 kb
Host smart-7d12ac3f-96b3-46c7-b81f-ff4a779fc708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241257867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4241257867
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2108819083
Short name T267
Test name
Test status
Simulation time 3367244857 ps
CPU time 9.66 seconds
Started Feb 18 02:13:36 PM PST 24
Finished Feb 18 02:14:25 PM PST 24
Peak memory 216452 kb
Host smart-36b6610d-b86a-4aca-bfaa-22d04bdf91dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108819083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2108819083
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1269023515
Short name T322
Test name
Test status
Simulation time 253658408 ps
CPU time 0.81 seconds
Started Feb 18 02:13:34 PM PST 24
Finished Feb 18 02:14:27 PM PST 24
Peak memory 205128 kb
Host smart-906d4d3b-d5ee-4a74-bc3e-128bfff8d6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269023515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1269023515
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2089783278
Short name T798
Test name
Test status
Simulation time 5148124822 ps
CPU time 8.34 seconds
Started Feb 18 02:13:36 PM PST 24
Finished Feb 18 02:14:26 PM PST 24
Peak memory 227768 kb
Host smart-dd4eb63b-fd4d-49c8-a008-a9016bb319d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089783278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2089783278
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2534311646
Short name T426
Test name
Test status
Simulation time 16263688 ps
CPU time 0.74 seconds
Started Feb 18 02:13:42 PM PST 24
Finished Feb 18 02:14:22 PM PST 24
Peak memory 204736 kb
Host smart-43df73b4-e866-41c1-91de-e58fe5e21ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534311646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2534311646
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2867112258
Short name T149
Test name
Test status
Simulation time 236379124 ps
CPU time 2.19 seconds
Started Feb 18 02:13:42 PM PST 24
Finished Feb 18 02:14:24 PM PST 24
Peak memory 216100 kb
Host smart-0d536164-eef7-43f5-9b86-bda243b23d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867112258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2867112258
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2913718721
Short name T599
Test name
Test status
Simulation time 235560510 ps
CPU time 0.78 seconds
Started Feb 18 02:13:41 PM PST 24
Finished Feb 18 02:14:34 PM PST 24
Peak memory 205844 kb
Host smart-f73befe6-5734-437b-b35f-c997fc483ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913718721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2913718721
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3723637175
Short name T770
Test name
Test status
Simulation time 3844716676 ps
CPU time 6.17 seconds
Started Feb 18 02:13:39 PM PST 24
Finished Feb 18 02:14:31 PM PST 24
Peak memory 234432 kb
Host smart-f17d995c-0030-4fd4-b478-cc0687214ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723637175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3723637175
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2008838276
Short name T437
Test name
Test status
Simulation time 37069723780 ps
CPU time 68.01 seconds
Started Feb 18 02:13:39 PM PST 24
Finished Feb 18 02:15:33 PM PST 24
Peak memory 237904 kb
Host smart-c63a93f3-7da7-4cb0-8f14-abc947a4ba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008838276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2008838276
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.4290394541
Short name T370
Test name
Test status
Simulation time 10145631093 ps
CPU time 134.63 seconds
Started Feb 18 02:13:39 PM PST 24
Finished Feb 18 02:16:37 PM PST 24
Peak memory 257216 kb
Host smart-91dc94ab-0a2a-419d-bd39-e1b0b870125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290394541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.4290394541
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1880466679
Short name T497
Test name
Test status
Simulation time 13160923209 ps
CPU time 32.15 seconds
Started Feb 18 02:13:34 PM PST 24
Finished Feb 18 02:14:47 PM PST 24
Peak memory 248040 kb
Host smart-5ff70f75-89e2-4927-a634-354e14807a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880466679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1880466679
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2869599401
Short name T390
Test name
Test status
Simulation time 541235032 ps
CPU time 2.59 seconds
Started Feb 18 02:13:41 PM PST 24
Finished Feb 18 02:14:36 PM PST 24
Peak memory 217212 kb
Host smart-319e63fc-188b-4f1b-8edb-33049ace236d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869599401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2869599401
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.713456021
Short name T229
Test name
Test status
Simulation time 189653170 ps
CPU time 5.09 seconds
Started Feb 18 02:13:34 PM PST 24
Finished Feb 18 02:14:21 PM PST 24
Peak memory 233452 kb
Host smart-8a71d26d-45c0-4e6a-aa72-0e2497e4eba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713456021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.713456021
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.4127859209
Short name T21
Test name
Test status
Simulation time 45272657 ps
CPU time 1.08 seconds
Started Feb 18 02:13:42 PM PST 24
Finished Feb 18 02:14:37 PM PST 24
Peak memory 216280 kb
Host smart-b13f9a4f-a0f5-4127-b0f2-59fd9696633e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127859209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.4127859209
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4091078177
Short name T199
Test name
Test status
Simulation time 40913412199 ps
CPU time 27.63 seconds
Started Feb 18 02:13:44 PM PST 24
Finished Feb 18 02:15:01 PM PST 24
Peak memory 217668 kb
Host smart-92176483-786a-438f-8c42-20e48ea471e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091078177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4091078177
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.770924886
Short name T36
Test name
Test status
Simulation time 415678940 ps
CPU time 5.16 seconds
Started Feb 18 02:13:33 PM PST 24
Finished Feb 18 02:14:18 PM PST 24
Peak memory 224252 kb
Host smart-ad9fb6ef-e668-419d-80d5-1975a59587fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770924886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.770924886
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.76024860
Short name T430
Test name
Test status
Simulation time 33077803 ps
CPU time 0.71 seconds
Started Feb 18 02:13:32 PM PST 24
Finished Feb 18 02:14:12 PM PST 24
Peak memory 215948 kb
Host smart-24649534-1b98-4a17-92cf-fd0e9629d965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76024860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.76024860
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4253999791
Short name T112
Test name
Test status
Simulation time 9837072720 ps
CPU time 5.72 seconds
Started Feb 18 02:13:41 PM PST 24
Finished Feb 18 02:14:28 PM PST 24
Peak memory 218696 kb
Host smart-d6886e9d-f7f4-4407-b16c-946c387efbb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4253999791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4253999791
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1993462660
Short name T874
Test name
Test status
Simulation time 432255101886 ps
CPU time 243.54 seconds
Started Feb 18 02:13:36 PM PST 24
Finished Feb 18 02:18:20 PM PST 24
Peak memory 249068 kb
Host smart-7eb296a8-5235-408d-9620-0016d2497a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993462660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1993462660
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4089280060
Short name T793
Test name
Test status
Simulation time 3067704788 ps
CPU time 17.59 seconds
Started Feb 18 02:13:39 PM PST 24
Finished Feb 18 02:14:36 PM PST 24
Peak memory 216172 kb
Host smart-90c81051-28bf-4515-8e94-09842e5f8dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089280060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4089280060
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1738771471
Short name T671
Test name
Test status
Simulation time 2242812130 ps
CPU time 10.83 seconds
Started Feb 18 02:13:41 PM PST 24
Finished Feb 18 02:14:33 PM PST 24
Peak memory 216216 kb
Host smart-2f564ac4-73bd-4831-9410-d099272add59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738771471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1738771471
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1003654024
Short name T871
Test name
Test status
Simulation time 265749032 ps
CPU time 2.31 seconds
Started Feb 18 02:13:36 PM PST 24
Finished Feb 18 02:14:21 PM PST 24
Peak memory 216236 kb
Host smart-337e604b-dc7e-4191-9911-e17fd170d576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003654024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1003654024
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3695947680
Short name T795
Test name
Test status
Simulation time 131526004 ps
CPU time 0.81 seconds
Started Feb 18 02:13:41 PM PST 24
Finished Feb 18 02:14:21 PM PST 24
Peak memory 205104 kb
Host smart-0fde7154-3df8-4b1e-9b5c-d633e3d29fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695947680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3695947680
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1331294334
Short name T371
Test name
Test status
Simulation time 13093125575 ps
CPU time 18.46 seconds
Started Feb 18 02:13:42 PM PST 24
Finished Feb 18 02:14:50 PM PST 24
Peak memory 233336 kb
Host smart-0f1f1d86-ae8e-4e6e-aee6-40c5ca787d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331294334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1331294334
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.554346597
Short name T284
Test name
Test status
Simulation time 16217013 ps
CPU time 0.75 seconds
Started Feb 18 02:13:46 PM PST 24
Finished Feb 18 02:14:26 PM PST 24
Peak memory 204724 kb
Host smart-766ed085-79cd-42f5-9485-6b5410c83f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554346597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.554346597
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1585694617
Short name T61
Test name
Test status
Simulation time 211459037 ps
CPU time 2.24 seconds
Started Feb 18 02:13:44 PM PST 24
Finished Feb 18 02:14:28 PM PST 24
Peak memory 216168 kb
Host smart-b7965fc8-02bc-491f-b447-5483288ac3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585694617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1585694617
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1227845495
Short name T276
Test name
Test status
Simulation time 32873695 ps
CPU time 0.76 seconds
Started Feb 18 02:13:45 PM PST 24
Finished Feb 18 02:14:26 PM PST 24
Peak memory 205844 kb
Host smart-795a2ff9-d512-40ac-bc5f-8025a711ace3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227845495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1227845495
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3527282634
Short name T454
Test name
Test status
Simulation time 355876443 ps
CPU time 4.8 seconds
Started Feb 18 02:13:46 PM PST 24
Finished Feb 18 02:14:32 PM PST 24
Peak memory 232408 kb
Host smart-772ccafb-e3e6-4937-b035-816843ef18f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527282634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3527282634
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.708022108
Short name T180
Test name
Test status
Simulation time 92292858225 ps
CPU time 680.32 seconds
Started Feb 18 02:13:43 PM PST 24
Finished Feb 18 02:25:52 PM PST 24
Peak memory 270576 kb
Host smart-3699185d-5638-446d-95a7-95361a3a13dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708022108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.708022108
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1762026943
Short name T837
Test name
Test status
Simulation time 5551485768 ps
CPU time 14.73 seconds
Started Feb 18 02:13:42 PM PST 24
Finished Feb 18 02:14:46 PM PST 24
Peak memory 248596 kb
Host smart-eab4c9b0-f1bd-4870-8373-d447b76fc7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762026943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1762026943
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.490236655
Short name T738
Test name
Test status
Simulation time 809303171 ps
CPU time 4.69 seconds
Started Feb 18 02:13:42 PM PST 24
Finished Feb 18 02:14:26 PM PST 24
Peak memory 218520 kb
Host smart-1087f241-5713-4d4b-ab30-8d1763e23cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490236655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.490236655
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1545323839
Short name T354
Test name
Test status
Simulation time 4364269902 ps
CPU time 9.6 seconds
Started Feb 18 02:13:51 PM PST 24
Finished Feb 18 02:14:44 PM PST 24
Peak memory 233312 kb
Host smart-04fd0aaf-7542-427d-879a-aec488ec8bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545323839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1545323839
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2953147341
Short name T740
Test name
Test status
Simulation time 84813282 ps
CPU time 1.04 seconds
Started Feb 18 02:14:00 PM PST 24
Finished Feb 18 02:15:02 PM PST 24
Peak memory 216312 kb
Host smart-a1d79fff-bbee-432c-a353-1c4b5e90d8a3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953147341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2953147341
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3681051660
Short name T409
Test name
Test status
Simulation time 83526041221 ps
CPU time 24.98 seconds
Started Feb 18 02:13:42 PM PST 24
Finished Feb 18 02:15:00 PM PST 24
Peak memory 240720 kb
Host smart-3c94048c-6420-42ec-8a2c-df51fcc4ca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681051660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3681051660
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.87410151
Short name T697
Test name
Test status
Simulation time 1303664351 ps
CPU time 10.99 seconds
Started Feb 18 02:13:51 PM PST 24
Finished Feb 18 02:14:44 PM PST 24
Peak memory 232952 kb
Host smart-9c54c034-608b-47e1-bfa7-8710c24ca880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87410151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.87410151
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.964442118
Short name T613
Test name
Test status
Simulation time 17321229 ps
CPU time 0.71 seconds
Started Feb 18 02:13:41 PM PST 24
Finished Feb 18 02:14:21 PM PST 24
Peak memory 215988 kb
Host smart-efa639bf-4881-4097-b907-7502f739a932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964442118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.964442118
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3614744615
Short name T40
Test name
Test status
Simulation time 1244997165 ps
CPU time 6.12 seconds
Started Feb 18 02:13:41 PM PST 24
Finished Feb 18 02:14:26 PM PST 24
Peak memory 222188 kb
Host smart-b68378c1-c76b-4a5e-831e-f2a5954db574
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3614744615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3614744615
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1422490905
Short name T505
Test name
Test status
Simulation time 19765325746 ps
CPU time 76.99 seconds
Started Feb 18 02:13:46 PM PST 24
Finished Feb 18 02:15:45 PM PST 24
Peak memory 237996 kb
Host smart-026704ae-cdf0-4475-ac30-48eed26b8bf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422490905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1422490905
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1913354025
Short name T16
Test name
Test status
Simulation time 3155725257 ps
CPU time 34.24 seconds
Started Feb 18 02:13:43 PM PST 24
Finished Feb 18 02:14:58 PM PST 24
Peak memory 216076 kb
Host smart-a05b9eaf-d406-4e9b-8999-9c33e8a2a47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913354025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1913354025
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1774320931
Short name T849
Test name
Test status
Simulation time 662223342 ps
CPU time 3.75 seconds
Started Feb 18 02:13:43 PM PST 24
Finished Feb 18 02:14:37 PM PST 24
Peak memory 216040 kb
Host smart-faabe171-812d-46d3-814c-7396d122a363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774320931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1774320931
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1705547610
Short name T830
Test name
Test status
Simulation time 83581302 ps
CPU time 1.14 seconds
Started Feb 18 02:13:40 PM PST 24
Finished Feb 18 02:14:33 PM PST 24
Peak memory 207476 kb
Host smart-daddccaf-81b2-4b79-be93-474cf09dce98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705547610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1705547610
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3441834019
Short name T605
Test name
Test status
Simulation time 549084224 ps
CPU time 1.14 seconds
Started Feb 18 02:13:46 PM PST 24
Finished Feb 18 02:14:29 PM PST 24
Peak memory 206132 kb
Host smart-1eeac70d-9a75-4625-9369-cdb0a6dbf881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441834019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3441834019
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2511299793
Short name T9
Test name
Test status
Simulation time 455717210 ps
CPU time 4.11 seconds
Started Feb 18 02:13:44 PM PST 24
Finished Feb 18 02:14:30 PM PST 24
Peak memory 233364 kb
Host smart-67843d02-488b-41d9-b659-b47d740af4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511299793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2511299793
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1251308392
Short name T720
Test name
Test status
Simulation time 13481520 ps
CPU time 0.7 seconds
Started Feb 18 02:12:29 PM PST 24
Finished Feb 18 02:13:10 PM PST 24
Peak memory 204704 kb
Host smart-e0d013db-34ab-4439-8fb7-cb0393290f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251308392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
251308392
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.889014435
Short name T863
Test name
Test status
Simulation time 1020634328 ps
CPU time 4.53 seconds
Started Feb 18 02:12:23 PM PST 24
Finished Feb 18 02:13:04 PM PST 24
Peak memory 218148 kb
Host smart-9510fce3-3be6-43e9-82ac-7d476f13dca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889014435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.889014435
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2979233616
Short name T274
Test name
Test status
Simulation time 73184892 ps
CPU time 0.78 seconds
Started Feb 18 02:12:17 PM PST 24
Finished Feb 18 02:12:51 PM PST 24
Peak memory 204840 kb
Host smart-911b76df-0ffb-46cd-877f-38c9e1b85feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979233616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2979233616
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3741687837
Short name T903
Test name
Test status
Simulation time 23588857526 ps
CPU time 140.04 seconds
Started Feb 18 02:12:21 PM PST 24
Finished Feb 18 02:15:15 PM PST 24
Peak memory 249360 kb
Host smart-d7ce937f-7262-43a6-a45d-6db423b9f5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741687837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3741687837
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1200497343
Short name T723
Test name
Test status
Simulation time 26565519365 ps
CPU time 135.65 seconds
Started Feb 18 02:12:20 PM PST 24
Finished Feb 18 02:15:10 PM PST 24
Peak memory 250080 kb
Host smart-6ddc5b2b-bdfd-48eb-8364-e3f7d5762e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200497343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1200497343
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.507853163
Short name T241
Test name
Test status
Simulation time 3955411367 ps
CPU time 45.84 seconds
Started Feb 18 02:12:22 PM PST 24
Finished Feb 18 02:13:43 PM PST 24
Peak memory 232636 kb
Host smart-0037fa4b-2959-455b-ab34-8c393a46d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507853163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
507853163
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1276775900
Short name T766
Test name
Test status
Simulation time 3110646188 ps
CPU time 13.19 seconds
Started Feb 18 02:12:22 PM PST 24
Finished Feb 18 02:13:09 PM PST 24
Peak memory 224332 kb
Host smart-c5a7ea8c-d537-4f05-a07f-1ad6290525b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276775900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1276775900
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4222811891
Short name T247
Test name
Test status
Simulation time 298512974 ps
CPU time 3.52 seconds
Started Feb 18 02:12:18 PM PST 24
Finished Feb 18 02:12:55 PM PST 24
Peak memory 218180 kb
Host smart-89a3e12f-2240-4c84-ad8b-83748546251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222811891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4222811891
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.412222130
Short name T365
Test name
Test status
Simulation time 222468154 ps
CPU time 3.12 seconds
Started Feb 18 02:12:16 PM PST 24
Finished Feb 18 02:12:54 PM PST 24
Peak memory 224140 kb
Host smart-cd398ed7-c77a-4121-98ae-f5692c842aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412222130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.412222130
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1411045351
Short name T19
Test name
Test status
Simulation time 132174057 ps
CPU time 1.09 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:13:05 PM PST 24
Peak memory 216312 kb
Host smart-0387dda3-26e3-41e9-830e-09a8e9245297
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411045351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1411045351
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2429754089
Short name T490
Test name
Test status
Simulation time 119724585 ps
CPU time 2.96 seconds
Started Feb 18 02:12:24 PM PST 24
Finished Feb 18 02:13:03 PM PST 24
Peak memory 232548 kb
Host smart-f989c050-9ad6-4d67-bd50-9a821bfdadb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429754089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2429754089
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.275030695
Short name T233
Test name
Test status
Simulation time 6806463615 ps
CPU time 11.28 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:13:12 PM PST 24
Peak memory 223772 kb
Host smart-b266994c-54ab-4caf-8b21-4a5cb9d1f876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275030695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.275030695
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.3868016380
Short name T635
Test name
Test status
Simulation time 15165053 ps
CPU time 0.79 seconds
Started Feb 18 02:12:24 PM PST 24
Finished Feb 18 02:13:00 PM PST 24
Peak memory 215908 kb
Host smart-a7827d30-6a66-4bc6-b4ae-d73d03389c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868016380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.3868016380
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2272383081
Short name T594
Test name
Test status
Simulation time 1913515943 ps
CPU time 4.6 seconds
Started Feb 18 02:12:24 PM PST 24
Finished Feb 18 02:13:04 PM PST 24
Peak memory 219596 kb
Host smart-2c62895f-23ed-40f3-a77a-c62325107e95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2272383081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2272383081
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1115411231
Short name T48
Test name
Test status
Simulation time 71213531 ps
CPU time 0.96 seconds
Started Feb 18 02:12:26 PM PST 24
Finished Feb 18 02:13:03 PM PST 24
Peak memory 235348 kb
Host smart-051ce2a6-eca1-452a-8281-fe60638d601f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115411231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1115411231
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.677649516
Short name T154
Test name
Test status
Simulation time 145366386253 ps
CPU time 301.31 seconds
Started Feb 18 02:12:22 PM PST 24
Finished Feb 18 02:17:58 PM PST 24
Peak memory 254184 kb
Host smart-b6c77ebf-a8e0-4c79-8215-f95cdecb074f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677649516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.677649516
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1248563958
Short name T828
Test name
Test status
Simulation time 176650779 ps
CPU time 2.36 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:13:06 PM PST 24
Peak memory 216088 kb
Host smart-47a24ced-945a-4af7-80e5-a8f7068b7654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248563958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1248563958
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1978234851
Short name T885
Test name
Test status
Simulation time 4704597066 ps
CPU time 2.45 seconds
Started Feb 18 02:12:22 PM PST 24
Finished Feb 18 02:12:59 PM PST 24
Peak memory 207728 kb
Host smart-eda634b6-e0c1-4629-a610-5189b6d5225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978234851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1978234851
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2464885625
Short name T15
Test name
Test status
Simulation time 341834789 ps
CPU time 4.37 seconds
Started Feb 18 02:12:30 PM PST 24
Finished Feb 18 02:13:15 PM PST 24
Peak memory 216052 kb
Host smart-2588107f-04b1-408c-b303-1b341f4652c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464885625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2464885625
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2237485097
Short name T581
Test name
Test status
Simulation time 186806143 ps
CPU time 0.87 seconds
Started Feb 18 02:12:24 PM PST 24
Finished Feb 18 02:13:01 PM PST 24
Peak memory 205104 kb
Host smart-ef67b3a7-f55b-42ca-9264-f95eb00edc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237485097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2237485097
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3697967720
Short name T612
Test name
Test status
Simulation time 13725648205 ps
CPU time 36.31 seconds
Started Feb 18 02:12:30 PM PST 24
Finished Feb 18 02:13:48 PM PST 24
Peak memory 228216 kb
Host smart-d51284ac-b363-4b0e-9d49-a943cf532082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697967720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3697967720
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1102625964
Short name T651
Test name
Test status
Simulation time 23104535 ps
CPU time 0.72 seconds
Started Feb 18 02:13:52 PM PST 24
Finished Feb 18 02:14:32 PM PST 24
Peak memory 204156 kb
Host smart-ae428216-e5eb-47d3-b559-c2b10bfd4385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102625964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1102625964
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3445790980
Short name T239
Test name
Test status
Simulation time 48636555 ps
CPU time 2.18 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:14:38 PM PST 24
Peak memory 224152 kb
Host smart-63631af3-329b-4d20-ae68-d8a6befdd3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445790980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3445790980
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.863863512
Short name T608
Test name
Test status
Simulation time 17735690 ps
CPU time 0.82 seconds
Started Feb 18 02:13:49 PM PST 24
Finished Feb 18 02:14:29 PM PST 24
Peak memory 205844 kb
Host smart-928f44d5-31cf-426f-abb3-1b2c287867af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863863512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.863863512
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3545566961
Short name T576
Test name
Test status
Simulation time 187845018936 ps
CPU time 225.02 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:18:23 PM PST 24
Peak memory 257524 kb
Host smart-15c6fd63-3c88-44a2-aff9-6a7510162b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545566961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3545566961
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.377273552
Short name T539
Test name
Test status
Simulation time 48203308547 ps
CPU time 309.77 seconds
Started Feb 18 02:13:57 PM PST 24
Finished Feb 18 02:19:48 PM PST 24
Peak memory 254108 kb
Host smart-332875fb-dc31-41f5-b8de-3edd6d0c50b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377273552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.377273552
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.217034521
Short name T226
Test name
Test status
Simulation time 80441873551 ps
CPU time 169.12 seconds
Started Feb 18 02:13:48 PM PST 24
Finished Feb 18 02:17:20 PM PST 24
Peak memory 255932 kb
Host smart-52e3d27d-7a12-4849-a3e4-29aac2b197ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217034521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.217034521
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2454048849
Short name T976
Test name
Test status
Simulation time 30653838335 ps
CPU time 56.53 seconds
Started Feb 18 02:13:52 PM PST 24
Finished Feb 18 02:15:29 PM PST 24
Peak memory 240436 kb
Host smart-7c706c7a-0a99-48e3-af7a-fae5ea6d1ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454048849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2454048849
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2257964080
Short name T838
Test name
Test status
Simulation time 97611236 ps
CPU time 3.08 seconds
Started Feb 18 02:13:56 PM PST 24
Finished Feb 18 02:14:40 PM PST 24
Peak memory 232640 kb
Host smart-3582a831-a5f8-45f6-a516-a12f9e7824cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257964080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2257964080
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.160223222
Short name T427
Test name
Test status
Simulation time 2172854442 ps
CPU time 4.35 seconds
Started Feb 18 02:13:58 PM PST 24
Finished Feb 18 02:14:43 PM PST 24
Peak memory 224132 kb
Host smart-1feb5ca2-4883-49bc-8764-ca2db526f2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160223222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.160223222
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2099692174
Short name T982
Test name
Test status
Simulation time 8868596490 ps
CPU time 25.75 seconds
Started Feb 18 02:13:57 PM PST 24
Finished Feb 18 02:15:03 PM PST 24
Peak memory 232692 kb
Host smart-2be8115c-9956-4c7d-b343-2bae90aca013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099692174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2099692174
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2301853790
Short name T762
Test name
Test status
Simulation time 4016872983 ps
CPU time 17.28 seconds
Started Feb 18 02:13:49 PM PST 24
Finished Feb 18 02:14:46 PM PST 24
Peak memory 229760 kb
Host smart-14f64c53-879c-4799-9ac0-7e66f2f516ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301853790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2301853790
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3796923136
Short name T321
Test name
Test status
Simulation time 202368815 ps
CPU time 3.36 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:14:39 PM PST 24
Peak memory 219664 kb
Host smart-de22c03d-7e7f-4a16-9ca2-ebed57f50503
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3796923136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3796923136
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2282440308
Short name T319
Test name
Test status
Simulation time 5603098527 ps
CPU time 43.94 seconds
Started Feb 18 02:13:48 PM PST 24
Finished Feb 18 02:15:22 PM PST 24
Peak memory 216176 kb
Host smart-8b8692d1-fbed-4423-9d6c-e352ab4bc688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282440308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2282440308
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2627756419
Short name T385
Test name
Test status
Simulation time 29245067724 ps
CPU time 26.05 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:15:02 PM PST 24
Peak memory 216208 kb
Host smart-86853cd8-2f89-4537-8e74-a75b7ed4ba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627756419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2627756419
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2478612858
Short name T303
Test name
Test status
Simulation time 685476958 ps
CPU time 2.35 seconds
Started Feb 18 02:13:47 PM PST 24
Finished Feb 18 02:14:29 PM PST 24
Peak memory 216180 kb
Host smart-aea702ad-de60-4051-9b70-b2cf0976ee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478612858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2478612858
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3201266080
Short name T565
Test name
Test status
Simulation time 115295007 ps
CPU time 0.98 seconds
Started Feb 18 02:13:55 PM PST 24
Finished Feb 18 02:14:37 PM PST 24
Peak memory 206128 kb
Host smart-1b225e69-5250-4e13-b5d5-7b73bac1605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201266080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3201266080
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2640413731
Short name T725
Test name
Test status
Simulation time 2655578905 ps
CPU time 8.13 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:14:46 PM PST 24
Peak memory 217472 kb
Host smart-d759b6ab-0607-4a93-b9a2-ab741d31ffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640413731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2640413731
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2847930080
Short name T260
Test name
Test status
Simulation time 15765517 ps
CPU time 0.73 seconds
Started Feb 18 02:13:55 PM PST 24
Finished Feb 18 02:14:44 PM PST 24
Peak memory 204732 kb
Host smart-377c9196-bb63-466a-bc42-c29da2f596f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847930080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2847930080
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4249608087
Short name T607
Test name
Test status
Simulation time 976966118 ps
CPU time 3.4 seconds
Started Feb 18 02:13:55 PM PST 24
Finished Feb 18 02:14:39 PM PST 24
Peak memory 233272 kb
Host smart-08e7ec38-b684-405c-8928-72c3076cb7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249608087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4249608087
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2960649106
Short name T706
Test name
Test status
Simulation time 28138995 ps
CPU time 0.77 seconds
Started Feb 18 02:13:51 PM PST 24
Finished Feb 18 02:14:36 PM PST 24
Peak memory 205868 kb
Host smart-e3dd2372-8f16-4027-8f53-7c0aed912e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960649106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2960649106
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.131663213
Short name T232
Test name
Test status
Simulation time 123603571578 ps
CPU time 158.49 seconds
Started Feb 18 02:13:50 PM PST 24
Finished Feb 18 02:17:12 PM PST 24
Peak memory 250024 kb
Host smart-f7975c8e-eb60-4ee7-8c6d-de347e2a55f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131663213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.131663213
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2178267688
Short name T181
Test name
Test status
Simulation time 55676705812 ps
CPU time 214.25 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:18:12 PM PST 24
Peak memory 249448 kb
Host smart-0d3b447a-3dcc-430f-9690-8797c50a30d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178267688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2178267688
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3932467303
Short name T293
Test name
Test status
Simulation time 5292616616 ps
CPU time 11.08 seconds
Started Feb 18 02:13:49 PM PST 24
Finished Feb 18 02:14:40 PM PST 24
Peak memory 245860 kb
Host smart-2d25361a-6f60-43fe-8606-f189624954ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932467303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3932467303
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3315134745
Short name T533
Test name
Test status
Simulation time 700588551 ps
CPU time 3.24 seconds
Started Feb 18 02:13:51 PM PST 24
Finished Feb 18 02:14:35 PM PST 24
Peak memory 233136 kb
Host smart-01771665-be2a-4a53-a212-800ee807d129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315134745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3315134745
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2579941123
Short name T757
Test name
Test status
Simulation time 51964534208 ps
CPU time 37.49 seconds
Started Feb 18 02:13:59 PM PST 24
Finished Feb 18 02:15:26 PM PST 24
Peak memory 240704 kb
Host smart-40cac51c-3be1-4a18-bba1-5b0e43a56e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579941123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2579941123
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3046840246
Short name T938
Test name
Test status
Simulation time 9119415947 ps
CPU time 13.56 seconds
Started Feb 18 02:13:55 PM PST 24
Finished Feb 18 02:14:49 PM PST 24
Peak memory 236512 kb
Host smart-0ce73e81-ef52-4329-ab33-b8fc9aeca971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046840246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3046840246
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4014651
Short name T172
Test name
Test status
Simulation time 903632702 ps
CPU time 5.02 seconds
Started Feb 18 02:13:51 PM PST 24
Finished Feb 18 02:14:39 PM PST 24
Peak memory 233776 kb
Host smart-bb8e897b-021e-4327-b6a5-379e483135b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4014651
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.361116678
Short name T538
Test name
Test status
Simulation time 8557584029 ps
CPU time 5.3 seconds
Started Feb 18 02:13:52 PM PST 24
Finished Feb 18 02:14:43 PM PST 24
Peak memory 219596 kb
Host smart-733f71e5-2364-47ec-bcd0-7fb81cd57646
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=361116678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.361116678
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1992178263
Short name T18
Test name
Test status
Simulation time 2232393994 ps
CPU time 21.65 seconds
Started Feb 18 02:13:55 PM PST 24
Finished Feb 18 02:14:57 PM PST 24
Peak memory 216200 kb
Host smart-c7a64d3e-dcbb-4c90-aedb-0e9cb70a8844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992178263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1992178263
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.711772785
Short name T763
Test name
Test status
Simulation time 185794499 ps
CPU time 1.04 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:14:37 PM PST 24
Peak memory 206280 kb
Host smart-8f6d36b1-a126-4606-acef-ab1420b82a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711772785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.711772785
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2753237238
Short name T897
Test name
Test status
Simulation time 249293678 ps
CPU time 3.15 seconds
Started Feb 18 02:13:52 PM PST 24
Finished Feb 18 02:14:38 PM PST 24
Peak memory 216088 kb
Host smart-2ccb5f5b-91b8-4f56-bafd-436b1d496097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753237238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2753237238
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1269187723
Short name T471
Test name
Test status
Simulation time 113571101 ps
CPU time 0.72 seconds
Started Feb 18 02:13:55 PM PST 24
Finished Feb 18 02:14:37 PM PST 24
Peak memory 205112 kb
Host smart-e7d5c208-9fa8-4391-bd16-74932863e276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269187723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1269187723
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.259325860
Short name T320
Test name
Test status
Simulation time 1196887614 ps
CPU time 11.16 seconds
Started Feb 18 02:13:55 PM PST 24
Finished Feb 18 02:14:54 PM PST 24
Peak memory 235436 kb
Host smart-80b877ff-7140-4d77-b19c-f22b28c673fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259325860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.259325860
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3446922965
Short name T656
Test name
Test status
Simulation time 41774170 ps
CPU time 0.69 seconds
Started Feb 18 02:13:58 PM PST 24
Finished Feb 18 02:14:39 PM PST 24
Peak memory 204700 kb
Host smart-99dc2585-db70-4221-8aa3-b656c331937e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446922965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3446922965
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3317010332
Short name T624
Test name
Test status
Simulation time 252947942 ps
CPU time 3.99 seconds
Started Feb 18 02:14:15 PM PST 24
Finished Feb 18 02:15:09 PM PST 24
Peak memory 232708 kb
Host smart-322792a7-4641-4f3a-a466-9f8e1db11874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317010332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3317010332
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2759443778
Short name T756
Test name
Test status
Simulation time 22645040 ps
CPU time 0.74 seconds
Started Feb 18 02:13:53 PM PST 24
Finished Feb 18 02:14:35 PM PST 24
Peak memory 204800 kb
Host smart-97d5743e-6737-4c69-a9ba-f092f3b4adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759443778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2759443778
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3752220465
Short name T234
Test name
Test status
Simulation time 87363853374 ps
CPU time 124.52 seconds
Started Feb 18 02:14:00 PM PST 24
Finished Feb 18 02:16:55 PM PST 24
Peak memory 248332 kb
Host smart-b3020ccf-2b83-4593-9536-5bf5c9ca9b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752220465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3752220465
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1325119708
Short name T457
Test name
Test status
Simulation time 38602078647 ps
CPU time 269.12 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:19:05 PM PST 24
Peak memory 253512 kb
Host smart-37391eaa-90fe-4a39-835e-0da257515dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325119708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1325119708
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1572907905
Short name T917
Test name
Test status
Simulation time 348990576980 ps
CPU time 274.56 seconds
Started Feb 18 02:13:59 PM PST 24
Finished Feb 18 02:19:23 PM PST 24
Peak memory 253504 kb
Host smart-dff0142a-c78f-4aab-8c7c-595041f8b103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572907905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1572907905
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.812914756
Short name T540
Test name
Test status
Simulation time 1071841127 ps
CPU time 16.01 seconds
Started Feb 18 02:13:57 PM PST 24
Finished Feb 18 02:14:55 PM PST 24
Peak memory 246660 kb
Host smart-5b5d17f1-dba0-4549-97f9-9334486fa82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812914756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.812914756
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3217656979
Short name T161
Test name
Test status
Simulation time 12672836392 ps
CPU time 11.63 seconds
Started Feb 18 02:14:01 PM PST 24
Finished Feb 18 02:14:55 PM PST 24
Peak memory 224304 kb
Host smart-747c66e9-611b-43b4-8893-f4839e112c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217656979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3217656979
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1375031853
Short name T516
Test name
Test status
Simulation time 29910027028 ps
CPU time 22.28 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:15:01 PM PST 24
Peak memory 248580 kb
Host smart-a06360b2-f697-4e96-a84f-747c9e8a6d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375031853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1375031853
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3646534682
Short name T844
Test name
Test status
Simulation time 712471039 ps
CPU time 3.05 seconds
Started Feb 18 02:13:58 PM PST 24
Finished Feb 18 02:14:41 PM PST 24
Peak memory 233096 kb
Host smart-62d7260e-b150-4ae2-94da-82094bd78346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646534682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3646534682
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3350651903
Short name T672
Test name
Test status
Simulation time 1263978679 ps
CPU time 7.34 seconds
Started Feb 18 02:14:12 PM PST 24
Finished Feb 18 02:15:04 PM PST 24
Peak memory 236652 kb
Host smart-b77517f3-40b0-4764-9bbe-569a9d1459f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350651903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3350651903
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2172833530
Short name T963
Test name
Test status
Simulation time 2156146887 ps
CPU time 7.44 seconds
Started Feb 18 02:13:54 PM PST 24
Finished Feb 18 02:14:43 PM PST 24
Peak memory 218588 kb
Host smart-ccf5493a-c48b-4b01-81ac-19a5a3ba62a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2172833530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2172833530
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.63322092
Short name T201
Test name
Test status
Simulation time 210921296399 ps
CPU time 339.98 seconds
Started Feb 18 02:13:59 PM PST 24
Finished Feb 18 02:20:29 PM PST 24
Peak memory 256272 kb
Host smart-80a7b84f-6017-47de-bf2c-bbe1c9b61b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63322092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress
_all.63322092
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1936370073
Short name T769
Test name
Test status
Simulation time 12173426731 ps
CPU time 28.36 seconds
Started Feb 18 02:14:25 PM PST 24
Finished Feb 18 02:15:40 PM PST 24
Peak memory 216120 kb
Host smart-f216329c-b4fd-4143-be99-59733278c0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936370073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1936370073
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2309747909
Short name T412
Test name
Test status
Simulation time 1515450516 ps
CPU time 6.38 seconds
Started Feb 18 02:13:56 PM PST 24
Finished Feb 18 02:14:52 PM PST 24
Peak memory 216080 kb
Host smart-ad04d039-cf78-4b6d-96c3-dcf48e9cbf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309747909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2309747909
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4193664983
Short name T299
Test name
Test status
Simulation time 274978254 ps
CPU time 1.62 seconds
Started Feb 18 02:14:14 PM PST 24
Finished Feb 18 02:15:01 PM PST 24
Peak memory 208216 kb
Host smart-e0dd80f4-6d08-476d-b02d-ff4feb7a9766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193664983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4193664983
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4251067540
Short name T592
Test name
Test status
Simulation time 472604588 ps
CPU time 0.92 seconds
Started Feb 18 02:14:12 PM PST 24
Finished Feb 18 02:14:55 PM PST 24
Peak memory 206116 kb
Host smart-9471f570-a304-4e63-9f40-d9998310b255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251067540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4251067540
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3237873068
Short name T532
Test name
Test status
Simulation time 388491055 ps
CPU time 4.22 seconds
Started Feb 18 02:14:27 PM PST 24
Finished Feb 18 02:15:16 PM PST 24
Peak memory 217104 kb
Host smart-3c9cdd67-7a1a-400e-84a2-8514c6150a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237873068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3237873068
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2380022228
Short name T662
Test name
Test status
Simulation time 53944549 ps
CPU time 0.76 seconds
Started Feb 18 02:14:08 PM PST 24
Finished Feb 18 02:14:50 PM PST 24
Peak memory 204720 kb
Host smart-0f53016e-fe87-49d8-9563-a742d99de47b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380022228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2380022228
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2116495274
Short name T801
Test name
Test status
Simulation time 3462481775 ps
CPU time 7.6 seconds
Started Feb 18 02:14:13 PM PST 24
Finished Feb 18 02:15:02 PM PST 24
Peak memory 234220 kb
Host smart-7496cdf0-8bb0-403a-a1d8-8615bf3cbf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116495274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2116495274
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1049087080
Short name T428
Test name
Test status
Simulation time 131857885 ps
CPU time 0.77 seconds
Started Feb 18 02:13:58 PM PST 24
Finished Feb 18 02:14:39 PM PST 24
Peak memory 205888 kb
Host smart-66f77718-efec-4dae-811b-e2b28e5a536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049087080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1049087080
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2304550377
Short name T34
Test name
Test status
Simulation time 8020070728 ps
CPU time 31.63 seconds
Started Feb 18 02:14:02 PM PST 24
Finished Feb 18 02:15:15 PM PST 24
Peak memory 248908 kb
Host smart-4561c2d6-6c5b-4ea7-aac1-2ee089616a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304550377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2304550377
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4172387430
Short name T295
Test name
Test status
Simulation time 7825008403 ps
CPU time 37.82 seconds
Started Feb 18 02:14:00 PM PST 24
Finished Feb 18 02:15:21 PM PST 24
Peak memory 235232 kb
Host smart-37363305-ffc8-4f87-900a-beb36d8cf4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172387430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4172387430
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3700868894
Short name T919
Test name
Test status
Simulation time 31943109217 ps
CPU time 114.22 seconds
Started Feb 18 02:14:12 PM PST 24
Finished Feb 18 02:16:48 PM PST 24
Peak memory 249016 kb
Host smart-2478ba7b-2d28-4798-8ead-28b879c5517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700868894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3700868894
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.330547153
Short name T679
Test name
Test status
Simulation time 23798607533 ps
CPU time 31.44 seconds
Started Feb 18 02:14:10 PM PST 24
Finished Feb 18 02:15:23 PM PST 24
Peak memory 233292 kb
Host smart-3f4ed760-042a-4dfe-ae9e-560ec4332a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330547153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.330547153
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1664303124
Short name T816
Test name
Test status
Simulation time 944744146 ps
CPU time 5.41 seconds
Started Feb 18 02:14:02 PM PST 24
Finished Feb 18 02:14:51 PM PST 24
Peak memory 232688 kb
Host smart-18ea0074-b284-46b3-9948-65fcfe14e38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664303124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1664303124
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3904754331
Short name T316
Test name
Test status
Simulation time 1737995948 ps
CPU time 5.61 seconds
Started Feb 18 02:14:02 PM PST 24
Finished Feb 18 02:14:52 PM PST 24
Peak memory 216520 kb
Host smart-0ac9b5c0-89bf-468d-afc0-411e5412a24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904754331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3904754331
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.57261673
Short name T860
Test name
Test status
Simulation time 3174558205 ps
CPU time 6.46 seconds
Started Feb 18 02:13:58 PM PST 24
Finished Feb 18 02:14:50 PM PST 24
Peak memory 218192 kb
Host smart-fdc5ca25-92a6-4cd2-9643-7d83eafe8dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57261673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.57261673
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1644348556
Short name T8
Test name
Test status
Simulation time 3665924372 ps
CPU time 11.43 seconds
Started Feb 18 02:14:02 PM PST 24
Finished Feb 18 02:14:57 PM PST 24
Peak memory 233204 kb
Host smart-379b9112-f492-40d1-b999-c3bb89450e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644348556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1644348556
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.577822332
Short name T677
Test name
Test status
Simulation time 1457053482 ps
CPU time 5.73 seconds
Started Feb 18 02:14:00 PM PST 24
Finished Feb 18 02:14:47 PM PST 24
Peak memory 216032 kb
Host smart-f41ff9c1-ad76-4e66-b333-af4442ea31b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=577822332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.577822332
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1865818945
Short name T131
Test name
Test status
Simulation time 108370743539 ps
CPU time 751.45 seconds
Started Feb 18 02:14:14 PM PST 24
Finished Feb 18 02:27:31 PM PST 24
Peak memory 271016 kb
Host smart-f45350b9-6690-4666-b032-675cd1e839b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865818945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1865818945
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.878889175
Short name T948
Test name
Test status
Simulation time 4891285477 ps
CPU time 42.59 seconds
Started Feb 18 02:14:00 PM PST 24
Finished Feb 18 02:15:27 PM PST 24
Peak memory 216184 kb
Host smart-312d7b9f-41dc-4c0f-abc5-fcbc78fc9039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878889175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.878889175
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3538558698
Short name T572
Test name
Test status
Simulation time 1015466385 ps
CPU time 6.24 seconds
Started Feb 18 02:13:59 PM PST 24
Finished Feb 18 02:14:55 PM PST 24
Peak memory 207740 kb
Host smart-69581de9-6139-49b5-9ded-11d87eae5c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538558698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3538558698
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1183184520
Short name T872
Test name
Test status
Simulation time 564804225 ps
CPU time 10.66 seconds
Started Feb 18 02:13:59 PM PST 24
Finished Feb 18 02:14:51 PM PST 24
Peak memory 216328 kb
Host smart-d4a7b4ba-c640-4aa3-bc8b-8aa734d59d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183184520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1183184520
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3869353123
Short name T944
Test name
Test status
Simulation time 64055466 ps
CPU time 0.98 seconds
Started Feb 18 02:14:08 PM PST 24
Finished Feb 18 02:14:53 PM PST 24
Peak memory 205116 kb
Host smart-829b450f-7c3d-486d-ad21-4cf5f4f13ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869353123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3869353123
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1940701043
Short name T492
Test name
Test status
Simulation time 1035837595 ps
CPU time 5.54 seconds
Started Feb 18 02:13:58 PM PST 24
Finished Feb 18 02:14:49 PM PST 24
Peak memory 232996 kb
Host smart-3c9cc011-94c3-4641-9585-127494f3a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940701043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1940701043
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.594131173
Short name T665
Test name
Test status
Simulation time 12364321 ps
CPU time 0.69 seconds
Started Feb 18 02:14:21 PM PST 24
Finished Feb 18 02:15:07 PM PST 24
Peak memory 204676 kb
Host smart-d2b36ca1-c6d9-4415-a58b-eb8db6450d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594131173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.594131173
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3448708348
Short name T394
Test name
Test status
Simulation time 246713563 ps
CPU time 2.84 seconds
Started Feb 18 02:14:22 PM PST 24
Finished Feb 18 02:15:11 PM PST 24
Peak memory 233252 kb
Host smart-ee32b1f4-e85d-45d6-a2b8-dcc869e2b643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448708348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3448708348
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1890513405
Short name T282
Test name
Test status
Simulation time 19687169 ps
CPU time 0.78 seconds
Started Feb 18 02:14:12 PM PST 24
Finished Feb 18 02:14:58 PM PST 24
Peak memory 205864 kb
Host smart-9a4b4760-a466-446d-a3ad-77ad6072203b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890513405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1890513405
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1189527535
Short name T401
Test name
Test status
Simulation time 13693967179 ps
CPU time 60.4 seconds
Started Feb 18 02:14:21 PM PST 24
Finished Feb 18 02:16:06 PM PST 24
Peak memory 249216 kb
Host smart-87eeb82b-cb15-4d04-9a92-706f00dc5a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189527535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1189527535
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.62091098
Short name T549
Test name
Test status
Simulation time 35358001912 ps
CPU time 108.43 seconds
Started Feb 18 02:14:06 PM PST 24
Finished Feb 18 02:16:39 PM PST 24
Peak memory 256732 kb
Host smart-dfcf07d4-0a6c-4afe-8c3b-8946afe55d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62091098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.62091098
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_intercept.831166660
Short name T231
Test name
Test status
Simulation time 697812674 ps
CPU time 3.42 seconds
Started Feb 18 02:14:09 PM PST 24
Finished Feb 18 02:14:54 PM PST 24
Peak memory 216088 kb
Host smart-cc2d8420-51ab-47c2-8dbd-cddedd534ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831166660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.831166660
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.83446177
Short name T753
Test name
Test status
Simulation time 880902283 ps
CPU time 7.45 seconds
Started Feb 18 02:14:10 PM PST 24
Finished Feb 18 02:14:59 PM PST 24
Peak memory 232392 kb
Host smart-af5c6965-95c3-49cf-821b-0a0811c52e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83446177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.83446177
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3190635160
Short name T852
Test name
Test status
Simulation time 5356014758 ps
CPU time 9.91 seconds
Started Feb 18 02:14:09 PM PST 24
Finished Feb 18 02:15:03 PM PST 24
Peak memory 233288 kb
Host smart-8c8647ef-fd86-4fb0-af75-5a8eda2ecffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190635160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3190635160
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.904452226
Short name T156
Test name
Test status
Simulation time 3911730772 ps
CPU time 4.9 seconds
Started Feb 18 02:14:11 PM PST 24
Finished Feb 18 02:14:57 PM PST 24
Peak memory 217876 kb
Host smart-6bd2817b-2046-4024-8e96-7bc7b0d0d9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904452226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.904452226
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4172907379
Short name T765
Test name
Test status
Simulation time 3110138883 ps
CPU time 5.17 seconds
Started Feb 18 02:14:08 PM PST 24
Finished Feb 18 02:15:10 PM PST 24
Peak memory 221896 kb
Host smart-e539f754-2649-444c-a478-2b2823c9ad7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4172907379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4172907379
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2637168079
Short name T56
Test name
Test status
Simulation time 12002995596 ps
CPU time 49.54 seconds
Started Feb 18 02:14:07 PM PST 24
Finished Feb 18 02:15:40 PM PST 24
Peak memory 216148 kb
Host smart-dfbe355c-df22-47d2-93a6-76b5ef66b493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637168079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2637168079
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2591722599
Short name T882
Test name
Test status
Simulation time 9362621784 ps
CPU time 25.38 seconds
Started Feb 18 02:14:13 PM PST 24
Finished Feb 18 02:15:25 PM PST 24
Peak memory 217168 kb
Host smart-19a145cb-633b-421e-91c1-edd90213bf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591722599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2591722599
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2402799923
Short name T729
Test name
Test status
Simulation time 117518210 ps
CPU time 1.66 seconds
Started Feb 18 02:14:15 PM PST 24
Finished Feb 18 02:15:08 PM PST 24
Peak memory 216024 kb
Host smart-4da18cb6-35cc-4c55-992e-06956a247fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402799923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2402799923
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.659420366
Short name T287
Test name
Test status
Simulation time 44873759 ps
CPU time 0.83 seconds
Started Feb 18 02:14:10 PM PST 24
Finished Feb 18 02:14:52 PM PST 24
Peak memory 205120 kb
Host smart-cd271a9d-10f0-4045-91fe-79d05f613dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659420366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.659420366
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.552307381
Short name T118
Test name
Test status
Simulation time 10896139064 ps
CPU time 18.51 seconds
Started Feb 18 02:14:14 PM PST 24
Finished Feb 18 02:15:18 PM PST 24
Peak memory 233436 kb
Host smart-8aef2367-3295-4a96-9c30-c9f798fe2927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552307381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.552307381
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3252653309
Short name T469
Test name
Test status
Simulation time 18371111 ps
CPU time 0.77 seconds
Started Feb 18 02:14:16 PM PST 24
Finished Feb 18 02:15:05 PM PST 24
Peak memory 204652 kb
Host smart-695aa7d9-2082-42e9-8329-39c92e8be7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252653309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3252653309
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1369497831
Short name T265
Test name
Test status
Simulation time 18106589299 ps
CPU time 14.51 seconds
Started Feb 18 02:14:19 PM PST 24
Finished Feb 18 02:15:18 PM PST 24
Peak memory 219336 kb
Host smart-68147bd4-cb34-4484-b99f-2f9fa6c573d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369497831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1369497831
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2590633436
Short name T615
Test name
Test status
Simulation time 76498565 ps
CPU time 0.79 seconds
Started Feb 18 02:14:16 PM PST 24
Finished Feb 18 02:15:03 PM PST 24
Peak memory 205828 kb
Host smart-69792bc9-5970-4e99-a999-8175e22c2f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590633436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2590633436
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.566342982
Short name T687
Test name
Test status
Simulation time 98685288863 ps
CPU time 236.7 seconds
Started Feb 18 02:14:23 PM PST 24
Finished Feb 18 02:19:08 PM PST 24
Peak memory 255448 kb
Host smart-907c3ac5-e600-4562-b43a-6e375152166c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566342982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.566342982
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3117996057
Short name T959
Test name
Test status
Simulation time 5158859204 ps
CPU time 72.92 seconds
Started Feb 18 02:14:16 PM PST 24
Finished Feb 18 02:16:13 PM PST 24
Peak memory 254320 kb
Host smart-b4d5709a-6459-495d-8349-cb04f48d4190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117996057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3117996057
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4125714158
Short name T811
Test name
Test status
Simulation time 68209306929 ps
CPU time 163.64 seconds
Started Feb 18 02:14:14 PM PST 24
Finished Feb 18 02:17:40 PM PST 24
Peak memory 252532 kb
Host smart-c799304e-da92-43cd-a2c9-22b13614e850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125714158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4125714158
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3026026391
Short name T862
Test name
Test status
Simulation time 9867112867 ps
CPU time 17.28 seconds
Started Feb 18 02:14:19 PM PST 24
Finished Feb 18 02:15:21 PM PST 24
Peak memory 233400 kb
Host smart-af09162c-572f-4e7f-92c8-2b17eb3cafc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026026391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3026026391
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2126175116
Short name T746
Test name
Test status
Simulation time 9115805030 ps
CPU time 8.13 seconds
Started Feb 18 02:14:12 PM PST 24
Finished Feb 18 02:15:11 PM PST 24
Peak memory 232988 kb
Host smart-4934c634-501c-4f93-86dd-6705a6402de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126175116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2126175116
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3888029589
Short name T700
Test name
Test status
Simulation time 3066668253 ps
CPU time 6.9 seconds
Started Feb 18 02:14:17 PM PST 24
Finished Feb 18 02:15:07 PM PST 24
Peak memory 233480 kb
Host smart-23c905a4-fdda-47ab-8a86-e8386828c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888029589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3888029589
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.67706960
Short name T513
Test name
Test status
Simulation time 9153397043 ps
CPU time 7.31 seconds
Started Feb 18 02:14:18 PM PST 24
Finished Feb 18 02:15:21 PM PST 24
Peak memory 224360 kb
Host smart-3d1ef736-9ae9-4c83-9837-62144e7f4f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67706960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.67706960
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.590991700
Short name T829
Test name
Test status
Simulation time 13524570384 ps
CPU time 10.31 seconds
Started Feb 18 02:14:11 PM PST 24
Finished Feb 18 02:15:05 PM PST 24
Peak memory 228608 kb
Host smart-3c43af45-5b0a-41ab-850c-d5dc02d33a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590991700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.590991700
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1912099889
Short name T626
Test name
Test status
Simulation time 91155543 ps
CPU time 3.19 seconds
Started Feb 18 02:14:17 PM PST 24
Finished Feb 18 02:15:06 PM PST 24
Peak memory 222296 kb
Host smart-8c3f1a50-e460-4c2b-8474-836173a3cb18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1912099889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1912099889
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.788621651
Short name T465
Test name
Test status
Simulation time 15233252570 ps
CPU time 140.82 seconds
Started Feb 18 02:14:12 PM PST 24
Finished Feb 18 02:17:18 PM PST 24
Peak memory 250004 kb
Host smart-5deb6e38-9ffe-4938-a419-12a184c684c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788621651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.788621651
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.244730933
Short name T898
Test name
Test status
Simulation time 2398334388 ps
CPU time 7.98 seconds
Started Feb 18 02:14:25 PM PST 24
Finished Feb 18 02:15:18 PM PST 24
Peak memory 218776 kb
Host smart-c240556c-da65-4e07-8464-cdc11721d049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244730933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.244730933
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1174674481
Short name T644
Test name
Test status
Simulation time 2488466519 ps
CPU time 4.8 seconds
Started Feb 18 02:14:17 PM PST 24
Finished Feb 18 02:15:07 PM PST 24
Peak memory 216184 kb
Host smart-241a7b91-55a9-4b5a-8514-69e888d2d5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174674481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1174674481
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.871036782
Short name T336
Test name
Test status
Simulation time 45156529 ps
CPU time 0.91 seconds
Started Feb 18 02:14:24 PM PST 24
Finished Feb 18 02:15:12 PM PST 24
Peak memory 206124 kb
Host smart-8294c263-13b0-412b-8f64-5168460caa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871036782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.871036782
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2414977691
Short name T306
Test name
Test status
Simulation time 95431837 ps
CPU time 0.76 seconds
Started Feb 18 02:14:15 PM PST 24
Finished Feb 18 02:14:59 PM PST 24
Peak memory 205120 kb
Host smart-dcd54b5a-4eb5-4a48-adbf-5c3cff712a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414977691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2414977691
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1803363322
Short name T739
Test name
Test status
Simulation time 6435547166 ps
CPU time 14.74 seconds
Started Feb 18 02:14:15 PM PST 24
Finished Feb 18 02:15:21 PM PST 24
Peak memory 227600 kb
Host smart-469b3d3e-3dcb-466a-81fa-4d055dc56e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803363322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1803363322
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3748418706
Short name T407
Test name
Test status
Simulation time 11206270 ps
CPU time 0.68 seconds
Started Feb 18 02:14:33 PM PST 24
Finished Feb 18 02:15:33 PM PST 24
Peak memory 205060 kb
Host smart-25718da6-bcaf-4e6d-bb48-7c163d7a89fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748418706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3748418706
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3494056060
Short name T927
Test name
Test status
Simulation time 862854322 ps
CPU time 3.25 seconds
Started Feb 18 02:14:21 PM PST 24
Finished Feb 18 02:15:08 PM PST 24
Peak memory 217492 kb
Host smart-904b01cf-96ff-41a8-9ad1-1c6bc79ebdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494056060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3494056060
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.689891976
Short name T906
Test name
Test status
Simulation time 17316726 ps
CPU time 0.73 seconds
Started Feb 18 02:14:18 PM PST 24
Finished Feb 18 02:15:12 PM PST 24
Peak memory 205100 kb
Host smart-634d58fa-f6f6-4c6b-984f-981e45ce5ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689891976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.689891976
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2425091693
Short name T240
Test name
Test status
Simulation time 3443305620 ps
CPU time 12.55 seconds
Started Feb 18 02:14:26 PM PST 24
Finished Feb 18 02:15:24 PM PST 24
Peak memory 234004 kb
Host smart-59adf93d-ab96-4997-8643-c1da94ca1459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425091693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2425091693
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2571082422
Short name T501
Test name
Test status
Simulation time 19003837606 ps
CPU time 19.1 seconds
Started Feb 18 02:14:30 PM PST 24
Finished Feb 18 02:15:43 PM PST 24
Peak memory 222104 kb
Host smart-0b23902b-ff1c-4f27-8494-c60e25792a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571082422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2571082422
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2894814005
Short name T873
Test name
Test status
Simulation time 3394160937 ps
CPU time 11.05 seconds
Started Feb 18 02:14:29 PM PST 24
Finished Feb 18 02:15:26 PM PST 24
Peak memory 233300 kb
Host smart-9107644a-3f4c-4993-b7d2-a770ef89591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894814005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2894814005
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2197427557
Short name T663
Test name
Test status
Simulation time 1903373125 ps
CPU time 7.21 seconds
Started Feb 18 02:14:17 PM PST 24
Finished Feb 18 02:15:07 PM PST 24
Peak memory 217624 kb
Host smart-d2ce942e-e1c3-4c20-87c1-a741358f8368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197427557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2197427557
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.729613708
Short name T868
Test name
Test status
Simulation time 1361804597 ps
CPU time 4.12 seconds
Started Feb 18 02:14:37 PM PST 24
Finished Feb 18 02:15:30 PM PST 24
Peak memory 218512 kb
Host smart-714c8091-5261-4c3d-8831-18d44ddc51d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=729613708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.729613708
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1840803915
Short name T173
Test name
Test status
Simulation time 245275938407 ps
CPU time 531.08 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:24:13 PM PST 24
Peak memory 281832 kb
Host smart-11151e9b-d46f-42ac-9d83-4b3f77180be4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840803915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1840803915
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3225793785
Short name T62
Test name
Test status
Simulation time 4841530232 ps
CPU time 7.62 seconds
Started Feb 18 02:14:19 PM PST 24
Finished Feb 18 02:15:21 PM PST 24
Peak memory 216092 kb
Host smart-0da7deeb-946b-4fed-b4b3-c842f9313f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225793785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3225793785
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.500092612
Short name T415
Test name
Test status
Simulation time 2497594348 ps
CPU time 9.59 seconds
Started Feb 18 02:14:32 PM PST 24
Finished Feb 18 02:15:28 PM PST 24
Peak memory 215412 kb
Host smart-834f3c9a-4657-4345-bd75-3e8455e9235d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500092612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.500092612
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3514978006
Short name T273
Test name
Test status
Simulation time 465807277 ps
CPU time 1.73 seconds
Started Feb 18 02:14:30 PM PST 24
Finished Feb 18 02:15:18 PM PST 24
Peak memory 216340 kb
Host smart-9ae4ed9b-e1ba-46ad-8810-052f3874a506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514978006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3514978006
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2429840482
Short name T425
Test name
Test status
Simulation time 68445754 ps
CPU time 0.78 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:15:25 PM PST 24
Peak memory 205076 kb
Host smart-ffd09a74-1f5b-4580-811e-2c37dc58aa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429840482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2429840482
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3755808947
Short name T914
Test name
Test status
Simulation time 7480640447 ps
CPU time 11.24 seconds
Started Feb 18 02:14:38 PM PST 24
Finished Feb 18 02:15:37 PM PST 24
Peak memory 234440 kb
Host smart-50d3f975-49fb-4555-b052-ba11bbecf789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755808947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3755808947
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.286293038
Short name T524
Test name
Test status
Simulation time 25314642 ps
CPU time 0.69 seconds
Started Feb 18 02:14:30 PM PST 24
Finished Feb 18 02:15:17 PM PST 24
Peak memory 205028 kb
Host smart-79e2dcc8-85de-4618-8800-5915d35ed85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286293038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.286293038
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1732827483
Short name T473
Test name
Test status
Simulation time 2459519773 ps
CPU time 8.69 seconds
Started Feb 18 02:14:37 PM PST 24
Finished Feb 18 02:15:35 PM PST 24
Peak memory 218860 kb
Host smart-e146483f-e183-480a-aa38-73fd4b4daf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732827483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1732827483
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.611234126
Short name T443
Test name
Test status
Simulation time 17968219 ps
CPU time 0.77 seconds
Started Feb 18 02:14:27 PM PST 24
Finished Feb 18 02:15:13 PM PST 24
Peak memory 204852 kb
Host smart-42141698-b0bf-43e2-b3a2-c6befd0cfd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611234126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.611234126
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1196661145
Short name T551
Test name
Test status
Simulation time 33176317188 ps
CPU time 41.17 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:16:03 PM PST 24
Peak memory 222060 kb
Host smart-964b31c8-5825-44e3-8459-c3bf08394b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196661145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1196661145
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3429717025
Short name T311
Test name
Test status
Simulation time 25687160116 ps
CPU time 62.8 seconds
Started Feb 18 02:14:32 PM PST 24
Finished Feb 18 02:16:21 PM PST 24
Peak memory 255096 kb
Host smart-5cc449f4-eaed-4643-93e2-1272480fbfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429717025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3429717025
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1264308975
Short name T109
Test name
Test status
Simulation time 23543982244 ps
CPU time 60.6 seconds
Started Feb 18 02:14:31 PM PST 24
Finished Feb 18 02:16:18 PM PST 24
Peak memory 248980 kb
Host smart-09a48966-fa76-437d-9940-c68caf57ddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264308975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1264308975
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2917241813
Short name T669
Test name
Test status
Simulation time 4426173201 ps
CPU time 11.52 seconds
Started Feb 18 02:14:47 PM PST 24
Finished Feb 18 02:15:48 PM PST 24
Peak memory 237604 kb
Host smart-313d165e-dce0-48ec-bb05-f54a1dc91976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917241813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2917241813
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3458395215
Short name T731
Test name
Test status
Simulation time 602740607 ps
CPU time 3.42 seconds
Started Feb 18 02:14:42 PM PST 24
Finished Feb 18 02:15:34 PM PST 24
Peak memory 217272 kb
Host smart-d04fad0d-f1dc-4744-995f-69aedc62df66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458395215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3458395215
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3952571020
Short name T590
Test name
Test status
Simulation time 84599005222 ps
CPU time 50.59 seconds
Started Feb 18 02:14:42 PM PST 24
Finished Feb 18 02:16:22 PM PST 24
Peak memory 232468 kb
Host smart-c6d1c000-255d-4e38-9a80-03e356b158ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952571020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3952571020
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2553963815
Short name T358
Test name
Test status
Simulation time 846684100 ps
CPU time 6.4 seconds
Started Feb 18 02:14:29 PM PST 24
Finished Feb 18 02:15:25 PM PST 24
Peak memory 228752 kb
Host smart-d7b1f6e2-894b-4d44-832c-35f674e99aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553963815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2553963815
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1432568354
Short name T157
Test name
Test status
Simulation time 3131480195 ps
CPU time 4 seconds
Started Feb 18 02:14:27 PM PST 24
Finished Feb 18 02:15:18 PM PST 24
Peak memory 217768 kb
Host smart-147d261b-638b-4983-b9b5-11d5d5292cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432568354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1432568354
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.794193551
Short name T610
Test name
Test status
Simulation time 1652673772 ps
CPU time 4.96 seconds
Started Feb 18 02:14:35 PM PST 24
Finished Feb 18 02:15:26 PM PST 24
Peak memory 220396 kb
Host smart-c60441d1-8213-4743-bdf4-d159859bfeb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=794193551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.794193551
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.352829137
Short name T951
Test name
Test status
Simulation time 9311813749 ps
CPU time 80.38 seconds
Started Feb 18 02:14:37 PM PST 24
Finished Feb 18 02:16:44 PM PST 24
Peak memory 240508 kb
Host smart-13a8f421-f112-4b44-83fe-a2bb11a33be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352829137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.352829137
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.837246729
Short name T328
Test name
Test status
Simulation time 7318500974 ps
CPU time 25.31 seconds
Started Feb 18 02:14:28 PM PST 24
Finished Feb 18 02:15:50 PM PST 24
Peak memory 216180 kb
Host smart-1dba2e4e-faa2-486a-b27b-e1fcd0d6db70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837246729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.837246729
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1482108339
Short name T625
Test name
Test status
Simulation time 1237352608 ps
CPU time 4.4 seconds
Started Feb 18 02:14:19 PM PST 24
Finished Feb 18 02:15:18 PM PST 24
Peak memory 216052 kb
Host smart-174aa28c-54d2-4745-80e2-4ef4a0069185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482108339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1482108339
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4257904003
Short name T511
Test name
Test status
Simulation time 66988539 ps
CPU time 1.14 seconds
Started Feb 18 02:14:26 PM PST 24
Finished Feb 18 02:15:21 PM PST 24
Peak memory 207124 kb
Host smart-17799d5a-8351-4b9e-9e28-47bbd026ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257904003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4257904003
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.297849027
Short name T272
Test name
Test status
Simulation time 184509588 ps
CPU time 0.88 seconds
Started Feb 18 02:14:32 PM PST 24
Finished Feb 18 02:15:19 PM PST 24
Peak memory 205116 kb
Host smart-94dd0906-5246-4cd5-8f1e-59db189654f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297849027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.297849027
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1836264747
Short name T424
Test name
Test status
Simulation time 207037953 ps
CPU time 2.66 seconds
Started Feb 18 02:14:29 PM PST 24
Finished Feb 18 02:15:21 PM PST 24
Peak memory 218324 kb
Host smart-c646569d-d3ec-4670-bff2-2be86c55fb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836264747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1836264747
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2289142767
Short name T602
Test name
Test status
Simulation time 46677609 ps
CPU time 0.74 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:15:25 PM PST 24
Peak memory 205028 kb
Host smart-f202b09a-8dcf-40df-8158-87112086c711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289142767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2289142767
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3876687528
Short name T242
Test name
Test status
Simulation time 2362762863 ps
CPU time 5.26 seconds
Started Feb 18 02:14:35 PM PST 24
Finished Feb 18 02:15:27 PM PST 24
Peak memory 234084 kb
Host smart-e44d3a3b-8f00-48f3-8896-4fff6cd9969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876687528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3876687528
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3950389370
Short name T817
Test name
Test status
Simulation time 13556152 ps
CPU time 0.76 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:15:28 PM PST 24
Peak memory 204856 kb
Host smart-6d280f7f-3d4c-4535-8f5d-0519c8031d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950389370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3950389370
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.456255319
Short name T327
Test name
Test status
Simulation time 4530685409 ps
CPU time 42.87 seconds
Started Feb 18 02:14:30 PM PST 24
Finished Feb 18 02:16:07 PM PST 24
Peak memory 240528 kb
Host smart-d15328e8-635f-4d64-a1ce-6aa4a686ab32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456255319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.456255319
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2266894476
Short name T30
Test name
Test status
Simulation time 91761278983 ps
CPU time 187.34 seconds
Started Feb 18 02:14:30 PM PST 24
Finished Feb 18 02:18:24 PM PST 24
Peak memory 255644 kb
Host smart-674646ae-594c-4581-a0b0-4f523c4efead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266894476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2266894476
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3501186619
Short name T645
Test name
Test status
Simulation time 126081058321 ps
CPU time 249.39 seconds
Started Feb 18 02:14:34 PM PST 24
Finished Feb 18 02:19:31 PM PST 24
Peak memory 253624 kb
Host smart-86552900-1996-4cbb-9ff5-9e9bd17faa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501186619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3501186619
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.788903077
Short name T116
Test name
Test status
Simulation time 811485518 ps
CPU time 9.26 seconds
Started Feb 18 02:14:47 PM PST 24
Finished Feb 18 02:15:46 PM PST 24
Peak memory 235104 kb
Host smart-085add26-e9a5-4739-85cc-2261562de5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788903077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.788903077
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3367303732
Short name T309
Test name
Test status
Simulation time 657212673 ps
CPU time 3.72 seconds
Started Feb 18 02:14:32 PM PST 24
Finished Feb 18 02:15:22 PM PST 24
Peak memory 215452 kb
Host smart-c7b41a39-e9eb-48e1-9290-a9674866cc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367303732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3367303732
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2188123259
Short name T699
Test name
Test status
Simulation time 2777567992 ps
CPU time 3.97 seconds
Started Feb 18 02:14:31 PM PST 24
Finished Feb 18 02:15:24 PM PST 24
Peak memory 233568 kb
Host smart-184484c9-1e11-4664-8be9-5c2e2595b78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188123259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2188123259
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3790217403
Short name T250
Test name
Test status
Simulation time 746415680 ps
CPU time 3.81 seconds
Started Feb 18 02:14:27 PM PST 24
Finished Feb 18 02:15:16 PM PST 24
Peak memory 216484 kb
Host smart-4b460c3c-cda2-4ad9-88a4-19dfbe435992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790217403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3790217403
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2480471309
Short name T168
Test name
Test status
Simulation time 7931882321 ps
CPU time 6.02 seconds
Started Feb 18 02:14:30 PM PST 24
Finished Feb 18 02:15:29 PM PST 24
Peak memory 233300 kb
Host smart-d85f271a-fb21-4b5c-b1b7-2589908585c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480471309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2480471309
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2774280335
Short name T352
Test name
Test status
Simulation time 2527171725 ps
CPU time 5.31 seconds
Started Feb 18 02:14:31 PM PST 24
Finished Feb 18 02:15:26 PM PST 24
Peak memory 221728 kb
Host smart-bcb2542b-60c9-425b-b8f1-50a8066a29b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2774280335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2774280335
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3918053388
Short name T256
Test name
Test status
Simulation time 17335304612 ps
CPU time 13.41 seconds
Started Feb 18 02:14:35 PM PST 24
Finished Feb 18 02:15:36 PM PST 24
Peak memory 216188 kb
Host smart-a2e47867-8cdf-4ed1-8436-70881c235c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918053388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3918053388
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1982828100
Short name T606
Test name
Test status
Simulation time 6484970581 ps
CPU time 7.61 seconds
Started Feb 18 02:14:30 PM PST 24
Finished Feb 18 02:15:24 PM PST 24
Peak memory 216176 kb
Host smart-dc35501d-6aaa-4e41-8dd1-26f4c086ef4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982828100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1982828100
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2846040896
Short name T570
Test name
Test status
Simulation time 69682193 ps
CPU time 2.74 seconds
Started Feb 18 02:14:34 PM PST 24
Finished Feb 18 02:15:29 PM PST 24
Peak memory 216112 kb
Host smart-9616f3ab-8ec1-4656-a15d-ff066bab40cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846040896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2846040896
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.879169632
Short name T827
Test name
Test status
Simulation time 153221520 ps
CPU time 1.2 seconds
Started Feb 18 02:14:28 PM PST 24
Finished Feb 18 02:15:26 PM PST 24
Peak memory 205108 kb
Host smart-bf33b03a-c41d-4a1b-b907-028b777e2c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879169632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.879169632
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3473107973
Short name T24
Test name
Test status
Simulation time 147280442829 ps
CPU time 37.08 seconds
Started Feb 18 02:14:34 PM PST 24
Finished Feb 18 02:15:59 PM PST 24
Peak memory 233204 kb
Host smart-292be88b-74c8-4dbe-a3ce-0e3a1722e02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473107973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3473107973
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.549614519
Short name T623
Test name
Test status
Simulation time 13197773 ps
CPU time 0.71 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:15:27 PM PST 24
Peak memory 204720 kb
Host smart-e44f91f9-371d-4d94-a318-fb248af7bc31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549614519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.549614519
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1845343726
Short name T714
Test name
Test status
Simulation time 398412977 ps
CPU time 2.9 seconds
Started Feb 18 02:14:41 PM PST 24
Finished Feb 18 02:15:31 PM PST 24
Peak memory 224172 kb
Host smart-75934e7d-bb36-4bed-935c-6b4c465ef04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845343726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1845343726
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.4277917680
Short name T491
Test name
Test status
Simulation time 70920208 ps
CPU time 0.77 seconds
Started Feb 18 02:14:31 PM PST 24
Finished Feb 18 02:15:26 PM PST 24
Peak memory 205140 kb
Host smart-24435ec2-eef3-4436-82c0-d35e4d658874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277917680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4277917680
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.491469454
Short name T462
Test name
Test status
Simulation time 14727845776 ps
CPU time 79.55 seconds
Started Feb 18 02:14:40 PM PST 24
Finished Feb 18 02:16:49 PM PST 24
Peak memory 240752 kb
Host smart-00bd338d-6255-48d0-b478-6dfc043ca04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491469454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.491469454
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2267007403
Short name T375
Test name
Test status
Simulation time 14979159571 ps
CPU time 74.34 seconds
Started Feb 18 02:14:41 PM PST 24
Finished Feb 18 02:16:45 PM PST 24
Peak memory 250848 kb
Host smart-047434b1-ef7c-400f-a514-7a04d357ba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267007403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2267007403
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3869885365
Short name T204
Test name
Test status
Simulation time 20976680413 ps
CPU time 88.66 seconds
Started Feb 18 02:14:42 PM PST 24
Finished Feb 18 02:17:00 PM PST 24
Peak memory 256888 kb
Host smart-63e03594-af19-4d76-9a05-a199b4069c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869885365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3869885365
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.218865512
Short name T279
Test name
Test status
Simulation time 4057564831 ps
CPU time 7.8 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:15:35 PM PST 24
Peak memory 234664 kb
Host smart-701c0692-a931-4e5b-b65e-ae6a8b89b393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218865512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.218865512
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4102762468
Short name T557
Test name
Test status
Simulation time 2822001748 ps
CPU time 7.54 seconds
Started Feb 18 02:14:30 PM PST 24
Finished Feb 18 02:15:31 PM PST 24
Peak memory 233328 kb
Host smart-5f2812be-6542-4839-a865-6a7c376b354d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102762468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4102762468
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1684319740
Short name T333
Test name
Test status
Simulation time 15539946103 ps
CPU time 40.53 seconds
Started Feb 18 02:14:29 PM PST 24
Finished Feb 18 02:15:58 PM PST 24
Peak memory 240604 kb
Host smart-b6345db8-66f5-458c-bbcf-0ef6bdf2b01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684319740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1684319740
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.635816630
Short name T556
Test name
Test status
Simulation time 220836033 ps
CPU time 2.19 seconds
Started Feb 18 02:14:31 PM PST 24
Finished Feb 18 02:15:23 PM PST 24
Peak memory 224156 kb
Host smart-3f56eba8-ceb7-47ea-bfab-40e0a16b71a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635816630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.635816630
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1641559004
Short name T296
Test name
Test status
Simulation time 2574689234 ps
CPU time 7.98 seconds
Started Feb 18 02:14:37 PM PST 24
Finished Feb 18 02:15:31 PM PST 24
Peak memory 217484 kb
Host smart-921ac1e4-c390-45e5-8c5b-64590e2a3125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641559004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1641559004
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3401154796
Short name T325
Test name
Test status
Simulation time 651666877 ps
CPU time 5.02 seconds
Started Feb 18 02:14:40 PM PST 24
Finished Feb 18 02:15:34 PM PST 24
Peak memory 222176 kb
Host smart-6280c621-3e2e-45a5-8a8d-47427b8ff06b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3401154796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3401154796
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1693096304
Short name T67
Test name
Test status
Simulation time 62238405958 ps
CPU time 448.93 seconds
Started Feb 18 02:14:41 PM PST 24
Finished Feb 18 02:23:00 PM PST 24
Peak memory 266412 kb
Host smart-35ca82e3-3505-4e56-939d-c49f90d5ba61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693096304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1693096304
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2478882005
Short name T573
Test name
Test status
Simulation time 2510216067 ps
CPU time 27.42 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:15:54 PM PST 24
Peak memory 216216 kb
Host smart-6b68bf59-e0d9-4df5-86e9-f432e61e5184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478882005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2478882005
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2343523126
Short name T14
Test name
Test status
Simulation time 2422029758 ps
CPU time 7.31 seconds
Started Feb 18 02:14:47 PM PST 24
Finished Feb 18 02:15:44 PM PST 24
Peak memory 216208 kb
Host smart-8906563b-7cbe-40b3-ae2f-42f9e459ff25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343523126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2343523126
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1169573378
Short name T555
Test name
Test status
Simulation time 28154281 ps
CPU time 0.74 seconds
Started Feb 18 02:14:30 PM PST 24
Finished Feb 18 02:15:20 PM PST 24
Peak memory 205132 kb
Host smart-61db2d31-8e8b-4c88-94f8-3406613015eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169573378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1169573378
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3327274973
Short name T512
Test name
Test status
Simulation time 106045663 ps
CPU time 0.86 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:15:27 PM PST 24
Peak memory 205088 kb
Host smart-97ccd9dc-61a4-4fb7-80d5-1852b530ca33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327274973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3327274973
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.607189322
Short name T541
Test name
Test status
Simulation time 35016445209 ps
CPU time 17.55 seconds
Started Feb 18 02:14:40 PM PST 24
Finished Feb 18 02:15:47 PM PST 24
Peak memory 229336 kb
Host smart-2765fd2a-8a71-4665-ab62-78ef60a5bfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607189322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.607189322
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2431685026
Short name T459
Test name
Test status
Simulation time 37583663 ps
CPU time 0.73 seconds
Started Feb 18 02:12:32 PM PST 24
Finished Feb 18 02:13:14 PM PST 24
Peak memory 204096 kb
Host smart-72ba3b2a-5122-44c6-a399-94b94a2169f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431685026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
431685026
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1731112360
Short name T383
Test name
Test status
Simulation time 661751472 ps
CPU time 3.17 seconds
Started Feb 18 02:12:30 PM PST 24
Finished Feb 18 02:13:13 PM PST 24
Peak memory 224184 kb
Host smart-354e19e3-0242-4acc-8070-eb49d0738c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731112360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1731112360
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1157145824
Short name T803
Test name
Test status
Simulation time 85236483 ps
CPU time 0.75 seconds
Started Feb 18 02:12:24 PM PST 24
Finished Feb 18 02:13:01 PM PST 24
Peak memory 204844 kb
Host smart-0b38f989-6378-49f8-bacf-3d768c1bf2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157145824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1157145824
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.127324517
Short name T388
Test name
Test status
Simulation time 7021192697 ps
CPU time 32.26 seconds
Started Feb 18 02:12:37 PM PST 24
Finished Feb 18 02:13:50 PM PST 24
Peak memory 218760 kb
Host smart-c5f9e678-5c8e-4ea8-a4bd-4b3db4eac100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127324517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.127324517
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1539548791
Short name T363
Test name
Test status
Simulation time 41883470426 ps
CPU time 55.74 seconds
Started Feb 18 02:12:28 PM PST 24
Finished Feb 18 02:14:03 PM PST 24
Peak memory 252692 kb
Host smart-f1841b7b-993c-4481-8b73-131c48362b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539548791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1539548791
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1769156798
Short name T636
Test name
Test status
Simulation time 9863846499 ps
CPU time 17.68 seconds
Started Feb 18 02:12:27 PM PST 24
Finished Feb 18 02:13:23 PM PST 24
Peak memory 235180 kb
Host smart-a9eb6113-f2b4-4c90-bf0b-8ea6511f78e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769156798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1769156798
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.833112915
Short name T313
Test name
Test status
Simulation time 270792294 ps
CPU time 2.91 seconds
Started Feb 18 02:12:18 PM PST 24
Finished Feb 18 02:12:54 PM PST 24
Peak memory 217092 kb
Host smart-5ec12aa0-2c34-40c1-b5bf-2fbd817b47c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833112915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.833112915
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2423419067
Short name T158
Test name
Test status
Simulation time 3781845446 ps
CPU time 11.93 seconds
Started Feb 18 02:12:37 PM PST 24
Finished Feb 18 02:13:31 PM PST 24
Peak memory 232596 kb
Host smart-c4225719-2ccf-457b-b149-0d6d195a7da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423419067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2423419067
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1788210767
Short name T433
Test name
Test status
Simulation time 60416833 ps
CPU time 1.09 seconds
Started Feb 18 02:12:26 PM PST 24
Finished Feb 18 02:13:04 PM PST 24
Peak memory 216316 kb
Host smart-81bb6c21-2017-4901-a58a-0651a5e5eb03
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788210767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1788210767
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.998559315
Short name T222
Test name
Test status
Simulation time 6435736866 ps
CPU time 21.81 seconds
Started Feb 18 02:12:29 PM PST 24
Finished Feb 18 02:13:31 PM PST 24
Peak memory 232668 kb
Host smart-113af107-7d9f-44c6-a607-3f7db9429335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998559315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
998559315
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3553280578
Short name T349
Test name
Test status
Simulation time 1640620790 ps
CPU time 3.77 seconds
Started Feb 18 02:12:23 PM PST 24
Finished Feb 18 02:13:03 PM PST 24
Peak memory 232748 kb
Host smart-ee99ef44-0967-4ae7-a20d-97dcc25af97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553280578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3553280578
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.674963661
Short name T46
Test name
Test status
Simulation time 18563573 ps
CPU time 0.75 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:13:04 PM PST 24
Peak memory 216000 kb
Host smart-ea0e6c7b-4ef1-4064-82d6-aa8206905a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674963661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.674963661
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3242518076
Short name T631
Test name
Test status
Simulation time 764175849 ps
CPU time 4.41 seconds
Started Feb 18 02:12:27 PM PST 24
Finished Feb 18 02:13:10 PM PST 24
Peak memory 216160 kb
Host smart-542610ce-710e-49c5-a853-6c6a3b08cf5f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3242518076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3242518076
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.73108103
Short name T49
Test name
Test status
Simulation time 143135351 ps
CPU time 0.92 seconds
Started Feb 18 02:12:36 PM PST 24
Finished Feb 18 02:13:18 PM PST 24
Peak memory 234812 kb
Host smart-fc99b078-a13d-4dff-907b-73cfaae9e292
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73108103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.73108103
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2712016903
Short name T423
Test name
Test status
Simulation time 24247519494 ps
CPU time 76.12 seconds
Started Feb 18 02:12:28 PM PST 24
Finished Feb 18 02:14:24 PM PST 24
Peak memory 249036 kb
Host smart-cf748947-a729-4dfc-b719-a06d067f8de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712016903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2712016903
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2995821373
Short name T966
Test name
Test status
Simulation time 2073895308 ps
CPU time 13.4 seconds
Started Feb 18 02:12:29 PM PST 24
Finished Feb 18 02:13:22 PM PST 24
Peak memory 216056 kb
Host smart-53a55242-b779-49b1-b482-c959b67f1063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995821373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2995821373
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3453207150
Short name T935
Test name
Test status
Simulation time 16352606358 ps
CPU time 10.75 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:13:12 PM PST 24
Peak memory 216160 kb
Host smart-11433163-434e-42dd-a067-113656b29ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453207150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3453207150
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3525941798
Short name T931
Test name
Test status
Simulation time 21733619 ps
CPU time 1.01 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:13:03 PM PST 24
Peak memory 207148 kb
Host smart-2a7b65fc-367c-4064-a1fa-96628747837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525941798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3525941798
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3428659191
Short name T582
Test name
Test status
Simulation time 53506307 ps
CPU time 0.7 seconds
Started Feb 18 02:12:30 PM PST 24
Finished Feb 18 02:13:10 PM PST 24
Peak memory 205092 kb
Host smart-44f7b08a-a792-45b7-9cea-3a5f323493d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428659191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3428659191
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2657248471
Short name T659
Test name
Test status
Simulation time 403456685 ps
CPU time 2.5 seconds
Started Feb 18 02:12:28 PM PST 24
Finished Feb 18 02:13:10 PM PST 24
Peak memory 216032 kb
Host smart-5920469e-e740-43f6-a5ed-d19f3fbc86f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657248471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2657248471
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2550884392
Short name T707
Test name
Test status
Simulation time 13343992 ps
CPU time 0.72 seconds
Started Feb 18 02:14:47 PM PST 24
Finished Feb 18 02:15:40 PM PST 24
Peak memory 205052 kb
Host smart-209ab4a4-0ca4-4eb5-b14a-41e65eac9457
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550884392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2550884392
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1067827928
Short name T650
Test name
Test status
Simulation time 488974554 ps
CPU time 4.61 seconds
Started Feb 18 02:14:52 PM PST 24
Finished Feb 18 02:15:44 PM PST 24
Peak memory 233332 kb
Host smart-00ec5293-5799-461b-9686-65050d5fd90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067827928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1067827928
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3095760659
Short name T713
Test name
Test status
Simulation time 17607839 ps
CPU time 0.79 seconds
Started Feb 18 02:14:52 PM PST 24
Finished Feb 18 02:15:39 PM PST 24
Peak memory 204816 kb
Host smart-fd699d06-07f3-4c7a-bfca-f3fd5185c414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095760659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3095760659
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.877322101
Short name T23
Test name
Test status
Simulation time 6633416389 ps
CPU time 15.15 seconds
Started Feb 18 02:14:49 PM PST 24
Finished Feb 18 02:15:53 PM PST 24
Peak memory 233532 kb
Host smart-afc51d6a-abd4-4fd7-8373-d8f2987a9d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877322101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.877322101
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2345873626
Short name T847
Test name
Test status
Simulation time 174270240973 ps
CPU time 148.55 seconds
Started Feb 18 02:14:49 PM PST 24
Finished Feb 18 02:18:04 PM PST 24
Peak memory 253836 kb
Host smart-d0f20a87-e868-461c-ac81-3cfbdae4a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345873626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2345873626
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.35539381
Short name T170
Test name
Test status
Simulation time 10567605433 ps
CPU time 66.57 seconds
Started Feb 18 02:14:47 PM PST 24
Finished Feb 18 02:16:41 PM PST 24
Peak memory 236644 kb
Host smart-619b4d16-3b87-47de-8a69-d335a793b8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35539381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.35539381
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1851339822
Short name T374
Test name
Test status
Simulation time 1375548988 ps
CPU time 14.51 seconds
Started Feb 18 02:14:48 PM PST 24
Finished Feb 18 02:15:51 PM PST 24
Peak memory 240640 kb
Host smart-244e82f9-71ba-482f-8f8f-f4bae396c1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851339822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1851339822
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4044144115
Short name T536
Test name
Test status
Simulation time 19823320267 ps
CPU time 13.77 seconds
Started Feb 18 02:14:39 PM PST 24
Finished Feb 18 02:15:40 PM PST 24
Peak memory 219128 kb
Host smart-ed0a86fb-59ff-456e-9c53-363b3d011ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044144115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4044144115
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2199654378
Short name T836
Test name
Test status
Simulation time 1279863971 ps
CPU time 6.56 seconds
Started Feb 18 02:14:48 PM PST 24
Finished Feb 18 02:15:41 PM PST 24
Peak memory 235512 kb
Host smart-51775f84-8c37-4d78-be2f-3a499faa5096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199654378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2199654378
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4278048155
Short name T198
Test name
Test status
Simulation time 11361922059 ps
CPU time 30.98 seconds
Started Feb 18 02:14:38 PM PST 24
Finished Feb 18 02:15:56 PM PST 24
Peak memory 228336 kb
Host smart-e9af8259-df83-495f-ad9d-cac785db9c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278048155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4278048155
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.477739891
Short name T821
Test name
Test status
Simulation time 2735665416 ps
CPU time 11 seconds
Started Feb 18 02:14:40 PM PST 24
Finished Feb 18 02:15:38 PM PST 24
Peak memory 233540 kb
Host smart-b0281143-4321-4365-9905-d6d527cd5fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477739891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.477739891
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.810476300
Short name T464
Test name
Test status
Simulation time 141684858 ps
CPU time 3.06 seconds
Started Feb 18 02:14:48 PM PST 24
Finished Feb 18 02:15:38 PM PST 24
Peak memory 216136 kb
Host smart-9bf0006c-e81e-4ac0-8134-402dde9e4f65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=810476300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.810476300
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3581340871
Short name T886
Test name
Test status
Simulation time 155789912 ps
CPU time 1.13 seconds
Started Feb 18 02:14:51 PM PST 24
Finished Feb 18 02:15:40 PM PST 24
Peak memory 206300 kb
Host smart-4bfb4201-3ae8-4084-abc7-4df9e2da6553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581340871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3581340871
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1653072716
Short name T861
Test name
Test status
Simulation time 590916723 ps
CPU time 5.45 seconds
Started Feb 18 02:14:44 PM PST 24
Finished Feb 18 02:15:40 PM PST 24
Peak memory 215936 kb
Host smart-105a0a42-6a48-4bb3-a6bc-4ed6b01d3b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653072716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1653072716
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2739989739
Short name T410
Test name
Test status
Simulation time 258731259 ps
CPU time 1.81 seconds
Started Feb 18 02:14:36 PM PST 24
Finished Feb 18 02:15:29 PM PST 24
Peak memory 206460 kb
Host smart-5792d186-db00-49a0-9173-f18dcd90af9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739989739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2739989739
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.694198631
Short name T342
Test name
Test status
Simulation time 22836976 ps
CPU time 0.94 seconds
Started Feb 18 02:14:39 PM PST 24
Finished Feb 18 02:15:27 PM PST 24
Peak memory 206472 kb
Host smart-a9654f33-d5f8-4079-8da3-ef462b80fa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694198631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.694198631
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.242502786
Short name T641
Test name
Test status
Simulation time 190162834 ps
CPU time 0.99 seconds
Started Feb 18 02:14:38 PM PST 24
Finished Feb 18 02:15:27 PM PST 24
Peak memory 205432 kb
Host smart-31404b56-964e-4e33-9b46-64e2ca5beb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242502786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.242502786
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2972670587
Short name T517
Test name
Test status
Simulation time 33241970391 ps
CPU time 8.74 seconds
Started Feb 18 02:14:48 PM PST 24
Finished Feb 18 02:15:45 PM PST 24
Peak memory 234384 kb
Host smart-7a1a0ea6-f631-4336-b04a-ade95acc7e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972670587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2972670587
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.729159774
Short name T627
Test name
Test status
Simulation time 91730794 ps
CPU time 0.72 seconds
Started Feb 18 02:14:54 PM PST 24
Finished Feb 18 02:15:40 PM PST 24
Peak memory 204132 kb
Host smart-f7e9182a-6ea4-436e-b498-7aa65bc45560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729159774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.729159774
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.362802848
Short name T414
Test name
Test status
Simulation time 368756621 ps
CPU time 2.14 seconds
Started Feb 18 02:14:47 PM PST 24
Finished Feb 18 02:15:39 PM PST 24
Peak memory 224168 kb
Host smart-1d6fd1bd-35d5-46cc-ad0f-cd39cb87049f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362802848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.362802848
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2730441590
Short name T467
Test name
Test status
Simulation time 16066013 ps
CPU time 0.76 seconds
Started Feb 18 02:14:48 PM PST 24
Finished Feb 18 02:15:37 PM PST 24
Peak memory 205144 kb
Host smart-1654168b-7d2e-4591-a0c8-e16423573ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730441590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2730441590
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.4153728275
Short name T142
Test name
Test status
Simulation time 50507097624 ps
CPU time 70.61 seconds
Started Feb 18 02:14:48 PM PST 24
Finished Feb 18 02:16:45 PM PST 24
Peak memory 240740 kb
Host smart-4e6b363a-d69b-42c2-86e5-48b15ff137f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153728275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4153728275
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1401988188
Short name T877
Test name
Test status
Simulation time 19685033621 ps
CPU time 64.96 seconds
Started Feb 18 02:14:59 PM PST 24
Finished Feb 18 02:16:48 PM PST 24
Peak memory 238408 kb
Host smart-5b23073a-6ab9-460f-8bd1-65424d5f4e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401988188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1401988188
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2971184708
Short name T69
Test name
Test status
Simulation time 2939882501 ps
CPU time 33.51 seconds
Started Feb 18 02:14:58 PM PST 24
Finished Feb 18 02:16:16 PM PST 24
Peak memory 240732 kb
Host smart-79e10d4c-efd5-4035-bd39-6c0a6ce7df3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971184708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2971184708
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1925835904
Short name T114
Test name
Test status
Simulation time 2367438215 ps
CPU time 14.05 seconds
Started Feb 18 02:14:48 PM PST 24
Finished Feb 18 02:15:50 PM PST 24
Peak memory 217896 kb
Host smart-0a0406ca-7980-4143-b959-6ce4ae5e0c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925835904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1925835904
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2120589665
Short name T787
Test name
Test status
Simulation time 586819347 ps
CPU time 3.39 seconds
Started Feb 18 02:14:47 PM PST 24
Finished Feb 18 02:15:39 PM PST 24
Peak memory 224144 kb
Host smart-27aa4446-66b3-498a-9a55-464204e8de79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120589665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2120589665
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.105677133
Short name T418
Test name
Test status
Simulation time 14475353320 ps
CPU time 14.13 seconds
Started Feb 18 02:14:47 PM PST 24
Finished Feb 18 02:15:53 PM PST 24
Peak memory 230432 kb
Host smart-196185d4-89f0-47f6-90ad-52591ff9a312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105677133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.105677133
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3281135514
Short name T718
Test name
Test status
Simulation time 3761087577 ps
CPU time 11.62 seconds
Started Feb 18 02:14:48 PM PST 24
Finished Feb 18 02:15:48 PM PST 24
Peak memory 239192 kb
Host smart-3114dfe0-118f-4a10-9cfb-2373ef21a827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281135514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3281135514
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2431554228
Short name T139
Test name
Test status
Simulation time 10181789407 ps
CPU time 14.44 seconds
Started Feb 18 02:14:47 PM PST 24
Finished Feb 18 02:15:54 PM PST 24
Peak memory 220392 kb
Host smart-ee62d23e-1e94-43c4-b9f9-c8171e160c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431554228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2431554228
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.539264421
Short name T408
Test name
Test status
Simulation time 1013578328 ps
CPU time 5.27 seconds
Started Feb 18 02:14:52 PM PST 24
Finished Feb 18 02:15:43 PM PST 24
Peak memory 222360 kb
Host smart-1a4c5435-481c-4a02-b14c-26dfdf8eef3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=539264421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.539264421
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3201081872
Short name T448
Test name
Test status
Simulation time 95321716601 ps
CPU time 126.48 seconds
Started Feb 18 02:14:59 PM PST 24
Finished Feb 18 02:17:50 PM PST 24
Peak memory 252624 kb
Host smart-1d66dbea-a6e6-46b0-82ae-87cb5f598689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201081872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3201081872
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.347897440
Short name T773
Test name
Test status
Simulation time 4254461956 ps
CPU time 28.84 seconds
Started Feb 18 02:14:50 PM PST 24
Finished Feb 18 02:16:05 PM PST 24
Peak memory 216208 kb
Host smart-5b79ea6b-8bd3-4db0-ba99-52e0608550c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347897440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.347897440
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3183435370
Short name T632
Test name
Test status
Simulation time 1543788979 ps
CPU time 8.28 seconds
Started Feb 18 02:14:48 PM PST 24
Finished Feb 18 02:15:43 PM PST 24
Peak memory 216112 kb
Host smart-112da2f9-fd58-4c38-801c-b1804d3c6442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183435370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3183435370
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3321917777
Short name T361
Test name
Test status
Simulation time 33462021 ps
CPU time 1.05 seconds
Started Feb 18 02:14:52 PM PST 24
Finished Feb 18 02:15:40 PM PST 24
Peak memory 207388 kb
Host smart-8224ce9a-dfcd-4a6c-972f-22e4cfbef911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321917777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3321917777
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.847345203
Short name T461
Test name
Test status
Simulation time 33773064 ps
CPU time 0.84 seconds
Started Feb 18 02:14:47 PM PST 24
Finished Feb 18 02:15:35 PM PST 24
Peak memory 205504 kb
Host smart-2e133de4-0cfa-4e72-8c2a-0f67575aa961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847345203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.847345203
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1326298700
Short name T174
Test name
Test status
Simulation time 1914924674 ps
CPU time 6.66 seconds
Started Feb 18 02:14:48 PM PST 24
Finished Feb 18 02:15:43 PM PST 24
Peak memory 240648 kb
Host smart-5e12936e-c25c-42bd-84e9-04fb2561deac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326298700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1326298700
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2836050984
Short name T559
Test name
Test status
Simulation time 13981327 ps
CPU time 0.73 seconds
Started Feb 18 02:14:58 PM PST 24
Finished Feb 18 02:15:43 PM PST 24
Peak memory 204744 kb
Host smart-290b7744-7ea2-474d-b9a8-ea6e04a3a4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836050984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2836050984
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.463122505
Short name T580
Test name
Test status
Simulation time 720784361 ps
CPU time 3.04 seconds
Started Feb 18 02:15:05 PM PST 24
Finished Feb 18 02:15:50 PM PST 24
Peak memory 232480 kb
Host smart-e83fd998-e505-4c77-aec4-d0c5ddce90e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463122505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.463122505
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1607409229
Short name T340
Test name
Test status
Simulation time 73271582 ps
CPU time 0.78 seconds
Started Feb 18 02:14:57 PM PST 24
Finished Feb 18 02:15:43 PM PST 24
Peak memory 205836 kb
Host smart-0145d976-e67e-4623-8a98-7863aea34a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607409229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1607409229
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1013078177
Short name T235
Test name
Test status
Simulation time 299438110528 ps
CPU time 184.23 seconds
Started Feb 18 02:15:01 PM PST 24
Finished Feb 18 02:18:48 PM PST 24
Peak memory 250652 kb
Host smart-571216b0-c5b0-46ac-9453-9e8aa110b167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013078177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1013078177
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1375212556
Short name T237
Test name
Test status
Simulation time 28891678758 ps
CPU time 122.11 seconds
Started Feb 18 02:14:55 PM PST 24
Finished Feb 18 02:17:42 PM PST 24
Peak memory 250792 kb
Host smart-c771c4af-878f-4788-8f6a-f2a3362e6cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375212556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1375212556
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2371317620
Short name T384
Test name
Test status
Simulation time 263199557258 ps
CPU time 430 seconds
Started Feb 18 02:14:58 PM PST 24
Finished Feb 18 02:22:52 PM PST 24
Peak memory 254376 kb
Host smart-1a3fb762-dc33-4d24-8f76-fd398eef357b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371317620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2371317620
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1100320794
Short name T323
Test name
Test status
Simulation time 3332392807 ps
CPU time 8.23 seconds
Started Feb 18 02:14:56 PM PST 24
Finished Feb 18 02:15:49 PM PST 24
Peak memory 238424 kb
Host smart-168d23cf-ef0c-45db-abbc-e6dfa81bd436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100320794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1100320794
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3661107266
Short name T685
Test name
Test status
Simulation time 762618285 ps
CPU time 5.63 seconds
Started Feb 18 02:14:58 PM PST 24
Finished Feb 18 02:15:49 PM PST 24
Peak memory 218208 kb
Host smart-d436b83c-411d-4b2a-870f-cf98fe9dc232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661107266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3661107266
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1291009664
Short name T498
Test name
Test status
Simulation time 13201689399 ps
CPU time 12.91 seconds
Started Feb 18 02:14:59 PM PST 24
Finished Feb 18 02:15:56 PM PST 24
Peak memory 216516 kb
Host smart-bc19e643-27ea-492e-b697-9d24712c859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291009664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1291009664
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1369973269
Short name T493
Test name
Test status
Simulation time 1997934027 ps
CPU time 8.26 seconds
Started Feb 18 02:14:55 PM PST 24
Finished Feb 18 02:15:49 PM PST 24
Peak memory 224200 kb
Host smart-4a8adeb3-6d16-4f26-9d74-ba9ea115eeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369973269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1369973269
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1125846631
Short name T331
Test name
Test status
Simulation time 4575056154 ps
CPU time 8.3 seconds
Started Feb 18 02:14:58 PM PST 24
Finished Feb 18 02:15:50 PM PST 24
Peak memory 232664 kb
Host smart-c7809d59-5d2b-446d-b372-2bf28a73089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125846631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1125846631
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.801994144
Short name T974
Test name
Test status
Simulation time 1834178843 ps
CPU time 5.76 seconds
Started Feb 18 02:15:02 PM PST 24
Finished Feb 18 02:15:51 PM PST 24
Peak memory 221400 kb
Host smart-87701bfc-d5c9-47f1-a174-ca38dee0c27c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=801994144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.801994144
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3600192822
Short name T135
Test name
Test status
Simulation time 153818258535 ps
CPU time 611.82 seconds
Started Feb 18 02:14:56 PM PST 24
Finished Feb 18 02:25:53 PM PST 24
Peak memory 289604 kb
Host smart-0ad15e89-149c-469e-9b1d-265ff4aded74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600192822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3600192822
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3291244921
Short name T719
Test name
Test status
Simulation time 1328374689 ps
CPU time 21.96 seconds
Started Feb 18 02:14:55 PM PST 24
Finished Feb 18 02:16:03 PM PST 24
Peak memory 216084 kb
Host smart-fdbc406e-315d-4864-9b48-c7a5f543134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291244921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3291244921
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2145522909
Short name T681
Test name
Test status
Simulation time 3522979543 ps
CPU time 7.79 seconds
Started Feb 18 02:15:04 PM PST 24
Finished Feb 18 02:15:54 PM PST 24
Peak memory 216168 kb
Host smart-63c4b785-8f0b-4bf7-bf29-47cb1da6918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145522909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2145522909
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2647668043
Short name T703
Test name
Test status
Simulation time 78636378 ps
CPU time 2.24 seconds
Started Feb 18 02:14:57 PM PST 24
Finished Feb 18 02:15:45 PM PST 24
Peak memory 217368 kb
Host smart-40989cc7-7e3a-4e7c-997f-0caee0fc14f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647668043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2647668043
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2071225926
Short name T351
Test name
Test status
Simulation time 145156383 ps
CPU time 0.97 seconds
Started Feb 18 02:14:55 PM PST 24
Finished Feb 18 02:15:41 PM PST 24
Peak memory 206136 kb
Host smart-3c472d13-0f2a-4315-ad24-a0bd8e2e56ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071225926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2071225926
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2213579749
Short name T833
Test name
Test status
Simulation time 14719771576 ps
CPU time 21.23 seconds
Started Feb 18 02:15:00 PM PST 24
Finished Feb 18 02:16:05 PM PST 24
Peak memory 233540 kb
Host smart-7a7173e8-7d15-4871-ad86-90daaeade9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213579749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2213579749
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4050282784
Short name T542
Test name
Test status
Simulation time 13769308 ps
CPU time 0.69 seconds
Started Feb 18 02:15:05 PM PST 24
Finished Feb 18 02:15:49 PM PST 24
Peak memory 204676 kb
Host smart-eca2a665-8c3a-4265-b555-7924b581205d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050282784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4050282784
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1003268872
Short name T902
Test name
Test status
Simulation time 63187788 ps
CPU time 2.64 seconds
Started Feb 18 02:15:05 PM PST 24
Finished Feb 18 02:15:49 PM PST 24
Peak memory 234312 kb
Host smart-ceaec13c-d951-44d0-82cc-79b297f78b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003268872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1003268872
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2360358371
Short name T314
Test name
Test status
Simulation time 39608650 ps
CPU time 0.8 seconds
Started Feb 18 02:15:01 PM PST 24
Finished Feb 18 02:15:45 PM PST 24
Peak memory 205884 kb
Host smart-fab81cf0-997f-4664-89ca-b734193a7d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360358371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2360358371
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1087135265
Short name T633
Test name
Test status
Simulation time 19433666117 ps
CPU time 117.84 seconds
Started Feb 18 02:15:06 PM PST 24
Finished Feb 18 02:17:52 PM PST 24
Peak memory 253944 kb
Host smart-610c3601-5a1a-46d0-a412-cf0488a3322e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087135265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1087135265
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.293260122
Short name T876
Test name
Test status
Simulation time 27484803152 ps
CPU time 227.83 seconds
Started Feb 18 02:15:05 PM PST 24
Finished Feb 18 02:19:36 PM PST 24
Peak memory 259660 kb
Host smart-5f8dacf5-68ca-4867-b665-722979fb5527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293260122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.293260122
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2128737031
Short name T344
Test name
Test status
Simulation time 4211854222 ps
CPU time 37.32 seconds
Started Feb 18 02:15:02 PM PST 24
Finished Feb 18 02:16:21 PM PST 24
Peak memory 235104 kb
Host smart-05badcbe-4784-43db-9990-9b422d16ce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128737031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2128737031
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1948211907
Short name T219
Test name
Test status
Simulation time 539340417 ps
CPU time 3.3 seconds
Started Feb 18 02:15:11 PM PST 24
Finished Feb 18 02:15:55 PM PST 24
Peak memory 224244 kb
Host smart-71fd3d40-42c3-4f0b-9bcc-a7a526e0a95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948211907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1948211907
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.253391002
Short name T815
Test name
Test status
Simulation time 47934392797 ps
CPU time 36.78 seconds
Started Feb 18 02:15:02 PM PST 24
Finished Feb 18 02:16:21 PM PST 24
Peak memory 240624 kb
Host smart-21e62b72-644b-44eb-b8e6-fc7e6717b68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253391002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.253391002
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2145788150
Short name T35
Test name
Test status
Simulation time 735963031 ps
CPU time 11.15 seconds
Started Feb 18 02:14:55 PM PST 24
Finished Feb 18 02:15:51 PM PST 24
Peak memory 236316 kb
Host smart-567904c1-3952-4472-9e04-a640ccf32624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145788150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2145788150
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2900920260
Short name T911
Test name
Test status
Simulation time 305304048 ps
CPU time 6.69 seconds
Started Feb 18 02:14:57 PM PST 24
Finished Feb 18 02:15:49 PM PST 24
Peak memory 240072 kb
Host smart-c415973c-f94e-454f-b9b5-5bbcd733a746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900920260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2900920260
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3360427541
Short name T396
Test name
Test status
Simulation time 217023550 ps
CPU time 3.57 seconds
Started Feb 18 02:15:05 PM PST 24
Finished Feb 18 02:15:50 PM PST 24
Peak memory 218572 kb
Host smart-84c3d171-e399-42ff-8057-076cbe821373
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3360427541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3360427541
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2167502485
Short name T478
Test name
Test status
Simulation time 3512639755 ps
CPU time 34.56 seconds
Started Feb 18 02:14:58 PM PST 24
Finished Feb 18 02:16:17 PM PST 24
Peak memory 216112 kb
Host smart-d09b9189-7517-44fd-916e-eaa8b28846e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167502485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2167502485
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3670817321
Short name T568
Test name
Test status
Simulation time 1672386522 ps
CPU time 5.33 seconds
Started Feb 18 02:14:57 PM PST 24
Finished Feb 18 02:15:47 PM PST 24
Peak memory 207792 kb
Host smart-5aef1088-3f41-42e2-9e04-86b343d0166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670817321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3670817321
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3743242480
Short name T453
Test name
Test status
Simulation time 40836621 ps
CPU time 2.1 seconds
Started Feb 18 02:14:58 PM PST 24
Finished Feb 18 02:15:46 PM PST 24
Peak memory 216208 kb
Host smart-04092a66-b96f-45dd-8351-08e9971dcf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743242480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3743242480
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2321419056
Short name T932
Test name
Test status
Simulation time 193197216 ps
CPU time 0.9 seconds
Started Feb 18 02:14:59 PM PST 24
Finished Feb 18 02:15:44 PM PST 24
Peak memory 206148 kb
Host smart-4854ab6c-5370-445e-91b2-a0c9190d51cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321419056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2321419056
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2728344578
Short name T585
Test name
Test status
Simulation time 2128218250 ps
CPU time 8.95 seconds
Started Feb 18 02:15:05 PM PST 24
Finished Feb 18 02:15:56 PM PST 24
Peak memory 217780 kb
Host smart-82ce718e-a224-4f3e-8031-4fc14e328102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728344578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2728344578
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3082961858
Short name T312
Test name
Test status
Simulation time 42851711 ps
CPU time 0.69 seconds
Started Feb 18 02:15:14 PM PST 24
Finished Feb 18 02:15:53 PM PST 24
Peak memory 204624 kb
Host smart-bf95cdd4-0613-4594-8d83-51f82a4f2a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082961858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3082961858
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.633116034
Short name T166
Test name
Test status
Simulation time 34966304 ps
CPU time 2.35 seconds
Started Feb 18 02:15:04 PM PST 24
Finished Feb 18 02:15:49 PM PST 24
Peak memory 232452 kb
Host smart-28f95f0a-bcda-4b91-ab0e-79fb0d2b34dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633116034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.633116034
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1712925405
Short name T318
Test name
Test status
Simulation time 68773126 ps
CPU time 0.74 seconds
Started Feb 18 02:15:09 PM PST 24
Finished Feb 18 02:15:51 PM PST 24
Peak memory 204800 kb
Host smart-837dfabf-57e5-43e1-9b4a-bb09cf0e8b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712925405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1712925405
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2942724915
Short name T960
Test name
Test status
Simulation time 163418929359 ps
CPU time 129.2 seconds
Started Feb 18 02:15:07 PM PST 24
Finished Feb 18 02:17:58 PM PST 24
Peak memory 249964 kb
Host smart-436eb348-0524-44c3-bc91-05291742066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942724915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2942724915
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1357428180
Short name T108
Test name
Test status
Simulation time 5244722079 ps
CPU time 93.37 seconds
Started Feb 18 02:14:58 PM PST 24
Finished Feb 18 02:17:17 PM PST 24
Peak memory 251808 kb
Host smart-f40ce9f5-0b7f-45dd-b0f3-999cdbc815a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357428180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1357428180
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.397968182
Short name T726
Test name
Test status
Simulation time 7643039510 ps
CPU time 60.96 seconds
Started Feb 18 02:14:58 PM PST 24
Finished Feb 18 02:16:43 PM PST 24
Peak memory 232636 kb
Host smart-3933469b-8309-45b5-ba68-577cb5cb1528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397968182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.397968182
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2731119520
Short name T824
Test name
Test status
Simulation time 7024153502 ps
CPU time 15.83 seconds
Started Feb 18 02:15:10 PM PST 24
Finished Feb 18 02:16:06 PM PST 24
Peak memory 224352 kb
Host smart-9be349ca-cbc5-4f26-8c26-cb3950da04d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731119520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2731119520
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.138918978
Short name T218
Test name
Test status
Simulation time 42281452700 ps
CPU time 16.5 seconds
Started Feb 18 02:15:05 PM PST 24
Finished Feb 18 02:16:04 PM PST 24
Peak memory 233288 kb
Host smart-0a56d1ec-c768-4f1c-a54e-27c7d7a0db2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138918978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.138918978
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3607114371
Short name T598
Test name
Test status
Simulation time 4985421289 ps
CPU time 8.88 seconds
Started Feb 18 02:15:00 PM PST 24
Finished Feb 18 02:15:52 PM PST 24
Peak memory 222624 kb
Host smart-62b11d9d-4e37-4bba-a0de-aafe8986e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607114371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3607114371
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.316923105
Short name T350
Test name
Test status
Simulation time 23740396257 ps
CPU time 10.7 seconds
Started Feb 18 02:15:05 PM PST 24
Finished Feb 18 02:15:57 PM PST 24
Peak memory 232796 kb
Host smart-f16a91b8-4d88-48ff-9833-58d40f45387f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316923105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.316923105
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3182088222
Short name T444
Test name
Test status
Simulation time 14221316578 ps
CPU time 9.69 seconds
Started Feb 18 02:15:06 PM PST 24
Finished Feb 18 02:15:57 PM PST 24
Peak memory 219384 kb
Host smart-8b76905a-3d04-44ec-835f-05eaba8cee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182088222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3182088222
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3519342600
Short name T326
Test name
Test status
Simulation time 5138834278 ps
CPU time 5.16 seconds
Started Feb 18 02:15:06 PM PST 24
Finished Feb 18 02:15:59 PM PST 24
Peak memory 221680 kb
Host smart-43472813-e85b-4fac-a3f0-383cdf7e0536
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3519342600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3519342600
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1534309098
Short name T136
Test name
Test status
Simulation time 9303328357 ps
CPU time 167.03 seconds
Started Feb 18 02:15:08 PM PST 24
Finished Feb 18 02:18:34 PM PST 24
Peak memory 265404 kb
Host smart-3930eccb-f953-4b1a-9834-b21535d0e783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534309098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1534309098
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.609656365
Short name T335
Test name
Test status
Simulation time 6602790793 ps
CPU time 28.01 seconds
Started Feb 18 02:15:02 PM PST 24
Finished Feb 18 02:16:12 PM PST 24
Peak memory 216048 kb
Host smart-38a22c83-ca83-41b6-9feb-337fb8e832c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609656365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.609656365
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3526315787
Short name T695
Test name
Test status
Simulation time 722640324 ps
CPU time 4.2 seconds
Started Feb 18 02:15:05 PM PST 24
Finished Feb 18 02:15:52 PM PST 24
Peak memory 207800 kb
Host smart-1c191b98-ed61-498d-9520-16e0740550cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526315787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3526315787
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.930946572
Short name T285
Test name
Test status
Simulation time 194333390 ps
CPU time 1.8 seconds
Started Feb 18 02:15:06 PM PST 24
Finished Feb 18 02:15:56 PM PST 24
Peak memory 208252 kb
Host smart-c2a8b2d0-124e-4704-ae51-4ba71953c49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930946572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.930946572
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1334416185
Short name T660
Test name
Test status
Simulation time 185346585 ps
CPU time 0.8 seconds
Started Feb 18 02:15:07 PM PST 24
Finished Feb 18 02:15:50 PM PST 24
Peak memory 205132 kb
Host smart-ce62de39-551f-49f0-8bdc-1759c48efc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334416185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1334416185
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4119592509
Short name T884
Test name
Test status
Simulation time 49677114741 ps
CPU time 26.7 seconds
Started Feb 18 02:15:08 PM PST 24
Finished Feb 18 02:16:16 PM PST 24
Peak memory 234124 kb
Host smart-9e1f6803-85f9-429c-9565-bbed3f71f18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119592509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4119592509
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1423203720
Short name T741
Test name
Test status
Simulation time 14274420 ps
CPU time 0.72 seconds
Started Feb 18 02:15:18 PM PST 24
Finished Feb 18 02:15:56 PM PST 24
Peak memory 204696 kb
Host smart-57dc7f19-f890-4808-aab3-81a3a0070ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423203720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1423203720
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1944483037
Short name T604
Test name
Test status
Simulation time 1318838959 ps
CPU time 5.76 seconds
Started Feb 18 02:15:36 PM PST 24
Finished Feb 18 02:16:20 PM PST 24
Peak memory 233968 kb
Host smart-cf223eb1-0b23-4e69-a5e0-d89d45a757e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944483037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1944483037
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.517937248
Short name T779
Test name
Test status
Simulation time 16537574 ps
CPU time 0.81 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:16:00 PM PST 24
Peak memory 204788 kb
Host smart-b2f27c34-f085-45ca-ab1e-0c8904aa37ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517937248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.517937248
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1468281766
Short name T477
Test name
Test status
Simulation time 27121957267 ps
CPU time 141.39 seconds
Started Feb 18 02:15:14 PM PST 24
Finished Feb 18 02:18:14 PM PST 24
Peak memory 265372 kb
Host smart-4d284732-135d-43f7-8d46-588a39a2a202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468281766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1468281766
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2667860288
Short name T197
Test name
Test status
Simulation time 7487386251 ps
CPU time 59.61 seconds
Started Feb 18 02:15:16 PM PST 24
Finished Feb 18 02:16:53 PM PST 24
Peak memory 250024 kb
Host smart-f561f9e4-57e2-4d87-9dea-38847a0bac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667860288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2667860288
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3565207466
Short name T680
Test name
Test status
Simulation time 5737042012 ps
CPU time 95.19 seconds
Started Feb 18 02:15:14 PM PST 24
Finished Feb 18 02:17:28 PM PST 24
Peak memory 265604 kb
Host smart-dce4aaf0-6442-4d05-a72b-da0305afa509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565207466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3565207466
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3424306193
Short name T630
Test name
Test status
Simulation time 1384375976 ps
CPU time 7.32 seconds
Started Feb 18 02:15:22 PM PST 24
Finished Feb 18 02:16:07 PM PST 24
Peak memory 232464 kb
Host smart-dcd71e39-c449-4c7f-aa4c-ec8248ef8936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424306193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3424306193
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3314625394
Short name T500
Test name
Test status
Simulation time 4800194873 ps
CPU time 6.79 seconds
Started Feb 18 02:15:14 PM PST 24
Finished Feb 18 02:15:59 PM PST 24
Peak memory 233588 kb
Host smart-316fcedb-3d21-47b1-9333-c1c4537883aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314625394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3314625394
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2692371099
Short name T348
Test name
Test status
Simulation time 18790318088 ps
CPU time 46.7 seconds
Started Feb 18 02:15:13 PM PST 24
Finished Feb 18 02:16:39 PM PST 24
Peak memory 218248 kb
Host smart-ce649975-ad8c-4ed9-9791-f854d0c0a9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692371099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2692371099
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2399714546
Short name T391
Test name
Test status
Simulation time 5221735021 ps
CPU time 8.65 seconds
Started Feb 18 02:15:16 PM PST 24
Finished Feb 18 02:16:02 PM PST 24
Peak memory 224412 kb
Host smart-652d6bfb-2892-402d-b766-2e6dfe818e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399714546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2399714546
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1311263704
Short name T249
Test name
Test status
Simulation time 108778200 ps
CPU time 2.5 seconds
Started Feb 18 02:15:14 PM PST 24
Finished Feb 18 02:15:55 PM PST 24
Peak memory 232464 kb
Host smart-32706404-41b3-4ace-b5b3-e025cb72ef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311263704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1311263704
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1755615377
Short name T947
Test name
Test status
Simulation time 1434174479 ps
CPU time 6.1 seconds
Started Feb 18 02:15:31 PM PST 24
Finished Feb 18 02:16:13 PM PST 24
Peak memory 219408 kb
Host smart-6e232e10-0981-4a13-be1a-1516fc5096b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1755615377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1755615377
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.317384379
Short name T129
Test name
Test status
Simulation time 55411842 ps
CPU time 0.99 seconds
Started Feb 18 02:15:13 PM PST 24
Finished Feb 18 02:15:53 PM PST 24
Peak memory 206288 kb
Host smart-a6dd68fe-0fd7-4d16-8370-c31f7c9c0d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317384379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.317384379
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1481589259
Short name T525
Test name
Test status
Simulation time 3139567659 ps
CPU time 28.96 seconds
Started Feb 18 02:15:17 PM PST 24
Finished Feb 18 02:16:24 PM PST 24
Peak memory 216164 kb
Host smart-e7bfe11a-e570-4476-9382-a19529fc20cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481589259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1481589259
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2589019055
Short name T648
Test name
Test status
Simulation time 231930562 ps
CPU time 1.84 seconds
Started Feb 18 02:15:31 PM PST 24
Finished Feb 18 02:16:09 PM PST 24
Peak memory 206512 kb
Host smart-af1159df-64ce-4914-9139-5537938dd825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589019055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2589019055
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3637318646
Short name T261
Test name
Test status
Simulation time 262769273 ps
CPU time 1.14 seconds
Started Feb 18 02:15:12 PM PST 24
Finished Feb 18 02:15:52 PM PST 24
Peak memory 207488 kb
Host smart-4fac0f66-32a7-4632-93f3-3c9cee52de2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637318646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3637318646
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2765141197
Short name T967
Test name
Test status
Simulation time 108761024 ps
CPU time 0.85 seconds
Started Feb 18 02:15:14 PM PST 24
Finished Feb 18 02:15:53 PM PST 24
Peak memory 205096 kb
Host smart-22ab80bb-ddd1-4c4f-9f3e-e9c35e8cdea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765141197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2765141197
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.246188279
Short name T367
Test name
Test status
Simulation time 1056931503 ps
CPU time 8.65 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:16:07 PM PST 24
Peak memory 239000 kb
Host smart-f17b8435-a648-473f-9524-2aecb39384b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246188279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.246188279
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3885084913
Short name T277
Test name
Test status
Simulation time 16973824 ps
CPU time 0.77 seconds
Started Feb 18 02:15:32 PM PST 24
Finished Feb 18 02:16:09 PM PST 24
Peak memory 205080 kb
Host smart-12b3939c-5452-4787-8870-a426d252054f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885084913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3885084913
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1971861632
Short name T291
Test name
Test status
Simulation time 1018462047 ps
CPU time 4.61 seconds
Started Feb 18 02:15:15 PM PST 24
Finished Feb 18 02:15:57 PM PST 24
Peak memory 238092 kb
Host smart-6840ef7c-77c4-4de7-a714-4e2775bd3a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971861632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1971861632
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2870385398
Short name T954
Test name
Test status
Simulation time 45500404 ps
CPU time 0.75 seconds
Started Feb 18 02:15:31 PM PST 24
Finished Feb 18 02:16:07 PM PST 24
Peak memory 204728 kb
Host smart-2da9860a-805e-40c3-a6fc-2ad6c5e52354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870385398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2870385398
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3344676191
Short name T791
Test name
Test status
Simulation time 110588573826 ps
CPU time 176.15 seconds
Started Feb 18 02:15:14 PM PST 24
Finished Feb 18 02:18:49 PM PST 24
Peak memory 272128 kb
Host smart-6824ad44-4aee-4f25-8499-16b8a1d7d0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344676191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3344676191
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4184864711
Short name T958
Test name
Test status
Simulation time 287788394594 ps
CPU time 515.25 seconds
Started Feb 18 02:15:17 PM PST 24
Finished Feb 18 02:24:30 PM PST 24
Peak memory 252888 kb
Host smart-78005860-4e75-42b7-babb-906b4225fd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184864711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4184864711
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4009169238
Short name T784
Test name
Test status
Simulation time 52584033339 ps
CPU time 112.8 seconds
Started Feb 18 02:15:22 PM PST 24
Finished Feb 18 02:17:52 PM PST 24
Peak memory 249052 kb
Host smart-46955a2a-213f-4760-bbcc-c0d57a62cf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009169238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4009169238
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2946027461
Short name T450
Test name
Test status
Simulation time 1719782928 ps
CPU time 7.38 seconds
Started Feb 18 02:15:18 PM PST 24
Finished Feb 18 02:16:03 PM PST 24
Peak memory 232448 kb
Host smart-cecd5451-77d0-406c-b34f-d73b6c0dc466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946027461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2946027461
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.108881665
Short name T878
Test name
Test status
Simulation time 852498151 ps
CPU time 2.71 seconds
Started Feb 18 02:15:15 PM PST 24
Finished Feb 18 02:15:56 PM PST 24
Peak memory 232468 kb
Host smart-c664fd9d-cfda-4e56-b579-ab0b6f518589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108881665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.108881665
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.751429888
Short name T577
Test name
Test status
Simulation time 807025837 ps
CPU time 4.39 seconds
Started Feb 18 02:15:19 PM PST 24
Finished Feb 18 02:16:00 PM PST 24
Peak memory 235476 kb
Host smart-db74c770-d5dd-404f-945e-21cc1b0b11af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751429888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.751429888
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3426728746
Short name T176
Test name
Test status
Simulation time 1521166043 ps
CPU time 7.64 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:16:06 PM PST 24
Peak memory 232460 kb
Host smart-e037c69c-87ec-46da-b262-8eaf2790a7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426728746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3426728746
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1014622418
Short name T79
Test name
Test status
Simulation time 8035773604 ps
CPU time 7.21 seconds
Started Feb 18 02:15:13 PM PST 24
Finished Feb 18 02:16:00 PM PST 24
Peak memory 224380 kb
Host smart-c500b350-6c79-4c4c-af6f-1f9bb08131c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014622418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1014622418
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1975098767
Short name T758
Test name
Test status
Simulation time 1368832196 ps
CPU time 5.97 seconds
Started Feb 18 02:15:14 PM PST 24
Finished Feb 18 02:15:58 PM PST 24
Peak memory 221872 kb
Host smart-13efa6ff-c0c4-423e-87cc-5b0a330dbf88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1975098767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1975098767
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3638701545
Short name T889
Test name
Test status
Simulation time 4504644591 ps
CPU time 48.37 seconds
Started Feb 18 02:15:17 PM PST 24
Finished Feb 18 02:16:45 PM PST 24
Peak memory 216188 kb
Host smart-daff689d-8b2e-476f-9a65-159ea83fe2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638701545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3638701545
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3259688642
Short name T643
Test name
Test status
Simulation time 672026851 ps
CPU time 4.05 seconds
Started Feb 18 02:15:13 PM PST 24
Finished Feb 18 02:15:56 PM PST 24
Peak memory 216052 kb
Host smart-142f77f4-b8a0-480f-bc0b-f789a2283ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259688642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3259688642
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4193383787
Short name T728
Test name
Test status
Simulation time 1214519086 ps
CPU time 10.36 seconds
Started Feb 18 02:15:30 PM PST 24
Finished Feb 18 02:16:17 PM PST 24
Peak memory 208012 kb
Host smart-9dc16c48-094b-4f22-846f-8b74c281cde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193383787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4193383787
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.641680070
Short name T822
Test name
Test status
Simulation time 64102574 ps
CPU time 0.92 seconds
Started Feb 18 02:15:15 PM PST 24
Finished Feb 18 02:15:54 PM PST 24
Peak memory 205128 kb
Host smart-13cb429c-8149-4c3d-8382-fc07870d8d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641680070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.641680070
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2546305065
Short name T399
Test name
Test status
Simulation time 2093214025 ps
CPU time 9.31 seconds
Started Feb 18 02:15:15 PM PST 24
Finished Feb 18 02:16:03 PM PST 24
Peak memory 239316 kb
Host smart-1b5de6b5-70db-4ad1-8f42-5896b96f519d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546305065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2546305065
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1520194040
Short name T952
Test name
Test status
Simulation time 23549257 ps
CPU time 0.75 seconds
Started Feb 18 02:15:19 PM PST 24
Finished Feb 18 02:15:57 PM PST 24
Peak memory 204160 kb
Host smart-f4f72d03-cbd9-4abc-ad5b-f163a06a813f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520194040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1520194040
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3124122677
Short name T578
Test name
Test status
Simulation time 101496310 ps
CPU time 2.51 seconds
Started Feb 18 02:15:27 PM PST 24
Finished Feb 18 02:16:05 PM PST 24
Peak memory 233528 kb
Host smart-0c324cdb-074e-4838-97cb-938d1bb9ca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124122677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3124122677
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2679797971
Short name T569
Test name
Test status
Simulation time 19513991 ps
CPU time 0.78 seconds
Started Feb 18 02:15:15 PM PST 24
Finished Feb 18 02:15:55 PM PST 24
Peak memory 205876 kb
Host smart-e4f9787f-8438-4ecb-bb60-dca31b113f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679797971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2679797971
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1429013789
Short name T916
Test name
Test status
Simulation time 37286858681 ps
CPU time 173.37 seconds
Started Feb 18 02:15:17 PM PST 24
Finished Feb 18 02:18:48 PM PST 24
Peak memory 252104 kb
Host smart-650efac5-c8a6-4f6c-b907-b18408eb4a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429013789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1429013789
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3230305431
Short name T193
Test name
Test status
Simulation time 50763385238 ps
CPU time 131.98 seconds
Started Feb 18 02:15:37 PM PST 24
Finished Feb 18 02:18:28 PM PST 24
Peak memory 267868 kb
Host smart-506d51af-1a57-4a79-a306-1a854f3b5999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230305431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3230305431
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.436375856
Short name T355
Test name
Test status
Simulation time 484360445992 ps
CPU time 338.37 seconds
Started Feb 18 02:15:22 PM PST 24
Finished Feb 18 02:21:37 PM PST 24
Peak memory 254004 kb
Host smart-8037036b-7d93-4e97-951c-9b4261a6d94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436375856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.436375856
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1534611929
Short name T251
Test name
Test status
Simulation time 245255296 ps
CPU time 8.7 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:16:08 PM PST 24
Peak memory 233120 kb
Host smart-9512830e-0d88-488a-bb75-6a928d5a0aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534611929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1534611929
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3501523648
Short name T244
Test name
Test status
Simulation time 429970211 ps
CPU time 4.66 seconds
Started Feb 18 02:15:20 PM PST 24
Finished Feb 18 02:16:02 PM PST 24
Peak memory 217148 kb
Host smart-c6006cfe-1c14-416e-8074-51801d71e173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501523648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3501523648
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1372465980
Short name T893
Test name
Test status
Simulation time 3335040326 ps
CPU time 6.3 seconds
Started Feb 18 02:15:19 PM PST 24
Finished Feb 18 02:16:02 PM PST 24
Peak memory 223040 kb
Host smart-1e57a83f-6a48-42ac-8458-adb2e99e85f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372465980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1372465980
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3781887999
Short name T950
Test name
Test status
Simulation time 162313828 ps
CPU time 2.71 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:16:01 PM PST 24
Peak memory 232388 kb
Host smart-f0ba9b88-4ba0-44d9-89d7-2c1adc155e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781887999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3781887999
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4291365536
Short name T674
Test name
Test status
Simulation time 3120032175 ps
CPU time 4.64 seconds
Started Feb 18 02:15:18 PM PST 24
Finished Feb 18 02:16:00 PM PST 24
Peak memory 234056 kb
Host smart-d01c0d87-b53f-41fe-95ad-b69031607a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291365536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4291365536
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2155889934
Short name T904
Test name
Test status
Simulation time 362318497 ps
CPU time 3.1 seconds
Started Feb 18 02:15:22 PM PST 24
Finished Feb 18 02:16:02 PM PST 24
Peak memory 216188 kb
Host smart-056a5592-426e-4d26-89fb-bbb6f2efa831
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2155889934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2155889934
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3019410355
Short name T980
Test name
Test status
Simulation time 206866502 ps
CPU time 1.09 seconds
Started Feb 18 02:15:26 PM PST 24
Finished Feb 18 02:16:03 PM PST 24
Peak memory 206668 kb
Host smart-2906471d-19de-4240-befc-1422a58b8709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019410355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3019410355
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3381543522
Short name T639
Test name
Test status
Simulation time 4990279944 ps
CPU time 18.36 seconds
Started Feb 18 02:15:23 PM PST 24
Finished Feb 18 02:16:19 PM PST 24
Peak memory 216196 kb
Host smart-2ff6f629-e1c7-4052-b851-bf1e8b0ddcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381543522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3381543522
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.730240016
Short name T17
Test name
Test status
Simulation time 3786560734 ps
CPU time 11.34 seconds
Started Feb 18 02:15:15 PM PST 24
Finished Feb 18 02:16:06 PM PST 24
Peak memory 216184 kb
Host smart-0dcb75fc-2ceb-4420-857e-d04de6ec7fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730240016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.730240016
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.199930706
Short name T281
Test name
Test status
Simulation time 103239047 ps
CPU time 1.32 seconds
Started Feb 18 02:15:22 PM PST 24
Finished Feb 18 02:16:02 PM PST 24
Peak memory 207888 kb
Host smart-5d704bc7-fecd-47c1-98e8-059433c508af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199930706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.199930706
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3183167069
Short name T971
Test name
Test status
Simulation time 25304820 ps
CPU time 0.72 seconds
Started Feb 18 02:15:17 PM PST 24
Finished Feb 18 02:15:56 PM PST 24
Peak memory 205108 kb
Host smart-75e733ab-c49b-41b3-bb19-c8188275fb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183167069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3183167069
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.452544765
Short name T496
Test name
Test status
Simulation time 8035042782 ps
CPU time 14.13 seconds
Started Feb 18 02:15:38 PM PST 24
Finished Feb 18 02:16:31 PM PST 24
Peak memory 237472 kb
Host smart-f3397fca-beea-4bd2-b6eb-e7c3cb627cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452544765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.452544765
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3415289756
Short name T761
Test name
Test status
Simulation time 43731752 ps
CPU time 0.68 seconds
Started Feb 18 02:15:19 PM PST 24
Finished Feb 18 02:15:57 PM PST 24
Peak memory 204732 kb
Host smart-6852ebd5-fb08-494c-b830-334d77974497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415289756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3415289756
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1745427599
Short name T587
Test name
Test status
Simulation time 993302746 ps
CPU time 4.97 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:16:03 PM PST 24
Peak memory 233296 kb
Host smart-6a9a9c34-d66b-40d8-baa3-4d7c51ecf843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745427599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1745427599
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1725029354
Short name T301
Test name
Test status
Simulation time 46976777 ps
CPU time 0.75 seconds
Started Feb 18 02:15:38 PM PST 24
Finished Feb 18 02:16:17 PM PST 24
Peak memory 205724 kb
Host smart-59f1091f-659b-4300-9641-d7e8f3721d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725029354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1725029354
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.704547703
Short name T783
Test name
Test status
Simulation time 23678198123 ps
CPU time 134.33 seconds
Started Feb 18 02:15:19 PM PST 24
Finished Feb 18 02:18:10 PM PST 24
Peak memory 256284 kb
Host smart-33aab173-fa9f-496c-b61d-7efb6aadb911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704547703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.704547703
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3590675224
Short name T189
Test name
Test status
Simulation time 19547279523 ps
CPU time 69.81 seconds
Started Feb 18 02:15:20 PM PST 24
Finished Feb 18 02:17:10 PM PST 24
Peak memory 250664 kb
Host smart-9b5f6d7b-6bef-499f-b049-5499e794aff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590675224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3590675224
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3933840289
Short name T772
Test name
Test status
Simulation time 79361450122 ps
CPU time 214.81 seconds
Started Feb 18 02:15:15 PM PST 24
Finished Feb 18 02:19:28 PM PST 24
Peak memory 251612 kb
Host smart-c7236cce-b00a-497a-b0cd-4c8d84e56c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933840289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3933840289
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.534698678
Short name T843
Test name
Test status
Simulation time 14430058419 ps
CPU time 24.35 seconds
Started Feb 18 02:15:37 PM PST 24
Finished Feb 18 02:16:40 PM PST 24
Peak memory 240748 kb
Host smart-95a9ad59-1103-4367-b302-14dd19413c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534698678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.534698678
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3311347190
Short name T246
Test name
Test status
Simulation time 176194857 ps
CPU time 3.11 seconds
Started Feb 18 02:15:31 PM PST 24
Finished Feb 18 02:16:11 PM PST 24
Peak memory 217072 kb
Host smart-4982d537-2147-4cbc-babb-4bb5ca4ede9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311347190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3311347190
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1328259268
Short name T946
Test name
Test status
Simulation time 96024845 ps
CPU time 2.53 seconds
Started Feb 18 02:15:37 PM PST 24
Finished Feb 18 02:16:19 PM PST 24
Peak memory 233228 kb
Host smart-b34f769d-a612-4068-9e8c-07a4aecbe5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328259268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1328259268
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2465096328
Short name T796
Test name
Test status
Simulation time 752719818 ps
CPU time 9.65 seconds
Started Feb 18 02:15:20 PM PST 24
Finished Feb 18 02:16:08 PM PST 24
Peak memory 233772 kb
Host smart-9917fc7a-9d8b-4e01-98b6-40b1956f706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465096328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2465096328
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1111764107
Short name T37
Test name
Test status
Simulation time 835608797 ps
CPU time 9.62 seconds
Started Feb 18 02:15:20 PM PST 24
Finished Feb 18 02:16:08 PM PST 24
Peak memory 237744 kb
Host smart-5f3d65f7-f397-4e22-a6e7-f4f0cb19ecc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111764107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1111764107
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.148669203
Short name T785
Test name
Test status
Simulation time 262013517 ps
CPU time 4.1 seconds
Started Feb 18 02:15:26 PM PST 24
Finished Feb 18 02:16:07 PM PST 24
Peak memory 222160 kb
Host smart-3d444df6-dcf9-44db-988c-0e259ba26802
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=148669203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.148669203
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.520111308
Short name T593
Test name
Test status
Simulation time 5613889842 ps
CPU time 28.98 seconds
Started Feb 18 02:15:38 PM PST 24
Finished Feb 18 02:16:46 PM PST 24
Peak memory 216060 kb
Host smart-91e659bc-9b60-49d0-bbc0-f1d7caa0b5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520111308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.520111308
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3713916689
Short name T429
Test name
Test status
Simulation time 24436029057 ps
CPU time 12.5 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:16:12 PM PST 24
Peak memory 216060 kb
Host smart-088b79ec-7494-45da-a6e3-bb38d51b9915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713916689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3713916689
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3051373060
Short name T584
Test name
Test status
Simulation time 999051751 ps
CPU time 1.46 seconds
Started Feb 18 02:15:37 PM PST 24
Finished Feb 18 02:16:17 PM PST 24
Peak memory 216072 kb
Host smart-7130ff5d-8147-41c7-9b12-8b0aa4b4ea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051373060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3051373060
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2623095277
Short name T518
Test name
Test status
Simulation time 34817337 ps
CPU time 0.89 seconds
Started Feb 18 02:15:38 PM PST 24
Finished Feb 18 02:16:18 PM PST 24
Peak memory 205364 kb
Host smart-55651b0b-08b7-4af8-9394-e647c34ba368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623095277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2623095277
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2250943474
Short name T767
Test name
Test status
Simulation time 30697362433 ps
CPU time 25.15 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:16:24 PM PST 24
Peak memory 224372 kb
Host smart-55ce3070-5a08-4898-92ef-7f085dae99fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250943474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2250943474
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3980361312
Short name T286
Test name
Test status
Simulation time 20531691 ps
CPU time 0.71 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:15:59 PM PST 24
Peak memory 204128 kb
Host smart-ac280e81-1029-4276-9a72-87dc03e54d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980361312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3980361312
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4049048813
Short name T683
Test name
Test status
Simulation time 197611873 ps
CPU time 3.4 seconds
Started Feb 18 02:15:19 PM PST 24
Finished Feb 18 02:16:00 PM PST 24
Peak memory 219056 kb
Host smart-69ea91b3-e3b8-4be6-b9af-e2a5efb40b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049048813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4049048813
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3082542198
Short name T290
Test name
Test status
Simulation time 21056637 ps
CPU time 0.75 seconds
Started Feb 18 02:15:29 PM PST 24
Finished Feb 18 02:16:06 PM PST 24
Peak memory 206192 kb
Host smart-ce674701-accc-4ba0-8bc2-1b14b813dc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082542198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3082542198
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1789354750
Short name T881
Test name
Test status
Simulation time 26617291423 ps
CPU time 39.28 seconds
Started Feb 18 02:15:29 PM PST 24
Finished Feb 18 02:16:45 PM PST 24
Peak memory 238592 kb
Host smart-2c5fd984-94a7-4405-a477-c040a7b22d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789354750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1789354750
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2257630869
Short name T329
Test name
Test status
Simulation time 7327844040 ps
CPU time 37.66 seconds
Started Feb 18 02:15:22 PM PST 24
Finished Feb 18 02:16:37 PM PST 24
Peak memory 246592 kb
Host smart-e9c77f41-12b4-4d8a-bd13-99aa9b329557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257630869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2257630869
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4168268502
Short name T398
Test name
Test status
Simulation time 1459932495 ps
CPU time 4.63 seconds
Started Feb 18 02:15:22 PM PST 24
Finished Feb 18 02:16:04 PM PST 24
Peak memory 234068 kb
Host smart-572198fb-3696-480e-a34e-244b9343e40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168268502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4168268502
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2846135633
Short name T597
Test name
Test status
Simulation time 28655217134 ps
CPU time 27.74 seconds
Started Feb 18 02:15:20 PM PST 24
Finished Feb 18 02:16:26 PM PST 24
Peak memory 247920 kb
Host smart-7c1ddad6-cca3-4d5e-8540-37c087c801d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846135633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2846135633
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3575177192
Short name T145
Test name
Test status
Simulation time 33436300 ps
CPU time 2.52 seconds
Started Feb 18 02:15:25 PM PST 24
Finished Feb 18 02:16:03 PM PST 24
Peak memory 232448 kb
Host smart-fe8ff4e1-ff67-4979-8616-8770efe47b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575177192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3575177192
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2375444449
Short name T310
Test name
Test status
Simulation time 6589013450 ps
CPU time 18.08 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:16:17 PM PST 24
Peak memory 233632 kb
Host smart-8e2038b2-4f33-43fa-a01e-c41462e57b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375444449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2375444449
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2226524548
Short name T859
Test name
Test status
Simulation time 1175147555 ps
CPU time 5.65 seconds
Started Feb 18 02:15:19 PM PST 24
Finished Feb 18 02:16:03 PM PST 24
Peak memory 218388 kb
Host smart-d2fd6aa5-80c0-4bdf-ad62-c9b69754aafd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2226524548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2226524548
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4082877130
Short name T137
Test name
Test status
Simulation time 521535666 ps
CPU time 0.9 seconds
Started Feb 18 02:15:30 PM PST 24
Finished Feb 18 02:16:07 PM PST 24
Peak memory 206360 kb
Host smart-8e27af6e-e2f4-458f-beec-4f76b88b616c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082877130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4082877130
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2544972411
Short name T879
Test name
Test status
Simulation time 5274516375 ps
CPU time 21.42 seconds
Started Feb 18 02:15:23 PM PST 24
Finished Feb 18 02:16:21 PM PST 24
Peak memory 219412 kb
Host smart-aa6048a6-f70d-4337-b31f-bc7932916e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544972411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2544972411
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1483741774
Short name T711
Test name
Test status
Simulation time 25742348427 ps
CPU time 18.63 seconds
Started Feb 18 02:15:22 PM PST 24
Finished Feb 18 02:16:19 PM PST 24
Peak memory 216136 kb
Host smart-e92aa36d-f639-489e-ba87-785402643ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483741774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1483741774
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2394554009
Short name T460
Test name
Test status
Simulation time 2138390910 ps
CPU time 4.34 seconds
Started Feb 18 02:15:21 PM PST 24
Finished Feb 18 02:16:04 PM PST 24
Peak memory 216056 kb
Host smart-5f1a2d2e-db1b-4d73-abdb-9de9d5b19af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394554009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2394554009
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2716076272
Short name T820
Test name
Test status
Simulation time 25300065 ps
CPU time 0.69 seconds
Started Feb 18 02:15:30 PM PST 24
Finished Feb 18 02:16:06 PM PST 24
Peak memory 205116 kb
Host smart-e4e0bd0f-ca07-4d13-b939-8283e09e82c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716076272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2716076272
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2967411022
Short name T678
Test name
Test status
Simulation time 262183753 ps
CPU time 4.04 seconds
Started Feb 18 02:15:20 PM PST 24
Finished Feb 18 02:16:02 PM PST 24
Peak memory 217128 kb
Host smart-82c5930b-4686-4214-9834-03fae47efcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967411022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2967411022
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3421417972
Short name T832
Test name
Test status
Simulation time 12862770 ps
CPU time 0.72 seconds
Started Feb 18 02:12:41 PM PST 24
Finished Feb 18 02:13:22 PM PST 24
Peak memory 204712 kb
Host smart-8ce163ab-db08-44e9-8894-e9e6be32e434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421417972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
421417972
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1264948787
Short name T380
Test name
Test status
Simulation time 289802869 ps
CPU time 2.32 seconds
Started Feb 18 02:12:28 PM PST 24
Finished Feb 18 02:13:08 PM PST 24
Peak memory 217112 kb
Host smart-3809c1dc-8ebd-4955-90fc-79c230d9fa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264948787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1264948787
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.362474640
Short name T529
Test name
Test status
Simulation time 41778456 ps
CPU time 0.76 seconds
Started Feb 18 02:12:26 PM PST 24
Finished Feb 18 02:13:04 PM PST 24
Peak memory 204812 kb
Host smart-189ae4a1-eed1-4b04-9a02-c6157cdae309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362474640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.362474640
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3985437225
Short name T890
Test name
Test status
Simulation time 85765075248 ps
CPU time 172.67 seconds
Started Feb 18 02:12:37 PM PST 24
Finished Feb 18 02:16:10 PM PST 24
Peak memory 254536 kb
Host smart-0db055fa-74e5-4a66-8b1a-5f8a210c6ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985437225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3985437225
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3324123029
Short name T307
Test name
Test status
Simulation time 13165827418 ps
CPU time 72.45 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:14:13 PM PST 24
Peak memory 256916 kb
Host smart-e811dec1-b3d2-4e24-834e-90430b659f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324123029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3324123029
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.602784803
Short name T324
Test name
Test status
Simulation time 10010258740 ps
CPU time 82.76 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:14:25 PM PST 24
Peak memory 239172 kb
Host smart-dea7198e-47dc-4b07-afab-60badf0cc5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602784803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
602784803
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3645386715
Short name T302
Test name
Test status
Simulation time 5635264999 ps
CPU time 21.53 seconds
Started Feb 18 02:12:32 PM PST 24
Finished Feb 18 02:13:35 PM PST 24
Peak memory 233188 kb
Host smart-5520b2d5-6613-49ce-81d3-f4b3ff215c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645386715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3645386715
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3415880299
Short name T537
Test name
Test status
Simulation time 497200379 ps
CPU time 4.67 seconds
Started Feb 18 02:12:27 PM PST 24
Finished Feb 18 02:13:10 PM PST 24
Peak memory 220532 kb
Host smart-d8540674-fc18-4726-9c1a-6c7f6d237ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415880299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3415880299
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3589967103
Short name T771
Test name
Test status
Simulation time 9854429401 ps
CPU time 18.64 seconds
Started Feb 18 02:12:35 PM PST 24
Finished Feb 18 02:13:34 PM PST 24
Peak memory 240688 kb
Host smart-7c52da7a-c673-46fc-bc9a-b46e827a0017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589967103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3589967103
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.865384833
Short name T317
Test name
Test status
Simulation time 54346059 ps
CPU time 1.04 seconds
Started Feb 18 02:12:27 PM PST 24
Finished Feb 18 02:13:05 PM PST 24
Peak memory 217532 kb
Host smart-7e419b01-f39c-48af-9c3c-5f1876d97093
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865384833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.865384833
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3533619322
Short name T786
Test name
Test status
Simulation time 8032267210 ps
CPU time 29.88 seconds
Started Feb 18 02:12:26 PM PST 24
Finished Feb 18 02:13:34 PM PST 24
Peak memory 246544 kb
Host smart-88db8d8f-ba56-4d82-aa40-eb1acd06b65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533619322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3533619322
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4009558225
Short name T564
Test name
Test status
Simulation time 12499446158 ps
CPU time 19.6 seconds
Started Feb 18 02:12:27 PM PST 24
Finished Feb 18 02:13:25 PM PST 24
Peak memory 232568 kb
Host smart-0fe8460d-0d6f-40e1-a925-4a3e8f2d36e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009558225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4009558225
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2735443354
Short name T294
Test name
Test status
Simulation time 26683922 ps
CPU time 0.76 seconds
Started Feb 18 02:12:32 PM PST 24
Finished Feb 18 02:13:14 PM PST 24
Peak memory 215952 kb
Host smart-2e1304e9-2206-43b6-ad3f-a9962f2d0d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735443354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2735443354
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1240267198
Short name T657
Test name
Test status
Simulation time 950943545 ps
CPU time 3.72 seconds
Started Feb 18 02:12:32 PM PST 24
Finished Feb 18 02:13:17 PM PST 24
Peak memory 221480 kb
Host smart-b5bfa8c0-4773-469c-85fd-171b18c26ad5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1240267198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1240267198
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3239723029
Short name T51
Test name
Test status
Simulation time 40759101 ps
CPU time 0.96 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:23 PM PST 24
Peak memory 234328 kb
Host smart-4dfdf45e-e37b-44ea-b2d5-a2aab78906aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239723029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3239723029
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3210300163
Short name T132
Test name
Test status
Simulation time 269592330 ps
CPU time 1.16 seconds
Started Feb 18 02:12:26 PM PST 24
Finished Feb 18 02:13:04 PM PST 24
Peak memory 206432 kb
Host smart-dff6e041-7be1-48d5-b3f8-5008b001acea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210300163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3210300163
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3667196196
Short name T338
Test name
Test status
Simulation time 39339907964 ps
CPU time 48.07 seconds
Started Feb 18 02:12:27 PM PST 24
Finished Feb 18 02:13:52 PM PST 24
Peak memory 216252 kb
Host smart-40f675c7-cf52-4d37-8641-c4a101cae918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667196196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3667196196
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.222160692
Short name T968
Test name
Test status
Simulation time 22490887662 ps
CPU time 6.72 seconds
Started Feb 18 02:12:25 PM PST 24
Finished Feb 18 02:13:08 PM PST 24
Peak memory 216136 kb
Host smart-98bf510c-943c-4912-b100-930b86439d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222160692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.222160692
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.66409323
Short name T54
Test name
Test status
Simulation time 15532658 ps
CPU time 0.79 seconds
Started Feb 18 02:12:27 PM PST 24
Finished Feb 18 02:13:05 PM PST 24
Peak memory 205124 kb
Host smart-842974c4-c131-4151-959c-614348a5e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66409323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.66409323
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4266383359
Short name T797
Test name
Test status
Simulation time 33456962 ps
CPU time 0.82 seconds
Started Feb 18 02:12:31 PM PST 24
Finished Feb 18 02:13:12 PM PST 24
Peak memory 205084 kb
Host smart-8538604a-1171-43bf-9d80-0945421fa2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266383359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4266383359
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.587554285
Short name T528
Test name
Test status
Simulation time 4455328444 ps
CPU time 8.34 seconds
Started Feb 18 02:12:28 PM PST 24
Finished Feb 18 02:13:16 PM PST 24
Peak memory 217212 kb
Host smart-7a651557-e65a-4837-942c-b76149f761d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587554285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.587554285
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4279563711
Short name T523
Test name
Test status
Simulation time 11698160 ps
CPU time 0.7 seconds
Started Feb 18 02:15:32 PM PST 24
Finished Feb 18 02:16:09 PM PST 24
Peak memory 204156 kb
Host smart-df961499-aa73-47b8-8c36-27e9689f3aaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279563711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4279563711
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2219070045
Short name T653
Test name
Test status
Simulation time 85772363 ps
CPU time 2.84 seconds
Started Feb 18 02:15:30 PM PST 24
Finished Feb 18 02:16:09 PM PST 24
Peak memory 233320 kb
Host smart-6b0f634e-0296-4c1c-832c-6ecc44264ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219070045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2219070045
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2099030867
Short name T297
Test name
Test status
Simulation time 152269174 ps
CPU time 0.76 seconds
Started Feb 18 02:15:20 PM PST 24
Finished Feb 18 02:15:58 PM PST 24
Peak memory 204820 kb
Host smart-2009130e-6637-4b73-9d0d-f501fd5e6075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099030867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2099030867
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2957166982
Short name T458
Test name
Test status
Simulation time 7980206211 ps
CPU time 40.53 seconds
Started Feb 18 02:15:36 PM PST 24
Finished Feb 18 02:16:54 PM PST 24
Peak memory 240776 kb
Host smart-b7114a53-e300-40f7-b0d1-7cbbe4863559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957166982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2957166982
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.445825214
Short name T527
Test name
Test status
Simulation time 22817470206 ps
CPU time 65.12 seconds
Started Feb 18 02:15:31 PM PST 24
Finished Feb 18 02:17:12 PM PST 24
Peak memory 239752 kb
Host smart-7cc5ee96-f6e9-41fb-ad79-ab979ce15fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445825214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.445825214
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3833736440
Short name T141
Test name
Test status
Simulation time 4296817878 ps
CPU time 16.66 seconds
Started Feb 18 02:15:32 PM PST 24
Finished Feb 18 02:16:25 PM PST 24
Peak memory 221640 kb
Host smart-86474078-48af-4a19-abb9-03bf3c12ea82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833736440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3833736440
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4066311326
Short name T60
Test name
Test status
Simulation time 30184059863 ps
CPU time 35.13 seconds
Started Feb 18 02:15:31 PM PST 24
Finished Feb 18 02:16:43 PM PST 24
Peak memory 234000 kb
Host smart-25a2efda-1baf-46fc-9f26-c3461bbed178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066311326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4066311326
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1460008991
Short name T406
Test name
Test status
Simulation time 1451886679 ps
CPU time 7.64 seconds
Started Feb 18 02:15:30 PM PST 24
Finished Feb 18 02:16:13 PM PST 24
Peak memory 232844 kb
Host smart-91fa76b3-14bb-4820-bfff-667b7837158c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460008991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1460008991
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1891641877
Short name T737
Test name
Test status
Simulation time 2131192415 ps
CPU time 9.63 seconds
Started Feb 18 02:15:30 PM PST 24
Finished Feb 18 02:16:16 PM PST 24
Peak memory 247724 kb
Host smart-aa69f015-3fe8-46a1-9e40-d7f1084940b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891641877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1891641877
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1264300949
Short name T483
Test name
Test status
Simulation time 4688562144 ps
CPU time 17.77 seconds
Started Feb 18 02:15:30 PM PST 24
Finished Feb 18 02:16:24 PM PST 24
Peak memory 224384 kb
Host smart-4c9c5d26-5b34-4e6f-a4e9-7c20d93b829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264300949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1264300949
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2102866837
Short name T588
Test name
Test status
Simulation time 2669492798 ps
CPU time 4.04 seconds
Started Feb 18 02:15:31 PM PST 24
Finished Feb 18 02:16:11 PM PST 24
Peak memory 232888 kb
Host smart-bcb6e36a-e15e-4e3a-91a8-8809ff1f4a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102866837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2102866837
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2605161662
Short name T502
Test name
Test status
Simulation time 324650129 ps
CPU time 3.86 seconds
Started Feb 18 02:15:31 PM PST 24
Finished Feb 18 02:16:11 PM PST 24
Peak memory 219888 kb
Host smart-2f94d440-5a29-4510-91cc-5eb2ce72d5b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2605161662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2605161662
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1848933350
Short name T138
Test name
Test status
Simulation time 19352958031 ps
CPU time 70.45 seconds
Started Feb 18 02:15:32 PM PST 24
Finished Feb 18 02:17:19 PM PST 24
Peak memory 234476 kb
Host smart-e0325c97-cf9e-4472-8528-9cb0f47f1193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848933350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1848933350
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1475426154
Short name T479
Test name
Test status
Simulation time 2785661808 ps
CPU time 20.97 seconds
Started Feb 18 02:15:30 PM PST 24
Finished Feb 18 02:16:27 PM PST 24
Peak memory 218896 kb
Host smart-e19a18d5-ef85-47b5-8362-5c0542441e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475426154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1475426154
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3164798789
Short name T400
Test name
Test status
Simulation time 21510176418 ps
CPU time 12.48 seconds
Started Feb 18 02:15:30 PM PST 24
Finished Feb 18 02:16:19 PM PST 24
Peak memory 216204 kb
Host smart-23ec5f49-d373-4cd0-9ba2-f0fdd7aa2efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164798789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3164798789
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1556571146
Short name T808
Test name
Test status
Simulation time 129708729 ps
CPU time 4.07 seconds
Started Feb 18 02:15:33 PM PST 24
Finished Feb 18 02:16:14 PM PST 24
Peak memory 207880 kb
Host smart-0ce4b663-541c-4fca-aac2-126ea35cc2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556571146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1556571146
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.316277053
Short name T649
Test name
Test status
Simulation time 343617084 ps
CPU time 0.85 seconds
Started Feb 18 02:15:38 PM PST 24
Finished Feb 18 02:16:18 PM PST 24
Peak memory 205116 kb
Host smart-07880c90-b129-4ed6-bfd0-00a490f12675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316277053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.316277053
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1159495766
Short name T389
Test name
Test status
Simulation time 39845154251 ps
CPU time 21.36 seconds
Started Feb 18 02:15:35 PM PST 24
Finished Feb 18 02:16:34 PM PST 24
Peak memory 220140 kb
Host smart-6dacd350-af74-457f-8a37-c4fbd3735289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159495766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1159495766
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2937646468
Short name T823
Test name
Test status
Simulation time 14662382 ps
CPU time 0.72 seconds
Started Feb 18 02:15:32 PM PST 24
Finished Feb 18 02:16:09 PM PST 24
Peak memory 204700 kb
Host smart-48c2c859-53b3-448b-be33-33ae042f5da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937646468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2937646468
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.255874643
Short name T732
Test name
Test status
Simulation time 1341008820 ps
CPU time 5.08 seconds
Started Feb 18 02:15:39 PM PST 24
Finished Feb 18 02:16:24 PM PST 24
Peak memory 236640 kb
Host smart-168890d4-a334-4867-93b7-94ee3d8aacfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255874643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.255874643
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1503597615
Short name T809
Test name
Test status
Simulation time 35746561 ps
CPU time 0.78 seconds
Started Feb 18 02:15:39 PM PST 24
Finished Feb 18 02:16:19 PM PST 24
Peak memory 205180 kb
Host smart-49084b79-0c80-4111-8dd7-04dd5f0c538d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503597615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1503597615
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.449944750
Short name T33
Test name
Test status
Simulation time 195995890320 ps
CPU time 153.8 seconds
Started Feb 18 02:15:32 PM PST 24
Finished Feb 18 02:18:42 PM PST 24
Peak memory 267976 kb
Host smart-7a9e685a-6d96-4225-b1a2-c83190d3866d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449944750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.449944750
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3898165045
Short name T191
Test name
Test status
Simulation time 846405117274 ps
CPU time 562.25 seconds
Started Feb 18 02:15:35 PM PST 24
Finished Feb 18 02:25:35 PM PST 24
Peak memory 254468 kb
Host smart-c10af34d-8eaf-4b6b-8cf9-72772faf771a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898165045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3898165045
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2228023460
Short name T107
Test name
Test status
Simulation time 11220607046 ps
CPU time 107.57 seconds
Started Feb 18 02:15:39 PM PST 24
Finished Feb 18 02:18:06 PM PST 24
Peak memory 238364 kb
Host smart-864b7d50-ca27-4a5c-840a-66ab4f80c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228023460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2228023460
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.657364704
Short name T858
Test name
Test status
Simulation time 4294815077 ps
CPU time 22.57 seconds
Started Feb 18 02:15:32 PM PST 24
Finished Feb 18 02:16:31 PM PST 24
Peak memory 232576 kb
Host smart-16cedd10-4865-4bd8-a415-687f6954ae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657364704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.657364704
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3504192685
Short name T487
Test name
Test status
Simulation time 4448414088 ps
CPU time 4.94 seconds
Started Feb 18 02:15:39 PM PST 24
Finished Feb 18 02:16:23 PM PST 24
Peak memory 224220 kb
Host smart-b32f7684-2a4d-4811-97ee-8dbe35df8c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504192685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3504192685
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.151515477
Short name T456
Test name
Test status
Simulation time 9273213272 ps
CPU time 18.24 seconds
Started Feb 18 02:15:39 PM PST 24
Finished Feb 18 02:16:37 PM PST 24
Peak memory 234500 kb
Host smart-6aebaa84-f40f-48bc-a542-323d725dea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151515477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.151515477
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.947816178
Short name T175
Test name
Test status
Simulation time 277210461 ps
CPU time 2.95 seconds
Started Feb 18 02:15:35 PM PST 24
Finished Feb 18 02:16:15 PM PST 24
Peak memory 232452 kb
Host smart-d5bcd9a9-55fa-4f77-a0cb-307cd13845e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947816178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.947816178
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3676637367
Short name T905
Test name
Test status
Simulation time 12521473849 ps
CPU time 32.35 seconds
Started Feb 18 02:15:32 PM PST 24
Finished Feb 18 02:16:41 PM PST 24
Peak memory 238944 kb
Host smart-d053c229-5841-4b5c-848c-10aabd72bdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676637367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3676637367
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2617153718
Short name T455
Test name
Test status
Simulation time 204990968 ps
CPU time 3.73 seconds
Started Feb 18 02:15:35 PM PST 24
Finished Feb 18 02:16:15 PM PST 24
Peak memory 222292 kb
Host smart-380293cf-48b7-4854-800d-0de5220c7053
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2617153718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2617153718
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2369489638
Short name T196
Test name
Test status
Simulation time 407842864193 ps
CPU time 704.93 seconds
Started Feb 18 02:15:35 PM PST 24
Finished Feb 18 02:27:57 PM PST 24
Peak memory 270036 kb
Host smart-c53f1d65-bf76-4b27-abc3-d78aa88ecaac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369489638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2369489638
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3761754904
Short name T413
Test name
Test status
Simulation time 26769802374 ps
CPU time 58.29 seconds
Started Feb 18 02:15:36 PM PST 24
Finished Feb 18 02:17:12 PM PST 24
Peak memory 216476 kb
Host smart-ad50a45a-0353-4cbf-8acc-24f5e179c37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761754904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3761754904
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3566817459
Short name T839
Test name
Test status
Simulation time 7202593242 ps
CPU time 19.99 seconds
Started Feb 18 02:15:35 PM PST 24
Finished Feb 18 02:16:32 PM PST 24
Peak memory 216136 kb
Host smart-3ccda09a-a3b2-4d87-b2c9-141655097841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566817459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3566817459
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2328548831
Short name T981
Test name
Test status
Simulation time 253205888 ps
CPU time 1.37 seconds
Started Feb 18 02:15:39 PM PST 24
Finished Feb 18 02:16:20 PM PST 24
Peak memory 207444 kb
Host smart-9471fd6b-d7c3-4c13-89e8-dad68f9a7156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328548831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2328548831
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1918048880
Short name T495
Test name
Test status
Simulation time 32115029 ps
CPU time 0.72 seconds
Started Feb 18 02:15:31 PM PST 24
Finished Feb 18 02:16:08 PM PST 24
Peak memory 205104 kb
Host smart-3d184451-7a09-419d-b108-fc78f96e56eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918048880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1918048880
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2903827780
Short name T913
Test name
Test status
Simulation time 37683524 ps
CPU time 2.11 seconds
Started Feb 18 02:15:34 PM PST 24
Finished Feb 18 02:16:14 PM PST 24
Peak memory 223084 kb
Host smart-d3f265e1-cc8b-4eb7-b4fe-f7728a0f7781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903827780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2903827780
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1201902400
Short name T853
Test name
Test status
Simulation time 1477863753 ps
CPU time 6.18 seconds
Started Feb 18 02:15:42 PM PST 24
Finished Feb 18 02:16:27 PM PST 24
Peak memory 224180 kb
Host smart-99ca9ad0-92fe-42a4-bfe5-831e16abe488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201902400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1201902400
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.60478117
Short name T330
Test name
Test status
Simulation time 20944224 ps
CPU time 0.78 seconds
Started Feb 18 02:15:40 PM PST 24
Finished Feb 18 02:16:20 PM PST 24
Peak memory 206104 kb
Host smart-68f61d0e-0b76-4d74-9c90-5b34e1119047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60478117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.60478117
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3663734073
Short name T26
Test name
Test status
Simulation time 2253019158 ps
CPU time 31.7 seconds
Started Feb 18 02:15:41 PM PST 24
Finished Feb 18 02:16:52 PM PST 24
Peak memory 256792 kb
Host smart-88fd5c7b-b931-4f9b-aba7-ec27227c1e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663734073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3663734073
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1330181907
Short name T31
Test name
Test status
Simulation time 7457503655 ps
CPU time 139.47 seconds
Started Feb 18 02:15:42 PM PST 24
Finished Feb 18 02:18:40 PM PST 24
Peak memory 273064 kb
Host smart-76156b11-44fc-4175-ad56-78f3c8cf6b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330181907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1330181907
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1600545765
Short name T600
Test name
Test status
Simulation time 14979557365 ps
CPU time 14.81 seconds
Started Feb 18 02:15:38 PM PST 24
Finished Feb 18 02:16:32 PM PST 24
Peak memory 233624 kb
Host smart-30da5315-94bb-4e77-8f4c-df191f1fa3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600545765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1600545765
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3695834707
Short name T514
Test name
Test status
Simulation time 111578341 ps
CPU time 2.61 seconds
Started Feb 18 02:15:39 PM PST 24
Finished Feb 18 02:16:21 PM PST 24
Peak memory 233264 kb
Host smart-00f545e0-4f5c-4b99-bef1-4b0c775eb2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695834707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3695834707
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2156164083
Short name T10
Test name
Test status
Simulation time 11480235021 ps
CPU time 11.87 seconds
Started Feb 18 02:15:52 PM PST 24
Finished Feb 18 02:16:41 PM PST 24
Peak memory 232588 kb
Host smart-8128a50f-e09a-4478-8f49-c683fce20f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156164083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2156164083
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2687377193
Short name T452
Test name
Test status
Simulation time 96879716860 ps
CPU time 34.11 seconds
Started Feb 18 02:15:38 PM PST 24
Finished Feb 18 02:16:52 PM PST 24
Peak memory 232532 kb
Host smart-46bcf0cd-3948-458a-9e5b-1f3694f669f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687377193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2687377193
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1982257019
Short name T689
Test name
Test status
Simulation time 1496089094 ps
CPU time 9.62 seconds
Started Feb 18 02:15:34 PM PST 24
Finished Feb 18 02:16:20 PM PST 24
Peak memory 226488 kb
Host smart-da528b57-1571-4071-8e96-a17132d91960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982257019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1982257019
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1122137697
Short name T710
Test name
Test status
Simulation time 1394389678 ps
CPU time 4.37 seconds
Started Feb 18 02:15:38 PM PST 24
Finished Feb 18 02:16:22 PM PST 24
Peak memory 216084 kb
Host smart-3f9a8f76-b088-4f72-bc80-aeb18bacdcc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1122137697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1122137697
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1037944817
Short name T130
Test name
Test status
Simulation time 15564601916 ps
CPU time 94.64 seconds
Started Feb 18 02:15:39 PM PST 24
Finished Feb 18 02:17:53 PM PST 24
Peak memory 268228 kb
Host smart-ea7fe5b3-e265-4558-bf32-62dc9e73015f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037944817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1037944817
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2288865619
Short name T596
Test name
Test status
Simulation time 5622996016 ps
CPU time 6.8 seconds
Started Feb 18 02:15:32 PM PST 24
Finished Feb 18 02:16:15 PM PST 24
Peak memory 216140 kb
Host smart-a9175386-c3f1-4945-90d2-5e77d0b83311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288865619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2288865619
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2776120839
Short name T575
Test name
Test status
Simulation time 20787357938 ps
CPU time 15.82 seconds
Started Feb 18 02:15:37 PM PST 24
Finished Feb 18 02:16:32 PM PST 24
Peak memory 216160 kb
Host smart-0d56cf6a-5314-4d4b-b766-15ba095941cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776120839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2776120839
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3361180013
Short name T308
Test name
Test status
Simulation time 503323985 ps
CPU time 4.85 seconds
Started Feb 18 02:15:46 PM PST 24
Finished Feb 18 02:16:29 PM PST 24
Peak memory 208232 kb
Host smart-7ede067e-b4f2-4d7f-bc5c-9f5cb5443c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361180013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3361180013
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.422746029
Short name T269
Test name
Test status
Simulation time 183793576 ps
CPU time 0.83 seconds
Started Feb 18 02:15:34 PM PST 24
Finished Feb 18 02:16:12 PM PST 24
Peak memory 205108 kb
Host smart-edd38b04-76b8-40f0-a321-d00d86e1d14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422746029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.422746029
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.4268067154
Short name T965
Test name
Test status
Simulation time 13811959169 ps
CPU time 49.05 seconds
Started Feb 18 02:15:40 PM PST 24
Finished Feb 18 02:17:09 PM PST 24
Peak memory 235732 kb
Host smart-c4f735b4-c239-41e0-894b-52896f6ba5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268067154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.4268067154
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2529303374
Short name T439
Test name
Test status
Simulation time 38289358 ps
CPU time 0.71 seconds
Started Feb 18 02:15:48 PM PST 24
Finished Feb 18 02:16:27 PM PST 24
Peak memory 204732 kb
Host smart-4580a224-f8fc-4bcf-a6a7-f2e6e3341148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529303374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2529303374
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1796277647
Short name T263
Test name
Test status
Simulation time 394076015 ps
CPU time 2.88 seconds
Started Feb 18 02:15:47 PM PST 24
Finished Feb 18 02:16:28 PM PST 24
Peak memory 224160 kb
Host smart-6f71f24a-0f30-4857-80ab-2737f79c22c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796277647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1796277647
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2342297604
Short name T392
Test name
Test status
Simulation time 19417897 ps
CPU time 0.8 seconds
Started Feb 18 02:15:41 PM PST 24
Finished Feb 18 02:16:21 PM PST 24
Peak memory 205856 kb
Host smart-98653a60-6cac-43f9-9116-a5cef4cbdf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342297604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2342297604
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4172097082
Short name T186
Test name
Test status
Simulation time 25370005583 ps
CPU time 61.64 seconds
Started Feb 18 02:15:49 PM PST 24
Finished Feb 18 02:17:28 PM PST 24
Peak memory 255552 kb
Host smart-3b42d651-0b12-4eec-a18b-3efa9badb141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172097082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4172097082
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4055208093
Short name T71
Test name
Test status
Simulation time 2565483324 ps
CPU time 38.78 seconds
Started Feb 18 02:15:47 PM PST 24
Finished Feb 18 02:17:04 PM PST 24
Peak memory 233700 kb
Host smart-d2a82f69-3728-4142-941a-9fb016d2c0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055208093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4055208093
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2516461107
Short name T888
Test name
Test status
Simulation time 33995146138 ps
CPU time 298.87 seconds
Started Feb 18 02:15:53 PM PST 24
Finished Feb 18 02:21:29 PM PST 24
Peak memory 253900 kb
Host smart-710ff863-01ae-4540-a08c-3069891989dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516461107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2516461107
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.139167920
Short name T619
Test name
Test status
Simulation time 9466182820 ps
CPU time 23.82 seconds
Started Feb 18 02:15:50 PM PST 24
Finished Feb 18 02:16:51 PM PST 24
Peak memory 232592 kb
Host smart-6126e675-f8de-4960-8f28-734b40843305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139167920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.139167920
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2272750327
Short name T403
Test name
Test status
Simulation time 354233717 ps
CPU time 2.24 seconds
Started Feb 18 02:15:51 PM PST 24
Finished Feb 18 02:16:30 PM PST 24
Peak memory 223592 kb
Host smart-45ebd52a-1192-4378-add9-5d841776d2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272750327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2272750327
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1022679902
Short name T225
Test name
Test status
Simulation time 13226370307 ps
CPU time 15.16 seconds
Started Feb 18 02:15:50 PM PST 24
Finished Feb 18 02:16:42 PM PST 24
Peak memory 237844 kb
Host smart-728ccf6d-5ca1-4702-a7e9-e9e87fca3942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022679902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1022679902
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2158175501
Short name T901
Test name
Test status
Simulation time 8257774037 ps
CPU time 24.09 seconds
Started Feb 18 02:15:49 PM PST 24
Finished Feb 18 02:16:50 PM PST 24
Peak memory 233172 kb
Host smart-461b913b-3c3c-49ad-b18b-3f0efafe4d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158175501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2158175501
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.158985287
Short name T221
Test name
Test status
Simulation time 35217686191 ps
CPU time 28.46 seconds
Started Feb 18 02:15:48 PM PST 24
Finished Feb 18 02:16:54 PM PST 24
Peak memory 240392 kb
Host smart-74e54502-79e2-4603-83ea-06200487b3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158985287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.158985287
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2464846183
Short name T534
Test name
Test status
Simulation time 1167656221 ps
CPU time 4.56 seconds
Started Feb 18 02:15:49 PM PST 24
Finished Feb 18 02:16:31 PM PST 24
Peak memory 222128 kb
Host smart-46d67bb4-6a39-4fac-b6e0-e4170a5c56d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2464846183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2464846183
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3247617906
Short name T977
Test name
Test status
Simulation time 188399660815 ps
CPU time 411 seconds
Started Feb 18 02:15:53 PM PST 24
Finished Feb 18 02:23:20 PM PST 24
Peak memory 268564 kb
Host smart-d23d74ae-42de-4ce2-b123-d0bd12e78b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247617906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3247617906
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4082465380
Short name T867
Test name
Test status
Simulation time 5687631679 ps
CPU time 45.12 seconds
Started Feb 18 02:15:41 PM PST 24
Finished Feb 18 02:17:05 PM PST 24
Peak memory 216196 kb
Host smart-e981d3f1-976c-4315-b6ee-6dec1c7450ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082465380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4082465380
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4015020463
Short name T449
Test name
Test status
Simulation time 166992064 ps
CPU time 1.37 seconds
Started Feb 18 02:15:39 PM PST 24
Finished Feb 18 02:16:20 PM PST 24
Peak memory 206300 kb
Host smart-ac0838a8-2567-499c-b44e-0088514f8176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015020463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4015020463
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3201540997
Short name T258
Test name
Test status
Simulation time 674079802 ps
CPU time 2.15 seconds
Started Feb 18 02:15:51 PM PST 24
Finished Feb 18 02:16:30 PM PST 24
Peak memory 216408 kb
Host smart-732b009a-861c-4734-9303-0bc79f3a9403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201540997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3201540997
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3746623386
Short name T924
Test name
Test status
Simulation time 74253508 ps
CPU time 0.93 seconds
Started Feb 18 02:15:49 PM PST 24
Finished Feb 18 02:16:28 PM PST 24
Peak memory 206148 kb
Host smart-e4e122d8-b092-4c3a-9277-cdc1eaa9919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746623386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3746623386
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3916736218
Short name T583
Test name
Test status
Simulation time 1079237849 ps
CPU time 9.55 seconds
Started Feb 18 02:15:48 PM PST 24
Finished Feb 18 02:16:36 PM PST 24
Peak memory 233720 kb
Host smart-11210d7e-9b87-4faa-882b-e7e1976cb482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916736218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3916736218
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.844285785
Short name T775
Test name
Test status
Simulation time 13045609 ps
CPU time 0.69 seconds
Started Feb 18 02:15:57 PM PST 24
Finished Feb 18 02:16:33 PM PST 24
Peak memory 204704 kb
Host smart-a13255d9-223b-4892-93be-3c3a7772b4ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844285785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.844285785
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2929642508
Short name T169
Test name
Test status
Simulation time 4206672226 ps
CPU time 5.49 seconds
Started Feb 18 02:15:55 PM PST 24
Finished Feb 18 02:16:38 PM PST 24
Peak memory 224376 kb
Host smart-691ee8bb-ce33-442c-9297-cfd0afab3d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929642508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2929642508
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2020202377
Short name T812
Test name
Test status
Simulation time 17648082 ps
CPU time 0.78 seconds
Started Feb 18 02:15:48 PM PST 24
Finished Feb 18 02:16:27 PM PST 24
Peak memory 205916 kb
Host smart-1f64d513-dd7e-4168-960a-6f70225d348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020202377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2020202377
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2536181777
Short name T22
Test name
Test status
Simulation time 16379660372 ps
CPU time 73.04 seconds
Started Feb 18 02:15:56 PM PST 24
Finished Feb 18 02:17:45 PM PST 24
Peak memory 268608 kb
Host smart-4dbd5a03-f9cf-41cc-acd5-903a0903c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536181777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2536181777
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.204080772
Short name T25
Test name
Test status
Simulation time 43966935358 ps
CPU time 109.93 seconds
Started Feb 18 02:15:56 PM PST 24
Finished Feb 18 02:18:22 PM PST 24
Peak memory 267236 kb
Host smart-b111a8ef-80af-40e5-90f7-46b45ed76fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204080772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.204080772
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3351312439
Short name T120
Test name
Test status
Simulation time 35480204455 ps
CPU time 122.03 seconds
Started Feb 18 02:15:56 PM PST 24
Finished Feb 18 02:18:34 PM PST 24
Peak memory 257172 kb
Host smart-92ee7be1-a90e-42d1-b893-c70c945e2c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351312439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3351312439
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.560992507
Short name T113
Test name
Test status
Simulation time 986776860 ps
CPU time 14.13 seconds
Started Feb 18 02:15:52 PM PST 24
Finished Feb 18 02:16:43 PM PST 24
Peak memory 247460 kb
Host smart-7cc49d3c-5d16-4005-a9a5-0fb4a858c7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560992507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.560992507
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2213372352
Short name T238
Test name
Test status
Simulation time 18165560340 ps
CPU time 14.2 seconds
Started Feb 18 02:16:03 PM PST 24
Finished Feb 18 02:16:52 PM PST 24
Peak memory 234400 kb
Host smart-f17a32a5-e964-4f3f-9d24-e7c2f83b6ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213372352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2213372352
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.358143270
Short name T531
Test name
Test status
Simulation time 23382830787 ps
CPU time 20.04 seconds
Started Feb 18 02:15:58 PM PST 24
Finished Feb 18 02:16:53 PM PST 24
Peak memory 232548 kb
Host smart-52e8a027-aee6-4eed-b541-2a2e9fc77b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358143270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.358143270
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1876337231
Short name T203
Test name
Test status
Simulation time 10029188445 ps
CPU time 19.1 seconds
Started Feb 18 02:15:57 PM PST 24
Finished Feb 18 02:16:53 PM PST 24
Peak memory 240300 kb
Host smart-ce374825-f3f2-4df7-9d42-fdb5ae48aa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876337231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1876337231
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4139345841
Short name T794
Test name
Test status
Simulation time 13071677694 ps
CPU time 10.32 seconds
Started Feb 18 02:15:54 PM PST 24
Finished Feb 18 02:16:41 PM PST 24
Peak memory 224332 kb
Host smart-b6708449-4f3c-45c1-af8b-cf5a5b0ca6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139345841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4139345841
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1286198959
Short name T57
Test name
Test status
Simulation time 516319691 ps
CPU time 4.19 seconds
Started Feb 18 02:16:00 PM PST 24
Finished Feb 18 02:16:39 PM PST 24
Peak memory 219532 kb
Host smart-ae429869-f106-435b-aa34-ff9e479df646
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1286198959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1286198959
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.648227027
Short name T955
Test name
Test status
Simulation time 54327478465 ps
CPU time 118.53 seconds
Started Feb 18 02:15:52 PM PST 24
Finished Feb 18 02:18:28 PM PST 24
Peak memory 236532 kb
Host smart-0dfaff1e-ee48-4573-a2b9-1c3b597166cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648227027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.648227027
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2389109717
Short name T257
Test name
Test status
Simulation time 21051395778 ps
CPU time 99.25 seconds
Started Feb 18 02:15:52 PM PST 24
Finished Feb 18 02:18:08 PM PST 24
Peak memory 219128 kb
Host smart-e5ffe8bd-456c-48f8-874f-76c58280f49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389109717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2389109717
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1395608021
Short name T788
Test name
Test status
Simulation time 7409344257 ps
CPU time 6.09 seconds
Started Feb 18 02:15:53 PM PST 24
Finished Feb 18 02:16:36 PM PST 24
Peak memory 216208 kb
Host smart-c70b3c91-a33b-40f5-ac2c-f692cddffb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395608021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1395608021
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.611493872
Short name T476
Test name
Test status
Simulation time 225319796 ps
CPU time 5.11 seconds
Started Feb 18 02:16:01 PM PST 24
Finished Feb 18 02:16:40 PM PST 24
Peak memory 216132 kb
Host smart-291c2cfe-1f98-48b6-a78b-a6a3eca9e481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611493872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.611493872
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.876013238
Short name T912
Test name
Test status
Simulation time 53291113 ps
CPU time 0.97 seconds
Started Feb 18 02:15:51 PM PST 24
Finished Feb 18 02:16:29 PM PST 24
Peak memory 206124 kb
Host smart-e7a4679d-5942-47f7-bbc0-0c7259ed4096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876013238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.876013238
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1172179042
Short name T854
Test name
Test status
Simulation time 27036533638 ps
CPU time 17.16 seconds
Started Feb 18 02:15:52 PM PST 24
Finished Feb 18 02:16:46 PM PST 24
Peak memory 224304 kb
Host smart-a7454f14-1feb-4ace-a291-b8fff7a3d95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172179042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1172179042
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3149283749
Short name T684
Test name
Test status
Simulation time 75523267 ps
CPU time 0.7 seconds
Started Feb 18 02:16:01 PM PST 24
Finished Feb 18 02:16:37 PM PST 24
Peak memory 204736 kb
Host smart-f4a6736a-1de2-44f9-be06-54440b1a687a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149283749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3149283749
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1790782625
Short name T790
Test name
Test status
Simulation time 109789844 ps
CPU time 2.23 seconds
Started Feb 18 02:15:58 PM PST 24
Finished Feb 18 02:16:35 PM PST 24
Peak memory 233028 kb
Host smart-836ce592-3fe6-4fea-a0e1-fa745f25a517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790782625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1790782625
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1779516343
Short name T484
Test name
Test status
Simulation time 16150634 ps
CPU time 0.75 seconds
Started Feb 18 02:15:57 PM PST 24
Finished Feb 18 02:16:33 PM PST 24
Peak memory 205168 kb
Host smart-5ca48bf7-96ef-4908-9739-2087f210002e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779516343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1779516343
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1213840735
Short name T3
Test name
Test status
Simulation time 17479739137 ps
CPU time 69.27 seconds
Started Feb 18 02:15:58 PM PST 24
Finished Feb 18 02:17:42 PM PST 24
Peak memory 249292 kb
Host smart-47c5e87f-bf1b-4bed-8be4-255c100d2d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213840735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1213840735
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.227124116
Short name T438
Test name
Test status
Simulation time 99573146721 ps
CPU time 116.54 seconds
Started Feb 18 02:16:01 PM PST 24
Finished Feb 18 02:18:32 PM PST 24
Peak memory 236032 kb
Host smart-0997158a-bc22-490b-b1f7-a6ba03c04ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227124116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.227124116
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1984089370
Short name T673
Test name
Test status
Simulation time 10173799741 ps
CPU time 51.73 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:17:28 PM PST 24
Peak memory 232684 kb
Host smart-0b1e33b5-9e7d-4f91-b8a3-7ad2a6532391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984089370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1984089370
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3534138340
Short name T748
Test name
Test status
Simulation time 2294244064 ps
CPU time 5.57 seconds
Started Feb 18 02:15:53 PM PST 24
Finished Feb 18 02:16:35 PM PST 24
Peak memory 233176 kb
Host smart-23321da5-2964-4404-9805-a9af3fbe478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534138340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3534138340
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1793489273
Short name T368
Test name
Test status
Simulation time 14396835831 ps
CPU time 31.23 seconds
Started Feb 18 02:15:52 PM PST 24
Finished Feb 18 02:17:00 PM PST 24
Peak memory 229144 kb
Host smart-0d2fbbf1-0d2d-47ae-b2cb-97f524d254b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793489273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1793489273
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1887069947
Short name T936
Test name
Test status
Simulation time 5413270217 ps
CPU time 7.8 seconds
Started Feb 18 02:15:54 PM PST 24
Finished Feb 18 02:16:38 PM PST 24
Peak memory 233112 kb
Host smart-8fecced6-5cfa-4798-8350-56b2bf9ea2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887069947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1887069947
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3396615889
Short name T148
Test name
Test status
Simulation time 5127496514 ps
CPU time 19.83 seconds
Started Feb 18 02:15:57 PM PST 24
Finished Feb 18 02:16:52 PM PST 24
Peak memory 237976 kb
Host smart-09ccd13e-6ff0-4590-83ec-d2b758c3afd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396615889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3396615889
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1563471945
Short name T404
Test name
Test status
Simulation time 87340978 ps
CPU time 3.43 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:16:40 PM PST 24
Peak memory 222368 kb
Host smart-9d876866-d328-4509-b011-fa1861772b8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1563471945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1563471945
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4147803274
Short name T202
Test name
Test status
Simulation time 486211447786 ps
CPU time 1141.61 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:35:38 PM PST 24
Peak memory 287496 kb
Host smart-dd78101e-2d37-46f1-b912-57586a52fd33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147803274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4147803274
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4204399573
Short name T589
Test name
Test status
Simulation time 11456940173 ps
CPU time 50.2 seconds
Started Feb 18 02:15:57 PM PST 24
Finished Feb 18 02:17:23 PM PST 24
Peak memory 216308 kb
Host smart-48ce0673-dfa9-4c0e-bac0-a5ce93263bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204399573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4204399573
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.219444146
Short name T745
Test name
Test status
Simulation time 750241999 ps
CPU time 4.61 seconds
Started Feb 18 02:15:55 PM PST 24
Finished Feb 18 02:16:36 PM PST 24
Peak memory 207672 kb
Host smart-ad1b3716-2eb4-4636-b73d-ea99c55d20fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219444146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.219444146
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2877652142
Short name T377
Test name
Test status
Simulation time 348804938 ps
CPU time 1.56 seconds
Started Feb 18 02:15:53 PM PST 24
Finished Feb 18 02:16:31 PM PST 24
Peak memory 207876 kb
Host smart-3a0fb5d2-475f-4a73-9b33-92a2d5eb908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877652142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2877652142
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3765486352
Short name T72
Test name
Test status
Simulation time 673980403 ps
CPU time 1.1 seconds
Started Feb 18 02:15:57 PM PST 24
Finished Feb 18 02:16:34 PM PST 24
Peak memory 206068 kb
Host smart-648dbd37-f588-433c-96e0-160943cc2006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765486352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3765486352
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2760731486
Short name T972
Test name
Test status
Simulation time 549090582 ps
CPU time 5.21 seconds
Started Feb 18 02:15:57 PM PST 24
Finished Feb 18 02:16:38 PM PST 24
Peak memory 234276 kb
Host smart-a068f5a3-3d84-4fe2-aa78-cfc007827450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760731486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2760731486
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3090589489
Short name T395
Test name
Test status
Simulation time 12874087 ps
CPU time 0.69 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:16:37 PM PST 24
Peak memory 204168 kb
Host smart-cf9fe5d6-8944-4c14-998d-7397b44ad608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090589489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3090589489
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3563042356
Short name T846
Test name
Test status
Simulation time 2460602865 ps
CPU time 5.4 seconds
Started Feb 18 02:15:59 PM PST 24
Finished Feb 18 02:16:39 PM PST 24
Peak memory 219368 kb
Host smart-3990b8e8-cca3-4a27-883d-c86357bd7af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563042356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3563042356
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1981994135
Short name T640
Test name
Test status
Simulation time 16051377 ps
CPU time 0.74 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:16:37 PM PST 24
Peak memory 205168 kb
Host smart-dc44612e-6bc1-4fc6-a007-267c4d269cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981994135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1981994135
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2207052742
Short name T941
Test name
Test status
Simulation time 8445804031 ps
CPU time 43.26 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:17:20 PM PST 24
Peak memory 232528 kb
Host smart-ada50b08-bc7f-4b99-b879-e08f0d89253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207052742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2207052742
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2638183371
Short name T611
Test name
Test status
Simulation time 114334421921 ps
CPU time 196.84 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:19:53 PM PST 24
Peak memory 250076 kb
Host smart-bd908977-2513-474c-86ef-76f97377179e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638183371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2638183371
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2661987597
Short name T940
Test name
Test status
Simulation time 110806641652 ps
CPU time 184.39 seconds
Started Feb 18 02:16:00 PM PST 24
Finished Feb 18 02:19:40 PM PST 24
Peak memory 255032 kb
Host smart-1f429904-ec64-453a-a120-501b1c2fa1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661987597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2661987597
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4225508443
Short name T887
Test name
Test status
Simulation time 2719474887 ps
CPU time 9.04 seconds
Started Feb 18 02:15:59 PM PST 24
Finished Feb 18 02:16:43 PM PST 24
Peak memory 254968 kb
Host smart-64d7ec42-8e5f-4102-b02c-00469249d79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225508443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4225508443
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1534055029
Short name T489
Test name
Test status
Simulation time 2209073747 ps
CPU time 10.05 seconds
Started Feb 18 02:15:58 PM PST 24
Finished Feb 18 02:16:43 PM PST 24
Peak memory 233588 kb
Host smart-21fd830d-5d5f-46da-8070-eb1e38f3e51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534055029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1534055029
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1344024444
Short name T224
Test name
Test status
Simulation time 1372334770 ps
CPU time 11.73 seconds
Started Feb 18 02:15:58 PM PST 24
Finished Feb 18 02:16:45 PM PST 24
Peak memory 232912 kb
Host smart-bc00bc77-a2e2-43b1-8edd-63cd8e265a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344024444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1344024444
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2876798813
Short name T896
Test name
Test status
Simulation time 283856539 ps
CPU time 3.33 seconds
Started Feb 18 02:16:01 PM PST 24
Finished Feb 18 02:16:39 PM PST 24
Peak memory 232460 kb
Host smart-29107c97-8214-4872-928e-812dafd88504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876798813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2876798813
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1989947757
Short name T984
Test name
Test status
Simulation time 13052612229 ps
CPU time 21.38 seconds
Started Feb 18 02:16:03 PM PST 24
Finished Feb 18 02:16:59 PM PST 24
Peak memory 234772 kb
Host smart-3e890b16-18e8-40fa-b15e-121b9c5c62b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989947757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1989947757
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1310738913
Short name T567
Test name
Test status
Simulation time 110742309 ps
CPU time 3.68 seconds
Started Feb 18 02:16:00 PM PST 24
Finished Feb 18 02:16:39 PM PST 24
Peak memory 222336 kb
Host smart-b6a435f9-fc0a-422d-b0c4-33a7e26093fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1310738913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1310738913
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1336747724
Short name T441
Test name
Test status
Simulation time 8631552801 ps
CPU time 52.25 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:17:29 PM PST 24
Peak memory 234588 kb
Host smart-d3dc8f0d-c5ec-44f4-8f6b-569bb958af12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336747724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1336747724
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2444192158
Short name T975
Test name
Test status
Simulation time 578788882 ps
CPU time 10.18 seconds
Started Feb 18 02:16:01 PM PST 24
Finished Feb 18 02:16:46 PM PST 24
Peak memory 216008 kb
Host smart-0119d55b-0090-46d1-af3b-4d8f0fc23f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444192158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2444192158
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3323659872
Short name T734
Test name
Test status
Simulation time 10134181000 ps
CPU time 10.79 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:16:47 PM PST 24
Peak memory 216164 kb
Host smart-a241f07a-063e-42ea-ba55-76df2a112a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323659872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3323659872
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2874093347
Short name T670
Test name
Test status
Simulation time 560760687 ps
CPU time 1.85 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:16:38 PM PST 24
Peak memory 207956 kb
Host smart-486529b6-1ad9-4f1e-9e6f-61d791349110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874093347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2874093347
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2829366953
Short name T921
Test name
Test status
Simulation time 26067655 ps
CPU time 0.69 seconds
Started Feb 18 02:16:01 PM PST 24
Finished Feb 18 02:16:36 PM PST 24
Peak memory 205104 kb
Host smart-5738f56d-580f-45fa-9267-84621651567b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829366953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2829366953
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.149703816
Short name T436
Test name
Test status
Simulation time 423093124 ps
CPU time 2.8 seconds
Started Feb 18 02:16:01 PM PST 24
Finished Feb 18 02:16:39 PM PST 24
Peak memory 232820 kb
Host smart-0a1967e3-2c62-4af6-88e7-d07416b345ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149703816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.149703816
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.481080805
Short name T268
Test name
Test status
Simulation time 40217937 ps
CPU time 0.71 seconds
Started Feb 18 02:16:06 PM PST 24
Finished Feb 18 02:16:41 PM PST 24
Peak memory 204752 kb
Host smart-9a23e018-f466-4815-8fd9-91acafb508cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481080805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.481080805
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3577889595
Short name T807
Test name
Test status
Simulation time 30440555 ps
CPU time 2.23 seconds
Started Feb 18 02:16:06 PM PST 24
Finished Feb 18 02:16:42 PM PST 24
Peak memory 224208 kb
Host smart-bfb5d8e8-2a14-4d20-90e0-782a2d1e5e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577889595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3577889595
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.288933774
Short name T545
Test name
Test status
Simulation time 49254314 ps
CPU time 0.78 seconds
Started Feb 18 02:16:03 PM PST 24
Finished Feb 18 02:16:39 PM PST 24
Peak memory 205844 kb
Host smart-92732197-34f2-4b78-85dc-fafb9a84d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288933774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.288933774
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3899193104
Short name T934
Test name
Test status
Simulation time 4131608078 ps
CPU time 60.55 seconds
Started Feb 18 02:16:05 PM PST 24
Finished Feb 18 02:17:40 PM PST 24
Peak memory 248892 kb
Host smart-852df137-82a2-4463-8149-649bef896cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899193104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3899193104
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.46921145
Short name T206
Test name
Test status
Simulation time 72494981351 ps
CPU time 130.66 seconds
Started Feb 18 02:16:06 PM PST 24
Finished Feb 18 02:18:51 PM PST 24
Peak memory 269064 kb
Host smart-04ed3566-d57a-45bf-8ad1-f9ea3cc3dfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46921145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.46921145
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3417490079
Short name T183
Test name
Test status
Simulation time 16389022288 ps
CPU time 129.77 seconds
Started Feb 18 02:16:06 PM PST 24
Finished Feb 18 02:18:50 PM PST 24
Peak memory 266192 kb
Host smart-cf7abfc8-a2b8-49c4-81b7-74e919fb85ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417490079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3417490079
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2257768255
Short name T506
Test name
Test status
Simulation time 8039704677 ps
CPU time 46.65 seconds
Started Feb 18 02:16:08 PM PST 24
Finished Feb 18 02:17:27 PM PST 24
Peak memory 233536 kb
Host smart-cf49e780-a772-4ff7-86de-c81f44a5576d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257768255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2257768255
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3319810532
Short name T243
Test name
Test status
Simulation time 221293607 ps
CPU time 2.69 seconds
Started Feb 18 02:16:05 PM PST 24
Finished Feb 18 02:16:42 PM PST 24
Peak memory 216020 kb
Host smart-8edfdce2-e752-452c-bd4e-4172f28fcd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319810532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3319810532
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4159737033
Short name T586
Test name
Test status
Simulation time 5106138760 ps
CPU time 14.4 seconds
Started Feb 18 02:16:09 PM PST 24
Finished Feb 18 02:16:55 PM PST 24
Peak memory 236012 kb
Host smart-1ad57174-c5c2-4f37-b571-776f6887f8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159737033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4159737033
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3135565437
Short name T160
Test name
Test status
Simulation time 12426089974 ps
CPU time 18.89 seconds
Started Feb 18 02:16:06 PM PST 24
Finished Feb 18 02:16:59 PM PST 24
Peak memory 250536 kb
Host smart-7fdce782-ec13-46d2-b63c-d00d7e8a29a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135565437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3135565437
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3443031570
Short name T891
Test name
Test status
Simulation time 305592957 ps
CPU time 2.92 seconds
Started Feb 18 02:16:05 PM PST 24
Finished Feb 18 02:16:42 PM PST 24
Peak memory 218020 kb
Host smart-813121cc-a37e-4f30-b4fb-2f457f19b02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443031570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3443031570
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.881731051
Short name T417
Test name
Test status
Simulation time 5653469094 ps
CPU time 6.13 seconds
Started Feb 18 02:16:07 PM PST 24
Finished Feb 18 02:16:46 PM PST 24
Peak memory 219748 kb
Host smart-a9ce43d2-082b-4f74-9ca7-78e22b6898f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=881731051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.881731051
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.166630550
Short name T133
Test name
Test status
Simulation time 86508406025 ps
CPU time 624.56 seconds
Started Feb 18 02:16:07 PM PST 24
Finished Feb 18 02:27:05 PM PST 24
Peak memory 268528 kb
Host smart-d908a1dc-20e6-47ea-badd-e5c547c6a27b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166630550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.166630550
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4174720494
Short name T918
Test name
Test status
Simulation time 14338395130 ps
CPU time 45.35 seconds
Started Feb 18 02:15:58 PM PST 24
Finished Feb 18 02:17:18 PM PST 24
Peak memory 216164 kb
Host smart-424a060e-4919-4fa8-8d92-728dda713b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174720494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4174720494
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4170612020
Short name T70
Test name
Test status
Simulation time 19506540150 ps
CPU time 28.77 seconds
Started Feb 18 02:16:02 PM PST 24
Finished Feb 18 02:17:05 PM PST 24
Peak memory 216200 kb
Host smart-4fe52376-b204-4e49-a0ac-77b74c6c94b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170612020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4170612020
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1030281933
Short name T701
Test name
Test status
Simulation time 442688939 ps
CPU time 1.78 seconds
Started Feb 18 02:16:06 PM PST 24
Finished Feb 18 02:16:42 PM PST 24
Peak memory 216096 kb
Host smart-bd67d0f1-c2c5-4e55-9438-796a86bb5011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030281933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1030281933
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.564051105
Short name T468
Test name
Test status
Simulation time 163782811 ps
CPU time 0.84 seconds
Started Feb 18 02:16:05 PM PST 24
Finished Feb 18 02:16:40 PM PST 24
Peak memory 205128 kb
Host smart-3c402ee2-9cbe-4924-a665-fa23496ede3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564051105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.564051105
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2651790128
Short name T5
Test name
Test status
Simulation time 815278906 ps
CPU time 5.03 seconds
Started Feb 18 02:16:05 PM PST 24
Finished Feb 18 02:16:45 PM PST 24
Peak memory 233320 kb
Host smart-752d4293-baff-423f-a889-aa54c85c4e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651790128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2651790128
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3108136149
Short name T43
Test name
Test status
Simulation time 24664686 ps
CPU time 0.7 seconds
Started Feb 18 02:16:15 PM PST 24
Finished Feb 18 02:16:46 PM PST 24
Peak memory 205036 kb
Host smart-e139c2ef-a634-4139-b9ac-b0a46be1510e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108136149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3108136149
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.348720878
Short name T376
Test name
Test status
Simulation time 550554889 ps
CPU time 4.09 seconds
Started Feb 18 02:16:07 PM PST 24
Finished Feb 18 02:16:44 PM PST 24
Peak memory 235660 kb
Host smart-787881b0-e4f4-491f-bbb1-30a399061c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348720878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.348720878
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3575215747
Short name T799
Test name
Test status
Simulation time 15275490 ps
CPU time 0.75 seconds
Started Feb 18 02:16:08 PM PST 24
Finished Feb 18 02:16:41 PM PST 24
Peak memory 204720 kb
Host smart-e1f13452-47d7-40b5-a4b0-4866c63f2cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575215747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3575215747
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1104535302
Short name T188
Test name
Test status
Simulation time 45468538756 ps
CPU time 59.8 seconds
Started Feb 18 02:16:18 PM PST 24
Finished Feb 18 02:17:47 PM PST 24
Peak memory 239740 kb
Host smart-71ff2463-e0e0-4740-ae87-9ed46e3de15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104535302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1104535302
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3176523385
Short name T776
Test name
Test status
Simulation time 45106184651 ps
CPU time 109.74 seconds
Started Feb 18 02:16:08 PM PST 24
Finished Feb 18 02:18:30 PM PST 24
Peak memory 256496 kb
Host smart-9a3ec132-1535-4313-8f54-872b4a4fd01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176523385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3176523385
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.864911198
Short name T759
Test name
Test status
Simulation time 6725172025 ps
CPU time 38.19 seconds
Started Feb 18 02:16:06 PM PST 24
Finished Feb 18 02:17:18 PM PST 24
Peak memory 248988 kb
Host smart-7d2c29c1-e03e-485a-894d-3476a283e017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864911198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.864911198
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2733235065
Short name T373
Test name
Test status
Simulation time 4555034003 ps
CPU time 22.31 seconds
Started Feb 18 02:16:09 PM PST 24
Finished Feb 18 02:17:04 PM PST 24
Peak memory 237160 kb
Host smart-93269e39-a832-49cb-b1ab-03dc8e802063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733235065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2733235065
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3214731590
Short name T526
Test name
Test status
Simulation time 657649532 ps
CPU time 3.59 seconds
Started Feb 18 02:16:06 PM PST 24
Finished Feb 18 02:16:43 PM PST 24
Peak memory 224212 kb
Host smart-d172b2a8-a591-4ad1-8c64-b48c6d6a59bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214731590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3214731590
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3066054721
Short name T900
Test name
Test status
Simulation time 37397797 ps
CPU time 2.35 seconds
Started Feb 18 02:16:19 PM PST 24
Finished Feb 18 02:16:50 PM PST 24
Peak memory 224172 kb
Host smart-af700ced-a059-42b2-8dee-f337bff27b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066054721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3066054721
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2166629142
Short name T666
Test name
Test status
Simulation time 3488454592 ps
CPU time 3.13 seconds
Started Feb 18 02:16:03 PM PST 24
Finished Feb 18 02:16:40 PM PST 24
Peak memory 216564 kb
Host smart-35157a6e-fdb0-4223-b82c-4e7dfa378cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166629142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2166629142
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.217145559
Short name T119
Test name
Test status
Simulation time 2776252079 ps
CPU time 9.52 seconds
Started Feb 18 02:16:18 PM PST 24
Finished Feb 18 02:16:56 PM PST 24
Peak memory 227684 kb
Host smart-643ae616-46b4-4bb6-85f8-48d7fdaeac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217145559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.217145559
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.111714071
Short name T111
Test name
Test status
Simulation time 1159052100 ps
CPU time 5.9 seconds
Started Feb 18 02:16:08 PM PST 24
Finished Feb 18 02:16:46 PM PST 24
Peak memory 221388 kb
Host smart-05552676-8fb4-4ac3-b15f-376c0b09dd1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111714071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.111714071
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2328537772
Short name T754
Test name
Test status
Simulation time 2344194908 ps
CPU time 32.68 seconds
Started Feb 18 02:16:10 PM PST 24
Finished Feb 18 02:17:14 PM PST 24
Peak memory 216196 kb
Host smart-7f26a956-faf7-4aee-82a9-b69077c09456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328537772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2328537772
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.450360771
Short name T907
Test name
Test status
Simulation time 228616387 ps
CPU time 1.1 seconds
Started Feb 18 02:16:06 PM PST 24
Finished Feb 18 02:16:41 PM PST 24
Peak memory 206296 kb
Host smart-f5a9efd8-19cf-4768-9382-0580e891c056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450360771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.450360771
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1684000954
Short name T475
Test name
Test status
Simulation time 279244077 ps
CPU time 3.68 seconds
Started Feb 18 02:16:08 PM PST 24
Finished Feb 18 02:16:44 PM PST 24
Peak memory 208992 kb
Host smart-cdbcd932-fbb8-4a5a-8d6a-0fd28ab79f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684000954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1684000954
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2578385987
Short name T402
Test name
Test status
Simulation time 51256972 ps
CPU time 0.79 seconds
Started Feb 18 02:16:08 PM PST 24
Finished Feb 18 02:16:41 PM PST 24
Peak memory 205060 kb
Host smart-16eaa8d4-7fa0-40a9-b512-8eee993f2a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578385987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2578385987
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1495882165
Short name T147
Test name
Test status
Simulation time 48242709848 ps
CPU time 24.85 seconds
Started Feb 18 02:16:08 PM PST 24
Finished Feb 18 02:17:05 PM PST 24
Peak memory 232556 kb
Host smart-62c61e01-a235-45ae-b3f9-89025b714b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495882165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1495882165
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1525089631
Short name T805
Test name
Test status
Simulation time 49533582 ps
CPU time 0.75 seconds
Started Feb 18 02:16:16 PM PST 24
Finished Feb 18 02:16:46 PM PST 24
Peak memory 204720 kb
Host smart-6fed33de-0f5b-4542-b852-6682891247d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525089631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1525089631
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.551151998
Short name T387
Test name
Test status
Simulation time 167635008 ps
CPU time 2.62 seconds
Started Feb 18 02:16:17 PM PST 24
Finished Feb 18 02:16:49 PM PST 24
Peak memory 216240 kb
Host smart-3945101c-aee5-4021-9fda-917a0f10b543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551151998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.551151998
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.933653224
Short name T730
Test name
Test status
Simulation time 36648791 ps
CPU time 0.76 seconds
Started Feb 18 02:16:16 PM PST 24
Finished Feb 18 02:16:46 PM PST 24
Peak memory 204816 kb
Host smart-966967cf-f513-4aca-b9fe-5c79dcc6bbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933653224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.933653224
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2463562129
Short name T205
Test name
Test status
Simulation time 11149044803 ps
CPU time 54.98 seconds
Started Feb 18 02:16:18 PM PST 24
Finished Feb 18 02:17:42 PM PST 24
Peak memory 249876 kb
Host smart-0b61d7d2-2938-47f7-8d0a-976d68f707f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463562129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2463562129
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.579344970
Short name T194
Test name
Test status
Simulation time 39749360097 ps
CPU time 305.45 seconds
Started Feb 18 02:16:17 PM PST 24
Finished Feb 18 02:21:51 PM PST 24
Peak memory 248652 kb
Host smart-a4791308-4727-4e30-812a-8fd628f50163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579344970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.579344970
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3403921452
Short name T970
Test name
Test status
Simulation time 3458940325 ps
CPU time 11.94 seconds
Started Feb 18 02:16:19 PM PST 24
Finished Feb 18 02:16:59 PM PST 24
Peak memory 232472 kb
Host smart-f1a23a9f-6240-44f0-8ee6-877a12c1dfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403921452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3403921452
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.829504385
Short name T422
Test name
Test status
Simulation time 225035644 ps
CPU time 3.4 seconds
Started Feb 18 02:16:17 PM PST 24
Finished Feb 18 02:16:49 PM PST 24
Peak memory 233244 kb
Host smart-ca7eb32d-d89d-41a7-a590-9dc0c31be06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829504385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.829504385
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2765818239
Short name T270
Test name
Test status
Simulation time 2079132540 ps
CPU time 14.56 seconds
Started Feb 18 02:16:16 PM PST 24
Finished Feb 18 02:17:00 PM PST 24
Peak memory 247572 kb
Host smart-5a4ce4cc-4bc0-4b4a-a920-c722f44ed4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765818239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2765818239
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3545433823
Short name T646
Test name
Test status
Simulation time 21193436542 ps
CPU time 12.82 seconds
Started Feb 18 02:16:16 PM PST 24
Finished Feb 18 02:16:58 PM PST 24
Peak memory 234852 kb
Host smart-a0c962ce-89a4-4930-9d1a-f1a2def1bd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545433823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3545433823
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4108170510
Short name T804
Test name
Test status
Simulation time 2874600407 ps
CPU time 4.67 seconds
Started Feb 18 02:16:14 PM PST 24
Finished Feb 18 02:16:49 PM PST 24
Peak memory 232748 kb
Host smart-e582e354-07fa-41da-8a6b-61c9fb35230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108170510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4108170510
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.228130345
Short name T618
Test name
Test status
Simulation time 1614922685 ps
CPU time 4.33 seconds
Started Feb 18 02:16:20 PM PST 24
Finished Feb 18 02:16:53 PM PST 24
Peak memory 221444 kb
Host smart-f11e2408-13dc-40fb-83ef-ee1086b5724d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=228130345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.228130345
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3233756281
Short name T144
Test name
Test status
Simulation time 116384926739 ps
CPU time 441.35 seconds
Started Feb 18 02:16:16 PM PST 24
Finished Feb 18 02:24:07 PM PST 24
Peak memory 264728 kb
Host smart-4db36c02-8cff-44b9-8ec4-9f0f90fd02d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233756281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3233756281
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.913227303
Short name T826
Test name
Test status
Simulation time 18085064811 ps
CPU time 114.5 seconds
Started Feb 18 02:16:15 PM PST 24
Finished Feb 18 02:18:40 PM PST 24
Peak memory 216200 kb
Host smart-bf831f10-e6c7-4fa3-a24a-e175e5c442fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913227303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.913227303
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3949081315
Short name T544
Test name
Test status
Simulation time 3241078188 ps
CPU time 14.55 seconds
Started Feb 18 02:16:17 PM PST 24
Finished Feb 18 02:17:01 PM PST 24
Peak memory 216224 kb
Host smart-f44f3bf6-249e-4788-9582-f937883b6db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949081315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3949081315
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3368706448
Short name T962
Test name
Test status
Simulation time 394710202 ps
CPU time 5.33 seconds
Started Feb 18 02:16:15 PM PST 24
Finished Feb 18 02:16:50 PM PST 24
Peak memory 207900 kb
Host smart-4fddfffb-8d0c-4400-a42a-2630f4d70af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368706448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3368706448
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3243193611
Short name T945
Test name
Test status
Simulation time 91013877 ps
CPU time 0.89 seconds
Started Feb 18 02:16:19 PM PST 24
Finished Feb 18 02:16:48 PM PST 24
Peak memory 205024 kb
Host smart-56317a88-3e86-461c-8e56-7599b1b11bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243193611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3243193611
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1521193559
Short name T933
Test name
Test status
Simulation time 2130441529 ps
CPU time 13.38 seconds
Started Feb 18 02:16:17 PM PST 24
Finished Feb 18 02:16:59 PM PST 24
Peak memory 232396 kb
Host smart-c9dec3f1-9b69-4cb9-a8e0-3c006124de79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521193559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1521193559
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1960054719
Short name T957
Test name
Test status
Simulation time 22974216 ps
CPU time 0.7 seconds
Started Feb 18 02:12:37 PM PST 24
Finished Feb 18 02:13:19 PM PST 24
Peak memory 204156 kb
Host smart-e6d1fd0f-bd52-4360-be98-ad36f26a7ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960054719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
960054719
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1579129750
Short name T434
Test name
Test status
Simulation time 261932795 ps
CPU time 3.25 seconds
Started Feb 18 02:12:34 PM PST 24
Finished Feb 18 02:13:17 PM PST 24
Peak memory 233024 kb
Host smart-6bdbda3a-5ec5-4ec6-baa9-7c4729a7c17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579129750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1579129750
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4239868524
Short name T292
Test name
Test status
Simulation time 142292534 ps
CPU time 0.78 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:28 PM PST 24
Peak memory 205804 kb
Host smart-b977a34b-8b66-4647-8f6e-b870850a1208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239868524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4239868524
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2324779367
Short name T953
Test name
Test status
Simulation time 18029692877 ps
CPU time 109.62 seconds
Started Feb 18 02:12:47 PM PST 24
Finished Feb 18 02:15:26 PM PST 24
Peak memory 253604 kb
Host smart-977bafaf-6e5e-46d8-86cb-645000ade14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324779367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2324779367
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4016378872
Short name T55
Test name
Test status
Simulation time 64374774624 ps
CPU time 159.15 seconds
Started Feb 18 02:12:39 PM PST 24
Finished Feb 18 02:16:00 PM PST 24
Peak memory 258896 kb
Host smart-f414d605-8d80-4a89-bb90-e178e0454344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016378872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4016378872
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4133926780
Short name T150
Test name
Test status
Simulation time 247220517194 ps
CPU time 799.19 seconds
Started Feb 18 02:12:41 PM PST 24
Finished Feb 18 02:26:40 PM PST 24
Peak memory 270632 kb
Host smart-624b20f4-a426-4a0d-9f97-e057bd7006aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133926780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4133926780
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3572136180
Short name T519
Test name
Test status
Simulation time 5277786731 ps
CPU time 18 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:40 PM PST 24
Peak memory 251940 kb
Host smart-7340cca4-cefe-41c8-bb3e-6ee8f58725a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572136180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3572136180
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2293844917
Short name T470
Test name
Test status
Simulation time 928295667 ps
CPU time 3.75 seconds
Started Feb 18 02:12:41 PM PST 24
Finished Feb 18 02:13:25 PM PST 24
Peak memory 232368 kb
Host smart-405f6a2d-7e0b-49fe-8d60-8fe203ab054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293844917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2293844917
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3328939912
Short name T283
Test name
Test status
Simulation time 371947334 ps
CPU time 2.52 seconds
Started Feb 18 02:12:42 PM PST 24
Finished Feb 18 02:13:25 PM PST 24
Peak memory 224172 kb
Host smart-0beb91d6-050a-4947-ab76-e15f1f895868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328939912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3328939912
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.523274508
Short name T609
Test name
Test status
Simulation time 119346131 ps
CPU time 1.05 seconds
Started Feb 18 02:12:38 PM PST 24
Finished Feb 18 02:13:20 PM PST 24
Peak memory 216304 kb
Host smart-21c0711a-7bba-49a0-9e9f-f3d66894dc89
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523274508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.523274508
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1761493264
Short name T721
Test name
Test status
Simulation time 21039156185 ps
CPU time 23.93 seconds
Started Feb 18 02:12:38 PM PST 24
Finished Feb 18 02:13:43 PM PST 24
Peak memory 231544 kb
Host smart-3b143f47-68b3-4018-84d1-d9fccefb693f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761493264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1761493264
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1696739125
Short name T937
Test name
Test status
Simulation time 3047511191 ps
CPU time 11.8 seconds
Started Feb 18 02:12:37 PM PST 24
Finished Feb 18 02:13:29 PM PST 24
Peak memory 232228 kb
Host smart-1cc05be6-6f66-4045-a87f-8ab7a29bfabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696739125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1696739125
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.1118926416
Short name T288
Test name
Test status
Simulation time 32271389 ps
CPU time 0.74 seconds
Started Feb 18 02:12:38 PM PST 24
Finished Feb 18 02:13:20 PM PST 24
Peak memory 216032 kb
Host smart-1ce29319-9b2c-4cb8-bbbd-0b56112f2921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118926416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1118926416
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3286215160
Short name T115
Test name
Test status
Simulation time 209295313 ps
CPU time 3.78 seconds
Started Feb 18 02:12:34 PM PST 24
Finished Feb 18 02:13:19 PM PST 24
Peak memory 222216 kb
Host smart-e735e905-8428-455d-a432-1f4eba86f38a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3286215160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3286215160
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1949849036
Short name T682
Test name
Test status
Simulation time 3854555356 ps
CPU time 41.05 seconds
Started Feb 18 02:12:35 PM PST 24
Finished Feb 18 02:13:56 PM PST 24
Peak memory 219948 kb
Host smart-e475b981-3718-4289-9bc3-944c1767d317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949849036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1949849036
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.888630348
Short name T369
Test name
Test status
Simulation time 44321187581 ps
CPU time 33.99 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:14:02 PM PST 24
Peak memory 216216 kb
Host smart-277b7979-aa8d-4b7b-98a0-6036d8acfa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888630348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.888630348
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2563959979
Short name T509
Test name
Test status
Simulation time 48446566 ps
CPU time 0.81 seconds
Started Feb 18 02:12:33 PM PST 24
Finished Feb 18 02:13:14 PM PST 24
Peak memory 205848 kb
Host smart-1da30a64-12b2-4e36-a7d9-befb197540fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563959979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2563959979
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.522974507
Short name T419
Test name
Test status
Simulation time 494183433 ps
CPU time 0.85 seconds
Started Feb 18 02:12:42 PM PST 24
Finished Feb 18 02:13:23 PM PST 24
Peak memory 205072 kb
Host smart-5a118dbc-bdce-459b-b7c7-827417adb18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522974507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.522974507
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.601460091
Short name T7
Test name
Test status
Simulation time 1511379233 ps
CPU time 6.19 seconds
Started Feb 18 02:12:46 PM PST 24
Finished Feb 18 02:13:41 PM PST 24
Peak memory 234568 kb
Host smart-10f30440-4d60-4ef5-8020-33446f0e0005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601460091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.601460091
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3762286223
Short name T275
Test name
Test status
Simulation time 42239337 ps
CPU time 0.79 seconds
Started Feb 18 02:12:38 PM PST 24
Finished Feb 18 02:13:20 PM PST 24
Peak memory 204168 kb
Host smart-cf67af31-7233-489e-aee8-7325a3db28b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762286223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
762286223
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2888015043
Short name T245
Test name
Test status
Simulation time 661083450 ps
CPU time 4.78 seconds
Started Feb 18 02:12:39 PM PST 24
Finished Feb 18 02:13:25 PM PST 24
Peak memory 233348 kb
Host smart-a8b5e9b3-6e00-47e2-8312-f8fcbb1521a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888015043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2888015043
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3985241952
Short name T722
Test name
Test status
Simulation time 66907944 ps
CPU time 0.73 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:23 PM PST 24
Peak memory 204744 kb
Host smart-10be0014-321a-47d5-bda5-26e6d6f34477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985241952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3985241952
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.689275811
Short name T691
Test name
Test status
Simulation time 15774263054 ps
CPU time 44.1 seconds
Started Feb 18 02:12:31 PM PST 24
Finished Feb 18 02:13:55 PM PST 24
Peak memory 240764 kb
Host smart-123c288b-808f-4549-bbbe-0e2c5e05e24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689275811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.689275811
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2238624904
Short name T254
Test name
Test status
Simulation time 13514182370 ps
CPU time 109.38 seconds
Started Feb 18 02:12:44 PM PST 24
Finished Feb 18 02:15:15 PM PST 24
Peak memory 235148 kb
Host smart-677ade83-d2ae-4336-9e82-262946e2cb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238624904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2238624904
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2865062636
Short name T595
Test name
Test status
Simulation time 125373135825 ps
CPU time 226.65 seconds
Started Feb 18 02:12:39 PM PST 24
Finished Feb 18 02:17:07 PM PST 24
Peak memory 251776 kb
Host smart-ad2700b1-a1db-40ee-81fc-4f9afa68d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865062636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2865062636
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_intercept.423821235
Short name T53
Test name
Test status
Simulation time 2226110805 ps
CPU time 5.4 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:33 PM PST 24
Peak memory 233912 kb
Host smart-1ccc9cbb-cb19-41b6-afcf-bd8c224d574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423821235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.423821235
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1179477386
Short name T688
Test name
Test status
Simulation time 10900953716 ps
CPU time 26.86 seconds
Started Feb 18 02:12:42 PM PST 24
Finished Feb 18 02:13:50 PM PST 24
Peak memory 224304 kb
Host smart-43ac3a5a-1196-43ef-ae54-1cfeed01234b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179477386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1179477386
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3857913637
Short name T792
Test name
Test status
Simulation time 89525521 ps
CPU time 1.06 seconds
Started Feb 18 02:12:41 PM PST 24
Finished Feb 18 02:13:23 PM PST 24
Peak memory 216312 kb
Host smart-90d059bf-70a5-4858-9535-acc493e5aec4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857913637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3857913637
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.524577857
Short name T780
Test name
Test status
Simulation time 2060922963 ps
CPU time 10.65 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:38 PM PST 24
Peak memory 216508 kb
Host smart-2b058bd1-efe3-4553-8235-f051b28d5a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524577857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
524577857
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2221558338
Short name T747
Test name
Test status
Simulation time 35433296778 ps
CPU time 21.07 seconds
Started Feb 18 02:12:37 PM PST 24
Finished Feb 18 02:13:39 PM PST 24
Peak memory 233008 kb
Host smart-b39652d2-23cd-4b9c-86dc-afab4c672619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221558338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2221558338
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.618109823
Short name T698
Test name
Test status
Simulation time 28998957 ps
CPU time 0.73 seconds
Started Feb 18 02:12:32 PM PST 24
Finished Feb 18 02:13:13 PM PST 24
Peak memory 215988 kb
Host smart-572b63e4-47e1-4635-9f6e-c9c9c0b7b8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618109823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.618109823
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.756035936
Short name T508
Test name
Test status
Simulation time 397474665 ps
CPU time 4.59 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:27 PM PST 24
Peak memory 222272 kb
Host smart-92156e1e-f301-4a1a-ace4-7bce5ba5cf55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=756035936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.756035936
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1988178889
Short name T810
Test name
Test status
Simulation time 90693537724 ps
CPU time 177.34 seconds
Started Feb 18 02:12:34 PM PST 24
Finished Feb 18 02:16:11 PM PST 24
Peak memory 249024 kb
Host smart-25f32d15-d738-4780-ac1f-2b7c17335797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988178889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1988178889
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.97768436
Short name T253
Test name
Test status
Simulation time 2963860451 ps
CPU time 6.54 seconds
Started Feb 18 02:12:42 PM PST 24
Finished Feb 18 02:13:30 PM PST 24
Peak memory 216204 kb
Host smart-aea2ad51-1ba0-41aa-8038-db258677250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97768436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.97768436
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.756575049
Short name T445
Test name
Test status
Simulation time 11741539023 ps
CPU time 2.58 seconds
Started Feb 18 02:12:41 PM PST 24
Finished Feb 18 02:13:26 PM PST 24
Peak memory 207784 kb
Host smart-e7e62a12-826e-4824-b59b-7e3b810a08ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756575049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.756575049
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3203987476
Short name T451
Test name
Test status
Simulation time 105578898 ps
CPU time 3.65 seconds
Started Feb 18 02:12:32 PM PST 24
Finished Feb 18 02:13:16 PM PST 24
Peak memory 216080 kb
Host smart-01826624-9ba3-44b6-8487-38534a8fbf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203987476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3203987476
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1997096013
Short name T271
Test name
Test status
Simulation time 53157596 ps
CPU time 0.88 seconds
Started Feb 18 02:12:42 PM PST 24
Finished Feb 18 02:13:24 PM PST 24
Peak memory 205128 kb
Host smart-b0050a60-9af8-4a16-ab0c-84c99bdb37b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997096013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1997096013
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3033006448
Short name T603
Test name
Test status
Simulation time 3768794128 ps
CPU time 5.01 seconds
Started Feb 18 02:12:35 PM PST 24
Finished Feb 18 02:13:20 PM PST 24
Peak memory 216156 kb
Host smart-d892c985-e4c7-4e5d-a2bf-1349a19a8898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033006448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3033006448
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1564150898
Short name T818
Test name
Test status
Simulation time 13104921 ps
CPU time 0.73 seconds
Started Feb 18 02:12:48 PM PST 24
Finished Feb 18 02:13:37 PM PST 24
Peak memory 204704 kb
Host smart-499724af-242d-4614-b907-39d3d31b193d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564150898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
564150898
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2931392943
Short name T236
Test name
Test status
Simulation time 72394727 ps
CPU time 2.25 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:24 PM PST 24
Peak memory 224216 kb
Host smart-6e4090f0-71b9-417d-abeb-c1f9745d76e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931392943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2931392943
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.106836922
Short name T574
Test name
Test status
Simulation time 16869968 ps
CPU time 0.77 seconds
Started Feb 18 02:12:35 PM PST 24
Finished Feb 18 02:13:16 PM PST 24
Peak memory 205840 kb
Host smart-2ca75bf2-dce1-4169-bc22-1b7f079699cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106836922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.106836922
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2190242757
Short name T661
Test name
Test status
Simulation time 331848691 ps
CPU time 4.23 seconds
Started Feb 18 02:12:39 PM PST 24
Finished Feb 18 02:13:23 PM PST 24
Peak memory 236424 kb
Host smart-aeb7f774-acc0-4221-8be2-ae2a10fb9e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190242757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2190242757
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2805713172
Short name T200
Test name
Test status
Simulation time 231432462686 ps
CPU time 361.58 seconds
Started Feb 18 02:12:43 PM PST 24
Finished Feb 18 02:19:26 PM PST 24
Peak memory 252552 kb
Host smart-e4808148-bf12-4eb8-b524-4ed0ba9b7532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805713172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2805713172
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.915130025
Short name T481
Test name
Test status
Simulation time 8712007106 ps
CPU time 64.99 seconds
Started Feb 18 02:12:42 PM PST 24
Finished Feb 18 02:14:28 PM PST 24
Peak memory 258820 kb
Host smart-39725d91-4dff-4264-8180-33e43155262a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915130025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
915130025
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4254909703
Short name T715
Test name
Test status
Simulation time 1800165755 ps
CPU time 15.77 seconds
Started Feb 18 02:12:41 PM PST 24
Finished Feb 18 02:13:38 PM PST 24
Peak memory 232448 kb
Host smart-09eaa61b-2e21-4afd-b8c3-cd3b64db474d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254909703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4254909703
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3360966509
Short name T362
Test name
Test status
Simulation time 4328566174 ps
CPU time 5.21 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:33 PM PST 24
Peak memory 217664 kb
Host smart-202dfde9-021e-4543-bc39-66a716f0c3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360966509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3360966509
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2917023926
Short name T167
Test name
Test status
Simulation time 7243406304 ps
CPU time 5.96 seconds
Started Feb 18 02:12:41 PM PST 24
Finished Feb 18 02:13:27 PM PST 24
Peak memory 218876 kb
Host smart-3e8ad8f4-e337-4b4e-a035-0868dd0091d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917023926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2917023926
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2014477121
Short name T510
Test name
Test status
Simulation time 43230668 ps
CPU time 1 seconds
Started Feb 18 02:12:42 PM PST 24
Finished Feb 18 02:13:24 PM PST 24
Peak memory 216312 kb
Host smart-02bf91f2-1a70-4931-b40a-c9f6a5ac2140
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014477121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2014477121
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3562981560
Short name T899
Test name
Test status
Simulation time 529646075 ps
CPU time 4.84 seconds
Started Feb 18 02:12:43 PM PST 24
Finished Feb 18 02:13:31 PM PST 24
Peak memory 224176 kb
Host smart-a9992b9d-e1fd-48c0-81c7-33279310b45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562981560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3562981560
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1629324556
Short name T155
Test name
Test status
Simulation time 11320118629 ps
CPU time 13.84 seconds
Started Feb 18 02:12:42 PM PST 24
Finished Feb 18 02:13:37 PM PST 24
Peak memory 218176 kb
Host smart-1d636486-a067-4413-8a55-8b94ead0c443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629324556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1629324556
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.3599135664
Short name T47
Test name
Test status
Simulation time 18665749 ps
CPU time 0.74 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:28 PM PST 24
Peak memory 215988 kb
Host smart-a3eb89c1-4021-4117-a254-8e362c30fddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599135664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.3599135664
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3968271615
Short name T382
Test name
Test status
Simulation time 1492190626 ps
CPU time 3.25 seconds
Started Feb 18 02:12:43 PM PST 24
Finished Feb 18 02:13:29 PM PST 24
Peak memory 219808 kb
Host smart-0546a141-f836-4916-97c3-22ebfba3b67b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3968271615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3968271615
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1422256763
Short name T961
Test name
Test status
Simulation time 55691019323 ps
CPU time 134.98 seconds
Started Feb 18 02:12:47 PM PST 24
Finished Feb 18 02:15:43 PM PST 24
Peak memory 256180 kb
Host smart-eed2edfa-91de-46ce-8d2c-f95ab09cb772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422256763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1422256763
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2691558344
Short name T346
Test name
Test status
Simulation time 2200271085 ps
CPU time 38.32 seconds
Started Feb 18 02:12:43 PM PST 24
Finished Feb 18 02:14:03 PM PST 24
Peak memory 216188 kb
Host smart-24eb2923-0655-4313-9b13-53a94e27660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691558344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2691558344
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1563751086
Short name T926
Test name
Test status
Simulation time 1352660310 ps
CPU time 8.87 seconds
Started Feb 18 02:12:41 PM PST 24
Finished Feb 18 02:13:31 PM PST 24
Peak memory 207768 kb
Host smart-b65922f8-a872-4a33-8225-0cb096612541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563751086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1563751086
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4233111996
Short name T840
Test name
Test status
Simulation time 158599745 ps
CPU time 1.83 seconds
Started Feb 18 02:12:39 PM PST 24
Finished Feb 18 02:13:22 PM PST 24
Peak memory 216268 kb
Host smart-110e85f4-4cd4-4cfe-b72d-20b24191d10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233111996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4233111996
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3559144321
Short name T866
Test name
Test status
Simulation time 285672926 ps
CPU time 0.97 seconds
Started Feb 18 02:12:40 PM PST 24
Finished Feb 18 02:13:29 PM PST 24
Peak memory 206120 kb
Host smart-eee9705e-b1b4-423a-b53c-ddaa078591fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559144321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3559144321
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2670753382
Short name T727
Test name
Test status
Simulation time 572988500 ps
CPU time 2.81 seconds
Started Feb 18 02:12:42 PM PST 24
Finished Feb 18 02:13:26 PM PST 24
Peak memory 223892 kb
Host smart-acef963f-117c-4742-93d3-63d4c10529da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670753382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2670753382
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.113109905
Short name T869
Test name
Test status
Simulation time 32986236 ps
CPU time 0.66 seconds
Started Feb 18 02:12:57 PM PST 24
Finished Feb 18 02:13:37 PM PST 24
Peak memory 204992 kb
Host smart-fd17536b-7443-4b96-9b35-7c8d32464e76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113109905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.113109905
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3050220113
Short name T973
Test name
Test status
Simulation time 59354199 ps
CPU time 2.33 seconds
Started Feb 18 02:12:47 PM PST 24
Finished Feb 18 02:13:30 PM PST 24
Peak memory 232616 kb
Host smart-f18c8450-8225-44d0-9605-51a9f4322ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050220113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3050220113
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.323796393
Short name T865
Test name
Test status
Simulation time 78328937 ps
CPU time 0.74 seconds
Started Feb 18 02:12:48 PM PST 24
Finished Feb 18 02:13:30 PM PST 24
Peak memory 205140 kb
Host smart-40281596-f2e2-4c0d-ad2e-10b7b5135fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323796393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.323796393
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3703116951
Short name T151
Test name
Test status
Simulation time 587631852290 ps
CPU time 163.44 seconds
Started Feb 18 02:12:48 PM PST 24
Finished Feb 18 02:16:13 PM PST 24
Peak memory 253780 kb
Host smart-9c168028-4161-4ff7-8df7-dea8556183e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703116951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3703116951
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1289869535
Short name T217
Test name
Test status
Simulation time 119054468311 ps
CPU time 168.41 seconds
Started Feb 18 02:12:53 PM PST 24
Finished Feb 18 02:16:22 PM PST 24
Peak memory 265420 kb
Host smart-e3fce5f1-c8cd-4b0a-b24c-1ad64ffb6780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289869535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1289869535
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3847735756
Short name T185
Test name
Test status
Simulation time 104132444333 ps
CPU time 691.02 seconds
Started Feb 18 02:12:59 PM PST 24
Finished Feb 18 02:25:16 PM PST 24
Peak memory 267332 kb
Host smart-a2e4a79b-3598-4bca-938d-76620d06df04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847735756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3847735756
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1977073196
Short name T908
Test name
Test status
Simulation time 4834806392 ps
CPU time 23.65 seconds
Started Feb 18 02:12:47 PM PST 24
Finished Feb 18 02:13:54 PM PST 24
Peak memory 232540 kb
Host smart-040e148b-0b17-476d-803a-3f5975aa554b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977073196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1977073196
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4103152910
Short name T717
Test name
Test status
Simulation time 2139551191 ps
CPU time 7.86 seconds
Started Feb 18 02:12:46 PM PST 24
Finished Feb 18 02:13:42 PM PST 24
Peak memory 218152 kb
Host smart-7821dab7-4430-44ac-9c4c-d0e1e327c854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103152910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4103152910
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3183102184
Short name T969
Test name
Test status
Simulation time 21551286398 ps
CPU time 54.14 seconds
Started Feb 18 02:12:53 PM PST 24
Finished Feb 18 02:14:28 PM PST 24
Peak memory 224360 kb
Host smart-7be3bb70-1e46-4aa3-8c19-43e032833464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183102184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3183102184
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3611469781
Short name T768
Test name
Test status
Simulation time 45096620 ps
CPU time 1.02 seconds
Started Feb 18 02:12:49 PM PST 24
Finished Feb 18 02:13:32 PM PST 24
Peak memory 217460 kb
Host smart-a850f558-e7c9-4ee6-9b13-8533d8d04494
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611469781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3611469781
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3708943519
Short name T504
Test name
Test status
Simulation time 20316790298 ps
CPU time 18.14 seconds
Started Feb 18 02:12:47 PM PST 24
Finished Feb 18 02:13:48 PM PST 24
Peak memory 233388 kb
Host smart-badbcc49-bfb2-43ae-93e9-ca9ffb7455e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708943519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3708943519
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.505853163
Short name T708
Test name
Test status
Simulation time 216724566 ps
CPU time 2.97 seconds
Started Feb 18 02:12:47 PM PST 24
Finished Feb 18 02:13:31 PM PST 24
Peak memory 232660 kb
Host smart-99b1f607-38fd-49cd-b599-b655a7a5086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505853163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.505853163
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.3287568991
Short name T930
Test name
Test status
Simulation time 17135339 ps
CPU time 0.75 seconds
Started Feb 18 02:12:47 PM PST 24
Finished Feb 18 02:13:29 PM PST 24
Peak memory 215984 kb
Host smart-183da64c-e4c2-46d5-a3cd-75d2fad96498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287568991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3287568991
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3000693235
Short name T834
Test name
Test status
Simulation time 344472376 ps
CPU time 3.65 seconds
Started Feb 18 02:12:49 PM PST 24
Finished Feb 18 02:13:35 PM PST 24
Peak memory 218592 kb
Host smart-e3a55b30-3637-4ab0-9a30-68af75dcd109
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3000693235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3000693235
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2053779155
Short name T230
Test name
Test status
Simulation time 73616386768 ps
CPU time 348.88 seconds
Started Feb 18 02:12:56 PM PST 24
Finished Feb 18 02:19:26 PM PST 24
Peak memory 281300 kb
Host smart-1eb3c569-a2c1-4824-ba63-9c330e6cbf1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053779155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2053779155
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3406217500
Short name T620
Test name
Test status
Simulation time 11005798742 ps
CPU time 39.58 seconds
Started Feb 18 02:12:53 PM PST 24
Finished Feb 18 02:14:14 PM PST 24
Peak memory 216424 kb
Host smart-7aa77d01-ac26-4e20-ab8e-94c44e59a88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406217500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3406217500
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2512581533
Short name T894
Test name
Test status
Simulation time 1395308222 ps
CPU time 8.61 seconds
Started Feb 18 02:12:49 PM PST 24
Finished Feb 18 02:13:38 PM PST 24
Peak memory 215988 kb
Host smart-ba97f5fd-e4a1-4f0e-bb87-2be46fada7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512581533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2512581533
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3773504322
Short name T978
Test name
Test status
Simulation time 192736832 ps
CPU time 2.37 seconds
Started Feb 18 02:12:47 PM PST 24
Finished Feb 18 02:13:30 PM PST 24
Peak memory 215940 kb
Host smart-4dca82ee-af9d-4084-987f-2726b0c4de53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773504322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3773504322
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1546588587
Short name T447
Test name
Test status
Simulation time 31950731 ps
CPU time 0.84 seconds
Started Feb 18 02:12:47 PM PST 24
Finished Feb 18 02:13:29 PM PST 24
Peak memory 205048 kb
Host smart-79df1823-e19d-4008-a258-fa2765b23be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546588587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1546588587
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3305822131
Short name T554
Test name
Test status
Simulation time 33673690492 ps
CPU time 54.42 seconds
Started Feb 18 02:12:49 PM PST 24
Finished Feb 18 02:14:25 PM PST 24
Peak memory 232400 kb
Host smart-225be939-d4bd-4db2-a7dc-7e95a1c380a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305822131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3305822131
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.233929033
Short name T716
Test name
Test status
Simulation time 35050139 ps
CPU time 0.69 seconds
Started Feb 18 02:13:05 PM PST 24
Finished Feb 18 02:13:51 PM PST 24
Peak memory 205128 kb
Host smart-b3fd7b77-a7aa-45b7-b856-a122c9f31952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233929033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.233929033
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1088721854
Short name T546
Test name
Test status
Simulation time 615526698 ps
CPU time 4.7 seconds
Started Feb 18 02:12:58 PM PST 24
Finished Feb 18 02:13:43 PM PST 24
Peak memory 218704 kb
Host smart-5cc71a1b-b79d-4b9e-a797-06f97d32fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088721854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1088721854
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4223048618
Short name T300
Test name
Test status
Simulation time 83657778 ps
CPU time 0.77 seconds
Started Feb 18 02:12:56 PM PST 24
Finished Feb 18 02:13:38 PM PST 24
Peak memory 206200 kb
Host smart-44a92a58-7bf2-4f6d-9ff7-4f4594e376b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223048618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4223048618
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1847033246
Short name T216
Test name
Test status
Simulation time 10611934257 ps
CPU time 127.21 seconds
Started Feb 18 02:13:00 PM PST 24
Finished Feb 18 02:15:53 PM PST 24
Peak memory 273304 kb
Host smart-27e659d8-4a63-4e62-8e9e-38ab390ce3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847033246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1847033246
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4145285469
Short name T943
Test name
Test status
Simulation time 9653868403 ps
CPU time 111.6 seconds
Started Feb 18 02:13:03 PM PST 24
Finished Feb 18 02:15:34 PM PST 24
Peak memory 256596 kb
Host smart-7f9148af-6db3-4011-bbe0-74a99efe56eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145285469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4145285469
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2100336634
Short name T164
Test name
Test status
Simulation time 80706813477 ps
CPU time 148.59 seconds
Started Feb 18 02:13:02 PM PST 24
Finished Feb 18 02:16:16 PM PST 24
Peak memory 249024 kb
Host smart-9a269e27-bac0-4c2c-9c5e-54e349283538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100336634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2100336634
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2539213022
Short name T356
Test name
Test status
Simulation time 5107863109 ps
CPU time 15.38 seconds
Started Feb 18 02:12:57 PM PST 24
Finished Feb 18 02:13:52 PM PST 24
Peak memory 240364 kb
Host smart-685df3c8-1241-4381-95fd-8e8b63b96bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539213022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2539213022
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1087536280
Short name T543
Test name
Test status
Simulation time 1728857162 ps
CPU time 8.6 seconds
Started Feb 18 02:12:57 PM PST 24
Finished Feb 18 02:13:47 PM PST 24
Peak memory 232792 kb
Host smart-d9e2cea1-5820-44d7-80ff-494201741de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087536280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1087536280
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.450944247
Short name T614
Test name
Test status
Simulation time 3493390364 ps
CPU time 11.51 seconds
Started Feb 18 02:12:56 PM PST 24
Finished Feb 18 02:13:56 PM PST 24
Peak memory 224300 kb
Host smart-cdfa4560-cc30-4898-967f-6afa96c5db4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450944247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.450944247
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3434444688
Short name T515
Test name
Test status
Simulation time 87228961 ps
CPU time 1 seconds
Started Feb 18 02:12:56 PM PST 24
Finished Feb 18 02:13:38 PM PST 24
Peak memory 217480 kb
Host smart-9025cd5a-1ecd-41ab-aeb9-f8cfb6b9aa9d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434444688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3434444688
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.422104425
Short name T925
Test name
Test status
Simulation time 3041737481 ps
CPU time 10.19 seconds
Started Feb 18 02:12:58 PM PST 24
Finished Feb 18 02:13:47 PM PST 24
Peak memory 234964 kb
Host smart-9f9acd6a-32ee-4778-bb71-f87f1c8fe5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422104425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
422104425
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.277070585
Short name T264
Test name
Test status
Simulation time 3180546018 ps
CPU time 10.27 seconds
Started Feb 18 02:12:58 PM PST 24
Finished Feb 18 02:13:49 PM PST 24
Peak memory 233208 kb
Host smart-73dee9c6-25fb-4952-a9cc-b756574ba103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277070585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.277070585
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2058322108
Short name T835
Test name
Test status
Simulation time 26711450 ps
CPU time 0.74 seconds
Started Feb 18 02:12:56 PM PST 24
Finished Feb 18 02:13:37 PM PST 24
Peak memory 216012 kb
Host smart-28f96bbc-3738-44e7-9de9-423efe6f06f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058322108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2058322108
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3366152336
Short name T922
Test name
Test status
Simulation time 590691771 ps
CPU time 4.47 seconds
Started Feb 18 02:13:00 PM PST 24
Finished Feb 18 02:13:49 PM PST 24
Peak memory 216196 kb
Host smart-3427624e-cb7e-4a93-b13c-f95dc88aa959
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3366152336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3366152336
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1697402589
Short name T184
Test name
Test status
Simulation time 194774680442 ps
CPU time 522.74 seconds
Started Feb 18 02:13:06 PM PST 24
Finished Feb 18 02:22:27 PM PST 24
Peak memory 270420 kb
Host smart-6680a1e0-c914-4401-a4e5-3acd264ad0a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697402589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1697402589
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2975756801
Short name T638
Test name
Test status
Simulation time 1599116313 ps
CPU time 29.07 seconds
Started Feb 18 02:12:58 PM PST 24
Finished Feb 18 02:14:07 PM PST 24
Peak memory 216036 kb
Host smart-68bcc677-ce7c-43bd-9ee4-d4920e54a33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975756801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2975756801
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.166883951
Short name T259
Test name
Test status
Simulation time 716483299 ps
CPU time 4.49 seconds
Started Feb 18 02:12:57 PM PST 24
Finished Feb 18 02:13:42 PM PST 24
Peak memory 215900 kb
Host smart-40f1d31e-893a-4d32-b19a-1ea95dbabb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166883951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.166883951
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.689070843
Short name T339
Test name
Test status
Simulation time 38984121 ps
CPU time 1.33 seconds
Started Feb 18 02:12:56 PM PST 24
Finished Feb 18 02:13:38 PM PST 24
Peak memory 207860 kb
Host smart-ebd052e4-46b4-4b79-9ec0-5f07ccd0d6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689070843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.689070843
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4039430112
Short name T485
Test name
Test status
Simulation time 24293949 ps
CPU time 0.77 seconds
Started Feb 18 02:12:58 PM PST 24
Finished Feb 18 02:13:38 PM PST 24
Peak memory 205040 kb
Host smart-54784797-4444-42de-9e27-8fb3920ee38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039430112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4039430112
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.122830890
Short name T664
Test name
Test status
Simulation time 584094612 ps
CPU time 7.56 seconds
Started Feb 18 02:12:58 PM PST 24
Finished Feb 18 02:13:45 PM PST 24
Peak memory 217732 kb
Host smart-7492a5bf-b991-41fd-a3b5-e445483d70bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122830890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.122830890
Directory /workspace/9.spi_device_upload/latest
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