Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7689471	1			T1	262		T2	1		T5	15386
all_values[1]	7689471	1			T1	262		T2	1		T5	15386
all_values[2]	7689471	1			T1	262		T2	1		T5	15386
all_values[3]	7689471	1			T1	262		T2	1		T5	15386
all_values[4]	7689471	1			T1	262		T2	1		T5	15386
all_values[5]	7689471	1			T1	262		T2	1		T5	15386

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44736937

1

T1

1572

T2

6

T5

92316

auto[1]

1399889

1

T11

46269

T16

16

T39

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46073877

1

T1

1572

T2

6

T5

91980

auto[1]

62949

1

T5

336

T8

275

T11

469

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7400376	1			T1	262		T2	1		T5	15112
all_values[0]	auto[0]	auto[1]	37044	1			T5	274		T8	163		T11	227
all_values[0]	auto[1]	auto[0]	251184	1			T11	4		T39	1		T40	2
all_values[0]	auto[1]	auto[1]	867	1			T39	1		T40	1		T41	1
all_values[1]	auto[0]	auto[0]	7364492	1			T1	262		T2	1		T5	15334
all_values[1]	auto[0]	auto[1]	17318	1			T5	52		T8	92		T11	71
all_values[1]	auto[1]	auto[0]	306794	1			T11	23017		T39	4		T40	1
all_values[1]	auto[1]	auto[1]	867	1			T11	104		T40	1		T139	6
all_values[2]	auto[0]	auto[0]	7392485	1			T1	262		T2	1		T5	15376
all_values[2]	auto[0]	auto[1]	5025	1			T5	10		T8	20		T11	47
all_values[2]	auto[1]	auto[0]	291469	1			T11	1		T16	2		T39	1
all_values[2]	auto[1]	auto[1]	492	1			T11	3		T16	2		T40	3
all_values[3]	auto[0]	auto[0]	7612555	1			T1	262		T2	1		T5	15386
all_values[3]	auto[0]	auto[1]	214	1			T11	2		T16	2		T156	1
all_values[3]	auto[1]	auto[0]	76522	1			T11	6		T16	1		T39	4
all_values[3]	auto[1]	auto[1]	180	1			T11	4		T16	1		T39	2
all_values[4]	auto[0]	auto[0]	7396699	1			T1	262		T2	1		T5	15386
all_values[4]	auto[0]	auto[1]	196	1			T40	1		T41	1		T157	1
all_values[4]	auto[1]	auto[0]	292376	1			T11	23119		T16	4		T39	4
all_values[4]	auto[1]	auto[1]	200	1			T11	5		T16	1		T39	2
all_values[5]	auto[0]	auto[0]	7510142	1			T1	262		T2	1		T5	15386
all_values[5]	auto[0]	auto[1]	391	1			T11	5		T16	1		T158	7
all_values[5]	auto[1]	auto[0]	178783	1			T11	5		T16	4		T39	1
all_values[5]	auto[1]	auto[1]	155	1			T11	1		T16	1		T40	1