---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.InterceptLevel_M	0	0	184884439	0	0	0
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.gen_assert_data_src2dst.SyncReqAckDataHoldSrc2Dst	0	0	584672384	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	584672384	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	584672384	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	584672384	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	584672384	0	0	930
tb.dut.u_tlul2sram_egress.rvalidHighReqFifoEmpty	0	0	584672384	0	0	0
tb.dut.u_tlul2sram_egress.rvalidHighWhenRspFifoFull	0	0	584672384	0	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.DataKnown_A	0	0	584672384	0	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	584672384	0	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.DataKnown_A	0	0	584672384	0	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	584672384	0	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	184883524	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	184883524	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	184883524	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	184883524	0	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.DataKnown_A	0	0	184883524	0	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	184883524	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnownO_A	0	0	584672384	584588177	0	0
tb.dut.CioSdoEnOKnown	0	0	584672384	584588177	0	0
tb.dut.CioSdoEnOffWhenInactive	0	0	584672384	584588177	0	0
tb.dut.CsPulseWidth_A	0	0	584672384	504569479	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	584672384	100	0	0
tb.dut.IntrReadbufFlipOKnown	0	0	584672384	584588177	0	0
tb.dut.IntrReadbufWatermarkOKnown	0	0	584672384	584588177	0	0
tb.dut.IntrTpmHeaderNotEmptyOKnown	0	0	584672384	584588177	0	0
tb.dut.IntrUploadCmdfifoNotEmptyOKnown	0	0	584672384	584588177	0	0
tb.dut.IntrUploadPayloadNotEmptyOKnown	0	0	584672384	584588177	0	0
tb.dut.IntrUploadPayloadOverflowOKnown	0	0	584672384	584588177	0	0
tb.dut.PayloadStartIdxWidthMatch_A	0	0	930	930	0	0
tb.dut.SpiModeKnown_A	0	0	584672384	584588177	0	0
tb.dut.TpmEnableWhenTpmCsbIdle_M	0	0	584672384	350	0	0
tb.dut.TpmRdfifoNotFull_A	0	0	584672384	266143	0	0
tb.dut.TpmWrPtrMatch_A	0	0	930	930	0	0
tb.dut.g_sram_connect[0].ReqAlwaysAccepted_A	0	0	584672384	2135952	0	0
tb.dut.g_sram_connect[1].ReqAlwaysAccepted_A	0	0	584672384	48864	0	0
tb.dut.g_sram_connect[2].ReqAlwaysAccepted_A	0	0	584672384	2275	0	0
tb.dut.g_sram_connect[3].ReqAlwaysAccepted_A	0	0	584672384	1695	0	0
tb.dut.scanmodeKnown	0	0	584672384	584672384	0	0
tb.dut.spi_device_csr_assert.TlulOOBAddrErr_A	0	0	587149954	3371	0	0
tb.dut.spi_device_csr_assert.addr_swap_data_rd_A	0	0	587149954	2020	0	0
tb.dut.spi_device_csr_assert.addr_swap_mask_rd_A	0	0	587149954	2024	0	0
tb.dut.spi_device_csr_assert.cfg_rd_A	0	0	587149954	2458	0	0
tb.dut.spi_device_csr_assert.cmd_filter_0_rd_A	0	0	587149954	8487	0	0
tb.dut.spi_device_csr_assert.cmd_filter_1_rd_A	0	0	587149954	8529	0	0
tb.dut.spi_device_csr_assert.cmd_filter_2_rd_A	0	0	587149954	7943	0	0
tb.dut.spi_device_csr_assert.cmd_filter_3_rd_A	0	0	587149954	8994	0	0
tb.dut.spi_device_csr_assert.cmd_filter_4_rd_A	0	0	587149954	8465	0	0
tb.dut.spi_device_csr_assert.cmd_filter_5_rd_A	0	0	587149954	7732	0	0
tb.dut.spi_device_csr_assert.cmd_filter_6_rd_A	0	0	587149954	7721	0	0
tb.dut.spi_device_csr_assert.cmd_filter_7_rd_A	0	0	587149954	7659	0	0
tb.dut.spi_device_csr_assert.cmd_info_0_rd_A	0	0	587149954	4167	0	0
tb.dut.spi_device_csr_assert.cmd_info_10_rd_A	0	0	587149954	4650	0	0
tb.dut.spi_device_csr_assert.cmd_info_11_rd_A	0	0	587149954	4374	0	0
tb.dut.spi_device_csr_assert.cmd_info_12_rd_A	0	0	587149954	4535	0	0
tb.dut.spi_device_csr_assert.cmd_info_13_rd_A	0	0	587149954	4858	0	0
tb.dut.spi_device_csr_assert.cmd_info_14_rd_A	0	0	587149954	4361	0	0
tb.dut.spi_device_csr_assert.cmd_info_15_rd_A	0	0	587149954	4315	0	0
tb.dut.spi_device_csr_assert.cmd_info_16_rd_A	0	0	587149954	4748	0	0
tb.dut.spi_device_csr_assert.cmd_info_17_rd_A	0	0	587149954	4320	0	0
tb.dut.spi_device_csr_assert.cmd_info_18_rd_A	0	0	587149954	4601	0	0
tb.dut.spi_device_csr_assert.cmd_info_19_rd_A	0	0	587149954	4506	0	0
tb.dut.spi_device_csr_assert.cmd_info_1_rd_A	0	0	587149954	4561	0	0
tb.dut.spi_device_csr_assert.cmd_info_20_rd_A	0	0	587149954	4646	0	0
tb.dut.spi_device_csr_assert.cmd_info_21_rd_A	0	0	587149954	4190	0	0
tb.dut.spi_device_csr_assert.cmd_info_22_rd_A	0	0	587149954	4971	0	0
tb.dut.spi_device_csr_assert.cmd_info_23_rd_A	0	0	587149954	4605	0	0
tb.dut.spi_device_csr_assert.cmd_info_2_rd_A	0	0	587149954	4457	0	0
tb.dut.spi_device_csr_assert.cmd_info_3_rd_A	0	0	587149954	4343	0	0
tb.dut.spi_device_csr_assert.cmd_info_4_rd_A	0	0	587149954	4208	0	0
tb.dut.spi_device_csr_assert.cmd_info_5_rd_A	0	0	587149954	3992	0	0
tb.dut.spi_device_csr_assert.cmd_info_6_rd_A	0	0	587149954	4399	0	0
tb.dut.spi_device_csr_assert.cmd_info_7_rd_A	0	0	587149954	4558	0	0
tb.dut.spi_device_csr_assert.cmd_info_8_rd_A	0	0	587149954	4625	0	0
tb.dut.spi_device_csr_assert.cmd_info_9_rd_A	0	0	587149954	4423	0	0
tb.dut.spi_device_csr_assert.cmd_info_en4b_rd_A	0	0	587149954	2071	0	0
tb.dut.spi_device_csr_assert.cmd_info_ex4b_rd_A	0	0	587149954	2143	0	0
tb.dut.spi_device_csr_assert.cmd_info_wrdi_rd_A	0	0	587149954	2039	0	0
tb.dut.spi_device_csr_assert.cmd_info_wren_rd_A	0	0	587149954	2145	0	0
tb.dut.spi_device_csr_assert.intercept_en_rd_A	0	0	587149954	2535	0	0
tb.dut.spi_device_csr_assert.intr_enable_rd_A	0	0	587149954	3732	0	0
tb.dut.spi_device_csr_assert.jedec_cc_rd_A	0	0	587149954	2139	0	0
tb.dut.spi_device_csr_assert.jedec_id_rd_A	0	0	587149954	2135	0	0
tb.dut.spi_device_csr_assert.mailbox_addr_rd_A	0	0	587149954	2034	0	0
tb.dut.spi_device_csr_assert.payload_swap_data_rd_A	0	0	587149954	1975	0	0
tb.dut.spi_device_csr_assert.payload_swap_mask_rd_A	0	0	587149954	2010	0	0
tb.dut.spi_device_csr_assert.read_threshold_rd_A	0	0	587149954	1924	0	0
tb.dut.spi_device_csr_assert.tpm_access_0_rd_A	0	0	587149954	2629	0	0
tb.dut.spi_device_csr_assert.tpm_access_1_rd_A	0	0	587149954	2044	0	0
tb.dut.spi_device_csr_assert.tpm_cfg_rd_A	0	0	587149954	2816	0	0
tb.dut.spi_device_csr_assert.tpm_did_vid_rd_A	0	0	587149954	2177	0	0
tb.dut.spi_device_csr_assert.tpm_int_enable_rd_A	0	0	587149954	2023	0	0
tb.dut.spi_device_csr_assert.tpm_int_status_rd_A	0	0	587149954	1898	0	0
tb.dut.spi_device_csr_assert.tpm_int_vector_rd_A	0	0	587149954	2031	0	0
tb.dut.spi_device_csr_assert.tpm_intf_capability_rd_A	0	0	587149954	1938	0	0
tb.dut.spi_device_csr_assert.tpm_rid_rd_A	0	0	587149954	1695	0	0
tb.dut.spi_device_csr_assert.tpm_sts_rd_A	0	0	587149954	1899	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	587149954	16986454	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	587149954	587020114	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	587149954	587020114	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	587149954	33406318	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	587149954	587020114	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	587149954	587020114	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
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tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1105	1105	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	587150667	6027329	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	587149954	7290	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	587150667	13655917	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	587150667	23890607	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	587149954	6003	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	587150667	16986454	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	587150667	33406318	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	587150667	16986454	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	587150667	33406318	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	587150667	33406318	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	587150667	33406318	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	587149954	5998	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	587149954	6376	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1105	1105	0	0
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown0	0	0	72931	72001	0	0
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown0	0	0	184884439	184883509	0	0
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown1	0	0	184883524	184882748	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown0	0	0	184883524	184882748	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown0	0	0	184884439	184883509	0	0
tb.dut.u_cmdparse.CmdOnlySelDpKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_cmdparse.OnlyOneDatapath_A	0	0	184883524	71130	0	0
tb.dut.u_cmdparse.SelDpKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_cmdparse.StKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	72001	71365	0	0
tb.dut.u_flash_readbuf_flip_pulse_sync.DstPulseCheck_A	0	0	584672384	490	0	0
tb.dut.u_flash_readbuf_flip_pulse_sync.SrcPulseCheck_M	0	0	184883524	490	0	0
tb.dut.u_flash_readbuf_watermark_pulse_sync.DstPulseCheck_A	0	0	584672384	303	0	0
tb.dut.u_flash_readbuf_watermark_pulse_sync.SrcPulseCheck_M	0	0	184883524	303	0	0
tb.dut.u_intr_cmdfifo_not_empty.IntrTKind_A	0	0	930	930	0	0
tb.dut.u_intr_payload_not_empty.IntrTKind_A	0	0	930	930	0	0
tb.dut.u_intr_payload_overflow.IntrTKind_A	0	0	930	930	0	0
tb.dut.u_intr_readbuf_flip.IntrTKind_A	0	0	930	930	0	0
tb.dut.u_intr_readbuf_watermark.IntrTKind_A	0	0	930	930	0	0
tb.dut.u_intr_tpm_cmdaddr_notempty.IntrTKind_A	0	0	930	930	0	0
tb.dut.u_jedec.JedecStKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_p2s.IoModeChangeValid_A	0	0	184884439	9029	0	0
tb.dut.u_p2s.IoModeDefault_A	0	0	184884439	26981	0	0
tb.dut.u_passthrough.PassThroughStKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_passthrough.PayloadSwapConstraint_M	0	0	184883524	1640264	0	0
tb.dut.u_readcmd.AddrIncNotAssertInAddressState_A	0	0	184883524	5641528	0	0
tb.dut.u_readcmd.MailboxSizeMatch_M	0	0	184883524	143843844	0	0
tb.dut.u_readcmd.ValidCmdConfig_A	0	0	184883524	256033	0	0
tb.dut.u_readcmd.u_readbuffer.StartWithAddressUpdate_A	0	0	184883524	9639	0	0
tb.dut.u_readcmd.u_readsram.AddrLatchedPulse_M	0	0	184883524	80734	0	0
tb.dut.u_readcmd.u_readsram.FifoNotEmpty_A	0	0	184883524	5641528	0	0
tb.dut.u_readcmd.u_readsram.NotOverflow_A	0	0	184883524	1422318	0	0
tb.dut.u_readcmd.u_readsram.ReqStrbRelation_M	0	0	184883524	9639	0	0
tb.dut.u_readcmd.u_readsram.SramDataReturnRequirement_M	0	0	184883524	1421732	0	0
tb.dut.u_readcmd.u_readsram.SramReadOnly_A	0	0	184883524	1422318	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.DataKnown_A	0	0	184883524	28156553	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.DepthKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.RvalidKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.WreadyKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	184883524	28156553	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A	0	0	184883524	26763152	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DepthKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.RvalidKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.WreadyKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	184883524	26763152	0	0
tb.dut.u_reg.en2addrHit	0	0	587149954	12440641	0	0
tb.dut.u_reg.reAfterRv	0	0	587149954	12440641	0	0
tb.dut.u_reg.rePulse	0	0	587149954	10243461	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1105	1105	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1105	1105	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1105	1105	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1105	1105	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1105	1105	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1105	1105	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1105	1105	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.NotOverflowed_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	587149954	16986454	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	587149954	33406318	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	587149954	3239326	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	587149954	3728011	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	587149954	55602	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	587149954	144837	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	587149954	13272017	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	587149954	29533470	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	587149954	587020114	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1105	1105	0	0
tb.dut.u_reg.u_socket.maxN	0	0	1105	1105	0	0
tb.dut.u_reg.wePulse	0	0	587149954	2197180	0	0
tb.dut.u_s2p.IoModeDefault_A	0	0	184883524	26981	0	0
tb.dut.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	930	930	0	0
tb.dut.u_scanmode_sync.OutputsKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	584672384	584588177	0	0
tb.dut.u_spi_tpm.CmdAddrAvailable_A	0	0	184883524	69167	0	0
tb.dut.u_spi_tpm.CmdAddrBitCntInAddrSt_A	0	0	184883524	743192	0	0
tb.dut.u_spi_tpm.CmdAddrInfo_A	0	0	184883524	73925	0	0
tb.dut.u_spi_tpm.CmdPowerof2_A	0	0	930	930	0	0
tb.dut.u_spi_tpm.DataFifoLessThan64_A	0	0	930	930	0	0
tb.dut.u_spi_tpm.DataSelKnown_A	0	0	184884439	39260354	0	0
tb.dut.u_spi_tpm.HwRegCondition2_a	0	0	184883524	14412	0	0
tb.dut.u_spi_tpm.HwRegCondition_A	0	0	184883524	92899	0	0
tb.dut.u_spi_tpm.HwRegIdxKnown_A	0	0	184884439	39260354	0	0
tb.dut.u_spi_tpm.LocalityLatchCondition_A	0	0	184883524	92899	0	0
tb.dut.u_spi_tpm.RdFifoDepthPoT_A	0	0	930	930	0	0
tb.dut.u_spi_tpm.RdFifoNumBytesPoT_A	0	0	930	930	0	0
tb.dut.u_spi_tpm.RdPowerof2_A	0	0	930	930	0	0
tb.dut.u_spi_tpm.SckFifoAddrLatchCondition_A	0	0	184883524	92899	0	0
tb.dut.u_spi_tpm.TpmRegCondition_A	0	0	184883524	92899	0	0
tb.dut.u_spi_tpm.TpmRegSizeMatch_A	0	0	930	930	0	0
tb.dut.u_spi_tpm.WrDepthSpec_A	0	0	930	930	0	0
tb.dut.u_spi_tpm.WrFifoAvailable_A	0	0	184883524	603531	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayRptr_A	0	0	584672384	584587050	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayWptr_A	0	0	184883524	184882729	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.ParamCheckDepth_A	0	0	930	930	0	0
tb.dut.u_spi_tpm.u_hw_reg_slice.ValidWidth_A	0	0	930	930	0	0
tb.dut.u_spi_tpm.u_rdfifo.GrayRptr_A	0	0	184884439	39167453	0	0
tb.dut.u_spi_tpm.u_rdfifo.GrayWptr_A	0	0	584672384	79829163	0	0
tb.dut.u_spi_tpm.u_rdfifo.ParamCheckDepth_A	0	0	930	930	0	0
tb.dut.u_spi_tpm.u_wrfifo.GrayRptr_A	0	0	584672384	584587050	0	0
tb.dut.u_spi_tpm.u_wrfifo.GrayWptr_A	0	0	184883524	184882729	0	0
tb.dut.u_spi_tpm.u_wrfifo.ParamCheckDepth_A	0	0	930	930	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.gen_assert_data_src2dst.SyncReqAckDataReg	0	0	930	930	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	184883524	595	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	584672384	595	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.CannotHaveEccAndParity_A	0	0	930	930	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.gen_byte_parity.ParityNeedsByteWriteMask_A	0	0	930	930	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.gen_byte_parity.WidthNeedsToBeByteAligned_A	0	0	930	930	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortA_A	0	0	584672384	2135952	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortB_A	0	0	184883524	559299	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortA_A	0	0	584672384	2135952	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortB_A	0	0	184883524	559299	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortA_A	0	0	584672384	2135952	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortB_A	0	0	184883524	559299	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortA_A	0	0	584672384	2135952	0	0
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortB_A	0	0	184883524	559299	0	0
tb.dut.u_spid_status.BusyBitZero_A	0	0	930	930	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.GrayRptr_A	0	0	184883524	184882729	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.GrayWptr_A	0	0	584672384	584587050	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.ParamCheckDepth_A	0	0	930	930	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	584672384	584588177	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	930	930	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	584672384	2188786	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	584672384	2188786	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	584672384	2188786	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	584672384	2188786	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	584672384	2188786	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	584672384	2188786	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	584672384	2188786	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.DataKnown_A	0	0	584672384	52834	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.DepthKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.RvalidKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.WreadyKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	584672384	52834	0	0
tb.dut.u_tlul2sram_egress.AddrOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.DataIntgOptions_A	0	0	930	930	0	0
tb.dut.u_tlul2sram_egress.ReqOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.SramDwHasByteGranularity_A	0	0	930	930	0	0
tb.dut.u_tlul2sram_egress.SramDwIsMultipleOfTlulWidth_A	0	0	930	930	0	0
tb.dut.u_tlul2sram_egress.TlOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.TlOutPayloadKnown_A	0	0	584672384	3670002	0	0
tb.dut.u_tlul2sram_egress.TlOutPayloadKnown_AKnownEnable	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.WdataOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.WeOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.WmaskOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.adapterNoReadOrWrite	0	0	930	930	0	0
tb.dut.u_tlul2sram_egress.u_err.dataWidthOnly32_A	0	0	930	930	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.DataKnown_A	0	0	584672384	3670002	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.DepthKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.RvalidKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.WreadyKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	584672384	3670002	0	0
tb.dut.u_tlul2sram_egress.u_rsp_gen.DataWidthCheck_A	0	0	930	930	0	0
tb.dut.u_tlul2sram_egress.u_rsp_gen.PayLoadWidthCheck	0	0	930	930	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.DepthKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.RvalidKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.WreadyKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.DepthKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.RvalidKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.WreadyKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.AddrOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.DataIntgOptions_A	0	0	930	930	0	0
tb.dut.u_tlul2sram_ingress.ReqOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.SramDwHasByteGranularity_A	0	0	930	930	0	0
tb.dut.u_tlul2sram_ingress.SramDwIsMultipleOfTlulWidth_A	0	0	930	930	0	0
tb.dut.u_tlul2sram_ingress.TlOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.TlOutPayloadKnown_A	0	0	584672384	128770	0	0
tb.dut.u_tlul2sram_ingress.TlOutPayloadKnown_AKnownEnable	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.WdataOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.WeOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.WmaskOutKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.adapterNoReadOrWrite	0	0	930	930	0	0
tb.dut.u_tlul2sram_ingress.rvalidHighReqFifoEmpty	0	0	584672384	48864	0	0
tb.dut.u_tlul2sram_ingress.rvalidHighWhenRspFifoFull	0	0	584672384	48864	0	0
tb.dut.u_tlul2sram_ingress.u_err.dataWidthOnly32_A	0	0	930	930	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.DataKnown_A	0	0	584672384	128770	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.DepthKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.RvalidKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.WreadyKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	584672384	128770	0	0
tb.dut.u_tlul2sram_ingress.u_rsp_gen.DataWidthCheck_A	0	0	930	930	0	0
tb.dut.u_tlul2sram_ingress.u_rsp_gen.PayLoadWidthCheck	0	0	930	930	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.DataKnown_A	0	0	584672384	128770	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.DepthKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.RvalidKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.WreadyKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	584672384	128770	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.DataKnown_A	0	0	584672384	48864	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.DepthKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.RvalidKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.WreadyKnown_A	0	0	584672384	584588177	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	584672384	48864	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	93783	93393	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	93783	93393	0	0
tb.dut.u_upload.AddrFifoNeverFull_M	0	0	184883524	1695	0	0
tb.dut.u_upload.CmdFifoNeverFull_M	0	0	184883524	2275	0	0
tb.dut.u_upload.CmdFifoPush_A	0	0	184883524	2275	0	0
tb.dut.u_upload.FifosOnlyOneValid_A	0	0	184883524	143843844	0	0
tb.dut.u_upload.PayloadNeverFull_M	0	0	184883524	555329	0	0
tb.dut.u_upload.u_addrfifo.MinDepth_A	0	0	930	930	0	0
tb.dut.u_upload.u_addrfifo.NoRAckInEmpty_A	0	0	584672384	1695	0	0
tb.dut.u_upload.u_addrfifo.NoWAckInFull_A	0	0	184883524	1695	0	0
tb.dut.u_upload.u_addrfifo.ParamCheckDepth_A	0	0	930	930	0	0
tb.dut.u_upload.u_addrfifo.RSramRvalidOneCycle_M	0	0	584672384	1695	0	0
tb.dut.u_upload.u_addrfifo.RptrGrayOneBitAtATime_A	0	0	584672384	1695	0	0
tb.dut.u_upload.u_addrfifo.RptrIncDataValid_A	0	0	584672384	1695	0	0
tb.dut.u_upload.u_addrfifo.RptrIncrease_A	0	0	584672384	1695	0	0
tb.dut.u_upload.u_addrfifo.SramRvalid_A	0	0	584672384	1695	0	0
tb.dut.u_upload.u_addrfifo.WSramRvalid_A	0	0	184883524	184883524	0	0
tb.dut.u_upload.u_addrfifo.WidthMatch_A	0	0	930	930	0	0
tb.dut.u_upload.u_addrfifo.WptrGrayOneBitAtATime_A	0	0	184883524	1695	0	0
tb.dut.u_upload.u_addrfifo.WptrIncrease_A	0	0	184883524	1695	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	184883524	143843844	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	930	930	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	184883524	559299	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	184883524	559299	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	184883524	559299	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	184883524	559299	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	184883524	559299	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	184883524	559299	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	184883524	559299	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.DepthKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.RvalidKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.WreadyKnown_A	0	0	184883524	143843844	0	0
tb.dut.u_upload.u_cmdfifo.MinDepth_A	0	0	930	930	0	0
tb.dut.u_upload.u_cmdfifo.NoRAckInEmpty_A	0	0	584672384	2275	0	0
tb.dut.u_upload.u_cmdfifo.NoWAckInFull_A	0	0	184883524	2275	0	0
tb.dut.u_upload.u_cmdfifo.ParamCheckDepth_A	0	0	930	930	0	0
tb.dut.u_upload.u_cmdfifo.RSramRvalidOneCycle_M	0	0	584672384	2275	0	0
tb.dut.u_upload.u_cmdfifo.RptrGrayOneBitAtATime_A	0	0	584672384	2275	0	0
tb.dut.u_upload.u_cmdfifo.RptrIncDataValid_A	0	0	584672384	2275	0	0
tb.dut.u_upload.u_cmdfifo.RptrIncrease_A	0	0	584672384	2275	0	0
tb.dut.u_upload.u_cmdfifo.SramRvalid_A	0	0	584672384	2275	0	0
tb.dut.u_upload.u_cmdfifo.WSramRvalid_A	0	0	184883524	184883524	0	0
tb.dut.u_upload.u_cmdfifo.WidthMatch_A	0	0	930	930	0	0
tb.dut.u_upload.u_cmdfifo.WptrGrayOneBitAtATime_A	0	0	184883524	2275	0	0
tb.dut.u_upload.u_cmdfifo.WptrIncrease_A	0	0	184883524	2275	0	0
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	0	0	930	930	0	0
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A	0	0	930	930	0	0
tb.dut.u_upload.u_payloadptr_clr_psync.DstPulseCheck_A	0	0	584672384	2275	0	0
tb.dut.u_upload.u_payloadptr_clr_psync.SrcPulseCheck_M	0	0	184883524	2275	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	584672384	0	0	930

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	587150667	91326	91326	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	587150667	1534	1534	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	587150667	1593	1593	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	587150667	1004	1004	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	587150667	177	177	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	587150667	791	791	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	587150667	925	925	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	587150667	15336	15336	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	587150667	1242930	1242930	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	587150667	6956220	6956220	1085

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	587150667	91326	91326	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	587150667	1534	1534	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	587150667	1593	1593	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	587150667	1004	1004	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	587150667	177	177	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	587150667	791	791	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	587150667	925	925	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	587150667	15336	15336	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	587150667	1242930	1242930	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	587150667	6956220	6956220	1085