Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	39354	1			T5	161		T7	8		T8	335
auto[SpiFlashAddrCfg]	8757	1			T5	29		T6	2		T7	4
auto[SpiFlashAddr3b]	10696	1			T1	9		T5	43		T7	8
auto[SpiFlashAddr4b]	9148	1			T5	31		T6	2		T7	8

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39530

1

T1

9

T5

156

T6

4

auto[1]

28425

1

T5

108

T8

333

T9

2

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35663

1

T1

9

T5

158

T7

4

auto[1]

32292

1

T5

106

T6

4

T7

24

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	44647	1			T5	181		T6	2		T7	12
values[1]	1245	1			T5	5		T8	4		T11	4
values[2]	1669	1			T5	6		T7	8		T8	3
values[3]	1627	1			T1	5		T5	6		T8	5
values[4]	1732	1			T5	9		T7	2		T8	7
values[5]	1698	1			T5	5		T8	6		T11	4
values[6]	1807	1			T5	5		T8	14		T11	4
values[7]	1768	1			T5	4		T8	1		T11	16
values[8]	11762	1			T1	4		T5	43		T6	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38067

1

T5

264

T6

4

T7

28

auto[1]

29888

1

T1

9

T14

116

T16

180

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

65466

1

T1

9

T5

254

T6

2

write

2489

1

T5

10

T6

2

T8

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

23261

1

T1

5

T5

100

T6

2

valids[0x1]

44694

1

T1

4

T5

164

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1807	1			T5	11		T7	4		T8	6
internal_process_ops[0x5a]	1835	1			T5	10		T8	9		T11	7
internal_process_ops[0x05]	23340	1			T5	76		T7	2		T8	272
internal_process_ops[0x35]	1797	1			T5	13		T7	2		T8	5
internal_process_ops[0x15]	1815	1			T5	10		T8	10		T11	3
internal_process_ops[0x03]	1399	1			T1	4		T5	8		T8	5
internal_process_ops[0x0b]	1259	1			T5	4		T7	2		T8	9
internal_process_ops[0x3b]	1440	1			T5	6		T6	2		T8	5
internal_process_ops[0x6b]	1338	1			T5	4		T7	4		T8	8
internal_process_ops[0xbb]	1293	1			T5	11		T6	2		T8	11
internal_process_ops[0xeb]	1374	1			T1	5		T5	5		T8	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66809

1

T1

9

T5

257

T6

4

auto[1]

1146

1

T5

7

T8

6

T11

11

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65680

1

T1

9

T5

254

T6

4

auto[1]

2275

1

T5

10

T8

15

T11

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13110

1

T5

93

T7

8

T8

60

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7173

1

T5

67

T8

272

T11

58

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2673

1

T5

14

T7

4

T8

19

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2342

1

T5

11

T8

17

T9

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3267

1

T5

21

T7

8

T8

25

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2808

1

T5

20

T8

25

T11

21

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2834

1

T5

22

T6

2

T7

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2544

1

T5

6

T8

12

T11

18

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

101

1

T11

3

T16

2

T27

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

78

1

T5

1

T8

1

T11

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

71

1

T8

1

T11

2

T27

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

91

1

T8

1

T11

6

T26

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

119

1

T6

2

T12

2

T16

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

73

1

T11

1

T16

2

T27

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

74

1

T5

2

T8

3

T11

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

97

1

T5

2

T8

1

T16

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

106

1

T148

2

T29

4

T149

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

75

1

T5

2

T8

1

T11

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

66

1

T8

1

T16

3

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

55

1

T27

2

T28

3

T29

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

119

1

T5

1

T8

1

T11

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

61

1

T5

2

T8

2

T16

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

62

1

T26

1

T30

1

T150

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

68

1

T11

1

T16

1

T27

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10849

1

T14

27

T16

54

T24

253

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7572

1

T14

30

T16

44

T24

292

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1651

1

T14

6

T16

8

T24

19

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1446

1

T14

9

T16

5

T24

30

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2120

1

T1

9

T14

10

T16

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1910

1

T14

7

T16

23

T24

35

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1709

1

T14

10

T16

19

T24

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1458

1

T14

7

T16

10

T24

22

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

84

1

T14

2

T24

2

T70

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

76

1

T24

6

T151

6

T152

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

76

1

T16

4

T24

1

T17

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

73

1

T14

2

T24

1

T25

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

86

1

T14

2

T24

4

T25

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

58

1

T24

1

T25

5

T33

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

77

1

T16

1

T24

1

T25

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

61

1

T151

1

T153

1

T119

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T33

1

T152

2

T54

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

65

1

T14

3

T25

1

T33

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

65

1

T16

1

T33

1

T154

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

71

1

T16

1

T24

3

T17

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

56

1

T24

2

T152

5

T155

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

72

1

T25

3

T33

3

T151

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

93

1

T24

4

T151

1

T155

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

72

1

T14

1

T25

3

T33

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	5339	1			T5	48		T8	38		T11	37
auto[0]	values[0]	valids[0x1]	18403	1			T5	133		T6	2		T7	12
auto[0]	values[1]	valids[0x1]	700	1			T5	5		T8	4		T11	4
auto[0]	values[2]	valids[0x0]	678	1			T5	5		T7	4		T8	2
auto[0]	values[2]	valids[0x1]	346	1			T5	1		T7	4		T8	1
auto[0]	values[3]	valids[0x0]	626	1			T5	5		T8	2		T11	3
auto[0]	values[3]	valids[0x1]	380	1			T5	1		T8	3		T11	2
auto[0]	values[4]	valids[0x0]	692	1			T5	5		T7	2		T8	7
auto[0]	values[4]	valids[0x1]	357	1			T5	4		T11	1		T83	4
auto[0]	values[5]	valids[0x0]	720	1			T5	3		T8	4		T11	2
auto[0]	values[5]	valids[0x1]	338	1			T5	2		T8	2		T11	2
auto[0]	values[6]	valids[0x0]	747	1			T5	5		T8	7		T11	2
auto[0]	values[6]	valids[0x1]	396	1			T8	7		T11	2		T83	4
auto[0]	values[7]	valids[0x0]	702	1			T5	3		T11	13		T12	2
auto[0]	values[7]	valids[0x1]	364	1			T5	1		T8	1		T11	3
auto[0]	values[8]	valids[0x0]	4553	1			T5	26		T6	2		T8	45
auto[0]	values[8]	valids[0x1]	2726	1			T5	17		T7	6		T8	17
auto[1]	values[0]	valids[0x0]	4181	1			T14	17		T16	36		T24	66
auto[1]	values[0]	valids[0x1]	16724	1			T14	50		T16	86		T24	539
auto[1]	values[1]	valids[0x1]	545	1			T14	2		T16	4		T24	6
auto[1]	values[2]	valids[0x0]	408	1			T14	2		T16	1		T17	1
auto[1]	values[2]	valids[0x1]	237	1			T16	5		T25	5		T33	5
auto[1]	values[3]	valids[0x0]	362	1			T1	5		T14	2		T24	4
auto[1]	values[3]	valids[0x1]	259	1			T14	2		T16	5		T24	3
auto[1]	values[4]	valids[0x0]	429	1			T14	2		T16	4		T24	5
auto[1]	values[4]	valids[0x1]	254	1			T16	4		T24	4		T25	3
auto[1]	values[5]	valids[0x0]	387	1			T14	1		T16	7		T24	12
auto[1]	values[5]	valids[0x1]	253	1			T16	2		T24	1		T25	8
auto[1]	values[6]	valids[0x0]	395	1			T14	1		T16	7		T24	2
auto[1]	values[6]	valids[0x1]	269	1			T14	2		T16	1		T24	4
auto[1]	values[7]	valids[0x0]	423	1			T14	3		T16	3		T24	4
auto[1]	values[7]	valids[0x1]	279	1			T16	1		T24	5		T25	7
auto[1]	values[8]	valids[0x0]	2619	1			T14	19		T16	13		T24	37
auto[1]	values[8]	valids[0x1]	1864	1			T1	4		T14	13		T16	1