Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18530

1

T1

15

T5

80

T6

2

auto[1]

23510

1

T5

74

T8

278

T11

54

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15476

1

T1

15

T5

55

T6

2

auto[1]

26564

1

T5

99

T7

4

T8

287

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7600	1			T1	9		T5	13		T7	5
auto[524288:1048575]	3786	1			T1	3		T5	38		T8	8
auto[1048576:1572863]	4658	1			T1	1		T5	2		T8	8
auto[1572864:2097151]	4895	1			T5	11		T8	2		T11	22
auto[2097152:2621439]	5589	1			T5	43		T6	2		T8	145
auto[2621440:3145727]	5046	1			T5	14		T8	4		T11	9
auto[3145728:3670015]	5548	1			T1	2		T5	19		T8	69
auto[3670016:4194303]	4918	1			T5	14		T8	30		T11	25

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41080

1

T1

15

T5

152

T6

2

auto[1]

960

1

T5

2

T8

10

T11

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34077

1

T1

15

T5

96

T6

2

auto[1]

7963

1

T5

58

T8

9

T11

7

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1891	1			T1	9		T5	7		T7	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	716	1			T5	3		T7	4		T8	3
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1233	1			T1	3		T5	6		T8	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	434	1			T5	1		T8	2		T45	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1301	1			T1	1		T8	4		T11	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	504	1			T5	2		T8	2		T11	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1242	1			T5	4		T8	2		T11	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	502	1			T5	3		T11	2		T45	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1315	1			T5	4		T6	2		T8	10
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	537	1			T5	4		T8	4		T11	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1336	1			T5	3		T8	1		T11	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	558	1			T5	4		T8	1		T45	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1226	1			T1	2		T5	2		T8	12
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	466	1			T5	5		T8	2		T11	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1290	1			T5	6		T8	11		T11	10
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	498	1			T5	5		T8	8		T45	5
auto[0]	auto[1]	auto[0:524287]	auto[0]	324	1			T8	4		T16	4		T24	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	164	1			T16	2		T24	2		T33	3
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	250	1			T5	1		T13	3		T16	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	114	1			T5	1		T25	1		T185	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	265	1			T8	1		T17	1		T25	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	132	1			T8	1		T24	1		T25	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	299	1			T5	2		T11	1		T16	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	140	1			T16	1		T151	1		T27	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	293	1			T5	5		T25	7		T33	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	134	1			T5	2		T8	1		T14	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	283	1			T8	2		T11	1		T13	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	128	1			T5	1		T25	1		T28	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	382	1			T5	3		T24	3		T132	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	162	1			T5	3		T33	3		T152	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	270	1			T5	2		T11	2		T13	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	141	1			T5	1		T11	3		T24	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	323	1			T5	1		T8	3		T16	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3475	1			T5	2		T8	79		T16	47
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	186	1			T5	2		T11	1		T16	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1258	1			T5	22		T11	1		T16	15
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	207	1			T11	1		T14	4		T16	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1807	1			T11	1		T14	10		T16	115
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	247	1			T5	1		T11	3		T16	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1980	1			T5	1		T11	7		T16	64
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	225	1			T5	1		T8	5		T11	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2480	1			T5	1		T8	125		T11	23
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	228	1			T5	1		T11	1		T16	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1890	1			T5	5		T11	2		T16	21
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	234	1			T8	5		T11	1		T14	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2391	1			T8	50		T11	2		T14	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	209	1			T8	2		T11	2		T14	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1888	1			T8	9		T11	8		T14	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	60	1			T16	1		T24	3		T33	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	647	1			T16	15		T24	60		T33	7
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	41	1			T5	1		T25	1		T27	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	270	1			T5	4		T25	1		T27	11
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	36	1			T33	2		T151	2		T31	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	406	1			T33	43		T151	35		T31	11
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	53	1			T30	1		T181	1		T41	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	432	1			T30	4		T181	18		T41	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	50	1			T5	2		T28	1		T29	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	555	1			T5	24		T28	14		T29	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	48	1			T25	1		T151	2		T27	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	575	1			T25	4		T151	22		T27	13
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	78	1			T5	1		T24	1		T33	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	609	1			T5	5		T24	27		T33	34
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	51	1			T24	1		T33	1		T151	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	571	1			T24	3		T33	1		T151	28

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	14641	1			T1	15		T5	59		T6	2
auto[0]	auto[0]	auto[1]	408	1			T8	9		T16	9		T24	11
auto[0]	auto[1]	auto[0]	3394	1			T5	20		T8	9		T11	7
auto[0]	auto[1]	auto[1]	87	1			T5	1		T24	2		T33	3
auto[1]	auto[0]	auto[0]	18650	1			T5	36		T8	277		T11	52
auto[1]	auto[0]	auto[1]	378	1			T5	1		T8	1		T11	2
auto[1]	auto[1]	auto[0]	4395	1			T5	37		T16	16		T24	95
auto[1]	auto[1]	auto[1]	87	1			T33	4		T151	5		T152	1