Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22616

1

T5

156

T6

4

T7

28

auto[1]

15451

1

T5

108

T8

333

T9

2

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4336	1			T5	116		T8	20		T11	23
values[1]	4229	1			T11	25		T45	18		T16	92
values[2]	4938	1			T5	66		T7	28		T8	45
values[3]	5732	1			T5	42		T8	59		T9	2
values[4]	4267	1			T5	20		T6	4		T11	44
values[5]	5134	1			T5	20		T8	153		T11	106
values[6]	4521	1			T10	14		T16	34		T186	6
values[7]	4910	1			T8	186		T16	26		T131	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4637	1			T5	47		T11	43		T83	32
values[1]	4736	1			T5	20		T8	201		T9	2
values[2]	5345	1			T8	20		T10	14		T11	69
values[3]	4808	1			T6	4		T8	20		T13	34
values[4]	4991	1			T5	91		T7	28		T8	40
values[5]	3778	1			T5	62		T8	98		T34	4
values[6]	4920	1			T5	44		T8	39		T11	27
values[7]	4852	1			T8	45		T11	43		T16	105

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	265	1			T5	12		T31	16		T210	28
auto[0]	values[0]	values[1]	471	1			T12	12		T148	56		T28	7
auto[0]	values[0]	values[2]	302	1			T72	24		T30	10		T31	11
auto[0]	values[0]	values[3]	298	1			T13	34		T117	8		T211	6
auto[0]	values[0]	values[4]	340	1			T5	49		T8	15		T11	10
auto[0]	values[0]	values[5]	221	1			T132	2		T29	9		T212	2
auto[0]	values[0]	values[6]	286	1			T26	17		T28	13		T29	9
auto[0]	values[0]	values[7]	272	1			T31	16		T150	10		T213	30
auto[0]	values[1]	values[0]	295	1			T16	10		T85	24		T27	19
auto[0]	values[1]	values[1]	337	1			T45	18		T27	10		T214	16
auto[0]	values[1]	values[2]	285	1			T11	13		T27	10		T56	32
auto[0]	values[1]	values[3]	441	1			T27	36		T31	12		T176	23
auto[0]	values[1]	values[4]	618	1			T16	21		T31	15		T196	9
auto[0]	values[1]	values[5]	240	1			T27	12		T117	9		T205	13
auto[0]	values[1]	values[6]	237	1			T30	11		T122	11		T215	14
auto[0]	values[1]	values[7]	269	1			T216	2		T196	10		T217	22
auto[0]	values[2]	values[0]	532	1			T209	8		T150	10		T189	10
auto[0]	values[2]	values[1]	308	1			T27	11		T190	18		T218	18
auto[0]	values[2]	values[2]	592	1			T29	8		T176	13		T219	4
auto[0]	values[2]	values[3]	275	1			T165	24		T28	14		T30	15
auto[0]	values[2]	values[4]	215	1			T7	28		T121	8		T141	9
auto[0]	values[2]	values[5]	195	1			T5	12		T190	30		T220	2
auto[0]	values[2]	values[6]	532	1			T5	34		T16	8		T26	9
auto[0]	values[2]	values[7]	388	1			T8	35		T27	8		T150	12
auto[0]	values[3]	values[0]	320	1			T182	26		T31	5		T181	7
auto[0]	values[3]	values[1]	349	1			T26	10		T221	4		T28	10
auto[0]	values[3]	values[2]	533	1			T16	96		T26	10		T27	10
auto[0]	values[3]	values[3]	272	1			T8	11		T130	4		T27	14
auto[0]	values[3]	values[4]	390	1			T5	15		T30	19		T181	12
auto[0]	values[3]	values[5]	319	1			T5	13		T31	29		T222	4
auto[0]	values[3]	values[6]	467	1			T8	13		T11	14		T27	44
auto[0]	values[3]	values[7]	600	1			T16	13		T30	12		T190	98
auto[0]	values[4]	values[0]	244	1			T83	32		T16	13		T103	16
auto[0]	values[4]	values[1]	254	1			T223	16		T117	13		T224	10
auto[0]	values[4]	values[2]	408	1			T11	15		T27	12		T225	2
auto[0]	values[4]	values[3]	264	1			T6	4		T27	8		T121	13
auto[0]	values[4]	values[4]	427	1			T16	95		T28	8		T30	14
auto[0]	values[4]	values[5]	297	1			T5	9		T34	4		T16	8
auto[0]	values[4]	values[6]	318	1			T29	13		T226	8		T117	20
auto[0]	values[4]	values[7]	321	1			T29	13		T121	37		T177	7
auto[0]	values[5]	values[0]	500	1			T11	29		T122	10		T227	18
auto[0]	values[5]	values[1]	476	1			T5	12		T8	10		T11	8
auto[0]	values[5]	values[2]	455	1			T117	8		T207	4		T228	55
auto[0]	values[5]	values[3]	474	1			T30	11		T205	11		T229	6
auto[0]	values[5]	values[4]	420	1			T8	6		T29	8		T31	14
auto[0]	values[5]	values[5]	227	1			T8	12		T16	12		T27	20
auto[0]	values[5]	values[6]	218	1			T26	13		T180	28		T149	24
auto[0]	values[5]	values[7]	278	1			T11	17		T165	18		T29	10
auto[0]	values[6]	values[0]	370	1			T27	11		T30	28		T230	28
auto[0]	values[6]	values[1]	269	1			T186	6		T29	12		T30	20
auto[0]	values[6]	values[2]	386	1			T10	14		T30	27		T31	20
auto[0]	values[6]	values[3]	380	1			T29	13		T181	11		T117	9
auto[0]	values[6]	values[4]	313	1			T16	23		T166	41		T28	10
auto[0]	values[6]	values[5]	305	1			T165	13		T28	17		T181	30
auto[0]	values[6]	values[6]	399	1			T27	13		T31	9		T121	13
auto[0]	values[6]	values[7]	355	1			T28	14		T194	30		T150	12
auto[0]	values[7]	values[0]	302	1			T28	13		T29	13		T31	28
auto[0]	values[7]	values[1]	221	1			T8	16		T16	17		T165	12
auto[0]	values[7]	values[2]	303	1			T8	12		T28	14		T30	9
auto[0]	values[7]	values[3]	550	1			T28	17		T150	13		T181	10
auto[0]	values[7]	values[4]	312	1			T29	15		T181	15		T175	6
auto[0]	values[7]	values[5]	208	1			T150	11		T231	6		T196	13
auto[0]	values[7]	values[6]	513	1			T28	14		T150	12		T184	16
auto[0]	values[7]	values[7]	385	1			T131	8		T28	13		T150	12
auto[1]	values[0]	values[0]	390	1			T5	35		T31	30		T172	22
auto[1]	values[0]	values[1]	244	1			T28	14		T30	23		T190	18
auto[1]	values[0]	values[2]	256	1			T30	10		T31	9		T177	69
auto[1]	values[0]	values[3]	90	1			T117	12		T176	10		T177	8
auto[1]	values[0]	values[4]	272	1			T5	20		T8	5		T11	13
auto[1]	values[0]	values[5]	205	1			T29	11		T210	9		T121	9
auto[1]	values[0]	values[6]	308	1			T26	7		T28	7		T29	11
auto[1]	values[0]	values[7]	116	1			T31	4		T150	20		T232	6
auto[1]	values[1]	values[0]	245	1			T16	10		T27	14		T28	10
auto[1]	values[1]	values[1]	166	1			T27	38		T150	13		T141	15
auto[1]	values[1]	values[2]	177	1			T11	12		T27	10		T181	11
auto[1]	values[1]	values[3]	231	1			T27	19		T31	8		T233	22
auto[1]	values[1]	values[4]	171	1			T16	51		T31	21		T196	11
auto[1]	values[1]	values[5]	134	1			T27	8		T117	16		T205	7
auto[1]	values[1]	values[6]	172	1			T30	9		T122	12		T168	2
auto[1]	values[1]	values[7]	211	1			T196	11		T234	9		T192	25
auto[1]	values[2]	values[0]	142	1			T150	10		T121	5		T227	7
auto[1]	values[2]	values[1]	268	1			T27	9		T190	66		T141	10
auto[1]	values[2]	values[2]	264	1			T29	12		T176	12		T227	6
auto[1]	values[2]	values[3]	234	1			T165	5		T28	8		T30	5
auto[1]	values[2]	values[4]	238	1			T121	12		T141	26		T168	6
auto[1]	values[2]	values[5]	121	1			T5	10		T190	5		T141	21
auto[1]	values[2]	values[6]	345	1			T5	10		T16	12		T26	11
auto[1]	values[2]	values[7]	289	1			T8	10		T27	28		T150	8
auto[1]	values[3]	values[0]	209	1			T31	20		T181	13		T168	3
auto[1]	values[3]	values[1]	342	1			T9	2		T26	14		T28	10
auto[1]	values[3]	values[2]	406	1			T16	11		T26	10		T27	10
auto[1]	values[3]	values[3]	258	1			T8	9		T27	9		T31	3
auto[1]	values[3]	values[4]	359	1			T5	7		T30	25		T181	8
auto[1]	values[3]	values[5]	317	1			T5	7		T31	15		T121	28
auto[1]	values[3]	values[6]	249	1			T8	26		T11	13		T27	9
auto[1]	values[3]	values[7]	342	1			T16	92		T174	20		T30	8
auto[1]	values[4]	values[0]	111	1			T16	7		T27	21		T168	18
auto[1]	values[4]	values[1]	156	1			T117	7		T234	6		T192	14
auto[1]	values[4]	values[2]	300	1			T11	29		T27	8		T150	10
auto[1]	values[4]	values[3]	177	1			T27	23		T171	30		T121	7
auto[1]	values[4]	values[4]	238	1			T16	23		T28	12		T30	6
auto[1]	values[4]	values[5]	382	1			T5	11		T16	123		T28	12
auto[1]	values[4]	values[6]	189	1			T29	11		T117	9		T141	18
auto[1]	values[4]	values[7]	181	1			T29	11		T187	20		T121	13
auto[1]	values[5]	values[0]	214	1			T11	14		T122	10		T227	3
auto[1]	values[5]	values[1]	323	1			T5	8		T8	25		T11	12
auto[1]	values[5]	values[2]	271	1			T235	18		T117	12		T192	11
auto[1]	values[5]	values[3]	283	1			T30	13		T205	15		T122	10
auto[1]	values[5]	values[4]	231	1			T8	14		T29	12		T31	6
auto[1]	values[5]	values[5]	279	1			T8	86		T16	8		T27	4
auto[1]	values[5]	values[6]	186	1			T26	10		T205	11		T122	10
auto[1]	values[5]	values[7]	299	1			T11	26		T165	6		T29	10
auto[1]	values[6]	values[0]	216	1			T27	9		T30	16		T181	6
auto[1]	values[6]	values[1]	174	1			T29	8		T30	6		T122	10
auto[1]	values[6]	values[2]	240	1			T30	16		T31	46		T175	32
auto[1]	values[6]	values[3]	306	1			T29	7		T181	71		T117	27
auto[1]	values[6]	values[4]	149	1			T16	11		T28	17		T31	12
auto[1]	values[6]	values[5]	135	1			T165	7		T28	5		T181	6
auto[1]	values[6]	values[6]	224	1			T27	7		T31	11		T121	7
auto[1]	values[6]	values[7]	300	1			T28	6		T150	11		T177	14
auto[1]	values[7]	values[0]	282	1			T28	59		T29	11		T31	15
auto[1]	values[7]	values[1]	378	1			T8	150		T16	9		T165	8
auto[1]	values[7]	values[2]	167	1			T8	8		T28	8		T30	11
auto[1]	values[7]	values[3]	275	1			T28	4		T150	7		T181	10
auto[1]	values[7]	values[4]	298	1			T29	5		T181	5		T175	17
auto[1]	values[7]	values[5]	193	1			T150	9		T196	10		T227	10
auto[1]	values[7]	values[6]	277	1			T28	8		T150	36		T175	9
auto[1]	values[7]	values[7]	246	1			T28	8		T150	8		T190	5