Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	557	1			T5	3		T8	2		T11	3
auto[ReadAddrCrossIntoMailbox]	445	1			T5	2		T8	3		T11	2
auto[ReadAddrCrossOutOfMailbox]	406	1			T5	3		T8	4		T11	1
auto[ReadAddrCrossAllMailbox]	291	1			T8	3		T11	2		T16	6
auto[ReadAddrOutsideMailbox]	4440	1			T5	30		T6	2		T7	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3044

1

T5

20

T6

1

T7

3

auto[1]

3095

1

T5

18

T6

1

T7

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	1103	1			T5	8		T8	5		T11	4
read_ops[0x0b]	906	1			T5	4		T7	2		T8	9
read_ops[0x3b]	1123	1			T5	6		T6	2		T8	5
read_ops[0x6b]	1035	1			T5	4		T7	4		T8	8
read_ops[0xbb]	962	1			T5	11		T8	11		T11	6
read_ops[0xeb]	1010	1			T5	5		T8	10		T11	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T5	1		T83	2		T186	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	56	1			T83	2		T186	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	39	1			T8	1		T27	2		T28	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T27	1		T30	2		T31	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T29	1		T31	1		T117	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T8	1		T11	1		T28	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T27	1		T28	1		T175	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	30	1			T16	1		T150	1		T190	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	419	1			T5	4		T8	1		T11	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	384	1			T5	3		T8	2		T11	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T28	1		T30	1		T214	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T16	1		T165	2		T214	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T27	1		T209	1		T30	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T209	1		T30	1		T181	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T28	1		T29	2		T30	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T5	1		T16	1		T31	3
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T27	1		T29	1		T195	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T29	1		T195	1		T141	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	370	1			T7	1		T8	5		T9	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T5	3		T7	1		T8	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	48	1			T83	1		T27	1		T30	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T11	1		T83	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	46	1			T11	1		T131	1		T27	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	42	1			T8	1		T16	1		T131	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	55	1			T16	1		T27	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T27	1		T30	3		T31	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	36	1			T11	1		T16	1		T26	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T8	1		T16	1		T165	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	383	1			T5	1		T6	1		T10	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	412	1			T5	5		T6	1		T8	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T11	1		T16	1		T131	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T8	1		T16	1		T131	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T5	1		T11	1		T28	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	48	1			T8	1		T16	1		T30	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T8	1		T26	1		T27	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T31	2		T196	1		T176	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T8	1		T31	1		T150	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	32	1			T27	1		T30	1		T31	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	370	1			T5	3		T7	2		T11	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	368	1			T7	2		T8	4		T11	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T5	1		T16	1		T165	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T5	1		T8	1		T26	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T5	1		T16	1		T26	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T16	2		T165	1		T195	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T5	2		T26	1		T27	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T8	1		T27	1		T28	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T11	1		T27	1		T195	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T8	1		T16	2		T30	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T5	2		T8	2		T11	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	375	1			T5	4		T8	6		T11	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	55	1			T11	1		T83	3		T27	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	58	1			T83	3		T26	2		T165	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T31	1		T117	1		T176	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	39	1			T26	1		T27	1		T28	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T8	1		T30	1		T181	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T165	2		T30	3		T196	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T16	1		T30	1		T177	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T28	1		T30	1		T150	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	342	1			T5	4		T8	4		T11	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	387	1			T5	1		T8	5		T11	1