Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7689471	1			T1	262		T2	1		T5	15386
all_pins[1]	7689471	1			T1	262		T2	1		T5	15386
all_pins[2]	7689471	1			T1	262		T2	1		T5	15386
all_pins[3]	7689471	1			T1	262		T2	1		T5	15386
all_pins[4]	7689471	1			T1	262		T2	1		T5	15386
all_pins[5]	7689471	1			T1	262		T2	1		T5	15386

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	46128424	1			T1	1572		T2	6		T5	92316
values[0x1]	8402	1			T11	122		T16	5		T39	5
transitions[0x0=>0x1]	7573	1			T11	118		T16	5		T39	5
transitions[0x1=>0x0]	7586	1			T11	118		T16	5		T39	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7688570	1			T1	262		T2	1		T5	15386
all_pins[0]	values[0x1]	901	1			T39	1		T40	1		T41	1
all_pins[0]	transitions[0x0=>0x1]	508	1			T39	1		T40	1		T41	1
all_pins[0]	transitions[0x1=>0x0]	515	1			T11	109		T40	1		T139	6
all_pins[1]	values[0x0]	7688563	1			T1	262		T2	1		T5	15386
all_pins[1]	values[0x1]	908	1			T11	109		T40	1		T139	6
all_pins[1]	transitions[0x0=>0x1]	680	1			T11	106		T40	1		T139	4
all_pins[1]	transitions[0x1=>0x0]	274	1			T16	2		T40	3		T41	1
all_pins[2]	values[0x0]	7688969	1			T1	262		T2	1		T5	15386
all_pins[2]	values[0x1]	502	1			T11	3		T16	2		T40	3
all_pins[2]	transitions[0x0=>0x1]	462	1			T11	2		T16	2		T40	2
all_pins[2]	transitions[0x1=>0x0]	140	1			T11	3		T16	1		T39	2
all_pins[3]	values[0x0]	7689291	1			T1	262		T2	1		T5	15386
all_pins[3]	values[0x1]	180	1			T11	4		T16	1		T39	2
all_pins[3]	transitions[0x0=>0x1]	130	1			T11	4		T16	1		T39	2
all_pins[3]	transitions[0x1=>0x0]	150	1			T11	5		T16	1		T39	2
all_pins[4]	values[0x0]	7689271	1			T1	262		T2	1		T5	15386
all_pins[4]	values[0x1]	200	1			T11	5		T16	1		T39	2
all_pins[4]	transitions[0x0=>0x1]	168	1			T11	5		T16	1		T39	2
all_pins[4]	transitions[0x1=>0x0]	5679	1			T11	1		T16	1		T40	1
all_pins[5]	values[0x0]	7683760	1			T1	262		T2	1		T5	15386
all_pins[5]	values[0x1]	5711	1			T11	1		T16	1		T40	1
all_pins[5]	transitions[0x0=>0x1]	5625	1			T11	1		T16	1		T40	1
all_pins[5]	transitions[0x1=>0x0]	828	1			T39	1		T40	1		T120	5