Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4645	1			T5	24		T8	118		T9	2
values[1]	4049	1			T7	28		T8	59		T10	14
values[2]	5890	1			T8	35		T11	45		T34	4
values[3]	4426	1			T5	114		T11	23		T16	125
values[4]	4408	1			T5	20		T8	45		T83	32
values[5]	5006	1			T5	86		T8	20		T11	49
values[6]	4512	1			T12	12		T16	20		T131	8
values[7]	5131	1			T5	20		T6	4		T8	186

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4946	1			T16	20		T165	24		T182	26
values[1]	4223	1			T5	22		T11	68		T34	4
values[2]	4917	1			T5	67		T8	20		T10	14
values[3]	5003	1			T5	69		T6	4		T8	183
values[4]	4660	1			T5	22		T11	21		T16	20
values[5]	4683	1			T5	44		T8	181		T11	89
values[6]	4585	1			T8	20		T11	27		T16	182
values[7]	5050	1			T5	40		T7	28		T8	59

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37469

1

T5

257

T6

4

T7

28

auto[1]

598

1

T5

7

T8

6

T11

11

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	617	1			T28	20		T29	21		T31	23
auto[0]	values[0]	values[1]	449	1			T11	23		T27	20		T190	59
auto[0]	values[0]	values[2]	448	1			T8	20		T130	4		T30	22
auto[0]	values[0]	values[3]	627	1			T5	24		T8	97		T28	18
auto[0]	values[0]	values[4]	471	1			T11	21		T28	21		T209	8
auto[0]	values[0]	values[5]	713	1			T13	34		T27	33		T28	89
auto[0]	values[0]	values[6]	416	1			T28	21		T223	16		T30	20
auto[0]	values[0]	values[7]	841	1			T9	2		T85	24		T31	20
auto[0]	values[1]	values[0]	446	1			T16	20		T31	48		T150	20
auto[0]	values[1]	values[1]	559	1			T16	17		T30	40		T121	20
auto[0]	values[1]	values[2]	252	1			T10	14		T186	6		T29	20
auto[0]	values[1]	values[3]	492	1			T31	20		T173	20		T236	22
auto[0]	values[1]	values[4]	662	1			T175	33		T210	20		T121	40
auto[0]	values[1]	values[5]	378	1			T11	59		T30	19		T234	42
auto[0]	values[1]	values[6]	560	1			T28	27		T207	4		T122	20
auto[0]	values[1]	values[7]	655	1			T7	28		T8	59		T16	72
auto[0]	values[2]	values[0]	661	1			T165	24		T27	20		T150	42
auto[0]	values[2]	values[1]	783	1			T34	4		T16	43		T226	8
auto[0]	values[2]	values[2]	905	1			T27	36		T28	19		T30	19
auto[0]	values[2]	values[3]	697	1			T148	56		T150	32		T122	20
auto[0]	values[2]	values[4]	672	1			T27	65		T31	46		T117	20
auto[0]	values[2]	values[5]	673	1			T8	34		T11	21		T30	20
auto[0]	values[2]	values[6]	612	1			T31	46		T176	29		T177	42
auto[0]	values[2]	values[7]	794	1			T11	20		T45	18		T28	18
auto[0]	values[3]	values[0]	556	1			T182	26		T28	22		T53	6
auto[0]	values[3]	values[1]	532	1			T11	22		T174	20		T29	20
auto[0]	values[3]	values[2]	596	1			T5	44		T103	16		T31	20
auto[0]	values[3]	values[3]	730	1			T5	23		T16	20		T72	24
auto[0]	values[3]	values[4]	482	1			T5	22		T30	24		T31	97
auto[0]	values[3]	values[5]	529	1			T16	105		T27	57		T150	33
auto[0]	values[3]	values[6]	404	1			T29	20		T194	30		T31	24
auto[0]	values[3]	values[7]	534	1			T5	19		T190	18		T205	20
auto[0]	values[4]	values[0]	439	1			T30	20		T150	20		T208	28
auto[0]	values[4]	values[1]	488	1			T83	32		T28	40		T181	40
auto[0]	values[4]	values[2]	957	1			T235	18		T29	22		T30	24
auto[0]	values[4]	values[3]	383	1			T5	19		T8	45		T29	24
auto[0]	values[4]	values[4]	444	1			T16	19		T141	20		T237	20
auto[0]	values[4]	values[5]	490	1			T29	23		T30	46		T229	6
auto[0]	values[4]	values[6]	711	1			T16	73		T181	18		T117	20
auto[0]	values[4]	values[7]	430	1			T16	26		T26	18		T187	20
auto[0]	values[5]	values[0]	667	1			T233	16		T238	10		T173	21
auto[0]	values[5]	values[1]	550	1			T5	22		T11	22		T28	20
auto[0]	values[5]	values[2]	576	1			T16	34		T26	24		T27	20
auto[0]	values[5]	values[3]	912	1			T8	20		T27	20		T167	98
auto[0]	values[5]	values[4]	520	1			T165	20		T190	130		T211	6
auto[0]	values[5]	values[5]	627	1			T5	44		T16	129		T30	20
auto[0]	values[5]	values[6]	660	1			T11	26		T165	20		T31	19
auto[0]	values[5]	values[7]	417	1			T5	20		T150	48		T190	20
auto[0]	values[6]	values[0]	851	1			T27	52		T30	23		T176	19
auto[0]	values[6]	values[1]	225	1			T131	8		T181	20		T196	21
auto[0]	values[6]	values[2]	862	1			T16	20		T239	10		T31	19
auto[0]	values[6]	values[3]	508	1			T12	12		T27	30		T29	19
auto[0]	values[6]	values[4]	597	1			T26	44		T210	20		T177	104
auto[0]	values[6]	values[5]	395	1			T173	25		T234	79		T240	8
auto[0]	values[6]	values[6]	394	1			T28	21		T31	76		T230	28
auto[0]	values[6]	values[7]	604	1			T132	2		T241	8		T180	28
auto[0]	values[7]	values[0]	602	1			T28	22		T30	20		T150	28
auto[0]	values[7]	values[1]	594	1			T165	28		T27	18		T30	24
auto[0]	values[7]	values[2]	250	1			T5	20		T242	24		T243	28
auto[0]	values[7]	values[3]	591	1			T6	4		T8	20		T181	80
auto[0]	values[7]	values[4]	735	1			T26	23		T29	44		T176	20
auto[0]	values[7]	values[5]	801	1			T8	145		T31	20		T175	51
auto[0]	values[7]	values[6]	746	1			T8	17		T16	103		T166	41
auto[0]	values[7]	values[7]	697	1			T27	19		T56	32		T189	10
auto[1]	values[0]	values[0]	10	1			T117	1		T244	1		T245	1
auto[1]	values[0]	values[1]	3	1			T141	2		T246	1		-	-
auto[1]	values[0]	values[2]	9	1			T30	1		T247	2		T227	3
auto[1]	values[0]	values[3]	6	1			T8	1		T28	2		T248	1
auto[1]	values[0]	values[4]	6	1			T31	1		T249	1		T250	1
auto[1]	values[0]	values[5]	12	1			T28	3		T234	1		T202	1
auto[1]	values[0]	values[6]	9	1			T28	1		T31	2		T243	2
auto[1]	values[0]	values[7]	8	1			T192	1		T178	2		T202	2
auto[1]	values[1]	values[0]	6	1			T73	2		T251	1		T252	1
auto[1]	values[1]	values[1]	5	1			T16	3		T246	2		-	-
auto[1]	values[1]	values[2]	3	1			T232	2		T243	1		-	-
auto[1]	values[1]	values[3]	6	1			T178	2		T253	2		T254	1
auto[1]	values[1]	values[4]	13	1			T175	3		T227	1		T255	2
auto[1]	values[1]	values[5]	8	1			T11	5		T30	1		T256	2
auto[1]	values[1]	values[6]	2	1			T246	1		T257	1		-	-
auto[1]	values[1]	values[7]	2	1			T150	1		T250	1		-	-
auto[1]	values[2]	values[0]	16	1			T150	2		T122	3		T144	2
auto[1]	values[2]	values[1]	9	1			T227	2		T232	2		T246	2
auto[1]	values[2]	values[2]	9	1			T28	1		T30	1		T190	1
auto[1]	values[2]	values[3]	10	1			T150	2		T168	1		T258	1
auto[1]	values[2]	values[4]	15	1			T27	3		T121	1		T168	2
auto[1]	values[2]	values[5]	19	1			T8	1		T11	4		T196	1
auto[1]	values[2]	values[6]	7	1			T176	1		T237	2		T259	1
auto[1]	values[2]	values[7]	8	1			T28	2		T234	1		T197	1
auto[1]	values[3]	values[0]	12	1			T176	2		T141	2		T259	2
auto[1]	values[3]	values[1]	3	1			T11	1		T73	1		T260	1
auto[1]	values[3]	values[2]	11	1			T5	3		T177	1		T168	1
auto[1]	values[3]	values[3]	9	1			T5	2		T117	1		T141	2
auto[1]	values[3]	values[4]	10	1			T31	1		T261	2		T255	1
auto[1]	values[3]	values[5]	4	1			T27	1		T262	3		-	-
auto[1]	values[3]	values[6]	3	1			T227	1		T256	1		T263	1
auto[1]	values[3]	values[7]	11	1			T5	1		T190	2		T237	2
auto[1]	values[4]	values[0]	3	1			T142	1		T252	1		T264	1
auto[1]	values[4]	values[1]	6	1			T28	1		T202	1		T248	1
auto[1]	values[4]	values[2]	5	1			T29	2		T178	1		T265	2
auto[1]	values[4]	values[3]	4	1			T5	1		T258	1		T266	1
auto[1]	values[4]	values[4]	6	1			T16	1		T266	3		T267	2
auto[1]	values[4]	values[5]	6	1			T168	1		T255	1		T246	1
auto[1]	values[4]	values[6]	23	1			T16	2		T181	2		T199	2
auto[1]	values[4]	values[7]	13	1			T26	2		T121	4		T227	1
auto[1]	values[5]	values[0]	20	1			T233	6		T192	2		T268	10
auto[1]	values[5]	values[1]	6	1			T142	3		T192	1		T178	1
auto[1]	values[5]	values[2]	12	1			T30	3		T175	1		T121	3
auto[1]	values[5]	values[3]	7	1			T121	1		T168	1		T269	1
auto[1]	values[5]	values[4]	8	1			T190	4		T232	1		T256	1
auto[1]	values[5]	values[5]	9	1			T16	2		T31	2		T270	1
auto[1]	values[5]	values[6]	6	1			T11	1		T31	1		T261	1
auto[1]	values[5]	values[7]	9	1			T168	2		T178	2		T271	2
auto[1]	values[6]	values[0]	17	1			T27	1		T176	1		T168	1
auto[1]	values[6]	values[1]	1	1			T269	1		-	-		-	-
auto[1]	values[6]	values[2]	19	1			T31	1		T181	2		T117	1
auto[1]	values[6]	values[3]	8	1			T29	1		T117	2		T178	2
auto[1]	values[6]	values[4]	8	1			T177	1		T141	1		T250	1
auto[1]	values[6]	values[5]	1	1			T146	1		-	-		-	-
auto[1]	values[6]	values[6]	7	1			T31	3		T272	2		T255	2
auto[1]	values[6]	values[7]	15	1			T27	1		T176	2		T168	2
auto[1]	values[7]	values[0]	23	1			T150	2		T205	1		T142	2
auto[1]	values[7]	values[1]	10	1			T165	1		T27	2		T266	1
auto[1]	values[7]	values[2]	3	1			T246	1		T251	1		T262	1
auto[1]	values[7]	values[3]	13	1			T181	2		T197	1		T273	2
auto[1]	values[7]	values[4]	11	1			T197	3		T232	4		T266	1
auto[1]	values[7]	values[5]	18	1			T8	1		T175	2		T205	7
auto[1]	values[7]	values[6]	25	1			T8	3		T16	4		T122	3
auto[1]	values[7]	values[7]	12	1			T27	1		T173	1		T234	2