Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2584

1

T2

3

T5

10

T11

17

auto[1]

2422

1

T2

8

T5

7

T11

11

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2757

1

T5

13

T11

28

T14

16

auto[1]

2249

1

T2

11

T5

4

T18

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3958

1

T2

11

T5

8

T11

18

auto[1]

1048

1

T5

9

T11

10

T14

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	922	1			T2	2		T5	3		T11	7
valid[1]	1022	1			T2	1		T5	3		T11	5
valid[2]	1014	1			T2	3		T5	3		T11	5
valid[3]	1031	1			T2	3		T5	3		T11	5
valid[4]	1017	1			T2	2		T5	5		T11	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	172	1			T5	1		T11	3		T14	2
auto[0]	auto[0]	valid[0]	auto[1]	196	1			T2	1		T5	1		T18	2
auto[0]	auto[0]	valid[1]	auto[0]	183	1			T11	2		T14	2		T15	1
auto[0]	auto[0]	valid[1]	auto[1]	249	1			T2	1		T19	2		T65	6
auto[0]	auto[0]	valid[2]	auto[0]	170	1			T11	1		T14	2		T17	1
auto[0]	auto[0]	valid[2]	auto[1]	236	1			T2	1		T19	2		T65	3
auto[0]	auto[0]	valid[3]	auto[0]	182	1			T11	3		T14	1		T59	1
auto[0]	auto[0]	valid[3]	auto[1]	238	1			T18	1		T19	4		T65	2
auto[0]	auto[0]	valid[4]	auto[0]	171	1			T5	1		T11	1		T14	1
auto[0]	auto[0]	valid[4]	auto[1]	237	1			T5	1		T19	5		T65	3
auto[0]	auto[1]	valid[0]	auto[0]	157	1			T5	1		T11	1		T16	2
auto[0]	auto[1]	valid[0]	auto[1]	203	1			T2	1		T18	1		T19	4
auto[0]	auto[1]	valid[1]	auto[0]	165	1			T5	1		T11	1		T14	1
auto[0]	auto[1]	valid[1]	auto[1]	210	1			T18	1		T19	1		T65	2
auto[0]	auto[1]	valid[2]	auto[0]	165	1			T11	2		T14	1		T15	1
auto[0]	auto[1]	valid[2]	auto[1]	235	1			T2	2		T5	1		T19	3
auto[0]	auto[1]	valid[3]	auto[0]	168	1			T11	2		T16	2		T18	2
auto[0]	auto[1]	valid[3]	auto[1]	221	1			T2	3		T5	1		T18	3
auto[0]	auto[1]	valid[4]	auto[0]	176	1			T11	2		T16	3		T18	4
auto[0]	auto[1]	valid[4]	auto[1]	224	1			T2	2		T18	3		T19	3
auto[1]	auto[0]	valid[0]	auto[0]	98	1			T11	2		T16	1		T17	1
auto[1]	auto[0]	valid[1]	auto[0]	108	1			T5	1		T16	1		T59	1
auto[1]	auto[0]	valid[2]	auto[0]	108	1			T5	2		T11	2		T16	1
auto[1]	auto[0]	valid[3]	auto[0]	120	1			T5	1		T16	1		T18	2
auto[1]	auto[0]	valid[4]	auto[0]	116	1			T5	2		T11	3		T14	1
auto[1]	auto[1]	valid[0]	auto[0]	96	1			T11	1		T14	2		T16	2
auto[1]	auto[1]	valid[1]	auto[0]	107	1			T5	1		T11	2		T18	1
auto[1]	auto[1]	valid[2]	auto[0]	100	1			T14	1		T18	1		T185	1
auto[1]	auto[1]	valid[3]	auto[0]	102	1			T5	1		T14	1		T16	1
auto[1]	auto[1]	valid[4]	auto[0]	93	1			T5	1		T14	1		T16	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal