Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69167

1

T5

265

T11

655

T14

432

auto[1]

23732

1

T2

11

T5

58

T15

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67328

1

T2

11

T5

212

T11

446

auto[1]

25571

1

T5

111

T11

209

T14

158

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	47685	1			T2	11		T5	162		T11	357
others[1]	7841	1			T5	27		T11	47		T14	38
others[2]	7909	1			T5	32		T11	49		T14	30
others[3]	8868	1			T5	31		T11	61		T14	46
interest[1]	5195	1			T5	21		T11	35		T14	30
interest[4]	31222	1			T2	11		T5	105		T11	228
interest[64]	15401	1			T5	50		T11	106		T14	72

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	22362	1			T5	71		T11	239		T14	137
auto[0]	auto[0]	others[1]	3716	1			T5	16		T11	36		T14	22
auto[0]	auto[0]	others[2]	3778	1			T5	18		T11	36		T14	19
auto[0]	auto[0]	others[3]	4154	1			T5	14		T11	44		T14	30
auto[0]	auto[0]	interest[1]	2426	1			T5	10		T11	27		T14	15
auto[0]	auto[0]	interest[4]	14570	1			T5	43		T11	155		T14	83
auto[0]	auto[0]	interest[64]	7160	1			T5	25		T11	64		T14	51
auto[0]	auto[1]	others[0]	12251	1			T2	11		T5	28		T15	6
auto[0]	auto[1]	others[1]	1924	1			T5	4		T18	11		T19	29
auto[0]	auto[1]	others[2]	1986	1			T5	4		T15	1		T18	8
auto[0]	auto[1]	others[3]	2237	1			T5	8		T18	5		T19	27
auto[0]	auto[1]	interest[1]	1326	1			T5	4		T18	3		T19	33
auto[0]	auto[1]	interest[4]	8132	1			T2	11		T5	17		T15	4
auto[0]	auto[1]	interest[64]	4008	1			T5	10		T15	2		T18	15
auto[1]	auto[0]	others[0]	13072	1			T5	63		T11	118		T14	79
auto[1]	auto[0]	others[1]	2201	1			T5	7		T11	11		T14	16
auto[1]	auto[0]	others[2]	2145	1			T5	10		T11	13		T14	11
auto[1]	auto[0]	others[3]	2477	1			T5	9		T11	17		T14	16
auto[1]	auto[0]	interest[1]	1443	1			T5	7		T11	8		T14	15
auto[1]	auto[0]	interest[4]	8520	1			T5	45		T11	73		T14	58
auto[1]	auto[0]	interest[64]	4233	1			T5	15		T11	42		T14	21

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal