Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	2	34	94.44

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	2	34	94.44	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	779	1			T11	14		T16	4		T39	4
all_values[1]	779	1			T11	14		T16	4		T39	4
all_values[2]	779	1			T11	14		T16	4		T39	4
all_values[3]	779	1			T11	14		T16	4		T39	4
all_values[4]	779	1			T11	14		T16	4		T39	4
all_values[5]	779	1			T11	14		T16	4		T39	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2470

1

T11

43

T16

17

T39

14

auto[1]

2204

1

T11

41

T16

7

T39

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1872

1

T11

40

T16

8

T39

12

auto[1]

2802

1

T11

44

T16

16

T39

12

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2661

1

T11

54

T16

13

T39

14

auto[1]

2013

1

T11

30

T16

11

T39

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	2	34	94.44	2
Automatically Generated Cross Bins	36	2	34	94.44	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	166	1			T11	6		T16	1		T39	2
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T16	2		T40	1		T41	1
all_values[0]	auto[0]	auto[1]	auto[0]	117	1			T11	3		T40	1		T41	1
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T11	1		T40	1		T41	1
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T11	4		T16	1		T39	1
all_values[0]	auto[1]	auto[1]	auto[1]	162	1			T39	1		T40	2		T120	4
all_values[1]	auto[0]	auto[0]	auto[0]	168	1			T11	3		T16	2		T39	1
all_values[1]	auto[0]	auto[0]	auto[1]	92	1			T11	2		T40	3		T41	1
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T11	2		T39	2		T41	3
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T11	3		T41	1		T139	2
all_values[1]	auto[1]	auto[0]	auto[1]	165	1			T11	1		T16	2		T39	1
all_values[1]	auto[1]	auto[1]	auto[1]	147	1			T11	3		T40	1		T120	2
all_values[2]	auto[0]	auto[0]	auto[0]	160	1			T11	2		T16	1		T39	1
all_values[2]	auto[0]	auto[0]	auto[1]	61	1			T11	4		T16	1		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	141	1			T39	1		T40	2		T41	1
all_values[2]	auto[0]	auto[1]	auto[1]	71	1			T11	1		T16	1		T40	2
all_values[2]	auto[1]	auto[0]	auto[1]	193	1			T11	5		T16	1		T39	1
all_values[2]	auto[1]	auto[1]	auto[1]	153	1			T11	2		T40	2		T41	1
all_values[3]	auto[0]	auto[0]	auto[0]	141	1			T11	2		T40	1		T120	2
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T16	1		T40	1		T41	1
all_values[3]	auto[0]	auto[1]	auto[0]	121	1			T11	5		T39	1		T40	1
all_values[3]	auto[0]	auto[1]	auto[1]	78	1			T11	1		T39	1		T40	2
all_values[3]	auto[1]	auto[0]	auto[1]	211	1			T11	2		T16	1		T39	1
all_values[3]	auto[1]	auto[1]	auto[1]	149	1			T11	4		T16	2		T39	1
all_values[4]	auto[0]	auto[0]	auto[0]	135	1			T11	3		T40	1		T41	2
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T40	2		T120	1		T139	1
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T11	6		T16	2		T39	1
all_values[4]	auto[0]	auto[1]	auto[1]	85	1			T11	2		T41	1		T120	1
all_values[4]	auto[1]	auto[0]	auto[1]	171	1			T16	2		T39	1		T40	2
all_values[4]	auto[1]	auto[1]	auto[1]	160	1			T11	3		T39	2		T40	1
all_values[5]	auto[0]	auto[0]	auto[0]	218	1			T11	4		T16	1		T39	3
all_values[5]	auto[0]	auto[1]	auto[0]	231	1			T11	4		T16	1		T40	2
all_values[5]	auto[1]	auto[0]	auto[1]	171	1			T11	5		T16	1		T39	1
all_values[5]	auto[1]	auto[1]	auto[1]	159	1			T11	1		T16	1		T40	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal