Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6025191	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6457583

1

T1

24

T2

75218

T4

918

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8136946	1			T1	1		T2	129886		T3	61
values[0x0]	2172205	1			T1	16		T2	21409		T4	460
values[0x1]	2173623	1			T1	15		T2	21468		T4	455

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4381264	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8101510

1

T1

24

T2

102223

T3

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49720	1			T2	642		T4	3		T8	84
valid_sources[0x01]	48524	1			T1	1		T2	678		T4	3
valid_sources[0x02]	47870	1			T2	656		T4	3		T8	81
valid_sources[0x03]	47214	1			T2	694		T4	5		T8	82
valid_sources[0x04]	49943	1			T2	659		T4	3		T8	79
valid_sources[0x05]	49748	1			T2	684		T4	3		T8	76
valid_sources[0x06]	46460	1			T2	626		T4	2		T8	76
valid_sources[0x07]	45771	1			T1	1		T2	683		T3	2
valid_sources[0x08]	48683	1			T2	627		T3	1		T4	4
valid_sources[0x09]	51619	1			T2	673		T4	4		T8	88
valid_sources[0x0a]	55597	1			T2	681		T4	3		T8	72
valid_sources[0x0b]	47783	1			T2	711		T3	6		T8	69
valid_sources[0x0c]	44081	1			T2	678		T4	1		T8	76
valid_sources[0x0d]	48846	1			T2	694		T4	4		T8	80
valid_sources[0x0e]	53309	1			T2	680		T4	7		T8	77
valid_sources[0x0f]	47597	1			T2	671		T4	9		T8	73
valid_sources[0x10]	51970	1			T2	658		T8	71		T9	1
valid_sources[0x11]	52980	1			T2	686		T8	72		T9	1
valid_sources[0x12]	45422	1			T2	627		T4	2		T8	81
valid_sources[0x13]	47223	1			T2	668		T8	81		T9	1
valid_sources[0x14]	49232	1			T2	677		T8	75		T9	4
valid_sources[0x15]	48026	1			T2	681		T4	1		T8	85
valid_sources[0x16]	53305	1			T2	697		T4	6		T7	1
valid_sources[0x17]	49894	1			T2	674		T4	1		T6	71
valid_sources[0x18]	46744	1			T2	667		T4	5		T8	71
valid_sources[0x19]	52256	1			T1	1		T2	715		T4	2
valid_sources[0x1a]	50486	1			T2	702		T4	3		T8	73
valid_sources[0x1b]	48153	1			T2	672		T8	58		T9	2
valid_sources[0x1c]	47712	1			T2	664		T4	3		T8	71
valid_sources[0x1d]	46707	1			T2	681		T4	2		T8	72
valid_sources[0x1e]	47739	1			T2	678		T4	3		T8	92
valid_sources[0x1f]	47704	1			T1	1		T2	720		T4	3
valid_sources[0x20]	51029	1			T2	622		T4	3		T8	73
valid_sources[0x21]	46267	1			T2	735		T4	8		T8	76
valid_sources[0x22]	47262	1			T2	672		T4	3		T8	76
valid_sources[0x23]	50310	1			T2	676		T4	5		T8	81
valid_sources[0x24]	46124	1			T2	681		T4	5		T8	60
valid_sources[0x25]	55884	1			T1	1		T2	661		T4	2
valid_sources[0x26]	47983	1			T2	717		T4	4		T8	90
valid_sources[0x27]	46545	1			T2	668		T4	3		T8	88
valid_sources[0x28]	52693	1			T2	644		T8	79		T9	1
valid_sources[0x29]	50723	1			T2	655		T4	15		T8	69
valid_sources[0x2a]	47152	1			T2	658		T4	6		T8	81
valid_sources[0x2b]	48321	1			T2	651		T4	3		T8	69
valid_sources[0x2c]	49813	1			T2	669		T4	3		T8	103
valid_sources[0x2d]	46836	1			T2	693		T4	4		T8	73
valid_sources[0x2e]	56697	1			T2	635		T4	6		T8	82
valid_sources[0x2f]	51082	1			T2	692		T4	8		T8	79
valid_sources[0x30]	48829	1			T1	1		T2	651		T4	2
valid_sources[0x31]	47942	1			T1	1		T2	673		T4	5
valid_sources[0x32]	48800	1			T2	710		T4	3		T8	84
valid_sources[0x33]	48312	1			T2	688		T4	2		T8	76
valid_sources[0x34]	46631	1			T2	689		T4	2		T8	81
valid_sources[0x35]	54732	1			T2	688		T4	3		T5	53
valid_sources[0x36]	47501	1			T2	710		T4	4		T8	75
valid_sources[0x37]	48603	1			T2	722		T4	1		T8	76
valid_sources[0x38]	50482	1			T2	631		T4	5		T8	81
valid_sources[0x39]	50035	1			T2	675		T4	5		T8	67
valid_sources[0x3a]	48887	1			T2	664		T4	6		T8	78
valid_sources[0x3b]	48041	1			T2	632		T8	83		T9	3
valid_sources[0x3c]	48895	1			T2	753		T4	5		T8	81
valid_sources[0x3d]	46499	1			T1	1		T2	684		T4	1
valid_sources[0x3e]	49460	1			T2	696		T4	5		T8	99
valid_sources[0x3f]	45979	1			T2	665		T4	3		T8	71
valid_sources[0x40]	49336	1			T2	666		T4	1		T8	60
valid_sources[0x41]	47770	1			T2	668		T4	2		T8	80
valid_sources[0x42]	56220	1			T2	698		T4	4		T8	76
valid_sources[0x43]	50311	1			T1	1		T2	663		T4	9
valid_sources[0x44]	48218	1			T2	705		T8	81		T9	5
valid_sources[0x45]	48231	1			T2	633		T4	3		T8	72
valid_sources[0x46]	49494	1			T1	1		T2	695		T4	4
valid_sources[0x47]	48104	1			T2	689		T4	2		T8	74
valid_sources[0x48]	48294	1			T2	694		T4	5		T8	71
valid_sources[0x49]	46551	1			T2	640		T3	2		T4	1
valid_sources[0x4a]	50207	1			T2	699		T4	1		T8	75
valid_sources[0x4b]	49297	1			T2	653		T3	3		T4	5
valid_sources[0x4c]	46862	1			T1	1		T2	645		T4	2
valid_sources[0x4d]	46959	1			T1	1		T2	687		T4	7
valid_sources[0x4e]	46952	1			T2	617		T3	1		T4	2
valid_sources[0x4f]	49628	1			T2	666		T4	6		T8	103
valid_sources[0x50]	47761	1			T2	711		T4	3		T8	54
valid_sources[0x51]	50916	1			T2	643		T4	5		T7	1
valid_sources[0x52]	51326	1			T2	666		T4	4		T8	86
valid_sources[0x53]	48305	1			T2	667		T4	2		T8	70
valid_sources[0x54]	45387	1			T2	687		T3	4		T8	80
valid_sources[0x55]	49177	1			T2	663		T4	6		T8	79
valid_sources[0x56]	50899	1			T2	629		T3	1		T4	2
valid_sources[0x57]	48091	1			T1	2		T2	619		T4	4
valid_sources[0x58]	47990	1			T1	1		T2	602		T4	1
valid_sources[0x59]	47297	1			T2	652		T4	1		T8	76
valid_sources[0x5a]	48738	1			T2	745		T8	90		T9	1
valid_sources[0x5b]	52109	1			T2	694		T4	6		T8	85
valid_sources[0x5c]	47581	1			T2	644		T3	2		T8	98
valid_sources[0x5d]	50045	1			T2	641		T4	5		T8	82
valid_sources[0x5e]	47890	1			T2	670		T3	4		T4	9
valid_sources[0x5f]	49189	1			T1	1		T2	675		T4	3
valid_sources[0x60]	48025	1			T2	656		T4	6		T8	78
valid_sources[0x61]	46881	1			T2	665		T4	5		T8	70
valid_sources[0x62]	53867	1			T2	665		T4	7		T8	63
valid_sources[0x63]	55288	1			T2	737		T4	5		T8	77
valid_sources[0x64]	49912	1			T2	717		T4	2		T8	97
valid_sources[0x65]	48083	1			T2	647		T4	2		T8	73
valid_sources[0x66]	45348	1			T2	670		T4	5		T8	59
valid_sources[0x67]	52168	1			T2	670		T4	11		T8	76
valid_sources[0x68]	47722	1			T2	637		T4	4		T8	89
valid_sources[0x69]	47212	1			T2	643		T4	14		T8	92
valid_sources[0x6a]	47439	1			T2	721		T4	3		T8	85
valid_sources[0x6b]	47462	1			T2	753		T4	3		T8	97
valid_sources[0x6c]	47048	1			T2	729		T3	1		T4	13
valid_sources[0x6d]	47005	1			T2	713		T3	1		T4	2
valid_sources[0x6e]	47055	1			T2	636		T4	3		T8	88
valid_sources[0x6f]	49678	1			T2	669		T8	71		T9	2
valid_sources[0x70]	45588	1			T2	739		T4	4		T8	75
valid_sources[0x71]	47487	1			T2	660		T4	2		T8	79
valid_sources[0x72]	50371	1			T1	1		T2	645		T3	1
valid_sources[0x73]	46195	1			T2	707		T4	14		T8	89
valid_sources[0x74]	47580	1			T2	667		T4	4		T8	90
valid_sources[0x75]	47697	1			T2	673		T4	8		T8	79
valid_sources[0x76]	49493	1			T2	665		T3	4		T4	1
valid_sources[0x77]	49283	1			T2	722		T4	5		T8	106
valid_sources[0x78]	50252	1			T2	704		T4	2		T8	113
valid_sources[0x79]	48987	1			T2	645		T4	6		T8	78
valid_sources[0x7a]	44065	1			T2	673		T8	83		T9	6
valid_sources[0x7b]	50040	1			T2	695		T4	2		T8	74
valid_sources[0x7c]	44111	1			T2	700		T3	6		T4	6
valid_sources[0x7d]	47558	1			T1	1		T2	704		T8	83
valid_sources[0x7e]	46462	1			T2	733		T4	4		T8	70
valid_sources[0x7f]	50609	1			T2	704		T4	6		T8	78
valid_sources[0x80]	48200	1			T2	655		T4	7		T8	76

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2555907

1

T2

38345

T4

11

T8

2432

values[0x0]

all_enables

biggest_size

1965261

1

T1

10

T2

18475

T4

458

values[0x1]

all_enables

biggest_size

1936415

1

T1

14

T2

18398

T4

449