Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6044914

1

T1

8

T2

97545

T3

61

full_word

6456652

1

T1

24

T2

75218

T4

918

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	12501126	1			T1	32		T2	172763		T3	61
auto[TlIntgErrCmd]	153	1			T88	9		T90	5		T91	3
auto[TlIntgErrData]	144	1			T88	12		T90	13		T91	2
auto[TlIntgErrBoth]	143	1			T88	9		T90	12		T91	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8138320

1

T1

1

T2

129886

T3

61

auto[1]

4363246

1

T1

31

T2

42877

T4

915

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5582124	1			T1	1		T2	91541		T3	61
auto[TlIntgErrNone]	partial	auto[1]	462389	1			T1	7		T2	6004		T4	8
auto[TlIntgErrNone]	full_word	auto[0]	2555982	1			T2	38345		T4	11		T8	2432
auto[TlIntgErrNone]	full_word	auto[1]	3900631	1			T1	24		T2	36873		T4	907
auto[TlIntgErrCmd]	partial	auto[0]	64	1			T88	2		T90	3		T91	3
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T88	7		T90	2		T250	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T245	1		T251	1		T252	3
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T248	1		T253	1		T246	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T88	8		T90	5		T91	1
auto[TlIntgErrData]	partial	auto[1]	61	1			T88	3		T90	7		T91	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T88	1		T254	1		T255	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T90	1		T255	1		T253	1
auto[TlIntgErrBoth]	partial	auto[0]	65	1			T88	3		T90	3		T91	3
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T88	5		T90	8		T91	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T256	1		T252	1		T247	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T88	1		T90	1		T245	1