Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584127548	14522521	0	0
DepthKnown_A	584127548	583992378	0	0
RvalidKnown_A	584127548	583992378	0	0
WreadyKnown_A	584127548	583992378	0	0
gen_passthru_fifo.paramCheckPass	1111	1111	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	14522521	0	0
T1	3939	32	0	0
T2	728077	178813	0	0
T3	1076	61	0	0
T4	52565	1774	0	0
T5	3731	53	0	0
T6	1332	71	0	0
T7	2308	8	0	0
T8	314306	28899	0	0
T9	10757	833	0	0
T10	113094	8241	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584127548	27832119	0	0
DepthKnown_A	584127548	583992378	0	0
RvalidKnown_A	584127548	583992378	0	0
WreadyKnown_A	584127548	583992378	0	0
gen_passthru_fifo.paramCheckPass	1111	1111	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	27832119	0	0
T1	3939	32	0	0
T2	728077	172763	0	0
T3	1076	61	0	0
T4	52565	1277	0	0
T5	3731	53	0	0
T6	1332	71	0	0
T7	2308	39	0	0
T8	314306	48550	0	0
T9	10757	833	0	0
T10	113094	18779	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584127548	3273896	0	0
DepthKnown_A	584127548	583992378	0	0
RvalidKnown_A	584127548	583992378	0	0
WreadyKnown_A	584127548	583992378	0	0
gen_passthru_fifo.paramCheckPass	1111	1111	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	3273896	0	0
T2	728077	15802	0	0
T3	1076	0	0	0
T4	52565	1670	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	18316	0	0
T9	10757	0	0	0
T10	113094	2496	0	0
T11	381827	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1663	0	0
T15	0	1663	0	0
T16	0	18299	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584127548	3792076	0	0
DepthKnown_A	584127548	583992378	0	0
RvalidKnown_A	584127548	583992378	0	0
WreadyKnown_A	584127548	583992378	0	0
gen_passthru_fifo.paramCheckPass	1111	1111	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	3792076	0	0
T2	728077	10816	0	0
T3	1076	0	0	0
T4	52565	839	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	24342	0	0
T9	10757	0	0	0
T10	113094	7879	0	0
T11	381827	832	0	0
T12	0	832	0	0
T13	0	2559	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	14144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584127548	204593	0	0
DepthKnown_A	584127548	583992378	0	0
RvalidKnown_A	584127548	583992378	0	0
WreadyKnown_A	584127548	583992378	0	0
gen_passthru_fifo.paramCheckPass	1111	1111	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	204593	0	0
T2	728077	699	0	0
T3	1076	0	0	0
T4	52565	0	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	649	0	0
T9	10757	48	0	0
T10	113094	211	0	0
T11	381827	64	0	0
T16	0	839	0	0
T17	0	312	0	0
T18	0	385	0	0
T25	0	242	0	0
T26	0	555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584127548	474124	0	0
DepthKnown_A	584127548	583992378	0	0
RvalidKnown_A	584127548	583992378	0	0
WreadyKnown_A	584127548	583992378	0	0
gen_passthru_fifo.paramCheckPass	1111	1111	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	474124	0	0
T2	728077	699	0	0
T3	1076	0	0	0
T4	52565	0	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	1980	0	0
T9	10757	48	0	0
T10	113094	643	0	0
T11	381827	64	0	0
T16	0	839	0	0
T17	0	312	0	0
T18	0	1778	0	0
T25	0	242	0	0
T26	0	555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584127548	583992378	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0