Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T2,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T11
1	0	Covered	T2,T8,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Unreachable
1	1	Covered	T2,T8,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	939139028	758378122	0	0
CheckNGreaterZero_A	2808	2808	0	0
GntImpliesReady_A	939139028	4128630	0	0
GntImpliesValid_A	939139028	4128630	0	0
GrantKnown_A	939139028	758378122	0	0
IdxKnown_A	939139028	758378122	0	0
IndexIsCorrect_A	939139028	4128630	0	0
LockArbDecision_A	939139028	0	0	0
NoReadyValidNoGrant_A	939139028	0	0	0
ReadyAndValidImplyGrant_A	939139028	4128630	0	0
ReqAndReadyImplyGrant_A	939139028	4128630	0	0
ReqImpliesValid_A	939139028	4128630	0	0
ReqStaysHighUntilGranted0_M	939139028	0	0	0
RoundRobin_A	939139028	7	0	936
ValidKnown_A	939139028	758378122	0	0
gen_data_port_assertion.DataFlow_A	939139028	4128630	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	758378122	0	0
T1	4659	4593	0	0
T2	2535201	1625020	0	0
T3	1076	1003	0	0
T4	245439	148717	0	0
T5	6293	4889	0	0
T6	1332	1272	0	0
T7	2596	2382	0	0
T8	1637656	971676	0	0
T9	19509	15054	0	0
T10	463154	285698	0	0
T11	187904	93952	0	0
T12	45782	22891	0	0
T13	16080	16080	0	0
T14	0	57088	0	0
T15	0	220058	0	0
T16	0	199902	0	0
T17	0	51904	0	0
T55	0	43776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2808	2808	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	4128630	0	0
T2	2535201	21149	0	0
T3	1076	0	0	0
T4	245439	832	0	0
T5	6293	0	0	0
T6	1332	0	0	0
T7	2596	0	0	0
T8	1637656	22151	0	0
T9	19509	357	0	0
T10	463154	4236	0	0
T11	569731	1168	0	0
T12	45782	832	0	0
T13	32160	832	0	0
T14	0	832	0	0
T16	0	9423	0	0
T17	0	2915	0	0
T18	0	10281	0	0
T25	0	1397	0	0
T26	0	2869	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0
T59	0	2363	0	0
T61	0	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	4128630	0	0
T2	2535201	21149	0	0
T3	1076	0	0	0
T4	245439	832	0	0
T5	6293	0	0	0
T6	1332	0	0	0
T7	2596	0	0	0
T8	1637656	22151	0	0
T9	19509	357	0	0
T10	463154	4236	0	0
T11	569731	1168	0	0
T12	45782	832	0	0
T13	32160	832	0	0
T14	0	832	0	0
T16	0	9423	0	0
T17	0	2915	0	0
T18	0	10281	0	0
T25	0	1397	0	0
T26	0	2869	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0
T59	0	2363	0	0
T61	0	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	758378122	0	0
T1	4659	4593	0	0
T2	2535201	1625020	0	0
T3	1076	1003	0	0
T4	245439	148717	0	0
T5	6293	4889	0	0
T6	1332	1272	0	0
T7	2596	2382	0	0
T8	1637656	971676	0	0
T9	19509	15054	0	0
T10	463154	285698	0	0
T11	187904	93952	0	0
T12	45782	22891	0	0
T13	16080	16080	0	0
T14	0	57088	0	0
T15	0	220058	0	0
T16	0	199902	0	0
T17	0	51904	0	0
T55	0	43776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	758378122	0	0
T1	4659	4593	0	0
T2	2535201	1625020	0	0
T3	1076	1003	0	0
T4	245439	148717	0	0
T5	6293	4889	0	0
T6	1332	1272	0	0
T7	2596	2382	0	0
T8	1637656	971676	0	0
T9	19509	15054	0	0
T10	463154	285698	0	0
T11	187904	93952	0	0
T12	45782	22891	0	0
T13	16080	16080	0	0
T14	0	57088	0	0
T15	0	220058	0	0
T16	0	199902	0	0
T17	0	51904	0	0
T55	0	43776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	4128630	0	0
T2	2535201	21149	0	0
T3	1076	0	0	0
T4	245439	832	0	0
T5	6293	0	0	0
T6	1332	0	0	0
T7	2596	0	0	0
T8	1637656	22151	0	0
T9	19509	357	0	0
T10	463154	4236	0	0
T11	569731	1168	0	0
T12	45782	832	0	0
T13	32160	832	0	0
T14	0	832	0	0
T16	0	9423	0	0
T17	0	2915	0	0
T18	0	10281	0	0
T25	0	1397	0	0
T26	0	2869	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0
T59	0	2363	0	0
T61	0	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	4128630	0	0
T2	2535201	21149	0	0
T3	1076	0	0	0
T4	245439	832	0	0
T5	6293	0	0	0
T6	1332	0	0	0
T7	2596	0	0	0
T8	1637656	22151	0	0
T9	19509	357	0	0
T10	463154	4236	0	0
T11	569731	1168	0	0
T12	45782	832	0	0
T13	32160	832	0	0
T14	0	832	0	0
T16	0	9423	0	0
T17	0	2915	0	0
T18	0	10281	0	0
T25	0	1397	0	0
T26	0	2869	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0
T59	0	2363	0	0
T61	0	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	4128630	0	0
T2	2535201	21149	0	0
T3	1076	0	0	0
T4	245439	832	0	0
T5	6293	0	0	0
T6	1332	0	0	0
T7	2596	0	0	0
T8	1637656	22151	0	0
T9	19509	357	0	0
T10	463154	4236	0	0
T11	569731	1168	0	0
T12	45782	832	0	0
T13	32160	832	0	0
T14	0	832	0	0
T16	0	9423	0	0
T17	0	2915	0	0
T18	0	10281	0	0
T25	0	1397	0	0
T26	0	2869	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0
T59	0	2363	0	0
T61	0	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	4128630	0	0
T2	2535201	21149	0	0
T3	1076	0	0	0
T4	245439	832	0	0
T5	6293	0	0	0
T6	1332	0	0	0
T7	2596	0	0	0
T8	1637656	22151	0	0
T9	19509	357	0	0
T10	463154	4236	0	0
T11	569731	1168	0	0
T12	45782	832	0	0
T13	32160	832	0	0
T14	0	832	0	0
T16	0	9423	0	0
T17	0	2915	0	0
T18	0	10281	0	0
T25	0	1397	0	0
T26	0	2869	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0
T59	0	2363	0	0
T61	0	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	7	0	936
T19	0	1	0	0
T51	144750	1	0	1
T52	441928	0	0	1
T53	841832	0	0	1
T54	1032	0	0	1
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	486686	0	0	1
T68	8927	0	0	1
T69	107130	0	0	1
T70	8494	0	0	1
T71	1835	0	0	1
T72	10999	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	758378122	0	0
T1	4659	4593	0	0
T2	2535201	1625020	0	0
T3	1076	1003	0	0
T4	245439	148717	0	0
T5	6293	4889	0	0
T6	1332	1272	0	0
T7	2596	2382	0	0
T8	1637656	971676	0	0
T9	19509	15054	0	0
T10	463154	285698	0	0
T11	187904	93952	0	0
T12	45782	22891	0	0
T13	16080	16080	0	0
T14	0	57088	0	0
T15	0	220058	0	0
T16	0	199902	0	0
T17	0	51904	0	0
T55	0	43776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939139028	4128630	0	0
T2	2535201	21149	0	0
T3	1076	0	0	0
T4	245439	832	0	0
T5	6293	0	0	0
T6	1332	0	0	0
T7	2596	0	0	0
T8	1637656	22151	0	0
T9	19509	357	0	0
T10	463154	4236	0	0
T11	569731	1168	0	0
T12	45782	832	0	0
T13	32160	832	0	0
T14	0	832	0	0
T16	0	9423	0	0
T17	0	2915	0	0
T18	0	10281	0	0
T25	0	1397	0	0
T26	0	2869	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0
T59	0	2363	0	0
T61	0	40	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T2,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	178882439	38019352	0	0
CheckNGreaterZero_A	936	936	0	0
GntImpliesReady_A	178882439	839166	0	0
GntImpliesValid_A	178882439	839166	0	0
GrantKnown_A	178882439	38019352	0	0
IdxKnown_A	178882439	38019352	0	0
IndexIsCorrect_A	178882439	839166	0	0
LockArbDecision_A	178882439	0	0	0
NoReadyValidNoGrant_A	178882439	0	0	0
ReadyAndValidImplyGrant_A	178882439	839166	0	0
ReqAndReadyImplyGrant_A	178882439	839166	0	0
ReqImpliesValid_A	178882439	839166	0	0
ReqStaysHighUntilGranted0_M	178882439	0	0	0
RoundRobin_A	178882439	0	0	0
ValidKnown_A	178882439	38019352	0	0
gen_data_port_assertion.DataFlow_A	178882439	839166	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	38019352	0	0
T1	720	720	0	0
T2	903562	49880	0	0
T4	96437	0	0	0
T5	1281	1224	0	0
T7	144	144	0	0
T8	661675	153640	0	0
T9	4376	4376	0	0
T10	175030	74232	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T16	0	68032	0	0
T17	0	51904	0	0
T55	0	43776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	936	936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	839166	0	0
T2	903562	2577	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	1677	0	0
T9	4376	252	0	0
T10	175030	1194	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	2985	0	0
T17	0	1920	0	0
T25	0	1397	0	0
T26	0	2482	0	0
T59	0	2363	0	0
T61	0	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	839166	0	0
T2	903562	2577	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	1677	0	0
T9	4376	252	0	0
T10	175030	1194	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	2985	0	0
T17	0	1920	0	0
T25	0	1397	0	0
T26	0	2482	0	0
T59	0	2363	0	0
T61	0	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	38019352	0	0
T1	720	720	0	0
T2	903562	49880	0	0
T4	96437	0	0	0
T5	1281	1224	0	0
T7	144	144	0	0
T8	661675	153640	0	0
T9	4376	4376	0	0
T10	175030	74232	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T16	0	68032	0	0
T17	0	51904	0	0
T55	0	43776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	38019352	0	0
T1	720	720	0	0
T2	903562	49880	0	0
T4	96437	0	0	0
T5	1281	1224	0	0
T7	144	144	0	0
T8	661675	153640	0	0
T9	4376	4376	0	0
T10	175030	74232	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T16	0	68032	0	0
T17	0	51904	0	0
T55	0	43776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	839166	0	0
T2	903562	2577	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	1677	0	0
T9	4376	252	0	0
T10	175030	1194	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	2985	0	0
T17	0	1920	0	0
T25	0	1397	0	0
T26	0	2482	0	0
T59	0	2363	0	0
T61	0	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	839166	0	0
T2	903562	2577	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	1677	0	0
T9	4376	252	0	0
T10	175030	1194	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	2985	0	0
T17	0	1920	0	0
T25	0	1397	0	0
T26	0	2482	0	0
T59	0	2363	0	0
T61	0	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	839166	0	0
T2	903562	2577	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	1677	0	0
T9	4376	252	0	0
T10	175030	1194	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	2985	0	0
T17	0	1920	0	0
T25	0	1397	0	0
T26	0	2482	0	0
T59	0	2363	0	0
T61	0	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	839166	0	0
T2	903562	2577	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	1677	0	0
T9	4376	252	0	0
T10	175030	1194	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	2985	0	0
T17	0	1920	0	0
T25	0	1397	0	0
T26	0	2482	0	0
T59	0	2363	0	0
T61	0	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	38019352	0	0
T1	720	720	0	0
T2	903562	49880	0	0
T4	96437	0	0	0
T5	1281	1224	0	0
T7	144	144	0	0
T8	661675	153640	0	0
T9	4376	4376	0	0
T10	175030	74232	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T16	0	68032	0	0
T17	0	51904	0	0
T55	0	43776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	839166	0	0
T2	903562	2577	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	1677	0	0
T9	4376	252	0	0
T10	175030	1194	0	0
T11	93952	0	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	2985	0	0
T17	0	1920	0	0
T25	0	1397	0	0
T26	0	2482	0	0
T59	0	2363	0	0
T61	0	40	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T11
1	0	Covered	T2,T8,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Unreachable
1	1	Covered	T2,T8,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T11
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	178882439	139071780	0	0
CheckNGreaterZero_A	936	936	0	0
GntImpliesReady_A	178882439	679145	0	0
GntImpliesValid_A	178882439	679145	0	0
GrantKnown_A	178882439	139071780	0	0
IdxKnown_A	178882439	139071780	0	0
IndexIsCorrect_A	178882439	679145	0	0
LockArbDecision_A	178882439	0	0	0
NoReadyValidNoGrant_A	178882439	0	0	0
ReadyAndValidImplyGrant_A	178882439	679145	0	0
ReqAndReadyImplyGrant_A	178882439	679145	0	0
ReqImpliesValid_A	178882439	679145	0	0
ReqStaysHighUntilGranted0_M	178882439	0	0	0
RoundRobin_A	178882439	0	0	0
ValidKnown_A	178882439	139071780	0	0
gen_data_port_assertion.DataFlow_A	178882439	679145	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	139071780	0	0
T2	903562	847084	0	0
T4	96437	96238	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	503824	0	0
T9	4376	0	0	0
T10	175030	98446	0	0
T11	93952	93952	0	0
T12	22891	22891	0	0
T13	16080	16080	0	0
T14	0	57088	0	0
T15	0	220058	0	0
T16	0	131870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	936	936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	679145	0	0
T2	903562	6336	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	6735	0	0
T9	4376	0	0	0
T10	175030	0	0	0
T11	93952	264	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	6438	0	0
T18	0	10281	0	0
T26	0	387	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	679145	0	0
T2	903562	6336	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	6735	0	0
T9	4376	0	0	0
T10	175030	0	0	0
T11	93952	264	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	6438	0	0
T18	0	10281	0	0
T26	0	387	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	139071780	0	0
T2	903562	847084	0	0
T4	96437	96238	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	503824	0	0
T9	4376	0	0	0
T10	175030	98446	0	0
T11	93952	93952	0	0
T12	22891	22891	0	0
T13	16080	16080	0	0
T14	0	57088	0	0
T15	0	220058	0	0
T16	0	131870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	139071780	0	0
T2	903562	847084	0	0
T4	96437	96238	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	503824	0	0
T9	4376	0	0	0
T10	175030	98446	0	0
T11	93952	93952	0	0
T12	22891	22891	0	0
T13	16080	16080	0	0
T14	0	57088	0	0
T15	0	220058	0	0
T16	0	131870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	679145	0	0
T2	903562	6336	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	6735	0	0
T9	4376	0	0	0
T10	175030	0	0	0
T11	93952	264	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	6438	0	0
T18	0	10281	0	0
T26	0	387	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	679145	0	0
T2	903562	6336	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	6735	0	0
T9	4376	0	0	0
T10	175030	0	0	0
T11	93952	264	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	6438	0	0
T18	0	10281	0	0
T26	0	387	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	679145	0	0
T2	903562	6336	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	6735	0	0
T9	4376	0	0	0
T10	175030	0	0	0
T11	93952	264	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	6438	0	0
T18	0	10281	0	0
T26	0	387	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	679145	0	0
T2	903562	6336	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	6735	0	0
T9	4376	0	0	0
T10	175030	0	0	0
T11	93952	264	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	6438	0	0
T18	0	10281	0	0
T26	0	387	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	139071780	0	0
T2	903562	847084	0	0
T4	96437	96238	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	503824	0	0
T9	4376	0	0	0
T10	175030	98446	0	0
T11	93952	93952	0	0
T12	22891	22891	0	0
T13	16080	16080	0	0
T14	0	57088	0	0
T15	0	220058	0	0
T16	0	131870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	679145	0	0
T2	903562	6336	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	6735	0	0
T9	4376	0	0	0
T10	175030	0	0	0
T11	93952	264	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	6438	0	0
T18	0	10281	0	0
T26	0	387	0	0
T27	0	6007	0	0
T56	0	1973	0	0
T57	0	297	0	0
T58	0	2573	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	581374150	581286990	0	0
CheckNGreaterZero_A	936	936	0	0
GntImpliesReady_A	581374150	2610319	0	0
GntImpliesValid_A	581374150	2610319	0	0
GrantKnown_A	581374150	581286990	0	0
IdxKnown_A	581374150	581286990	0	0
IndexIsCorrect_A	581374150	2610319	0	0
LockArbDecision_A	581374150	0	0	0
NoReadyValidNoGrant_A	581374150	0	0	0
ReadyAndValidImplyGrant_A	581374150	2610319	0	0
ReqAndReadyImplyGrant_A	581374150	2610319	0	0
ReqImpliesValid_A	581374150	2610319	0	0
ReqStaysHighUntilGranted0_M	581374150	0	0	0
RoundRobin_A	581374150	7	0	936
ValidKnown_A	581374150	581286990	0	0
gen_data_port_assertion.DataFlow_A	581374150	2610319	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	936	936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	2610319	0	0
T2	728077	12236	0	0
T3	1076	0	0	0
T4	52565	832	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	13739	0	0
T9	10757	105	0	0
T10	113094	3042	0	0
T11	381827	904	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T17	0	995	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	2610319	0	0
T2	728077	12236	0	0
T3	1076	0	0	0
T4	52565	832	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	13739	0	0
T9	10757	105	0	0
T10	113094	3042	0	0
T11	381827	904	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T17	0	995	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	2610319	0	0
T2	728077	12236	0	0
T3	1076	0	0	0
T4	52565	832	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	13739	0	0
T9	10757	105	0	0
T10	113094	3042	0	0
T11	381827	904	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T17	0	995	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	2610319	0	0
T2	728077	12236	0	0
T3	1076	0	0	0
T4	52565	832	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	13739	0	0
T9	10757	105	0	0
T10	113094	3042	0	0
T11	381827	904	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T17	0	995	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	2610319	0	0
T2	728077	12236	0	0
T3	1076	0	0	0
T4	52565	832	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	13739	0	0
T9	10757	105	0	0
T10	113094	3042	0	0
T11	381827	904	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T17	0	995	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	2610319	0	0
T2	728077	12236	0	0
T3	1076	0	0	0
T4	52565	832	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	13739	0	0
T9	10757	105	0	0
T10	113094	3042	0	0
T11	381827	904	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T17	0	995	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	7	0	936
T19	0	1	0	0
T51	144750	1	0	1
T52	441928	0	0	1
T53	841832	0	0	1
T54	1032	0	0	1
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	486686	0	0	1
T68	8927	0	0	1
T69	107130	0	0	1
T70	8494	0	0	1
T71	1835	0	0	1
T72	10999	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	2610319	0	0
T2	728077	12236	0	0
T3	1076	0	0	0
T4	52565	832	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	13739	0	0
T9	10757	105	0	0
T10	113094	3042	0	0
T11	381827	904	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T17	0	995	0	0