Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.52 94.56 98.61 89.36 97.29 96.09 98.07


Total test records in report: 1111
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T248 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1803343782 Feb 25 01:50:31 PM PST 24 Feb 25 01:50:52 PM PST 24 838935717 ps
T1019 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1734617461 Feb 25 01:50:31 PM PST 24 Feb 25 01:50:32 PM PST 24 31351829 ps
T112 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.27153047 Feb 25 01:50:09 PM PST 24 Feb 25 01:50:23 PM PST 24 840156537 ps
T1020 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.734480848 Feb 25 01:50:45 PM PST 24 Feb 25 01:50:46 PM PST 24 14184899 ps
T1021 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1151622218 Feb 25 01:50:53 PM PST 24 Feb 25 01:50:55 PM PST 24 88590078 ps
T255 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2331744604 Feb 25 01:50:10 PM PST 24 Feb 25 01:50:23 PM PST 24 1156192003 ps
T249 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3659146524 Feb 25 01:50:30 PM PST 24 Feb 25 01:50:41 PM PST 24 2164853698 ps
T113 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.797842331 Feb 25 01:49:52 PM PST 24 Feb 25 01:50:01 PM PST 24 758101992 ps
T1022 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1689409935 Feb 25 01:50:51 PM PST 24 Feb 25 01:50:52 PM PST 24 84757944 ps
T98 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1772991483 Feb 25 01:50:49 PM PST 24 Feb 25 01:50:52 PM PST 24 995261291 ps
T1023 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1633105434 Feb 25 01:50:51 PM PST 24 Feb 25 01:50:52 PM PST 24 14993054 ps
T114 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.428465511 Feb 25 01:49:26 PM PST 24 Feb 25 01:49:28 PM PST 24 71860907 ps
T1024 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3126702113 Feb 25 01:49:35 PM PST 24 Feb 25 01:49:36 PM PST 24 11300600 ps
T1025 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.768971058 Feb 25 01:50:48 PM PST 24 Feb 25 01:50:48 PM PST 24 17063319 ps
T253 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2949527978 Feb 25 01:49:51 PM PST 24 Feb 25 01:50:14 PM PST 24 1757760018 ps
T1026 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.56709865 Feb 25 01:50:52 PM PST 24 Feb 25 01:50:53 PM PST 24 61073306 ps
T1027 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2566511969 Feb 25 01:50:12 PM PST 24 Feb 25 01:50:13 PM PST 24 12603599 ps
T1028 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1348525117 Feb 25 01:49:42 PM PST 24 Feb 25 01:50:08 PM PST 24 4826407751 ps
T1029 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.714857293 Feb 25 01:50:19 PM PST 24 Feb 25 01:50:20 PM PST 24 18703880 ps
T1030 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3558805504 Feb 25 01:50:40 PM PST 24 Feb 25 01:50:46 PM PST 24 272381963 ps
T1031 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.380553045 Feb 25 01:50:51 PM PST 24 Feb 25 01:50:52 PM PST 24 22336953 ps
T1032 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2305004008 Feb 25 01:50:16 PM PST 24 Feb 25 01:50:16 PM PST 24 12724834 ps
T1033 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1821119182 Feb 25 01:49:27 PM PST 24 Feb 25 01:49:30 PM PST 24 355762739 ps
T1034 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.172904983 Feb 25 01:50:52 PM PST 24 Feb 25 01:50:53 PM PST 24 30184007 ps
T1035 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1020795074 Feb 25 01:50:29 PM PST 24 Feb 25 01:50:32 PM PST 24 86173811 ps
T246 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3125290905 Feb 25 01:50:31 PM PST 24 Feb 25 01:50:44 PM PST 24 536799409 ps
T116 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2097723780 Feb 25 01:49:49 PM PST 24 Feb 25 01:49:51 PM PST 24 48054609 ps
T1036 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2484674146 Feb 25 01:50:16 PM PST 24 Feb 25 01:50:18 PM PST 24 313445557 ps
T1037 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3769533986 Feb 25 01:50:51 PM PST 24 Feb 25 01:50:52 PM PST 24 13250624 ps
T251 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2748424821 Feb 25 01:49:42 PM PST 24 Feb 25 01:49:50 PM PST 24 3652870000 ps
T1038 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2735132752 Feb 25 01:50:10 PM PST 24 Feb 25 01:50:15 PM PST 24 59102555 ps
T1039 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3077964316 Feb 25 01:50:22 PM PST 24 Feb 25 01:50:23 PM PST 24 21638173 ps
T1040 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.822790809 Feb 25 01:50:23 PM PST 24 Feb 25 01:50:27 PM PST 24 1259523294 ps
T1041 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.897391506 Feb 25 01:50:54 PM PST 24 Feb 25 01:50:55 PM PST 24 66376583 ps
T256 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4005311977 Feb 25 01:50:13 PM PST 24 Feb 25 01:50:35 PM PST 24 3982451089 ps
T77 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.311103298 Feb 25 01:50:09 PM PST 24 Feb 25 01:50:11 PM PST 24 22720434 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3941190839 Feb 25 01:49:34 PM PST 24 Feb 25 01:49:38 PM PST 24 116205121 ps
T1043 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2649910095 Feb 25 01:49:55 PM PST 24 Feb 25 01:49:57 PM PST 24 71047098 ps
T1044 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2108752625 Feb 25 01:50:09 PM PST 24 Feb 25 01:50:11 PM PST 24 133404127 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1331886196 Feb 25 01:49:24 PM PST 24 Feb 25 01:49:48 PM PST 24 1800038088 ps
T1046 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.573983621 Feb 25 01:50:52 PM PST 24 Feb 25 01:50:53 PM PST 24 23606823 ps
T115 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2377810950 Feb 25 01:49:33 PM PST 24 Feb 25 01:49:35 PM PST 24 87022373 ps
T1047 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4007425108 Feb 25 01:50:11 PM PST 24 Feb 25 01:50:13 PM PST 24 71047160 ps
T1048 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1141053692 Feb 25 01:50:19 PM PST 24 Feb 25 01:50:26 PM PST 24 401328398 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1238521580 Feb 25 01:49:52 PM PST 24 Feb 25 01:50:31 PM PST 24 10262961547 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2264881528 Feb 25 01:49:52 PM PST 24 Feb 25 01:49:54 PM PST 24 123595009 ps
T1051 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.179381086 Feb 25 01:50:29 PM PST 24 Feb 25 01:50:32 PM PST 24 89808324 ps
T1052 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.552451432 Feb 25 01:50:26 PM PST 24 Feb 25 01:50:28 PM PST 24 82704444 ps
T244 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2987018320 Feb 25 01:49:35 PM PST 24 Feb 25 01:49:38 PM PST 24 123874564 ps
T1053 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.239138440 Feb 25 01:50:10 PM PST 24 Feb 25 01:50:15 PM PST 24 157978619 ps
T1054 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2413735964 Feb 25 01:50:53 PM PST 24 Feb 25 01:50:53 PM PST 24 35816288 ps
T1055 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3749076749 Feb 25 01:50:09 PM PST 24 Feb 25 01:50:41 PM PST 24 2181383485 ps
T1056 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4249679431 Feb 25 01:50:10 PM PST 24 Feb 25 01:50:12 PM PST 24 205654719 ps
T1057 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3178352463 Feb 25 01:50:49 PM PST 24 Feb 25 01:50:50 PM PST 24 20951665 ps
T1058 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4084014508 Feb 25 01:50:24 PM PST 24 Feb 25 01:50:29 PM PST 24 61576510 ps
T1059 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2159174905 Feb 25 01:49:37 PM PST 24 Feb 25 01:49:53 PM PST 24 609813805 ps
T1060 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.461930633 Feb 25 01:50:32 PM PST 24 Feb 25 01:50:38 PM PST 24 217467613 ps
T1061 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1686239582 Feb 25 01:49:54 PM PST 24 Feb 25 01:50:01 PM PST 24 713242966 ps
T1062 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2438688561 Feb 25 01:50:30 PM PST 24 Feb 25 01:50:33 PM PST 24 37020214 ps
T1063 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2162455660 Feb 25 01:50:16 PM PST 24 Feb 25 01:50:21 PM PST 24 186414477 ps
T1064 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.537206227 Feb 25 01:51:02 PM PST 24 Feb 25 01:51:03 PM PST 24 18160336 ps
T1065 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3948354368 Feb 25 01:50:18 PM PST 24 Feb 25 01:50:20 PM PST 24 26855672 ps
T1066 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2830339233 Feb 25 01:50:55 PM PST 24 Feb 25 01:50:56 PM PST 24 17073884 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3350446023 Feb 25 01:50:23 PM PST 24 Feb 25 01:50:29 PM PST 24 143680630 ps
T1068 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1368724233 Feb 25 01:49:41 PM PST 24 Feb 25 01:49:43 PM PST 24 338097920 ps
T1069 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2650344403 Feb 25 01:50:54 PM PST 24 Feb 25 01:50:55 PM PST 24 100897019 ps
T1070 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3237981150 Feb 25 01:49:52 PM PST 24 Feb 25 01:49:53 PM PST 24 21114960 ps
T1071 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1107819510 Feb 25 01:50:09 PM PST 24 Feb 25 01:50:14 PM PST 24 551861803 ps
T1072 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1506428206 Feb 25 01:50:09 PM PST 24 Feb 25 01:50:10 PM PST 24 44512956 ps
T1073 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2456836862 Feb 25 01:50:08 PM PST 24 Feb 25 01:50:10 PM PST 24 90859945 ps
T1074 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3347164291 Feb 25 01:50:34 PM PST 24 Feb 25 01:50:36 PM PST 24 197001419 ps
T1075 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2431477840 Feb 25 01:50:29 PM PST 24 Feb 25 01:50:32 PM PST 24 176744967 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2463207683 Feb 25 01:50:23 PM PST 24 Feb 25 01:50:29 PM PST 24 246220966 ps
T1077 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.684681836 Feb 25 01:49:49 PM PST 24 Feb 25 01:49:53 PM PST 24 658020526 ps
T1078 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.845189178 Feb 25 01:50:31 PM PST 24 Feb 25 01:50:37 PM PST 24 221077317 ps
T1079 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2761818454 Feb 25 01:50:54 PM PST 24 Feb 25 01:50:55 PM PST 24 26835597 ps
T1080 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3653825376 Feb 25 01:49:34 PM PST 24 Feb 25 01:49:42 PM PST 24 1089784391 ps
T1081 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1611910751 Feb 25 01:50:23 PM PST 24 Feb 25 01:50:26 PM PST 24 190194574 ps
T1082 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2160814195 Feb 25 01:50:21 PM PST 24 Feb 25 01:50:23 PM PST 24 52012446 ps
T1083 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1529796693 Feb 25 01:50:37 PM PST 24 Feb 25 01:50:40 PM PST 24 154081768 ps
T1084 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2043885981 Feb 25 01:49:21 PM PST 24 Feb 25 01:49:23 PM PST 24 57131859 ps
T1085 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1490886380 Feb 25 01:50:16 PM PST 24 Feb 25 01:50:18 PM PST 24 90338028 ps
T252 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3589548273 Feb 25 01:50:18 PM PST 24 Feb 25 01:50:43 PM PST 24 10905355167 ps
T1086 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3937552172 Feb 25 01:50:54 PM PST 24 Feb 25 01:50:55 PM PST 24 22381564 ps
T247 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3041128818 Feb 25 01:50:32 PM PST 24 Feb 25 01:50:55 PM PST 24 1029419722 ps
T1087 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1444541625 Feb 25 01:50:36 PM PST 24 Feb 25 01:50:39 PM PST 24 569603390 ps
T78 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1216960078 Feb 25 01:49:32 PM PST 24 Feb 25 01:49:34 PM PST 24 33962583 ps
T1088 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1918254505 Feb 25 01:50:30 PM PST 24 Feb 25 01:50:33 PM PST 24 384071981 ps
T1089 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3869723743 Feb 25 01:50:22 PM PST 24 Feb 25 01:50:24 PM PST 24 78733577 ps
T1090 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3717315087 Feb 25 01:50:44 PM PST 24 Feb 25 01:50:47 PM PST 24 46867730 ps
T1091 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3574492528 Feb 25 01:50:09 PM PST 24 Feb 25 01:50:12 PM PST 24 80654488 ps
T1092 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.916150969 Feb 25 01:49:49 PM PST 24 Feb 25 01:49:54 PM PST 24 163328649 ps
T1093 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4115282872 Feb 25 01:50:41 PM PST 24 Feb 25 01:50:43 PM PST 24 130471096 ps
T1094 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1483939070 Feb 25 01:50:51 PM PST 24 Feb 25 01:50:52 PM PST 24 42516821 ps
T1095 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2136724780 Feb 25 01:50:23 PM PST 24 Feb 25 01:50:29 PM PST 24 325528667 ps
T1096 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3034667750 Feb 25 01:50:22 PM PST 24 Feb 25 01:50:30 PM PST 24 1191200280 ps
T1097 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1047279563 Feb 25 01:49:18 PM PST 24 Feb 25 01:49:21 PM PST 24 86004508 ps
T1098 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4207185703 Feb 25 01:50:23 PM PST 24 Feb 25 01:50:46 PM PST 24 1005306798 ps
T1099 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1801535747 Feb 25 01:50:50 PM PST 24 Feb 25 01:50:52 PM PST 24 12139303 ps
T1100 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2154660946 Feb 25 01:49:41 PM PST 24 Feb 25 01:49:49 PM PST 24 104909261 ps
T1101 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.617279239 Feb 25 01:49:20 PM PST 24 Feb 25 01:49:22 PM PST 24 291776123 ps
T1102 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.960554583 Feb 25 01:50:27 PM PST 24 Feb 25 01:50:28 PM PST 24 33681374 ps
T1103 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3850932999 Feb 25 01:50:53 PM PST 24 Feb 25 01:50:53 PM PST 24 29922163 ps
T1104 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.479055981 Feb 25 01:50:32 PM PST 24 Feb 25 01:50:45 PM PST 24 640751410 ps
T1105 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2264960949 Feb 25 01:50:31 PM PST 24 Feb 25 01:50:37 PM PST 24 341238917 ps
T1106 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1600229243 Feb 25 01:50:22 PM PST 24 Feb 25 01:50:24 PM PST 24 927615201 ps
T1107 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.334302592 Feb 25 01:49:28 PM PST 24 Feb 25 01:49:30 PM PST 24 20893459 ps
T1108 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2466027972 Feb 25 01:49:33 PM PST 24 Feb 25 01:49:34 PM PST 24 21640618 ps
T1109 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3047412145 Feb 25 01:49:43 PM PST 24 Feb 25 01:49:44 PM PST 24 14105893 ps
T1110 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2062278193 Feb 25 01:49:26 PM PST 24 Feb 25 01:49:50 PM PST 24 31136785381 ps
T1111 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1478860095 Feb 25 01:50:31 PM PST 24 Feb 25 01:50:35 PM PST 24 60007381 ps

Test location /workspace/coverage/default/27.spi_device_stress_all.1674088301
Short name T2
Test name
Test status
Simulation time 73543094916 ps
CPU time 438.51 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:51:35 PM PST 24
Peak memory 253272 kb
Host smart-dd4c5661-bdb8-40d0-9d6f-8c8b046a0a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674088301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1674088301
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.331674633
Short name T26
Test name
Test status
Simulation time 4641155199 ps
CPU time 36.38 seconds
Started Feb 25 02:42:52 PM PST 24
Finished Feb 25 02:43:29 PM PST 24
Peak memory 222964 kb
Host smart-b531877e-2e51-4ce9-9e64-b46d5e2d56e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331674633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
331674633
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3779463182
Short name T29
Test name
Test status
Simulation time 16096491504 ps
CPU time 201 seconds
Started Feb 25 02:44:00 PM PST 24
Finished Feb 25 02:47:22 PM PST 24
Peak memory 253408 kb
Host smart-806f4d08-2fab-484d-9a06-a8f8d1537684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779463182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3779463182
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1870964109
Short name T90
Test name
Test status
Simulation time 3876252439 ps
CPU time 19.92 seconds
Started Feb 25 01:50:35 PM PST 24
Finished Feb 25 01:50:55 PM PST 24
Peak memory 216764 kb
Host smart-87fda310-b3cb-4da8-b3d2-acfb705524fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870964109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1870964109
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1834268327
Short name T154
Test name
Test status
Simulation time 133131541450 ps
CPU time 301.96 seconds
Started Feb 25 02:44:52 PM PST 24
Finished Feb 25 02:49:55 PM PST 24
Peak memory 271752 kb
Host smart-d269d170-e5bb-4555-b785-0bfe1d41a0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834268327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1834268327
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3587179889
Short name T51
Test name
Test status
Simulation time 904689448202 ps
CPU time 1041.4 seconds
Started Feb 25 02:45:14 PM PST 24
Finished Feb 25 03:02:35 PM PST 24
Peak memory 287632 kb
Host smart-365581ca-8c4b-4462-8024-484386d1cf3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587179889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3587179889
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.925668208
Short name T462
Test name
Test status
Simulation time 17033663 ps
CPU time 0.74 seconds
Started Feb 25 02:43:07 PM PST 24
Finished Feb 25 02:43:08 PM PST 24
Peak memory 215712 kb
Host smart-acfdc8c5-0ea7-489c-9aae-7dba67d97114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925668208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.925668208
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.280167825
Short name T16
Test name
Test status
Simulation time 57606021187 ps
CPU time 398.91 seconds
Started Feb 25 02:44:19 PM PST 24
Finished Feb 25 02:50:59 PM PST 24
Peak memory 260744 kb
Host smart-13593045-f7fc-498b-881b-999b2ed917b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280167825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.280167825
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1265577251
Short name T122
Test name
Test status
Simulation time 348699337308 ps
CPU time 632.75 seconds
Started Feb 25 02:42:59 PM PST 24
Finished Feb 25 02:53:32 PM PST 24
Peak memory 265168 kb
Host smart-d99d068b-676b-482e-a008-7290bc5bc620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265577251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1265577251
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2822841716
Short name T94
Test name
Test status
Simulation time 45493888 ps
CPU time 3.56 seconds
Started Feb 25 01:50:40 PM PST 24
Finished Feb 25 01:50:44 PM PST 24
Peak memory 215532 kb
Host smart-56ec36cb-3ae2-4010-96b4-4ed57b83e2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822841716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2822841716
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1970309341
Short name T41
Test name
Test status
Simulation time 103572758 ps
CPU time 1.17 seconds
Started Feb 25 02:43:04 PM PST 24
Finished Feb 25 02:43:06 PM PST 24
Peak memory 235116 kb
Host smart-353a8da0-9ba3-4128-933f-8cac5f4533f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970309341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1970309341
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2843507724
Short name T126
Test name
Test status
Simulation time 17353700444 ps
CPU time 33.24 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:44 PM PST 24
Peak memory 242464 kb
Host smart-156cb42d-039a-481c-8f58-3dc25888d42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843507724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2843507724
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4088144564
Short name T136
Test name
Test status
Simulation time 17257438937 ps
CPU time 181.39 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:46:34 PM PST 24
Peak memory 266240 kb
Host smart-1299d3eb-943d-4096-8494-0659d408d78c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088144564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4088144564
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3346023526
Short name T155
Test name
Test status
Simulation time 8225590972 ps
CPU time 68.36 seconds
Started Feb 25 02:43:13 PM PST 24
Finished Feb 25 02:44:21 PM PST 24
Peak memory 248680 kb
Host smart-dfa495d9-40c8-4372-b420-0043116ebb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346023526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3346023526
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.428465511
Short name T114
Test name
Test status
Simulation time 71860907 ps
CPU time 1.18 seconds
Started Feb 25 01:49:26 PM PST 24
Finished Feb 25 01:49:28 PM PST 24
Peak memory 207000 kb
Host smart-bab30689-8a34-4a03-84dd-7cbf80f004b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428465511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.428465511
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4134450386
Short name T27
Test name
Test status
Simulation time 300254735699 ps
CPU time 294.37 seconds
Started Feb 25 02:44:34 PM PST 24
Finished Feb 25 02:49:29 PM PST 24
Peak memory 265532 kb
Host smart-ef7f2990-efbc-4074-8dfa-f7830278f315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134450386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4134450386
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3876678917
Short name T229
Test name
Test status
Simulation time 775317858657 ps
CPU time 521.49 seconds
Started Feb 25 02:42:51 PM PST 24
Finished Feb 25 02:51:33 PM PST 24
Peak memory 260596 kb
Host smart-ae851ced-4888-4b8e-9cc1-697df7903805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876678917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3876678917
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3522890209
Short name T22
Test name
Test status
Simulation time 92358719 ps
CPU time 1.1 seconds
Started Feb 25 02:42:51 PM PST 24
Finished Feb 25 02:42:53 PM PST 24
Peak memory 216132 kb
Host smart-6cfe149c-1efc-4ce4-9183-bbca9292e775
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522890209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3522890209
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1512984362
Short name T204
Test name
Test status
Simulation time 453139821628 ps
CPU time 527.15 seconds
Started Feb 25 02:42:45 PM PST 24
Finished Feb 25 02:51:33 PM PST 24
Peak memory 266464 kb
Host smart-be01b02f-33b9-45af-83c4-3223eb0d0e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512984362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1512984362
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1323617851
Short name T8
Test name
Test status
Simulation time 13096256108 ps
CPU time 64.44 seconds
Started Feb 25 02:43:48 PM PST 24
Finished Feb 25 02:44:53 PM PST 24
Peak memory 265124 kb
Host smart-f2cdedd0-e5a6-44c8-b2c5-03478d8d34b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323617851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1323617851
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1708412001
Short name T217
Test name
Test status
Simulation time 166900197105 ps
CPU time 269.75 seconds
Started Feb 25 02:43:26 PM PST 24
Finished Feb 25 02:47:55 PM PST 24
Peak memory 265532 kb
Host smart-18f3e5d0-3831-43dc-b338-a63cb7f180aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708412001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1708412001
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.373612132
Short name T202
Test name
Test status
Simulation time 65412914188 ps
CPU time 147.86 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:45:57 PM PST 24
Peak memory 272244 kb
Host smart-ca16660f-8d0a-4107-bb36-b4193bc3279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373612132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
373612132
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4211994357
Short name T33
Test name
Test status
Simulation time 69256916 ps
CPU time 0.7 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:31 PM PST 24
Peak memory 203968 kb
Host smart-a87a6106-e10c-4bff-be82-a31e9366b07b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211994357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4211994357
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.891244455
Short name T135
Test name
Test status
Simulation time 44528561074 ps
CPU time 304.86 seconds
Started Feb 25 02:43:53 PM PST 24
Finished Feb 25 02:48:58 PM PST 24
Peak memory 272368 kb
Host smart-25f30eef-6f6e-4aec-9fb4-f070ac079c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891244455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.891244455
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.511197811
Short name T18
Test name
Test status
Simulation time 270106729638 ps
CPU time 333.27 seconds
Started Feb 25 02:44:05 PM PST 24
Finished Feb 25 02:49:40 PM PST 24
Peak memory 256176 kb
Host smart-e792de76-c69f-46a1-bf40-c4f762bcfa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511197811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.511197811
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1559337258
Short name T298
Test name
Test status
Simulation time 4781744919 ps
CPU time 11.52 seconds
Started Feb 25 02:42:48 PM PST 24
Finished Feb 25 02:43:00 PM PST 24
Peak memory 215856 kb
Host smart-764fdcc4-1d6d-4745-98b5-800b3a57bf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559337258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1559337258
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.117100321
Short name T171
Test name
Test status
Simulation time 20960865269 ps
CPU time 77.37 seconds
Started Feb 25 02:44:20 PM PST 24
Finished Feb 25 02:45:38 PM PST 24
Peak memory 265052 kb
Host smart-ece0ebc4-912d-4165-9f55-f008924f398a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117100321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.117100321
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4005311977
Short name T256
Test name
Test status
Simulation time 3982451089 ps
CPU time 22.07 seconds
Started Feb 25 01:50:13 PM PST 24
Finished Feb 25 01:50:35 PM PST 24
Peak memory 215524 kb
Host smart-525b7522-f147-4747-aa34-5dd80d0d7d01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005311977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4005311977
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1571329153
Short name T213
Test name
Test status
Simulation time 41141412083 ps
CPU time 249.97 seconds
Started Feb 25 02:43:32 PM PST 24
Finished Feb 25 02:47:42 PM PST 24
Peak memory 273092 kb
Host smart-e8ae8ed7-4920-478d-94e9-6df7652e53ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571329153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1571329153
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3892651148
Short name T293
Test name
Test status
Simulation time 2761262769 ps
CPU time 38.51 seconds
Started Feb 25 02:43:49 PM PST 24
Finished Feb 25 02:44:28 PM PST 24
Peak memory 215896 kb
Host smart-18e95fbf-5622-4068-acb7-342321bd100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892651148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3892651148
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1240202576
Short name T206
Test name
Test status
Simulation time 164973361563 ps
CPU time 678.17 seconds
Started Feb 25 02:45:28 PM PST 24
Finished Feb 25 02:56:47 PM PST 24
Peak memory 282440 kb
Host smart-db95b935-1434-4f5d-9aaa-e9db364af6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240202576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1240202576
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.17224029
Short name T972
Test name
Test status
Simulation time 91009216527 ps
CPU time 189.76 seconds
Started Feb 25 02:43:22 PM PST 24
Finished Feb 25 02:46:31 PM PST 24
Peak memory 272988 kb
Host smart-eefa76b5-d37a-4b6d-95e9-8794fad2aef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17224029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.17224029
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1701928282
Short name T570
Test name
Test status
Simulation time 2689119321 ps
CPU time 17.18 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:42 PM PST 24
Peak memory 233372 kb
Host smart-e18dc555-6479-4d72-a3db-bf8ded349512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701928282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1701928282
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2948273963
Short name T172
Test name
Test status
Simulation time 284929872552 ps
CPU time 469.69 seconds
Started Feb 25 02:44:12 PM PST 24
Finished Feb 25 02:52:02 PM PST 24
Peak memory 270444 kb
Host smart-7afc1ca7-e064-4887-ac88-d0359143e902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948273963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2948273963
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3087988189
Short name T30
Test name
Test status
Simulation time 81543912301 ps
CPU time 183.84 seconds
Started Feb 25 02:43:08 PM PST 24
Finished Feb 25 02:46:12 PM PST 24
Peak memory 252120 kb
Host smart-c235bde8-0a10-4fa0-978b-2b09cab6c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087988189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3087988189
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1772991483
Short name T98
Test name
Test status
Simulation time 995261291 ps
CPU time 2.76 seconds
Started Feb 25 01:50:49 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 215496 kb
Host smart-9d2f70ef-4e03-4081-9aa1-3e232695bc77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772991483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1772991483
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1045583051
Short name T79
Test name
Test status
Simulation time 2581969155 ps
CPU time 39.25 seconds
Started Feb 25 02:43:35 PM PST 24
Finished Feb 25 02:44:15 PM PST 24
Peak memory 248768 kb
Host smart-12265e1e-3251-4b13-9001-d587cb3a9f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045583051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1045583051
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1368116349
Short name T245
Test name
Test status
Simulation time 2204780079 ps
CPU time 20.77 seconds
Started Feb 25 01:50:31 PM PST 24
Finished Feb 25 01:50:51 PM PST 24
Peak memory 215596 kb
Host smart-0d1b7b63-2425-4351-a70f-db422debf520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368116349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1368116349
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3585727962
Short name T448
Test name
Test status
Simulation time 29229622299 ps
CPU time 20.18 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:43:48 PM PST 24
Peak memory 218476 kb
Host smart-3d60c58a-ca00-4bb7-ae56-81877135cbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585727962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3585727962
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1291703796
Short name T143
Test name
Test status
Simulation time 10179306153 ps
CPU time 153.19 seconds
Started Feb 25 02:43:35 PM PST 24
Finished Feb 25 02:46:08 PM PST 24
Peak memory 267500 kb
Host smart-cd3eaf74-ca73-4149-b85a-2fbaee3edfa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291703796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1291703796
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1131076156
Short name T658
Test name
Test status
Simulation time 14280252374 ps
CPU time 35.48 seconds
Started Feb 25 02:43:26 PM PST 24
Finished Feb 25 02:44:01 PM PST 24
Peak memory 240532 kb
Host smart-989db9c5-338c-4404-9380-b2da7b348cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131076156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1131076156
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4032934605
Short name T232
Test name
Test status
Simulation time 54242643279 ps
CPU time 59.09 seconds
Started Feb 25 02:44:08 PM PST 24
Finished Feb 25 02:45:09 PM PST 24
Peak memory 256944 kb
Host smart-a7ed73bb-3b74-44d6-be71-d59532e85506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032934605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4032934605
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2884260156
Short name T226
Test name
Test status
Simulation time 247237545184 ps
CPU time 248.85 seconds
Started Feb 25 02:44:18 PM PST 24
Finished Feb 25 02:48:27 PM PST 24
Peak memory 268576 kb
Host smart-432a7094-17c1-461c-9a45-909bf6ce1141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884260156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2884260156
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1995037799
Short name T222
Test name
Test status
Simulation time 328664683850 ps
CPU time 649.2 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:55:05 PM PST 24
Peak memory 282328 kb
Host smart-10fe32b0-7bef-4cb6-88a9-7a5afd989e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995037799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1995037799
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.66483332
Short name T212
Test name
Test status
Simulation time 6643174722 ps
CPU time 118.58 seconds
Started Feb 25 02:44:58 PM PST 24
Finished Feb 25 02:46:57 PM PST 24
Peak memory 264972 kb
Host smart-ed01282b-31ad-4a74-8189-baa40ce8210c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66483332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.66483332
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.490567241
Short name T85
Test name
Test status
Simulation time 25813015729 ps
CPU time 23.17 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:48 PM PST 24
Peak memory 218392 kb
Host smart-1be3c78d-2116-4ca9-bb3e-7ebfe9711c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490567241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.490567241
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.493510279
Short name T97
Test name
Test status
Simulation time 85147755 ps
CPU time 1.57 seconds
Started Feb 25 01:49:26 PM PST 24
Finished Feb 25 01:49:28 PM PST 24
Peak memory 215616 kb
Host smart-ec3a85a3-c393-42f7-a6c8-1f43946d3053
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493510279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.493510279
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1216960078
Short name T78
Test name
Test status
Simulation time 33962583 ps
CPU time 1.21 seconds
Started Feb 25 01:49:32 PM PST 24
Finished Feb 25 01:49:34 PM PST 24
Peak memory 207076 kb
Host smart-af64f76c-965b-431e-96b5-f53c35a76cb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216960078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1216960078
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1331886196
Short name T1045
Test name
Test status
Simulation time 1800038088 ps
CPU time 23.59 seconds
Started Feb 25 01:49:24 PM PST 24
Finished Feb 25 01:49:48 PM PST 24
Peak memory 207148 kb
Host smart-b61b1c6b-462e-4e5c-bfef-bbb050edf0a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331886196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1331886196
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2062278193
Short name T1110
Test name
Test status
Simulation time 31136785381 ps
CPU time 24.06 seconds
Started Feb 25 01:49:26 PM PST 24
Finished Feb 25 01:49:50 PM PST 24
Peak memory 207108 kb
Host smart-d3469541-5834-48a6-9464-bd4910948f70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062278193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2062278193
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1694975903
Short name T996
Test name
Test status
Simulation time 74656100 ps
CPU time 2.48 seconds
Started Feb 25 01:49:27 PM PST 24
Finished Feb 25 01:49:30 PM PST 24
Peak memory 216512 kb
Host smart-f835dbd2-6f1a-4455-9df6-96b949a2c1b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694975903 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1694975903
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.617279239
Short name T1101
Test name
Test status
Simulation time 291776123 ps
CPU time 1.94 seconds
Started Feb 25 01:49:20 PM PST 24
Finished Feb 25 01:49:22 PM PST 24
Peak memory 207052 kb
Host smart-2f6dfb4d-8f03-480b-8cbb-abd2ea76969a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617279239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.617279239
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1467473592
Short name T994
Test name
Test status
Simulation time 19445839 ps
CPU time 0.71 seconds
Started Feb 25 01:49:26 PM PST 24
Finished Feb 25 01:49:27 PM PST 24
Peak memory 203400 kb
Host smart-f4c525df-144f-42ba-ae45-02861fd27416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467473592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
467473592
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2043885981
Short name T1084
Test name
Test status
Simulation time 57131859 ps
CPU time 1.63 seconds
Started Feb 25 01:49:21 PM PST 24
Finished Feb 25 01:49:23 PM PST 24
Peak memory 215404 kb
Host smart-1d40f588-7575-41c7-a0bf-cd0f19161540
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043885981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2043885981
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.334302592
Short name T1107
Test name
Test status
Simulation time 20893459 ps
CPU time 0.67 seconds
Started Feb 25 01:49:28 PM PST 24
Finished Feb 25 01:49:30 PM PST 24
Peak memory 203056 kb
Host smart-81294f66-9197-4a13-b898-af3f7264a739
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334302592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.334302592
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1047279563
Short name T1097
Test name
Test status
Simulation time 86004508 ps
CPU time 2.92 seconds
Started Feb 25 01:49:18 PM PST 24
Finished Feb 25 01:49:21 PM PST 24
Peak memory 207240 kb
Host smart-a34bba53-5f66-4e40-8575-cf5d370ab173
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047279563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1047279563
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2509247953
Short name T88
Test name
Test status
Simulation time 3179850042 ps
CPU time 22.02 seconds
Started Feb 25 01:49:22 PM PST 24
Finished Feb 25 01:49:44 PM PST 24
Peak memory 215540 kb
Host smart-afa063fb-ba03-453d-829d-82cdc3214f2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509247953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2509247953
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2159174905
Short name T1059
Test name
Test status
Simulation time 609813805 ps
CPU time 15.66 seconds
Started Feb 25 01:49:37 PM PST 24
Finished Feb 25 01:49:53 PM PST 24
Peak memory 215328 kb
Host smart-a6c2576f-384a-4399-bfb6-58a0fc1d48e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159174905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2159174905
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.546460507
Short name T1013
Test name
Test status
Simulation time 390206605 ps
CPU time 23.53 seconds
Started Feb 25 01:49:36 PM PST 24
Finished Feb 25 01:50:00 PM PST 24
Peak memory 207136 kb
Host smart-247a748c-1070-403d-aead-02b3bf22de41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546460507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.546460507
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3941190839
Short name T1042
Test name
Test status
Simulation time 116205121 ps
CPU time 3.02 seconds
Started Feb 25 01:49:34 PM PST 24
Finished Feb 25 01:49:38 PM PST 24
Peak memory 216528 kb
Host smart-6114c7ed-038d-4cd9-8c5a-5f40fb8478fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941190839 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3941190839
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2377810950
Short name T115
Test name
Test status
Simulation time 87022373 ps
CPU time 1.71 seconds
Started Feb 25 01:49:33 PM PST 24
Finished Feb 25 01:49:35 PM PST 24
Peak memory 215324 kb
Host smart-3fb832b2-b8e3-4c03-939d-276a4567611b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377810950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
377810950
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3126702113
Short name T1024
Test name
Test status
Simulation time 11300600 ps
CPU time 0.69 seconds
Started Feb 25 01:49:35 PM PST 24
Finished Feb 25 01:49:36 PM PST 24
Peak memory 203328 kb
Host smart-3543accd-6a17-428d-826a-f01705d7754c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126702113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
126702113
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1703692751
Short name T105
Test name
Test status
Simulation time 80970635 ps
CPU time 1.7 seconds
Started Feb 25 01:49:35 PM PST 24
Finished Feb 25 01:49:37 PM PST 24
Peak memory 215368 kb
Host smart-cf47be33-bb3e-43a2-b39e-de58de83d0de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703692751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1703692751
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3075204789
Short name T985
Test name
Test status
Simulation time 29950263 ps
CPU time 0.61 seconds
Started Feb 25 01:49:33 PM PST 24
Finished Feb 25 01:49:34 PM PST 24
Peak memory 203368 kb
Host smart-b9e067d4-1917-42d4-93c7-f2623f106e22
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075204789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3075204789
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3186936016
Short name T990
Test name
Test status
Simulation time 163470342 ps
CPU time 4.3 seconds
Started Feb 25 01:49:34 PM PST 24
Finished Feb 25 01:49:38 PM PST 24
Peak memory 207464 kb
Host smart-a152791a-3fce-416f-90ee-092dbd88cecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186936016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3186936016
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1821119182
Short name T1033
Test name
Test status
Simulation time 355762739 ps
CPU time 2.61 seconds
Started Feb 25 01:49:27 PM PST 24
Finished Feb 25 01:49:30 PM PST 24
Peak memory 215576 kb
Host smart-6795882e-9756-46de-8627-f84136ead7cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821119182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
821119182
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2903921185
Short name T250
Test name
Test status
Simulation time 424202033 ps
CPU time 6.46 seconds
Started Feb 25 01:49:35 PM PST 24
Finished Feb 25 01:49:41 PM PST 24
Peak memory 215396 kb
Host smart-163943fc-d876-4540-aa1e-c15c87cd1b09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903921185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2903921185
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2463207683
Short name T1076
Test name
Test status
Simulation time 246220966 ps
CPU time 5.9 seconds
Started Feb 25 01:50:23 PM PST 24
Finished Feb 25 01:50:29 PM PST 24
Peak memory 217916 kb
Host smart-ccda97e8-0ea9-443e-9dce-f8d40d2f6a5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463207683 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2463207683
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.28175415
Short name T109
Test name
Test status
Simulation time 76146362 ps
CPU time 2.06 seconds
Started Feb 25 01:50:28 PM PST 24
Finished Feb 25 01:50:31 PM PST 24
Peak memory 215348 kb
Host smart-2a3b959e-394e-4a0f-9533-96380f6a0662
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28175415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.28175415
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.960554583
Short name T1102
Test name
Test status
Simulation time 33681374 ps
CPU time 0.7 seconds
Started Feb 25 01:50:27 PM PST 24
Finished Feb 25 01:50:28 PM PST 24
Peak memory 203396 kb
Host smart-08d28a78-f2f1-4dc7-9c18-c0971d3aa237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960554583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.960554583
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1283243165
Short name T1009
Test name
Test status
Simulation time 109030361 ps
CPU time 1.76 seconds
Started Feb 25 01:50:22 PM PST 24
Finished Feb 25 01:50:24 PM PST 24
Peak memory 215164 kb
Host smart-4d963479-7dc6-40be-8111-60776b05ca84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283243165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1283243165
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1600229243
Short name T1106
Test name
Test status
Simulation time 927615201 ps
CPU time 1.76 seconds
Started Feb 25 01:50:22 PM PST 24
Finished Feb 25 01:50:24 PM PST 24
Peak memory 215544 kb
Host smart-84a0b03b-33ee-4302-b40d-4f45c98c6933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600229243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1600229243
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3125290905
Short name T246
Test name
Test status
Simulation time 536799409 ps
CPU time 12.55 seconds
Started Feb 25 01:50:31 PM PST 24
Finished Feb 25 01:50:44 PM PST 24
Peak memory 215412 kb
Host smart-1022236d-3a92-4894-9ad2-1e99dc956e50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125290905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3125290905
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2136724780
Short name T1095
Test name
Test status
Simulation time 325528667 ps
CPU time 5.99 seconds
Started Feb 25 01:50:23 PM PST 24
Finished Feb 25 01:50:29 PM PST 24
Peak memory 218644 kb
Host smart-7e1efbe6-2808-45ad-bfc1-e4de4cde2858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136724780 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2136724780
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2160814195
Short name T1082
Test name
Test status
Simulation time 52012446 ps
CPU time 1.42 seconds
Started Feb 25 01:50:21 PM PST 24
Finished Feb 25 01:50:23 PM PST 24
Peak memory 215324 kb
Host smart-b88d092d-1508-44be-b558-bcb5093aaed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160814195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2160814195
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1734617461
Short name T1019
Test name
Test status
Simulation time 31351829 ps
CPU time 0.73 seconds
Started Feb 25 01:50:31 PM PST 24
Finished Feb 25 01:50:32 PM PST 24
Peak memory 202840 kb
Host smart-19469634-69fa-42e3-a52f-ae65e985b0c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734617461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1734617461
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1020795074
Short name T1035
Test name
Test status
Simulation time 86173811 ps
CPU time 2.84 seconds
Started Feb 25 01:50:29 PM PST 24
Finished Feb 25 01:50:32 PM PST 24
Peak memory 215432 kb
Host smart-7022368b-bff3-4ec6-834b-b790f04aff5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020795074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1020795074
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2870734427
Short name T95
Test name
Test status
Simulation time 160752462 ps
CPU time 2.81 seconds
Started Feb 25 01:50:26 PM PST 24
Finished Feb 25 01:50:29 PM PST 24
Peak memory 215748 kb
Host smart-dc11f4ca-f473-4b63-a124-534468e4d4ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870734427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2870734427
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3350446023
Short name T1067
Test name
Test status
Simulation time 143680630 ps
CPU time 5.81 seconds
Started Feb 25 01:50:23 PM PST 24
Finished Feb 25 01:50:29 PM PST 24
Peak memory 217744 kb
Host smart-dec41b3c-63ed-4509-8b59-48980c5676ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350446023 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3350446023
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2431477840
Short name T1075
Test name
Test status
Simulation time 176744967 ps
CPU time 2.48 seconds
Started Feb 25 01:50:29 PM PST 24
Finished Feb 25 01:50:32 PM PST 24
Peak memory 207184 kb
Host smart-94525148-db22-4a7e-a3cb-ae0a100481dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431477840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2431477840
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1204431214
Short name T1016
Test name
Test status
Simulation time 23786086 ps
CPU time 0.71 seconds
Started Feb 25 01:50:29 PM PST 24
Finished Feb 25 01:50:30 PM PST 24
Peak memory 203092 kb
Host smart-b45042be-85e8-4387-8304-f3cac815d8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204431214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1204431214
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1478860095
Short name T1111
Test name
Test status
Simulation time 60007381 ps
CPU time 3.99 seconds
Started Feb 25 01:50:31 PM PST 24
Finished Feb 25 01:50:35 PM PST 24
Peak memory 215300 kb
Host smart-cbc75673-9927-4466-b8c9-a64cbf7d46e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478860095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1478860095
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4084014508
Short name T1058
Test name
Test status
Simulation time 61576510 ps
CPU time 4.26 seconds
Started Feb 25 01:50:24 PM PST 24
Finished Feb 25 01:50:29 PM PST 24
Peak memory 215496 kb
Host smart-7b6ae1da-9f16-4be6-9901-77e4b11c4948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084014508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4084014508
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3034667750
Short name T1096
Test name
Test status
Simulation time 1191200280 ps
CPU time 7.98 seconds
Started Feb 25 01:50:22 PM PST 24
Finished Feb 25 01:50:30 PM PST 24
Peak memory 215444 kb
Host smart-1f09fc4c-99ad-4f2d-9943-91509bc0c7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034667750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3034667750
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.845189178
Short name T1078
Test name
Test status
Simulation time 221077317 ps
CPU time 6.46 seconds
Started Feb 25 01:50:31 PM PST 24
Finished Feb 25 01:50:37 PM PST 24
Peak memory 216876 kb
Host smart-335d1d68-27bf-4d36-85cc-032be870a808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845189178 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.845189178
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3869723743
Short name T1089
Test name
Test status
Simulation time 78733577 ps
CPU time 2.03 seconds
Started Feb 25 01:50:22 PM PST 24
Finished Feb 25 01:50:24 PM PST 24
Peak memory 215332 kb
Host smart-8ff05c55-6afe-4303-981f-d54d5741a0f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869723743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3869723743
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3686277198
Short name T981
Test name
Test status
Simulation time 18447549 ps
CPU time 0.79 seconds
Started Feb 25 01:50:27 PM PST 24
Finished Feb 25 01:50:28 PM PST 24
Peak memory 203120 kb
Host smart-a54b56eb-0d40-46b2-b774-b05cc3cc4746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686277198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3686277198
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.552451432
Short name T1052
Test name
Test status
Simulation time 82704444 ps
CPU time 1.91 seconds
Started Feb 25 01:50:26 PM PST 24
Finished Feb 25 01:50:28 PM PST 24
Peak memory 215244 kb
Host smart-128c3cc6-a866-4531-a603-089e2e51f211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552451432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.552451432
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.822790809
Short name T1040
Test name
Test status
Simulation time 1259523294 ps
CPU time 3.36 seconds
Started Feb 25 01:50:23 PM PST 24
Finished Feb 25 01:50:27 PM PST 24
Peak memory 215432 kb
Host smart-73cd0d37-e692-4c1f-9039-cd4597c63376
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822790809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.822790809
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1803343782
Short name T248
Test name
Test status
Simulation time 838935717 ps
CPU time 20.89 seconds
Started Feb 25 01:50:31 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 215480 kb
Host smart-5fadebfc-08fd-4fe1-9096-970284b0c892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803343782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1803343782
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2264960949
Short name T1105
Test name
Test status
Simulation time 341238917 ps
CPU time 5.39 seconds
Started Feb 25 01:50:31 PM PST 24
Finished Feb 25 01:50:37 PM PST 24
Peak memory 217264 kb
Host smart-713eefb5-65bd-45ac-bb06-86d657dc43b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264960949 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2264960949
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2605245308
Short name T111
Test name
Test status
Simulation time 115319764 ps
CPU time 2.87 seconds
Started Feb 25 01:50:23 PM PST 24
Finished Feb 25 01:50:26 PM PST 24
Peak memory 207240 kb
Host smart-47dcc54c-d9bf-4742-a01d-b97ec3163d4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605245308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2605245308
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3077964316
Short name T1039
Test name
Test status
Simulation time 21638173 ps
CPU time 0.72 seconds
Started Feb 25 01:50:22 PM PST 24
Finished Feb 25 01:50:23 PM PST 24
Peak memory 203440 kb
Host smart-bfe60b38-98ab-48c4-b5ff-899109f830ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077964316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3077964316
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1444541625
Short name T1087
Test name
Test status
Simulation time 569603390 ps
CPU time 3.01 seconds
Started Feb 25 01:50:36 PM PST 24
Finished Feb 25 01:50:39 PM PST 24
Peak memory 207276 kb
Host smart-88b4be52-bc0b-4674-b9a0-f9b537b4b6f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444541625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1444541625
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2333459835
Short name T1006
Test name
Test status
Simulation time 63347949 ps
CPU time 2.46 seconds
Started Feb 25 01:50:24 PM PST 24
Finished Feb 25 01:50:26 PM PST 24
Peak memory 215548 kb
Host smart-4938682b-ff59-4fb3-afeb-c3f31934b8c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333459835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2333459835
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4207185703
Short name T1098
Test name
Test status
Simulation time 1005306798 ps
CPU time 22.9 seconds
Started Feb 25 01:50:23 PM PST 24
Finished Feb 25 01:50:46 PM PST 24
Peak memory 215484 kb
Host smart-0dae9df5-ade9-4974-a595-7ef4e2eddece
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207185703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4207185703
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.461930633
Short name T1060
Test name
Test status
Simulation time 217467613 ps
CPU time 6.6 seconds
Started Feb 25 01:50:32 PM PST 24
Finished Feb 25 01:50:38 PM PST 24
Peak memory 219120 kb
Host smart-bfa18b3a-d4b8-474e-93e3-5c3d7ccd9b29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461930633 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.461930633
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3347164291
Short name T1074
Test name
Test status
Simulation time 197001419 ps
CPU time 1.45 seconds
Started Feb 25 01:50:34 PM PST 24
Finished Feb 25 01:50:36 PM PST 24
Peak memory 207040 kb
Host smart-8930e763-78db-4696-a601-a9040263a82c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347164291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3347164291
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3631176888
Short name T1011
Test name
Test status
Simulation time 82357558 ps
CPU time 0.73 seconds
Started Feb 25 01:50:31 PM PST 24
Finished Feb 25 01:50:32 PM PST 24
Peak memory 202960 kb
Host smart-26bcd9e4-01c9-4715-917b-8b1c84d7ebaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631176888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3631176888
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4115282872
Short name T1093
Test name
Test status
Simulation time 130471096 ps
CPU time 1.71 seconds
Started Feb 25 01:50:41 PM PST 24
Finished Feb 25 01:50:43 PM PST 24
Peak memory 215100 kb
Host smart-a3bc554c-b6ad-4554-bc1f-c8a6cdec64ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115282872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4115282872
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.132472127
Short name T86
Test name
Test status
Simulation time 82322990 ps
CPU time 3.04 seconds
Started Feb 25 01:50:30 PM PST 24
Finished Feb 25 01:50:33 PM PST 24
Peak memory 215540 kb
Host smart-7f557ec3-342e-4b90-a248-12fd727500bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132472127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.132472127
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3041128818
Short name T247
Test name
Test status
Simulation time 1029419722 ps
CPU time 22.97 seconds
Started Feb 25 01:50:32 PM PST 24
Finished Feb 25 01:50:55 PM PST 24
Peak memory 215404 kb
Host smart-daaddc51-2e97-48f0-9b3a-eb9ed6a8f87d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041128818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3041128818
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3558805504
Short name T1030
Test name
Test status
Simulation time 272381963 ps
CPU time 5.56 seconds
Started Feb 25 01:50:40 PM PST 24
Finished Feb 25 01:50:46 PM PST 24
Peak memory 217548 kb
Host smart-5edde33a-97a6-4881-b28c-60f074c5271e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558805504 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3558805504
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2002446263
Short name T991
Test name
Test status
Simulation time 291684467 ps
CPU time 1.19 seconds
Started Feb 25 01:50:42 PM PST 24
Finished Feb 25 01:50:43 PM PST 24
Peak memory 207000 kb
Host smart-6fea8d83-9447-43ae-9626-ae08a6d9df8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002446263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2002446263
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1067244470
Short name T997
Test name
Test status
Simulation time 17247703 ps
CPU time 0.72 seconds
Started Feb 25 01:50:40 PM PST 24
Finished Feb 25 01:50:41 PM PST 24
Peak memory 203436 kb
Host smart-0a828a16-1d7b-45d0-ab6e-0376e4926ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067244470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1067244470
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.108696253
Short name T982
Test name
Test status
Simulation time 370948841 ps
CPU time 3 seconds
Started Feb 25 01:50:32 PM PST 24
Finished Feb 25 01:50:35 PM PST 24
Peak memory 207256 kb
Host smart-b6e0ec7c-9ad6-489a-8a3d-2f4572b26a3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108696253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.108696253
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2438688561
Short name T1062
Test name
Test status
Simulation time 37020214 ps
CPU time 2.54 seconds
Started Feb 25 01:50:30 PM PST 24
Finished Feb 25 01:50:33 PM PST 24
Peak memory 215468 kb
Host smart-e4ecf32c-9fec-4a64-9182-78b887e5c6ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438688561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2438688561
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3659146524
Short name T249
Test name
Test status
Simulation time 2164853698 ps
CPU time 11.25 seconds
Started Feb 25 01:50:30 PM PST 24
Finished Feb 25 01:50:41 PM PST 24
Peak memory 216836 kb
Host smart-6c26899f-95fa-45a1-977a-a98a87fbe0d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659146524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3659146524
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1529796693
Short name T1083
Test name
Test status
Simulation time 154081768 ps
CPU time 2.06 seconds
Started Feb 25 01:50:37 PM PST 24
Finished Feb 25 01:50:40 PM PST 24
Peak memory 215624 kb
Host smart-27cd7447-4d94-4cc4-9af6-b0702eef1622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529796693 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1529796693
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1918254505
Short name T1088
Test name
Test status
Simulation time 384071981 ps
CPU time 2.67 seconds
Started Feb 25 01:50:30 PM PST 24
Finished Feb 25 01:50:33 PM PST 24
Peak memory 215364 kb
Host smart-1cb38139-5031-46ff-bfe1-c5f43203dcac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918254505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1918254505
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2333674861
Short name T989
Test name
Test status
Simulation time 14854263 ps
CPU time 0.72 seconds
Started Feb 25 01:50:32 PM PST 24
Finished Feb 25 01:50:33 PM PST 24
Peak memory 203440 kb
Host smart-ceda9696-ac9a-44b3-af5e-6b03d6c8ad9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333674861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2333674861
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2121674744
Short name T984
Test name
Test status
Simulation time 45145072 ps
CPU time 3.03 seconds
Started Feb 25 01:50:40 PM PST 24
Finished Feb 25 01:50:43 PM PST 24
Peak memory 215412 kb
Host smart-9aacd07b-92b0-45da-b04d-92dbdd3dc688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121674744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2121674744
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.479055981
Short name T1104
Test name
Test status
Simulation time 640751410 ps
CPU time 13.14 seconds
Started Feb 25 01:50:32 PM PST 24
Finished Feb 25 01:50:45 PM PST 24
Peak memory 215420 kb
Host smart-f56aa476-bf83-4297-915b-b00520f885ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479055981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.479055981
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1613950113
Short name T133
Test name
Test status
Simulation time 2747980614 ps
CPU time 5.57 seconds
Started Feb 25 01:50:46 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 217884 kb
Host smart-3831bb06-8878-47c2-9466-bb1156c3306f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613950113 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1613950113
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1941581361
Short name T106
Test name
Test status
Simulation time 489012453 ps
CPU time 2.09 seconds
Started Feb 25 01:50:42 PM PST 24
Finished Feb 25 01:50:44 PM PST 24
Peak memory 215168 kb
Host smart-f203a882-9145-46f8-a605-505f529ca228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941581361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1941581361
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.734480848
Short name T1020
Test name
Test status
Simulation time 14184899 ps
CPU time 0.72 seconds
Started Feb 25 01:50:45 PM PST 24
Finished Feb 25 01:50:46 PM PST 24
Peak memory 203376 kb
Host smart-c0f13729-90c5-4935-85d0-50d5055e424e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734480848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.734480848
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.980523515
Short name T988
Test name
Test status
Simulation time 172947818 ps
CPU time 2.79 seconds
Started Feb 25 01:50:41 PM PST 24
Finished Feb 25 01:50:44 PM PST 24
Peak memory 207296 kb
Host smart-278a09c6-9e7f-4148-8cf2-87ef550b4731
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980523515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.980523515
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2409274610
Short name T89
Test name
Test status
Simulation time 58715779 ps
CPU time 4.07 seconds
Started Feb 25 01:50:37 PM PST 24
Finished Feb 25 01:50:42 PM PST 24
Peak memory 215492 kb
Host smart-be56ee30-e558-46f4-9fde-cf6b3acf99a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409274610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2409274610
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3534268428
Short name T100
Test name
Test status
Simulation time 457166078 ps
CPU time 4.55 seconds
Started Feb 25 01:50:41 PM PST 24
Finished Feb 25 01:50:46 PM PST 24
Peak memory 218440 kb
Host smart-48e34ce7-354d-48e8-a142-adc513d15dd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534268428 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3534268428
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3533194205
Short name T1010
Test name
Test status
Simulation time 111451160 ps
CPU time 1.2 seconds
Started Feb 25 01:50:45 PM PST 24
Finished Feb 25 01:50:46 PM PST 24
Peak memory 207008 kb
Host smart-7727bf4b-1e9f-485d-aa9e-24c8ab24281f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533194205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3533194205
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3178352463
Short name T1057
Test name
Test status
Simulation time 20951665 ps
CPU time 0.72 seconds
Started Feb 25 01:50:49 PM PST 24
Finished Feb 25 01:50:50 PM PST 24
Peak memory 203024 kb
Host smart-a4b14610-2c66-4596-a4ae-ed35946fbfe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178352463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3178352463
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3717315087
Short name T1090
Test name
Test status
Simulation time 46867730 ps
CPU time 2.95 seconds
Started Feb 25 01:50:44 PM PST 24
Finished Feb 25 01:50:47 PM PST 24
Peak memory 215064 kb
Host smart-9d94f0bb-9178-4823-b5a6-c656e064b046
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717315087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3717315087
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3253906355
Short name T254
Test name
Test status
Simulation time 1671351953 ps
CPU time 19.36 seconds
Started Feb 25 01:50:47 PM PST 24
Finished Feb 25 01:51:06 PM PST 24
Peak memory 215372 kb
Host smart-899e35af-1887-4749-8e76-ceb242e11c7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253906355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3253906355
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2154660946
Short name T1100
Test name
Test status
Simulation time 104909261 ps
CPU time 7.65 seconds
Started Feb 25 01:49:41 PM PST 24
Finished Feb 25 01:49:49 PM PST 24
Peak memory 215304 kb
Host smart-e798a8ff-5033-4582-b126-f46ca5b6b220
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154660946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2154660946
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1348525117
Short name T1028
Test name
Test status
Simulation time 4826407751 ps
CPU time 25.73 seconds
Started Feb 25 01:49:42 PM PST 24
Finished Feb 25 01:50:08 PM PST 24
Peak memory 207196 kb
Host smart-99a35a92-9c3a-4b85-9407-cf7e64c8d332
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348525117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1348525117
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1023583251
Short name T107
Test name
Test status
Simulation time 31318033 ps
CPU time 1.17 seconds
Started Feb 25 01:49:42 PM PST 24
Finished Feb 25 01:49:43 PM PST 24
Peak memory 216364 kb
Host smart-abd0a6f9-1f3a-473d-990d-c4f0cd1f082e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023583251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1023583251
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.684681836
Short name T1077
Test name
Test status
Simulation time 658020526 ps
CPU time 3.79 seconds
Started Feb 25 01:49:49 PM PST 24
Finished Feb 25 01:49:53 PM PST 24
Peak memory 217680 kb
Host smart-cfd5b54c-a855-4aa2-af16-bf6fcc6352d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684681836 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.684681836
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1368724233
Short name T1068
Test name
Test status
Simulation time 338097920 ps
CPU time 1.36 seconds
Started Feb 25 01:49:41 PM PST 24
Finished Feb 25 01:49:43 PM PST 24
Peak memory 207204 kb
Host smart-c5874b43-b003-4472-8fcd-58080d6c8585
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368724233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
368724233
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2466027972
Short name T1108
Test name
Test status
Simulation time 21640618 ps
CPU time 0.77 seconds
Started Feb 25 01:49:33 PM PST 24
Finished Feb 25 01:49:34 PM PST 24
Peak memory 203132 kb
Host smart-06bfb79c-67af-44a6-9788-6a66506be8a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466027972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
466027972
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3577114853
Short name T110
Test name
Test status
Simulation time 109903340 ps
CPU time 1.96 seconds
Started Feb 25 01:49:43 PM PST 24
Finished Feb 25 01:49:45 PM PST 24
Peak memory 215312 kb
Host smart-3b5b6fce-6b45-46f3-b00c-46553fbef928
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577114853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3577114853
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1948505318
Short name T995
Test name
Test status
Simulation time 20918184 ps
CPU time 0.64 seconds
Started Feb 25 01:49:35 PM PST 24
Finished Feb 25 01:49:36 PM PST 24
Peak memory 203020 kb
Host smart-d5b2518e-0fa4-4a65-92df-68b792f4cfc5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948505318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1948505318
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.614068246
Short name T998
Test name
Test status
Simulation time 120184737 ps
CPU time 1.82 seconds
Started Feb 25 01:49:42 PM PST 24
Finished Feb 25 01:49:44 PM PST 24
Peak memory 205900 kb
Host smart-93b6ead5-cc01-42c4-93bd-98f56b230829
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614068246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.614068246
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2987018320
Short name T244
Test name
Test status
Simulation time 123874564 ps
CPU time 3.47 seconds
Started Feb 25 01:49:35 PM PST 24
Finished Feb 25 01:49:38 PM PST 24
Peak memory 215440 kb
Host smart-03d7b4eb-319e-44cc-9873-78f1e9fcf779
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987018320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
987018320
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3653825376
Short name T1080
Test name
Test status
Simulation time 1089784391 ps
CPU time 8.08 seconds
Started Feb 25 01:49:34 PM PST 24
Finished Feb 25 01:49:42 PM PST 24
Peak memory 215444 kb
Host smart-552bfdb0-f200-40d8-a61c-e2b268443cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653825376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3653825376
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2705827875
Short name T983
Test name
Test status
Simulation time 17333212 ps
CPU time 0.72 seconds
Started Feb 25 01:50:41 PM PST 24
Finished Feb 25 01:50:42 PM PST 24
Peak memory 203448 kb
Host smart-172a98a0-20b4-4772-ab05-4cd75c2ce8c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705827875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2705827875
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.768971058
Short name T1025
Test name
Test status
Simulation time 17063319 ps
CPU time 0.74 seconds
Started Feb 25 01:50:48 PM PST 24
Finished Feb 25 01:50:48 PM PST 24
Peak memory 203140 kb
Host smart-a84e2ccf-cf56-46a9-9f9b-9193bb7c27e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768971058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.768971058
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.898910278
Short name T992
Test name
Test status
Simulation time 167918163 ps
CPU time 0.71 seconds
Started Feb 25 01:50:52 PM PST 24
Finished Feb 25 01:50:53 PM PST 24
Peak memory 203140 kb
Host smart-cc23e797-f8cb-4d8b-8d0f-b2f2d2ed6f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898910278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.898910278
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2650344403
Short name T1069
Test name
Test status
Simulation time 100897019 ps
CPU time 0.68 seconds
Started Feb 25 01:50:54 PM PST 24
Finished Feb 25 01:50:55 PM PST 24
Peak memory 203060 kb
Host smart-74d44840-3f15-47da-b78c-46a27fb601ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650344403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2650344403
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1633105434
Short name T1023
Test name
Test status
Simulation time 14993054 ps
CPU time 0.73 seconds
Started Feb 25 01:50:51 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 203096 kb
Host smart-4b27c64b-9ba8-4bfe-a834-62a172a277c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633105434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1633105434
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1483939070
Short name T1094
Test name
Test status
Simulation time 42516821 ps
CPU time 0.76 seconds
Started Feb 25 01:50:51 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 203132 kb
Host smart-e41c6bf9-bdf6-4afa-a27e-62005a850d75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483939070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1483939070
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2310669914
Short name T1008
Test name
Test status
Simulation time 18593602 ps
CPU time 0.78 seconds
Started Feb 25 01:50:51 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 203084 kb
Host smart-decbb4bd-6f31-44c8-b8ba-c0db18cf8ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310669914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2310669914
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.897391506
Short name T1041
Test name
Test status
Simulation time 66376583 ps
CPU time 0.74 seconds
Started Feb 25 01:50:54 PM PST 24
Finished Feb 25 01:50:55 PM PST 24
Peak memory 203092 kb
Host smart-c19b1716-3b0a-45e1-b231-fdbfb083fa64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897391506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.897391506
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4126025984
Short name T1017
Test name
Test status
Simulation time 96843623 ps
CPU time 0.69 seconds
Started Feb 25 01:50:53 PM PST 24
Finished Feb 25 01:50:53 PM PST 24
Peak memory 203168 kb
Host smart-4d026627-9daf-436b-ab93-57c68685c5c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126025984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4126025984
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2761818454
Short name T1079
Test name
Test status
Simulation time 26835597 ps
CPU time 0.72 seconds
Started Feb 25 01:50:54 PM PST 24
Finished Feb 25 01:50:55 PM PST 24
Peak memory 203092 kb
Host smart-1d33d983-7f1f-4a55-b6a7-2c99bb854161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761818454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2761818454
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.797842331
Short name T113
Test name
Test status
Simulation time 758101992 ps
CPU time 8.69 seconds
Started Feb 25 01:49:52 PM PST 24
Finished Feb 25 01:50:01 PM PST 24
Peak memory 215336 kb
Host smart-4b1a643c-dfc2-4a41-a3d4-d90c1c858ba9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797842331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.797842331
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1238521580
Short name T1049
Test name
Test status
Simulation time 10262961547 ps
CPU time 38.04 seconds
Started Feb 25 01:49:52 PM PST 24
Finished Feb 25 01:50:31 PM PST 24
Peak memory 207104 kb
Host smart-003c057d-aaf4-4182-82a1-9f3cc812ab3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238521580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1238521580
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.550512846
Short name T108
Test name
Test status
Simulation time 35713394 ps
CPU time 1.08 seconds
Started Feb 25 01:49:49 PM PST 24
Finished Feb 25 01:49:50 PM PST 24
Peak memory 207044 kb
Host smart-dfe5f99c-c5b5-4735-9a61-96e09bd360b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550512846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.550512846
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1686239582
Short name T1061
Test name
Test status
Simulation time 713242966 ps
CPU time 5.77 seconds
Started Feb 25 01:49:54 PM PST 24
Finished Feb 25 01:50:01 PM PST 24
Peak memory 218332 kb
Host smart-059f46f3-612d-4795-8fb9-c7778dd61be7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686239582 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1686239582
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1347136830
Short name T1012
Test name
Test status
Simulation time 44164382 ps
CPU time 2.41 seconds
Started Feb 25 01:49:51 PM PST 24
Finished Feb 25 01:49:53 PM PST 24
Peak memory 207208 kb
Host smart-6fa34c63-1d1c-4207-a8f7-4f3b309e44af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347136830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
347136830
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1517318149
Short name T999
Test name
Test status
Simulation time 14223135 ps
CPU time 0.71 seconds
Started Feb 25 01:49:43 PM PST 24
Finished Feb 25 01:49:44 PM PST 24
Peak memory 203376 kb
Host smart-e6342214-016e-48fd-a524-fe8c668b6f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517318149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
517318149
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2097723780
Short name T116
Test name
Test status
Simulation time 48054609 ps
CPU time 1.82 seconds
Started Feb 25 01:49:49 PM PST 24
Finished Feb 25 01:49:51 PM PST 24
Peak memory 215272 kb
Host smart-ea1e7dca-29b5-4b35-bd51-727296f49728
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097723780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2097723780
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3047412145
Short name T1109
Test name
Test status
Simulation time 14105893 ps
CPU time 0.66 seconds
Started Feb 25 01:49:43 PM PST 24
Finished Feb 25 01:49:44 PM PST 24
Peak memory 203024 kb
Host smart-9003129a-f60e-48cb-b535-28e17c741c73
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047412145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3047412145
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2264881528
Short name T1050
Test name
Test status
Simulation time 123595009 ps
CPU time 1.79 seconds
Started Feb 25 01:49:52 PM PST 24
Finished Feb 25 01:49:54 PM PST 24
Peak memory 215352 kb
Host smart-27c5b356-2d5d-48d6-821d-f1e0d8e8d63e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264881528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2264881528
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.916150969
Short name T1092
Test name
Test status
Simulation time 163328649 ps
CPU time 4.68 seconds
Started Feb 25 01:49:49 PM PST 24
Finished Feb 25 01:49:54 PM PST 24
Peak memory 215388 kb
Host smart-355794fa-9b71-4b00-b2fb-acac4c96d6dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916150969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.916150969
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2748424821
Short name T251
Test name
Test status
Simulation time 3652870000 ps
CPU time 8 seconds
Started Feb 25 01:49:42 PM PST 24
Finished Feb 25 01:49:50 PM PST 24
Peak memory 215564 kb
Host smart-09499235-b2cc-40a1-92f0-9810bcbc906d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748424821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2748424821
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2413735964
Short name T1054
Test name
Test status
Simulation time 35816288 ps
CPU time 0.66 seconds
Started Feb 25 01:50:53 PM PST 24
Finished Feb 25 01:50:53 PM PST 24
Peak memory 203224 kb
Host smart-81cf1509-a4e0-4df4-8c2e-60110f2a54fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413735964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2413735964
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1901569539
Short name T1007
Test name
Test status
Simulation time 34858404 ps
CPU time 0.74 seconds
Started Feb 25 01:50:51 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 203096 kb
Host smart-a90b647d-a226-48ed-b5f0-a52f9587e55c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901569539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1901569539
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.380553045
Short name T1031
Test name
Test status
Simulation time 22336953 ps
CPU time 0.68 seconds
Started Feb 25 01:50:51 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 203448 kb
Host smart-62b13fcc-c681-49cc-9ee3-8e66da5ebe65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380553045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.380553045
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.56709865
Short name T1026
Test name
Test status
Simulation time 61073306 ps
CPU time 0.71 seconds
Started Feb 25 01:50:52 PM PST 24
Finished Feb 25 01:50:53 PM PST 24
Peak memory 203104 kb
Host smart-f1bdd7d8-b7c4-4e18-91f4-44917065e7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56709865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.56709865
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3587794598
Short name T1002
Test name
Test status
Simulation time 40802876 ps
CPU time 0.74 seconds
Started Feb 25 01:50:53 PM PST 24
Finished Feb 25 01:50:54 PM PST 24
Peak memory 203136 kb
Host smart-5ea9a3a7-2c01-4bf0-b958-7bafce23f1d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587794598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3587794598
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.573983621
Short name T1046
Test name
Test status
Simulation time 23606823 ps
CPU time 0.75 seconds
Started Feb 25 01:50:52 PM PST 24
Finished Feb 25 01:50:53 PM PST 24
Peak memory 203384 kb
Host smart-0437bc3e-1ba2-4525-a2cc-161317e36fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573983621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.573983621
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2602533797
Short name T986
Test name
Test status
Simulation time 12990698 ps
CPU time 0.74 seconds
Started Feb 25 01:50:50 PM PST 24
Finished Feb 25 01:50:51 PM PST 24
Peak memory 203180 kb
Host smart-bcf03723-d323-4375-842a-11884337eba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602533797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2602533797
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1801535747
Short name T1099
Test name
Test status
Simulation time 12139303 ps
CPU time 0.66 seconds
Started Feb 25 01:50:50 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 203096 kb
Host smart-ecfd0d36-7efd-4ebf-aab4-adf07900e67a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801535747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1801535747
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3769533986
Short name T1037
Test name
Test status
Simulation time 13250624 ps
CPU time 0.72 seconds
Started Feb 25 01:50:51 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 203412 kb
Host smart-f44c8f78-4a73-4871-bfdb-9a41d6200d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769533986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3769533986
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.227980428
Short name T1001
Test name
Test status
Simulation time 14385284 ps
CPU time 0.71 seconds
Started Feb 25 01:50:57 PM PST 24
Finished Feb 25 01:50:58 PM PST 24
Peak memory 203440 kb
Host smart-5394a7e0-ab54-47e0-b454-0c0e465f0e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227980428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.227980428
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.27153047
Short name T112
Test name
Test status
Simulation time 840156537 ps
CPU time 13.36 seconds
Started Feb 25 01:50:09 PM PST 24
Finished Feb 25 01:50:23 PM PST 24
Peak memory 215344 kb
Host smart-1375a736-2287-4919-90da-9e76535bcf19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27153047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
aliasing.27153047
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3749076749
Short name T1055
Test name
Test status
Simulation time 2181383485 ps
CPU time 32.22 seconds
Started Feb 25 01:50:09 PM PST 24
Finished Feb 25 01:50:41 PM PST 24
Peak memory 206876 kb
Host smart-117403c1-73e1-4d00-ac0c-0a14afbf339b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749076749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3749076749
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.311103298
Short name T77
Test name
Test status
Simulation time 22720434 ps
CPU time 1.36 seconds
Started Feb 25 01:50:09 PM PST 24
Finished Feb 25 01:50:11 PM PST 24
Peak memory 207140 kb
Host smart-9df7c1b2-d443-4023-a35d-0e9e30d1fa30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311103298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.311103298
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.388167064
Short name T99
Test name
Test status
Simulation time 529459614 ps
CPU time 6.44 seconds
Started Feb 25 01:50:09 PM PST 24
Finished Feb 25 01:50:16 PM PST 24
Peak memory 217708 kb
Host smart-535d389d-15d0-43ef-9dcf-62b03c8bec78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388167064 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.388167064
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1366990717
Short name T987
Test name
Test status
Simulation time 39630332 ps
CPU time 1.42 seconds
Started Feb 25 01:50:10 PM PST 24
Finished Feb 25 01:50:11 PM PST 24
Peak memory 207132 kb
Host smart-f22905d5-a9ed-4a8d-a606-764444cdd993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366990717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
366990717
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3237981150
Short name T1070
Test name
Test status
Simulation time 21114960 ps
CPU time 0.68 seconds
Started Feb 25 01:49:52 PM PST 24
Finished Feb 25 01:49:53 PM PST 24
Peak memory 203124 kb
Host smart-ecfb6376-4f1c-40c8-b036-c9074406dd4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237981150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
237981150
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2456836862
Short name T1073
Test name
Test status
Simulation time 90859945 ps
CPU time 1.51 seconds
Started Feb 25 01:50:08 PM PST 24
Finished Feb 25 01:50:10 PM PST 24
Peak memory 215380 kb
Host smart-bcf75185-e6a7-4787-9ad2-1f6f95993573
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456836862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2456836862
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2649910095
Short name T1043
Test name
Test status
Simulation time 71047098 ps
CPU time 0.62 seconds
Started Feb 25 01:49:55 PM PST 24
Finished Feb 25 01:49:57 PM PST 24
Peak memory 203372 kb
Host smart-437af503-21e0-45e1-9b58-5bfeaeede62e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649910095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2649910095
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.239138440
Short name T1053
Test name
Test status
Simulation time 157978619 ps
CPU time 4.17 seconds
Started Feb 25 01:50:10 PM PST 24
Finished Feb 25 01:50:15 PM PST 24
Peak memory 215400 kb
Host smart-af29e64f-9158-4104-af65-d3190f0ed908
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239138440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.239138440
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1955503773
Short name T96
Test name
Test status
Simulation time 252947901 ps
CPU time 5.93 seconds
Started Feb 25 01:49:53 PM PST 24
Finished Feb 25 01:50:00 PM PST 24
Peak memory 216476 kb
Host smart-851dc94b-30b0-40fd-91d4-12941d10321d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955503773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
955503773
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2949527978
Short name T253
Test name
Test status
Simulation time 1757760018 ps
CPU time 22.51 seconds
Started Feb 25 01:49:51 PM PST 24
Finished Feb 25 01:50:14 PM PST 24
Peak memory 215500 kb
Host smart-504ce807-3c7d-464a-84fe-40c436050c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949527978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2949527978
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3850932999
Short name T1103
Test name
Test status
Simulation time 29922163 ps
CPU time 0.7 seconds
Started Feb 25 01:50:53 PM PST 24
Finished Feb 25 01:50:53 PM PST 24
Peak memory 203240 kb
Host smart-818c07a6-f4a8-4a06-90f6-141aca20dd1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850932999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3850932999
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1695153623
Short name T1005
Test name
Test status
Simulation time 23894032 ps
CPU time 0.75 seconds
Started Feb 25 01:50:53 PM PST 24
Finished Feb 25 01:50:54 PM PST 24
Peak memory 203072 kb
Host smart-299bc9d4-9995-4214-b38c-da3b569b8ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695153623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1695153623
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2830339233
Short name T1066
Test name
Test status
Simulation time 17073884 ps
CPU time 0.74 seconds
Started Feb 25 01:50:55 PM PST 24
Finished Feb 25 01:50:56 PM PST 24
Peak memory 203124 kb
Host smart-ceeeb8bc-e2c9-454f-af4e-41ecc4758f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830339233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2830339233
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.172904983
Short name T1034
Test name
Test status
Simulation time 30184007 ps
CPU time 0.76 seconds
Started Feb 25 01:50:52 PM PST 24
Finished Feb 25 01:50:53 PM PST 24
Peak memory 203440 kb
Host smart-1c560488-b208-4375-bc74-76894e7887ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172904983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.172904983
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1151622218
Short name T1021
Test name
Test status
Simulation time 88590078 ps
CPU time 0.69 seconds
Started Feb 25 01:50:53 PM PST 24
Finished Feb 25 01:50:55 PM PST 24
Peak memory 203048 kb
Host smart-03187899-4fa3-46d0-895a-7e281d0bd697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151622218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1151622218
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3937552172
Short name T1086
Test name
Test status
Simulation time 22381564 ps
CPU time 0.77 seconds
Started Feb 25 01:50:54 PM PST 24
Finished Feb 25 01:50:55 PM PST 24
Peak memory 203184 kb
Host smart-6c13ffac-c1be-44ff-8555-9df8f3da0ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937552172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3937552172
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.75170541
Short name T1014
Test name
Test status
Simulation time 99515161 ps
CPU time 0.68 seconds
Started Feb 25 01:50:53 PM PST 24
Finished Feb 25 01:50:53 PM PST 24
Peak memory 203132 kb
Host smart-7e847c68-f86d-4128-8a7a-56c9e3699d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75170541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.75170541
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1689409935
Short name T1022
Test name
Test status
Simulation time 84757944 ps
CPU time 0.71 seconds
Started Feb 25 01:50:51 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 203400 kb
Host smart-e7edb964-9f1d-4bbf-a527-dfba730d99de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689409935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1689409935
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.537206227
Short name T1064
Test name
Test status
Simulation time 18160336 ps
CPU time 0.74 seconds
Started Feb 25 01:51:02 PM PST 24
Finished Feb 25 01:51:03 PM PST 24
Peak memory 203132 kb
Host smart-b468c556-fea9-41bf-8b38-871c6ed53f56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537206227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.537206227
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3118645533
Short name T1015
Test name
Test status
Simulation time 14485312 ps
CPU time 0.69 seconds
Started Feb 25 01:51:04 PM PST 24
Finished Feb 25 01:51:05 PM PST 24
Peak memory 203484 kb
Host smart-cff0f803-8c9b-40c0-b83b-e813724f5eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118645533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3118645533
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2066237861
Short name T1000
Test name
Test status
Simulation time 52975962 ps
CPU time 3.78 seconds
Started Feb 25 01:50:09 PM PST 24
Finished Feb 25 01:50:13 PM PST 24
Peak memory 217272 kb
Host smart-d292df66-3c54-47e7-92d3-713e41c8a6e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066237861 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2066237861
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4249679431
Short name T1056
Test name
Test status
Simulation time 205654719 ps
CPU time 1.54 seconds
Started Feb 25 01:50:10 PM PST 24
Finished Feb 25 01:50:12 PM PST 24
Peak memory 207040 kb
Host smart-d9b5fdf1-c41f-4157-a87c-ee7190aefc74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249679431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
249679431
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1506428206
Short name T1072
Test name
Test status
Simulation time 44512956 ps
CPU time 0.72 seconds
Started Feb 25 01:50:09 PM PST 24
Finished Feb 25 01:50:10 PM PST 24
Peak memory 203100 kb
Host smart-708d4303-2648-4cdc-a2c4-459ea454eadf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506428206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
506428206
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1372755611
Short name T132
Test name
Test status
Simulation time 524886289 ps
CPU time 4 seconds
Started Feb 25 01:50:09 PM PST 24
Finished Feb 25 01:50:13 PM PST 24
Peak memory 215456 kb
Host smart-b8eb669b-3cb1-45b0-8766-fd77654403b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372755611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1372755611
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1107819510
Short name T1071
Test name
Test status
Simulation time 551861803 ps
CPU time 4.3 seconds
Started Feb 25 01:50:09 PM PST 24
Finished Feb 25 01:50:14 PM PST 24
Peak memory 215560 kb
Host smart-c98c3903-485c-4c25-88dc-87d661971552
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107819510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
107819510
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2331744604
Short name T255
Test name
Test status
Simulation time 1156192003 ps
CPU time 12.9 seconds
Started Feb 25 01:50:10 PM PST 24
Finished Feb 25 01:50:23 PM PST 24
Peak memory 215476 kb
Host smart-853edb25-077a-4197-836b-a121bf2e6fc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331744604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2331744604
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3574492528
Short name T1091
Test name
Test status
Simulation time 80654488 ps
CPU time 3.26 seconds
Started Feb 25 01:50:09 PM PST 24
Finished Feb 25 01:50:12 PM PST 24
Peak memory 217204 kb
Host smart-7a7059a6-ec2b-4212-811e-5bb4807deacd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574492528 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3574492528
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.277780527
Short name T993
Test name
Test status
Simulation time 31032787 ps
CPU time 1.95 seconds
Started Feb 25 01:50:10 PM PST 24
Finished Feb 25 01:50:12 PM PST 24
Peak memory 215332 kb
Host smart-638e712c-9208-490b-b1e7-cecb93acba8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277780527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.277780527
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2566511969
Short name T1027
Test name
Test status
Simulation time 12603599 ps
CPU time 0.7 seconds
Started Feb 25 01:50:12 PM PST 24
Finished Feb 25 01:50:13 PM PST 24
Peak memory 203056 kb
Host smart-3cff72a1-4436-48ea-a7de-d24cc59f743b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566511969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
566511969
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2108752625
Short name T1044
Test name
Test status
Simulation time 133404127 ps
CPU time 1.99 seconds
Started Feb 25 01:50:09 PM PST 24
Finished Feb 25 01:50:11 PM PST 24
Peak memory 206932 kb
Host smart-a545fdab-64cd-4717-b1b6-ae713c4c68d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108752625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2108752625
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4007425108
Short name T1047
Test name
Test status
Simulation time 71047160 ps
CPU time 1.51 seconds
Started Feb 25 01:50:11 PM PST 24
Finished Feb 25 01:50:13 PM PST 24
Peak memory 215532 kb
Host smart-342e7f2f-e603-4c87-aa24-c9bde26ccc1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007425108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
007425108
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.718248995
Short name T91
Test name
Test status
Simulation time 287098786 ps
CPU time 8.73 seconds
Started Feb 25 01:50:12 PM PST 24
Finished Feb 25 01:50:21 PM PST 24
Peak memory 215868 kb
Host smart-158f962f-6d14-4707-b4fb-05ae855216b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718248995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.718248995
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3109264240
Short name T1004
Test name
Test status
Simulation time 35992180 ps
CPU time 2.62 seconds
Started Feb 25 01:50:15 PM PST 24
Finished Feb 25 01:50:18 PM PST 24
Peak memory 215388 kb
Host smart-a0d23557-4435-48f9-a175-d974bb8bc611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109264240 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3109264240
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1490886380
Short name T1085
Test name
Test status
Simulation time 90338028 ps
CPU time 1.35 seconds
Started Feb 25 01:50:16 PM PST 24
Finished Feb 25 01:50:18 PM PST 24
Peak memory 207240 kb
Host smart-cb54bcfd-f151-4518-8a12-09b71042c7fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490886380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
490886380
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.714857293
Short name T1029
Test name
Test status
Simulation time 18703880 ps
CPU time 0.73 seconds
Started Feb 25 01:50:19 PM PST 24
Finished Feb 25 01:50:20 PM PST 24
Peak memory 203412 kb
Host smart-84e4c4b5-b677-4312-bcaf-7ebca400a22e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714857293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.714857293
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2484674146
Short name T1036
Test name
Test status
Simulation time 313445557 ps
CPU time 2.06 seconds
Started Feb 25 01:50:16 PM PST 24
Finished Feb 25 01:50:18 PM PST 24
Peak memory 215348 kb
Host smart-82c121c3-e141-4c2e-be2e-a225d481bcf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484674146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2484674146
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2735132752
Short name T1038
Test name
Test status
Simulation time 59102555 ps
CPU time 4.8 seconds
Started Feb 25 01:50:10 PM PST 24
Finished Feb 25 01:50:15 PM PST 24
Peak memory 215484 kb
Host smart-45ba6f7a-d4bb-4aa7-b50f-eaa7cd77695f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735132752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
735132752
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.701728264
Short name T102
Test name
Test status
Simulation time 184588394 ps
CPU time 4.67 seconds
Started Feb 25 01:50:17 PM PST 24
Finished Feb 25 01:50:22 PM PST 24
Peak memory 217364 kb
Host smart-f0bc2ba3-fff9-4797-aa6e-d31c8b058168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701728264 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.701728264
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3948354368
Short name T1065
Test name
Test status
Simulation time 26855672 ps
CPU time 1.74 seconds
Started Feb 25 01:50:18 PM PST 24
Finished Feb 25 01:50:20 PM PST 24
Peak memory 215332 kb
Host smart-39112c9e-efd1-4b9d-8432-5dfde6c8ce4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948354368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
948354368
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2305004008
Short name T1032
Test name
Test status
Simulation time 12724834 ps
CPU time 0.74 seconds
Started Feb 25 01:50:16 PM PST 24
Finished Feb 25 01:50:16 PM PST 24
Peak memory 203116 kb
Host smart-3c1e3821-556d-4a07-a5ac-df2b884a6668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305004008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
305004008
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2162455660
Short name T1063
Test name
Test status
Simulation time 186414477 ps
CPU time 3.99 seconds
Started Feb 25 01:50:16 PM PST 24
Finished Feb 25 01:50:21 PM PST 24
Peak memory 215428 kb
Host smart-266aa74f-f1d4-4601-85ff-753175fc1d54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162455660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2162455660
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2849603106
Short name T1018
Test name
Test status
Simulation time 162144132 ps
CPU time 2.03 seconds
Started Feb 25 01:50:16 PM PST 24
Finished Feb 25 01:50:19 PM PST 24
Peak memory 215500 kb
Host smart-b7e6f30d-2ce4-4bb9-b250-77100d8dc870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849603106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
849603106
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3589548273
Short name T252
Test name
Test status
Simulation time 10905355167 ps
CPU time 24.86 seconds
Started Feb 25 01:50:18 PM PST 24
Finished Feb 25 01:50:43 PM PST 24
Peak memory 215572 kb
Host smart-69f90bab-ba24-46f1-899b-4ef2021d2069
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589548273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3589548273
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2573283307
Short name T101
Test name
Test status
Simulation time 123533904 ps
CPU time 5.21 seconds
Started Feb 25 01:50:28 PM PST 24
Finished Feb 25 01:50:34 PM PST 24
Peak memory 217500 kb
Host smart-9b5c1e72-c025-4f19-8e37-6a19e70c2b8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573283307 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2573283307
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.179381086
Short name T1051
Test name
Test status
Simulation time 89808324 ps
CPU time 2.7 seconds
Started Feb 25 01:50:29 PM PST 24
Finished Feb 25 01:50:32 PM PST 24
Peak memory 215244 kb
Host smart-b148a57c-66ce-4519-8fcd-ac86a5b39718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179381086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.179381086
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1640867063
Short name T1003
Test name
Test status
Simulation time 47483851 ps
CPU time 0.72 seconds
Started Feb 25 01:50:20 PM PST 24
Finished Feb 25 01:50:21 PM PST 24
Peak memory 203088 kb
Host smart-88f81874-e06b-449f-87e9-f98edbbef936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640867063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
640867063
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1611910751
Short name T1081
Test name
Test status
Simulation time 190194574 ps
CPU time 2.86 seconds
Started Feb 25 01:50:23 PM PST 24
Finished Feb 25 01:50:26 PM PST 24
Peak memory 207212 kb
Host smart-6b41b624-62ee-4280-a19e-922bd138b60a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611910751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1611910751
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4193612196
Short name T87
Test name
Test status
Simulation time 142144945 ps
CPU time 1.88 seconds
Started Feb 25 01:50:17 PM PST 24
Finished Feb 25 01:50:19 PM PST 24
Peak memory 215648 kb
Host smart-dacaab7d-133b-40c1-8001-4ecc571ad755
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193612196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
193612196
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1141053692
Short name T1048
Test name
Test status
Simulation time 401328398 ps
CPU time 6.4 seconds
Started Feb 25 01:50:19 PM PST 24
Finished Feb 25 01:50:26 PM PST 24
Peak memory 215408 kb
Host smart-eefabb22-1f0f-4f6c-aa85-71ad92e2b898
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141053692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1141053692
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2802139836
Short name T460
Test name
Test status
Simulation time 11673803 ps
CPU time 0.71 seconds
Started Feb 25 02:42:55 PM PST 24
Finished Feb 25 02:42:55 PM PST 24
Peak memory 204516 kb
Host smart-ae001280-4517-46af-b239-94062bfbced9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802139836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
802139836
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2341814952
Short name T823
Test name
Test status
Simulation time 4354468982 ps
CPU time 3.52 seconds
Started Feb 25 02:42:45 PM PST 24
Finished Feb 25 02:42:49 PM PST 24
Peak memory 217800 kb
Host smart-719b3faa-94e9-4238-b722-1dd00bd6a910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341814952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2341814952
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2727621812
Short name T517
Test name
Test status
Simulation time 26446123 ps
CPU time 0.72 seconds
Started Feb 25 02:42:53 PM PST 24
Finished Feb 25 02:42:54 PM PST 24
Peak memory 204540 kb
Host smart-7722ed25-7407-4734-9bc2-ce10ff471ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727621812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2727621812
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2820287875
Short name T347
Test name
Test status
Simulation time 361937592 ps
CPU time 4.5 seconds
Started Feb 25 02:43:05 PM PST 24
Finished Feb 25 02:43:10 PM PST 24
Peak memory 219748 kb
Host smart-ff2af6b4-81e3-49d8-bcd7-205f7e8d5553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820287875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2820287875
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3785018717
Short name T201
Test name
Test status
Simulation time 804091807166 ps
CPU time 486.36 seconds
Started Feb 25 02:42:53 PM PST 24
Finished Feb 25 02:51:00 PM PST 24
Peak memory 248752 kb
Host smart-bb4deb57-8a1c-4418-b228-3d4002caa5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785018717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3785018717
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_intercept.94654047
Short name T810
Test name
Test status
Simulation time 121080058 ps
CPU time 3.45 seconds
Started Feb 25 02:42:49 PM PST 24
Finished Feb 25 02:42:53 PM PST 24
Peak memory 232528 kb
Host smart-d41ee7ad-80fc-4002-92bd-4b468aa30fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94654047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.94654047
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2374875838
Short name T456
Test name
Test status
Simulation time 1390386247 ps
CPU time 11.23 seconds
Started Feb 25 02:42:49 PM PST 24
Finished Feb 25 02:43:00 PM PST 24
Peak memory 232264 kb
Host smart-7581d129-0639-451b-9eaa-d8045ded3326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374875838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2374875838
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2706127519
Short name T281
Test name
Test status
Simulation time 12301128684 ps
CPU time 7.49 seconds
Started Feb 25 02:42:48 PM PST 24
Finished Feb 25 02:42:56 PM PST 24
Peak memory 224148 kb
Host smart-752a78f4-218c-45b8-9d3a-5279cd37360f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706127519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2706127519
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3470571510
Short name T199
Test name
Test status
Simulation time 3705517319 ps
CPU time 7.15 seconds
Started Feb 25 02:42:52 PM PST 24
Finished Feb 25 02:42:59 PM PST 24
Peak memory 233952 kb
Host smart-8d9c92f7-9ed6-4afd-aa10-0c85df2f7a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470571510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3470571510
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.566767844
Short name T377
Test name
Test status
Simulation time 993762163 ps
CPU time 5.22 seconds
Started Feb 25 02:43:00 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 221636 kb
Host smart-203eb3b9-0ef1-4bd6-99d4-7e8e157640fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=566767844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.566767844
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2871267757
Short name T42
Test name
Test status
Simulation time 68814013 ps
CPU time 1.06 seconds
Started Feb 25 02:42:46 PM PST 24
Finished Feb 25 02:42:47 PM PST 24
Peak memory 235088 kb
Host smart-1cdade26-8b9a-44ed-bb45-9ccfbffce29f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871267757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2871267757
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.345725372
Short name T142
Test name
Test status
Simulation time 58494096 ps
CPU time 1.08 seconds
Started Feb 25 02:42:58 PM PST 24
Finished Feb 25 02:42:59 PM PST 24
Peak memory 206324 kb
Host smart-823eebe2-f299-48c9-b3eb-111530d4545d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345725372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.345725372
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2225199675
Short name T897
Test name
Test status
Simulation time 3023620958 ps
CPU time 22.22 seconds
Started Feb 25 02:42:51 PM PST 24
Finished Feb 25 02:43:13 PM PST 24
Peak memory 215820 kb
Host smart-5ad74032-9d58-48db-b7b8-541337b38062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225199675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2225199675
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.88688677
Short name T397
Test name
Test status
Simulation time 114527159 ps
CPU time 2.93 seconds
Started Feb 25 02:42:51 PM PST 24
Finished Feb 25 02:42:54 PM PST 24
Peak memory 215836 kb
Host smart-dc96c88f-0223-4881-86e9-4d93b6842987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88688677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.88688677
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1781318369
Short name T342
Test name
Test status
Simulation time 147294526 ps
CPU time 0.99 seconds
Started Feb 25 02:42:54 PM PST 24
Finished Feb 25 02:42:56 PM PST 24
Peak memory 204928 kb
Host smart-a1512c96-26d8-4dda-aa32-f1d4f8c9686a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781318369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1781318369
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1225635705
Short name T801
Test name
Test status
Simulation time 1901116111 ps
CPU time 7.7 seconds
Started Feb 25 02:43:03 PM PST 24
Finished Feb 25 02:43:11 PM PST 24
Peak memory 234964 kb
Host smart-e5054440-127d-4221-ae7b-0885c56766ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225635705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1225635705
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2975457679
Short name T647
Test name
Test status
Simulation time 52935519 ps
CPU time 0.68 seconds
Started Feb 25 02:42:51 PM PST 24
Finished Feb 25 02:42:51 PM PST 24
Peak memory 204884 kb
Host smart-13b4ccf7-9ad0-4296-ac56-10d310596ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975457679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
975457679
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.508892228
Short name T649
Test name
Test status
Simulation time 106573614 ps
CPU time 2.97 seconds
Started Feb 25 02:42:52 PM PST 24
Finished Feb 25 02:42:55 PM PST 24
Peak memory 233128 kb
Host smart-acf0873a-a1c6-4874-a563-811a56fd9459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508892228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.508892228
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1501786841
Short name T819
Test name
Test status
Simulation time 21643321 ps
CPU time 0.82 seconds
Started Feb 25 02:42:52 PM PST 24
Finished Feb 25 02:42:53 PM PST 24
Peak memory 205712 kb
Host smart-24fda3d4-81aa-47d8-9862-5945b9921316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501786841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1501786841
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3278146674
Short name T789
Test name
Test status
Simulation time 6704343867 ps
CPU time 67.07 seconds
Started Feb 25 02:42:49 PM PST 24
Finished Feb 25 02:43:56 PM PST 24
Peak memory 255668 kb
Host smart-e06333f4-1f7b-492e-a8c6-e298b5d53f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278146674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3278146674
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2156819198
Short name T444
Test name
Test status
Simulation time 7669569088 ps
CPU time 75.11 seconds
Started Feb 25 02:42:52 PM PST 24
Finished Feb 25 02:44:07 PM PST 24
Peak memory 253940 kb
Host smart-19cbdec6-512d-4e0b-87c1-8d1275a38559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156819198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2156819198
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.380442318
Short name T285
Test name
Test status
Simulation time 10746759082 ps
CPU time 17.24 seconds
Started Feb 25 02:42:48 PM PST 24
Finished Feb 25 02:43:06 PM PST 24
Peak memory 233388 kb
Host smart-6a607162-3ccc-49fa-99a6-114452b9354b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380442318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.380442318
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2217484898
Short name T258
Test name
Test status
Simulation time 272869666 ps
CPU time 5.17 seconds
Started Feb 25 02:42:49 PM PST 24
Finished Feb 25 02:42:54 PM PST 24
Peak memory 218224 kb
Host smart-d517d8e7-e656-409c-bc87-f3a51fee3945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217484898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2217484898
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1978316315
Short name T721
Test name
Test status
Simulation time 14859162641 ps
CPU time 37.6 seconds
Started Feb 25 02:42:48 PM PST 24
Finished Feb 25 02:43:26 PM PST 24
Peak memory 240500 kb
Host smart-cddc6c49-905b-42d2-a3a0-c798da224f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978316315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1978316315
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3224215631
Short name T451
Test name
Test status
Simulation time 30704627 ps
CPU time 1 seconds
Started Feb 25 02:43:03 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 217372 kb
Host smart-0bee3e2c-c3e7-48f9-ac6a-c585c44c7992
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224215631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3224215631
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3875795814
Short name T600
Test name
Test status
Simulation time 66114651707 ps
CPU time 26.53 seconds
Started Feb 25 02:42:52 PM PST 24
Finished Feb 25 02:43:18 PM PST 24
Peak memory 223468 kb
Host smart-e8c6a14b-0ee0-4250-9dda-4c743ed4cd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875795814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3875795814
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.192734724
Short name T471
Test name
Test status
Simulation time 7472523150 ps
CPU time 11.18 seconds
Started Feb 25 02:42:48 PM PST 24
Finished Feb 25 02:43:00 PM PST 24
Peak memory 228552 kb
Host smart-17e99839-0856-488d-b4c1-7e941b0d331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192734724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.192734724
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.2362237564
Short name T39
Test name
Test status
Simulation time 30250538 ps
CPU time 0.73 seconds
Started Feb 25 02:43:08 PM PST 24
Finished Feb 25 02:43:09 PM PST 24
Peak memory 215712 kb
Host smart-9e10b9d0-1ffb-412c-be04-7ebfff877fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362237564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.2362237564
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2747016120
Short name T495
Test name
Test status
Simulation time 336181230 ps
CPU time 3.81 seconds
Started Feb 25 02:43:07 PM PST 24
Finished Feb 25 02:43:11 PM PST 24
Peak memory 218604 kb
Host smart-bbbbfb36-9db9-45ba-9a9d-803f5dc4254d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2747016120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2747016120
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2954632353
Short name T296
Test name
Test status
Simulation time 15043598173 ps
CPU time 19.57 seconds
Started Feb 25 02:42:45 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 215884 kb
Host smart-25f59fe8-6794-4ac8-9fa4-622beee746af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954632353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2954632353
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3695995385
Short name T974
Test name
Test status
Simulation time 4008397820 ps
CPU time 7.91 seconds
Started Feb 25 02:42:54 PM PST 24
Finished Feb 25 02:43:02 PM PST 24
Peak memory 216648 kb
Host smart-9bca93b4-aa91-496f-9858-ff1bc1e903df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695995385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3695995385
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1787597871
Short name T634
Test name
Test status
Simulation time 111762099 ps
CPU time 1.37 seconds
Started Feb 25 02:42:48 PM PST 24
Finished Feb 25 02:42:49 PM PST 24
Peak memory 207628 kb
Host smart-6925005f-a0e2-4809-8dfe-5bddadaec084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787597871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1787597871
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1294507720
Short name T954
Test name
Test status
Simulation time 47083408 ps
CPU time 0.74 seconds
Started Feb 25 02:42:55 PM PST 24
Finished Feb 25 02:42:56 PM PST 24
Peak memory 204948 kb
Host smart-3b3d8683-865d-49aa-aafe-eae17ac02cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294507720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1294507720
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.898594267
Short name T937
Test name
Test status
Simulation time 21670071915 ps
CPU time 26.35 seconds
Started Feb 25 02:42:47 PM PST 24
Finished Feb 25 02:43:13 PM PST 24
Peak memory 220608 kb
Host smart-08d90f80-570c-4747-b301-b1573d7bf9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898594267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.898594267
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2217269811
Short name T478
Test name
Test status
Simulation time 50265171 ps
CPU time 0.73 seconds
Started Feb 25 02:43:24 PM PST 24
Finished Feb 25 02:43:24 PM PST 24
Peak memory 203952 kb
Host smart-327a14c4-423c-40a1-9637-cebecfb51b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217269811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2217269811
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1533773885
Short name T688
Test name
Test status
Simulation time 3826977266 ps
CPU time 6.52 seconds
Started Feb 25 02:43:27 PM PST 24
Finished Feb 25 02:43:34 PM PST 24
Peak memory 232984 kb
Host smart-0bfcda40-ab70-4e32-ae98-7cccca7f8606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533773885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1533773885
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1959121014
Short name T459
Test name
Test status
Simulation time 154133958 ps
CPU time 0.77 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:43:24 PM PST 24
Peak memory 205012 kb
Host smart-1a10d09d-af83-480c-88e2-ef70985e23c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959121014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1959121014
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2314784
Short name T952
Test name
Test status
Simulation time 36161259982 ps
CPU time 208.47 seconds
Started Feb 25 02:43:18 PM PST 24
Finished Feb 25 02:46:46 PM PST 24
Peak memory 248616 kb
Host smart-f4bf06e3-9f0a-418c-9ff6-439245882e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2314784
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3432608166
Short name T200
Test name
Test status
Simulation time 52158694227 ps
CPU time 360.04 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:49:30 PM PST 24
Peak memory 255804 kb
Host smart-69bbeb00-ac41-4277-97d9-d35eff9eb580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432608166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3432608166
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1590565766
Short name T697
Test name
Test status
Simulation time 51202834355 ps
CPU time 325.08 seconds
Started Feb 25 02:43:15 PM PST 24
Finished Feb 25 02:48:40 PM PST 24
Peak memory 271964 kb
Host smart-3939f5fd-804a-4afc-8680-c3d20e941d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590565766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1590565766
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3814404458
Short name T944
Test name
Test status
Simulation time 519223671 ps
CPU time 15.95 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:43:45 PM PST 24
Peak memory 248800 kb
Host smart-b3beeaed-0f9d-412e-be6c-b8892dcee229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814404458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3814404458
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2946922874
Short name T47
Test name
Test status
Simulation time 888716294 ps
CPU time 6.98 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:43:30 PM PST 24
Peak memory 234056 kb
Host smart-a6bd6ec4-6436-4fc9-80e9-fa02aeac287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946922874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2946922874
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.228859694
Short name T694
Test name
Test status
Simulation time 29362685 ps
CPU time 1.01 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:43:30 PM PST 24
Peak memory 216116 kb
Host smart-3ebba605-09c2-4e68-a978-3e45e64477d1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228859694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.228859694
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.522620919
Short name T310
Test name
Test status
Simulation time 2026510588 ps
CPU time 3.67 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:29 PM PST 24
Peak memory 217032 kb
Host smart-c64ea6c9-10c2-4065-9ec7-565c3a45969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522620919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.522620919
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1151448391
Short name T192
Test name
Test status
Simulation time 7083966721 ps
CPU time 18.3 seconds
Started Feb 25 02:43:16 PM PST 24
Finished Feb 25 02:43:34 PM PST 24
Peak memory 217476 kb
Host smart-f37b90bc-638a-4ec5-971b-bac21aaca86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151448391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1151448391
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.1548400122
Short name T976
Test name
Test status
Simulation time 26616359 ps
CPU time 0.75 seconds
Started Feb 25 02:43:19 PM PST 24
Finished Feb 25 02:43:20 PM PST 24
Peak memory 215708 kb
Host smart-4b1887a4-b498-4b32-a07f-864ef61e161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548400122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1548400122
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3900511844
Short name T562
Test name
Test status
Simulation time 2626899459 ps
CPU time 4.18 seconds
Started Feb 25 02:43:20 PM PST 24
Finished Feb 25 02:43:24 PM PST 24
Peak memory 220628 kb
Host smart-4b1dc3f5-62b5-42eb-b5e2-4ad0f4f34aad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3900511844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3900511844
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3828330161
Short name T25
Test name
Test status
Simulation time 7587360606 ps
CPU time 9.54 seconds
Started Feb 25 02:43:27 PM PST 24
Finished Feb 25 02:43:37 PM PST 24
Peak memory 215872 kb
Host smart-6fde930f-b183-4c17-a2ca-60525fee754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828330161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3828330161
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.22042551
Short name T55
Test name
Test status
Simulation time 1212908393 ps
CPU time 5.63 seconds
Started Feb 25 02:43:21 PM PST 24
Finished Feb 25 02:43:26 PM PST 24
Peak memory 215832 kb
Host smart-4850337a-1146-44bd-9918-fd9f2b8dd885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22042551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.22042551
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1643484879
Short name T492
Test name
Test status
Simulation time 89010159 ps
CPU time 0.78 seconds
Started Feb 25 02:43:21 PM PST 24
Finished Feb 25 02:43:22 PM PST 24
Peak memory 204940 kb
Host smart-87fdd607-6cf7-4bd1-a99b-1aebe14d4d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643484879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1643484879
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3970771167
Short name T941
Test name
Test status
Simulation time 528506748 ps
CPU time 1.12 seconds
Started Feb 25 02:43:22 PM PST 24
Finished Feb 25 02:43:23 PM PST 24
Peak memory 205976 kb
Host smart-846c3103-2176-4147-9c5c-0e98eacd710a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970771167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3970771167
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2296822785
Short name T917
Test name
Test status
Simulation time 386787010 ps
CPU time 2.31 seconds
Started Feb 25 02:43:32 PM PST 24
Finished Feb 25 02:43:35 PM PST 24
Peak memory 215860 kb
Host smart-081370f7-94af-430f-acad-44831dcbf12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296822785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2296822785
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.422497142
Short name T280
Test name
Test status
Simulation time 105880886 ps
CPU time 2.72 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:43:31 PM PST 24
Peak memory 233012 kb
Host smart-011f646e-5901-4835-928b-d52ab1865afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422497142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.422497142
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1023062144
Short name T533
Test name
Test status
Simulation time 56431697 ps
CPU time 0.82 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:31 PM PST 24
Peak memory 205692 kb
Host smart-e3c0fb87-8fb2-4776-86d5-33900b369cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023062144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1023062144
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2582852070
Short name T428
Test name
Test status
Simulation time 26105106582 ps
CPU time 148.78 seconds
Started Feb 25 02:43:22 PM PST 24
Finished Feb 25 02:45:51 PM PST 24
Peak memory 256696 kb
Host smart-c7251a5e-1d2d-4004-986e-4ee011523769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582852070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2582852070
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3708669531
Short name T447
Test name
Test status
Simulation time 158820891151 ps
CPU time 151.94 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:45:57 PM PST 24
Peak memory 252888 kb
Host smart-4198fbb9-e651-49d9-971f-b1dea0674ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708669531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3708669531
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3505431008
Short name T885
Test name
Test status
Simulation time 12175557789 ps
CPU time 33.27 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:58 PM PST 24
Peak memory 251176 kb
Host smart-673996d8-8815-4cff-b8b3-43d9fcad4a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505431008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3505431008
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3976758805
Short name T512
Test name
Test status
Simulation time 895576754 ps
CPU time 3.55 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:43:32 PM PST 24
Peak memory 232668 kb
Host smart-b5d7407e-dc71-47f5-987d-aa75e36f7916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976758805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3976758805
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2977184961
Short name T539
Test name
Test status
Simulation time 60493905164 ps
CPU time 37.57 seconds
Started Feb 25 02:43:31 PM PST 24
Finished Feb 25 02:44:09 PM PST 24
Peak memory 234484 kb
Host smart-679f7141-c470-4e68-b8b5-ec0440b35e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977184961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2977184961
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2129563902
Short name T793
Test name
Test status
Simulation time 122354921 ps
CPU time 1.09 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:31 PM PST 24
Peak memory 216080 kb
Host smart-43a2c6e9-0b14-4150-9fde-aec5e996662a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129563902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2129563902
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1262963370
Short name T399
Test name
Test status
Simulation time 3848734361 ps
CPU time 6.09 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:43:34 PM PST 24
Peak memory 233136 kb
Host smart-283753c2-4d1a-4e91-95e6-f4454f970c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262963370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1262963370
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1397068392
Short name T371
Test name
Test status
Simulation time 5140076573 ps
CPU time 11.37 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:41 PM PST 24
Peak memory 233840 kb
Host smart-818f7645-17b3-46bf-b120-14cd03d073d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397068392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1397068392
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.94407364
Short name T564
Test name
Test status
Simulation time 23629811 ps
CPU time 0.74 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:43:24 PM PST 24
Peak memory 215704 kb
Host smart-375c8a13-3d9d-4f43-b6ee-37770bba45f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94407364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.94407364
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.927841475
Short name T887
Test name
Test status
Simulation time 1244701752 ps
CPU time 4.25 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:43:34 PM PST 24
Peak memory 221320 kb
Host smart-c6e3f7ea-5433-46a9-9013-d41ff897e9cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=927841475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.927841475
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.291687545
Short name T953
Test name
Test status
Simulation time 5850030369 ps
CPU time 34.31 seconds
Started Feb 25 02:43:22 PM PST 24
Finished Feb 25 02:43:56 PM PST 24
Peak memory 215892 kb
Host smart-dc5714bf-4e58-4cee-a10b-a0bb5f9b7b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291687545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.291687545
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3270117307
Short name T337
Test name
Test status
Simulation time 12704965598 ps
CPU time 20 seconds
Started Feb 25 02:43:22 PM PST 24
Finished Feb 25 02:43:42 PM PST 24
Peak memory 216472 kb
Host smart-4ede7137-b402-4098-9524-e6292392b76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270117307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3270117307
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1096998455
Short name T660
Test name
Test status
Simulation time 535450549 ps
CPU time 2.09 seconds
Started Feb 25 02:43:21 PM PST 24
Finished Feb 25 02:43:23 PM PST 24
Peak memory 215876 kb
Host smart-aff9169f-eb6d-4a7d-bfd0-cab46ba03d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096998455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1096998455
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.935614291
Short name T586
Test name
Test status
Simulation time 67759122 ps
CPU time 0.87 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:43:29 PM PST 24
Peak memory 204940 kb
Host smart-09fc5adc-b153-454f-a5c9-d4336d0ae8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935614291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.935614291
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4081287229
Short name T273
Test name
Test status
Simulation time 54835646455 ps
CPU time 35.93 seconds
Started Feb 25 02:43:26 PM PST 24
Finished Feb 25 02:44:02 PM PST 24
Peak memory 228300 kb
Host smart-0856df67-215c-4e95-a8d2-e4e5038cad40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081287229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4081287229
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3152686705
Short name T767
Test name
Test status
Simulation time 39333636 ps
CPU time 0.69 seconds
Started Feb 25 02:43:37 PM PST 24
Finished Feb 25 02:43:37 PM PST 24
Peak memory 203964 kb
Host smart-8a6174a5-ba3c-4621-85f6-0e4df4a6af11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152686705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3152686705
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1013492488
Short name T549
Test name
Test status
Simulation time 1518950244 ps
CPU time 6.5 seconds
Started Feb 25 02:43:27 PM PST 24
Finished Feb 25 02:43:34 PM PST 24
Peak memory 224068 kb
Host smart-a251b4fe-d069-4aa7-ab84-1ab47409d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013492488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1013492488
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.799866396
Short name T118
Test name
Test status
Simulation time 16432761 ps
CPU time 0.78 seconds
Started Feb 25 02:43:27 PM PST 24
Finished Feb 25 02:43:29 PM PST 24
Peak memory 205680 kb
Host smart-18f18f6f-1b41-43e9-bba7-a699a39776c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799866396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.799866396
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3316829731
Short name T935
Test name
Test status
Simulation time 127240053137 ps
CPU time 237.92 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:47:27 PM PST 24
Peak memory 273292 kb
Host smart-75e9d975-2d2e-44d8-8de0-0d8e38515ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316829731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3316829731
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2909693231
Short name T10
Test name
Test status
Simulation time 1178130435 ps
CPU time 16.51 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:42 PM PST 24
Peak memory 221628 kb
Host smart-db3b550f-b159-4933-a241-0028cc746651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909693231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2909693231
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3365855135
Short name T734
Test name
Test status
Simulation time 2582011430 ps
CPU time 7.17 seconds
Started Feb 25 02:43:37 PM PST 24
Finished Feb 25 02:43:44 PM PST 24
Peak memory 233292 kb
Host smart-937c3e84-8e9a-4d0f-a2ca-b93580ee7c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365855135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3365855135
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3431937054
Short name T950
Test name
Test status
Simulation time 2043558272 ps
CPU time 6.68 seconds
Started Feb 25 02:43:37 PM PST 24
Finished Feb 25 02:43:43 PM PST 24
Peak memory 240156 kb
Host smart-bb45ef24-1058-4617-8397-51b6168933fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431937054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3431937054
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1056881557
Short name T809
Test name
Test status
Simulation time 52099402 ps
CPU time 1.12 seconds
Started Feb 25 02:43:35 PM PST 24
Finished Feb 25 02:43:37 PM PST 24
Peak memory 217276 kb
Host smart-b2bb39ba-33d1-4207-afaf-3d8622454851
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056881557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1056881557
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4196628978
Short name T763
Test name
Test status
Simulation time 1464892984 ps
CPU time 3 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:43:32 PM PST 24
Peak memory 217048 kb
Host smart-945baad9-ef79-4615-9618-5f5eedba4e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196628978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4196628978
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1246732836
Short name T787
Test name
Test status
Simulation time 122760605170 ps
CPU time 24.78 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:43:58 PM PST 24
Peak memory 240060 kb
Host smart-cdceb3b5-663c-4121-85ec-8f6491f373de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246732836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1246732836
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.1081891895
Short name T642
Test name
Test status
Simulation time 43943047 ps
CPU time 0.71 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:26 PM PST 24
Peak memory 215712 kb
Host smart-77de8ce7-49c1-4cbb-bc9d-2283473c33ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081891895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.1081891895
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3216463504
Short name T557
Test name
Test status
Simulation time 479842355 ps
CPU time 3.55 seconds
Started Feb 25 02:43:32 PM PST 24
Finished Feb 25 02:43:36 PM PST 24
Peak memory 221596 kb
Host smart-d5048fd6-6cf3-4052-9a41-f15b10ee6b21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3216463504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3216463504
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.342778564
Short name T327
Test name
Test status
Simulation time 59870485 ps
CPU time 1.16 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:43:31 PM PST 24
Peak memory 206368 kb
Host smart-152a8681-ba55-4a39-b006-0123a58d30be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342778564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.342778564
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3015162991
Short name T289
Test name
Test status
Simulation time 63343159947 ps
CPU time 51.31 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:44:19 PM PST 24
Peak memory 215820 kb
Host smart-49af7338-dece-4a02-bffb-c7e73a875b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015162991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3015162991
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2338646383
Short name T528
Test name
Test status
Simulation time 38240495182 ps
CPU time 14.33 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:39 PM PST 24
Peak memory 215984 kb
Host smart-c26ab678-284f-4766-9727-c091bf49b58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338646383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2338646383
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2678101556
Short name T351
Test name
Test status
Simulation time 446041403 ps
CPU time 4.16 seconds
Started Feb 25 02:43:35 PM PST 24
Finished Feb 25 02:43:40 PM PST 24
Peak memory 215712 kb
Host smart-109319fe-4052-400a-8a5d-56f3eb4ee873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678101556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2678101556
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1819555248
Short name T480
Test name
Test status
Simulation time 1734248406 ps
CPU time 1.09 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:43:34 PM PST 24
Peak memory 206000 kb
Host smart-6b7a38de-e580-411f-a5e2-b549df72d918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819555248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1819555248
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.4000438590
Short name T828
Test name
Test status
Simulation time 48330277474 ps
CPU time 17.44 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:43:40 PM PST 24
Peak memory 232368 kb
Host smart-2ed5e5af-a60d-498c-9751-cff8127435a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000438590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.4000438590
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3630743239
Short name T905
Test name
Test status
Simulation time 27745467 ps
CPU time 0.71 seconds
Started Feb 25 02:43:31 PM PST 24
Finished Feb 25 02:43:32 PM PST 24
Peak memory 204568 kb
Host smart-f8bff6cb-f738-4123-bf58-f12a71d178ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630743239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3630743239
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2034195458
Short name T186
Test name
Test status
Simulation time 302410337 ps
CPU time 2.36 seconds
Started Feb 25 02:43:26 PM PST 24
Finished Feb 25 02:43:28 PM PST 24
Peak memory 217920 kb
Host smart-39954513-062f-4da4-87d3-53c94d69e4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034195458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2034195458
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2643752205
Short name T566
Test name
Test status
Simulation time 45406172 ps
CPU time 0.75 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:31 PM PST 24
Peak memory 205032 kb
Host smart-24a30c75-394b-4735-bdb1-05e648749d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643752205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2643752205
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3208885878
Short name T243
Test name
Test status
Simulation time 133182102936 ps
CPU time 140.36 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:45:49 PM PST 24
Peak memory 256308 kb
Host smart-e133a595-3a3c-40e9-b17a-830f0bc6d024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208885878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3208885878
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2303796528
Short name T871
Test name
Test status
Simulation time 95930010191 ps
CPU time 47.84 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:44:11 PM PST 24
Peak memory 234428 kb
Host smart-03ae3f70-5e8e-4108-9636-79c0079f2398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303796528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2303796528
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1925935104
Short name T733
Test name
Test status
Simulation time 5475508942 ps
CPU time 28.52 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:58 PM PST 24
Peak memory 232288 kb
Host smart-91778146-6ce8-4075-990d-a3674ae4d1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925935104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1925935104
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2961787620
Short name T760
Test name
Test status
Simulation time 559268636 ps
CPU time 4.27 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:35 PM PST 24
Peak memory 233208 kb
Host smart-fc193b33-9551-4ecc-99c2-b8176e5ff699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961787620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2961787620
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3830278974
Short name T276
Test name
Test status
Simulation time 37930971733 ps
CPU time 24.78 seconds
Started Feb 25 02:43:37 PM PST 24
Finished Feb 25 02:44:02 PM PST 24
Peak memory 231176 kb
Host smart-1dae8fa8-b4ee-4b66-a197-6478d23ac0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830278974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3830278974
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2675169935
Short name T690
Test name
Test status
Simulation time 29376517 ps
CPU time 1.12 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:43:24 PM PST 24
Peak memory 216124 kb
Host smart-e36d5151-582d-408f-9e8b-eaad29d3b635
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675169935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2675169935
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.835261155
Short name T726
Test name
Test status
Simulation time 2426193017 ps
CPU time 6.63 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:36 PM PST 24
Peak memory 236512 kb
Host smart-750555f6-c44b-4c1f-a35b-d6626ee8bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835261155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.835261155
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.442975260
Short name T40
Test name
Test status
Simulation time 89174566 ps
CPU time 0.7 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:43:30 PM PST 24
Peak memory 215584 kb
Host smart-789195eb-b2ab-44f8-9909-94736f388b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442975260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.442975260
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.168553976
Short name T130
Test name
Test status
Simulation time 210293136 ps
CPU time 4.53 seconds
Started Feb 25 02:43:35 PM PST 24
Finished Feb 25 02:43:40 PM PST 24
Peak memory 221632 kb
Host smart-c47af45c-28a8-40e3-a003-dd749db696ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=168553976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.168553976
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.373945893
Short name T353
Test name
Test status
Simulation time 4057416339 ps
CPU time 29.06 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:44:03 PM PST 24
Peak memory 215320 kb
Host smart-c388238b-9b53-4bd6-89ab-1fc1057005c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373945893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.373945893
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2734659042
Short name T614
Test name
Test status
Simulation time 9386867023 ps
CPU time 8.3 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:39 PM PST 24
Peak memory 215816 kb
Host smart-400b2d36-e2ae-4187-b783-06bc11f8e038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734659042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2734659042
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4175766048
Short name T326
Test name
Test status
Simulation time 77018179 ps
CPU time 1.83 seconds
Started Feb 25 02:43:27 PM PST 24
Finished Feb 25 02:43:30 PM PST 24
Peak memory 217132 kb
Host smart-3aeb875a-7aad-45d8-af30-3b451a1d918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175766048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4175766048
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.860298566
Short name T381
Test name
Test status
Simulation time 155337979 ps
CPU time 1.09 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:31 PM PST 24
Peak memory 205316 kb
Host smart-f6e9c09e-9a99-4de0-b7c1-8f0beb62a430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860298566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.860298566
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3083635003
Short name T382
Test name
Test status
Simulation time 1237855364 ps
CPU time 5.86 seconds
Started Feb 25 02:43:37 PM PST 24
Finished Feb 25 02:43:43 PM PST 24
Peak memory 240416 kb
Host smart-7c1e1085-c7d9-4b64-ad1c-234c81eb10c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083635003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3083635003
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.230251078
Short name T322
Test name
Test status
Simulation time 11301698 ps
CPU time 0.7 seconds
Started Feb 25 02:43:27 PM PST 24
Finished Feb 25 02:43:28 PM PST 24
Peak memory 204076 kb
Host smart-08efaf0a-1dc4-46e3-a0f0-07fcb1ab64dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230251078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.230251078
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1941100622
Short name T554
Test name
Test status
Simulation time 468711489 ps
CPU time 5.32 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:43:39 PM PST 24
Peak memory 234156 kb
Host smart-396b8184-f423-4ca8-83f3-723aa08eb21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941100622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1941100622
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2235654969
Short name T848
Test name
Test status
Simulation time 52671820 ps
CPU time 0.72 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:43:34 PM PST 24
Peak memory 205056 kb
Host smart-f6a44bb2-30d6-41b7-ad72-55d4fd69b4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235654969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2235654969
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3557570117
Short name T588
Test name
Test status
Simulation time 3533168635 ps
CPU time 37.76 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:44:03 PM PST 24
Peak memory 250780 kb
Host smart-cbf79451-0ed3-49ce-9be6-667258a24eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557570117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3557570117
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3269985407
Short name T64
Test name
Test status
Simulation time 22015715860 ps
CPU time 205.23 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:46:51 PM PST 24
Peak memory 264972 kb
Host smart-558a1b11-3b31-484a-b782-f0ebc0ea064c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269985407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3269985407
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.471463025
Short name T624
Test name
Test status
Simulation time 2173959728 ps
CPU time 5.69 seconds
Started Feb 25 02:43:37 PM PST 24
Finished Feb 25 02:43:43 PM PST 24
Peak memory 224100 kb
Host smart-87b7f759-d765-4bfa-a9e0-1f43bbc2114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471463025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.471463025
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1991428026
Short name T775
Test name
Test status
Simulation time 1004882243 ps
CPU time 15.97 seconds
Started Feb 25 02:43:24 PM PST 24
Finished Feb 25 02:43:41 PM PST 24
Peak memory 238600 kb
Host smart-cf7c4a87-d011-4baf-8b70-05b493207f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991428026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1991428026
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2509611046
Short name T24
Test name
Test status
Simulation time 29230699 ps
CPU time 1 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:43:30 PM PST 24
Peak memory 217356 kb
Host smart-ca603bbf-8f98-4a21-91be-cf161af68670
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509611046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2509611046
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2334826572
Short name T439
Test name
Test status
Simulation time 4123817702 ps
CPU time 6.25 seconds
Started Feb 25 02:43:27 PM PST 24
Finished Feb 25 02:43:34 PM PST 24
Peak memory 223788 kb
Host smart-d7390270-9079-447a-8664-480828e8c9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334826572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2334826572
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1375952800
Short name T529
Test name
Test status
Simulation time 331036822 ps
CPU time 6.35 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:43:40 PM PST 24
Peak memory 233252 kb
Host smart-bb04410b-53b5-430b-90d0-c6f450799147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375952800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1375952800
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1138488135
Short name T551
Test name
Test status
Simulation time 17785241 ps
CPU time 0.77 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:31 PM PST 24
Peak memory 215664 kb
Host smart-cdb181b3-2159-4e15-9dba-b1edf3b65ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138488135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1138488135
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2971050946
Short name T757
Test name
Test status
Simulation time 177902011 ps
CPU time 3.83 seconds
Started Feb 25 02:43:31 PM PST 24
Finished Feb 25 02:43:35 PM PST 24
Peak memory 222108 kb
Host smart-afa2e4de-6e71-4371-9c1a-e0599616d78f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2971050946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2971050946
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4261001732
Short name T744
Test name
Test status
Simulation time 7750149476 ps
CPU time 25.4 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:43:54 PM PST 24
Peak memory 215864 kb
Host smart-0ae38501-cefb-49d5-8141-fe20df573f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261001732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4261001732
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3703180040
Short name T749
Test name
Test status
Simulation time 9606418176 ps
CPU time 10.38 seconds
Started Feb 25 02:43:30 PM PST 24
Finished Feb 25 02:43:40 PM PST 24
Peak memory 215844 kb
Host smart-192df366-6f25-4bfc-8f8e-957d7f71007d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703180040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3703180040
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.235164231
Short name T559
Test name
Test status
Simulation time 39220618 ps
CPU time 1.66 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:43:35 PM PST 24
Peak memory 215876 kb
Host smart-84edd816-7741-49ef-9d54-2592a8fd118b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235164231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.235164231
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1224466098
Short name T916
Test name
Test status
Simulation time 148289510 ps
CPU time 0.82 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:43:29 PM PST 24
Peak memory 204944 kb
Host smart-2c515a8e-8044-4e43-a171-35a027818b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224466098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1224466098
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.263640617
Short name T325
Test name
Test status
Simulation time 14929579707 ps
CPU time 23.43 seconds
Started Feb 25 02:43:22 PM PST 24
Finished Feb 25 02:43:45 PM PST 24
Peak memory 216980 kb
Host smart-d1f4db84-1ab2-419e-9eaa-048ad91e7f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263640617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.263640617
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3997180113
Short name T627
Test name
Test status
Simulation time 14257532 ps
CPU time 0.73 seconds
Started Feb 25 02:43:40 PM PST 24
Finished Feb 25 02:43:41 PM PST 24
Peak memory 204516 kb
Host smart-ff2d0041-6120-40ee-8eca-c29f074517d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997180113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3997180113
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.402359140
Short name T568
Test name
Test status
Simulation time 3970698325 ps
CPU time 6.95 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:51 PM PST 24
Peak memory 239060 kb
Host smart-fa66a69c-a131-4ed9-a258-6717e7f80a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402359140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.402359140
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.472136339
Short name T374
Test name
Test status
Simulation time 109675254 ps
CPU time 0.76 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:43:34 PM PST 24
Peak memory 205728 kb
Host smart-2d47c3ce-bc5a-4555-8b95-2612808ef67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472136339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.472136339
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.917956360
Short name T240
Test name
Test status
Simulation time 29115787531 ps
CPU time 42.67 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:44:24 PM PST 24
Peak memory 240172 kb
Host smart-6ad5c5f2-bed3-4c6e-b24a-a156a48845ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917956360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.917956360
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.4274603661
Short name T750
Test name
Test status
Simulation time 45898205834 ps
CPU time 271.57 seconds
Started Feb 25 02:43:39 PM PST 24
Finished Feb 25 02:48:11 PM PST 24
Peak memory 261660 kb
Host smart-3b6832ea-ff4e-404d-8dbf-0d8e2232bb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274603661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4274603661
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4183922071
Short name T67
Test name
Test status
Simulation time 99322914552 ps
CPU time 300.92 seconds
Started Feb 25 02:43:40 PM PST 24
Finished Feb 25 02:48:46 PM PST 24
Peak memory 254860 kb
Host smart-e944a331-40c9-4c86-8993-4417f731bc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183922071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4183922071
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.4170782658
Short name T538
Test name
Test status
Simulation time 8630986369 ps
CPU time 14.72 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:43:56 PM PST 24
Peak memory 224124 kb
Host smart-e2da03d7-7f85-4584-a16e-a636258d3dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170782658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4170782658
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2399224375
Short name T531
Test name
Test status
Simulation time 585761594 ps
CPU time 5.08 seconds
Started Feb 25 02:43:40 PM PST 24
Finished Feb 25 02:43:46 PM PST 24
Peak memory 219304 kb
Host smart-5b624d71-74ed-4c5e-9797-bc8e62557c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399224375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2399224375
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3637195555
Short name T672
Test name
Test status
Simulation time 3109118052 ps
CPU time 9.49 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:43:51 PM PST 24
Peak memory 248664 kb
Host smart-698dd043-f924-4f59-b6a0-dd1845e40eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637195555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3637195555
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3134276132
Short name T461
Test name
Test status
Simulation time 79020720 ps
CPU time 1.11 seconds
Started Feb 25 02:43:31 PM PST 24
Finished Feb 25 02:43:32 PM PST 24
Peak memory 216144 kb
Host smart-14576cc8-c976-4415-9fbb-fb73b4cf2095
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134276132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3134276132
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2528175145
Short name T825
Test name
Test status
Simulation time 2125917222 ps
CPU time 8.87 seconds
Started Feb 25 02:43:42 PM PST 24
Finished Feb 25 02:43:51 PM PST 24
Peak memory 234496 kb
Host smart-3fadb703-e679-4977-b50c-3f36e80ece8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528175145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2528175145
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3511999339
Short name T158
Test name
Test status
Simulation time 5374730351 ps
CPU time 19 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:44:03 PM PST 24
Peak memory 248188 kb
Host smart-50f3082f-fe29-4ac5-9ba5-a8a9a5b26445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511999339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3511999339
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.547141246
Short name T681
Test name
Test status
Simulation time 46506701 ps
CPU time 0.75 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:26 PM PST 24
Peak memory 215712 kb
Host smart-1b4327d8-3158-4b2a-903b-b2801410b788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547141246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.547141246
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2465423943
Short name T877
Test name
Test status
Simulation time 1389591278 ps
CPU time 4.1 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:48 PM PST 24
Peak memory 218324 kb
Host smart-17f9415f-68ea-4bd9-8a87-5196bcc65585
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2465423943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2465423943
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1603087470
Short name T37
Test name
Test status
Simulation time 68927444923 ps
CPU time 74.5 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:44:56 PM PST 24
Peak memory 240560 kb
Host smart-7b8401b6-390a-48a4-959e-0d30940676b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603087470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1603087470
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3126918573
Short name T748
Test name
Test status
Simulation time 15435596641 ps
CPU time 75.56 seconds
Started Feb 25 02:43:31 PM PST 24
Finished Feb 25 02:44:47 PM PST 24
Peak memory 215836 kb
Host smart-d5578841-37d7-451a-80af-d87babf1b423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126918573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3126918573
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.774803798
Short name T866
Test name
Test status
Simulation time 3588988246 ps
CPU time 4.84 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:43:38 PM PST 24
Peak memory 215928 kb
Host smart-2fa088b4-309a-4b1e-8835-97f6e2d95028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774803798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.774803798
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1138755214
Short name T292
Test name
Test status
Simulation time 140094932 ps
CPU time 1.27 seconds
Started Feb 25 02:43:31 PM PST 24
Finished Feb 25 02:43:32 PM PST 24
Peak memory 215776 kb
Host smart-fcf9eca1-28af-42ad-8f57-d32ccaabcf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138755214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1138755214
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3306113813
Short name T5
Test name
Test status
Simulation time 149304069 ps
CPU time 0.94 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:26 PM PST 24
Peak memory 205948 kb
Host smart-31b3b216-448c-4c12-9571-13dc097aea78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306113813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3306113813
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4046787395
Short name T875
Test name
Test status
Simulation time 38454299 ps
CPU time 2.44 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:43:44 PM PST 24
Peak memory 224104 kb
Host smart-f06dcacd-db56-471c-8087-45f58cefa6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046787395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4046787395
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.288801242
Short name T572
Test name
Test status
Simulation time 12753136 ps
CPU time 0.71 seconds
Started Feb 25 02:43:40 PM PST 24
Finished Feb 25 02:43:41 PM PST 24
Peak memory 204524 kb
Host smart-5f2be0ad-07e3-48bd-994d-40909c5afb21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288801242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.288801242
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3728509337
Short name T834
Test name
Test status
Simulation time 615665867 ps
CPU time 3.86 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:43:45 PM PST 24
Peak memory 217216 kb
Host smart-29bf821e-2f5f-4118-a215-c7ae81c78d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728509337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3728509337
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2840239662
Short name T3
Test name
Test status
Simulation time 89758005 ps
CPU time 0.75 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:45 PM PST 24
Peak memory 205704 kb
Host smart-6ecad236-e3f2-411e-ac1c-9c8fde41a741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840239662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2840239662
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3732563419
Short name T746
Test name
Test status
Simulation time 10606573555 ps
CPU time 65.85 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:44:47 PM PST 24
Peak memory 261028 kb
Host smart-00272993-85d0-434c-be17-32e145849408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732563419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3732563419
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3253041609
Short name T502
Test name
Test status
Simulation time 3321317628 ps
CPU time 11.17 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:55 PM PST 24
Peak memory 220180 kb
Host smart-873388f1-1824-4523-a8ac-10711b5a0f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253041609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3253041609
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1988714651
Short name T203
Test name
Test status
Simulation time 110615796007 ps
CPU time 394.24 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:50:16 PM PST 24
Peak memory 262340 kb
Host smart-cf81753b-d916-451f-9648-db4e610e6f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988714651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1988714651
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.710761103
Short name T884
Test name
Test status
Simulation time 1086248094 ps
CPU time 6.42 seconds
Started Feb 25 02:43:37 PM PST 24
Finished Feb 25 02:43:44 PM PST 24
Peak memory 238464 kb
Host smart-854e8505-bd9b-4e13-8b6a-bcfea18d8867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710761103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.710761103
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.943518825
Short name T176
Test name
Test status
Simulation time 1463735924 ps
CPU time 7.74 seconds
Started Feb 25 02:43:38 PM PST 24
Finished Feb 25 02:43:46 PM PST 24
Peak memory 234616 kb
Host smart-8549e70b-d15a-4573-8cb4-6038756a566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943518825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.943518825
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4152946350
Short name T198
Test name
Test status
Simulation time 8449207549 ps
CPU time 14.33 seconds
Started Feb 25 02:43:36 PM PST 24
Finished Feb 25 02:43:50 PM PST 24
Peak memory 230728 kb
Host smart-4705cb54-541f-4456-a4dc-95da687add80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152946350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4152946350
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2813887193
Short name T609
Test name
Test status
Simulation time 31947517 ps
CPU time 1.11 seconds
Started Feb 25 02:43:38 PM PST 24
Finished Feb 25 02:43:40 PM PST 24
Peak memory 216076 kb
Host smart-33724423-3e33-48a8-8c42-9ce79771e95d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813887193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2813887193
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4150439798
Short name T196
Test name
Test status
Simulation time 3849704494 ps
CPU time 11.06 seconds
Started Feb 25 02:43:50 PM PST 24
Finished Feb 25 02:44:01 PM PST 24
Peak memory 224020 kb
Host smart-5e8addf4-0718-4eea-8ad3-88ae0644bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150439798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4150439798
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1134587867
Short name T610
Test name
Test status
Simulation time 9626311658 ps
CPU time 16.64 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:43:58 PM PST 24
Peak memory 245932 kb
Host smart-ad3acafa-d256-4a4e-8a42-a0316f71730d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134587867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1134587867
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.1122321233
Short name T864
Test name
Test status
Simulation time 15073838 ps
CPU time 0.75 seconds
Started Feb 25 02:43:39 PM PST 24
Finished Feb 25 02:43:40 PM PST 24
Peak memory 215712 kb
Host smart-efe84258-6ced-4184-b1bb-1310588e23de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122321233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.1122321233
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.503317586
Short name T483
Test name
Test status
Simulation time 2971473335 ps
CPU time 7.7 seconds
Started Feb 25 02:43:42 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 222216 kb
Host smart-a61cf541-b60c-4efa-aded-283463b30c42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=503317586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.503317586
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3039710769
Short name T777
Test name
Test status
Simulation time 72751191 ps
CPU time 1.23 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:45 PM PST 24
Peak memory 206284 kb
Host smart-6756744a-2db4-4659-981e-aa31ac48dd51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039710769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3039710769
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2617991893
Short name T437
Test name
Test status
Simulation time 720473144 ps
CPU time 5.53 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:50 PM PST 24
Peak memory 207576 kb
Host smart-a82f6a1b-a12d-47f8-af90-0910598c7c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617991893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2617991893
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3876708777
Short name T752
Test name
Test status
Simulation time 39184217 ps
CPU time 0.86 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:43:42 PM PST 24
Peak memory 205452 kb
Host smart-ca060a06-dc51-4064-9ce4-05eb08ee81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876708777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3876708777
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.184787421
Short name T821
Test name
Test status
Simulation time 99520182 ps
CPU time 1 seconds
Started Feb 25 02:43:41 PM PST 24
Finished Feb 25 02:43:43 PM PST 24
Peak memory 205236 kb
Host smart-07fc9684-40a8-4890-a76d-c42188486749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184787421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.184787421
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.826227450
Short name T817
Test name
Test status
Simulation time 2522026818 ps
CPU time 7.79 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:52 PM PST 24
Peak memory 233696 kb
Host smart-ecf6ebf2-f30b-4f64-a904-2e7472b308b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826227450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.826227450
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2507138447
Short name T639
Test name
Test status
Simulation time 15189764 ps
CPU time 0.7 seconds
Started Feb 25 02:43:46 PM PST 24
Finished Feb 25 02:43:47 PM PST 24
Peak memory 204532 kb
Host smart-f965acec-cd03-40ce-b5b5-f8c64f4134c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507138447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2507138447
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.896672844
Short name T667
Test name
Test status
Simulation time 833408770 ps
CPU time 2.95 seconds
Started Feb 25 02:43:45 PM PST 24
Finished Feb 25 02:43:48 PM PST 24
Peak memory 224036 kb
Host smart-fa2c099c-4925-4560-8c6c-ecbeaf24b79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896672844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.896672844
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.354039961
Short name T927
Test name
Test status
Simulation time 57194154 ps
CPU time 0.74 seconds
Started Feb 25 02:43:39 PM PST 24
Finished Feb 25 02:43:40 PM PST 24
Peak memory 205008 kb
Host smart-95871530-2313-45e9-b132-599688b141bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354039961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.354039961
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.952964157
Short name T918
Test name
Test status
Simulation time 25097984073 ps
CPU time 66.1 seconds
Started Feb 25 02:43:52 PM PST 24
Finished Feb 25 02:44:58 PM PST 24
Peak memory 255076 kb
Host smart-4bce740b-8c73-4b14-848b-bf4b76e70340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952964157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.952964157
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1535272763
Short name T727
Test name
Test status
Simulation time 34615466751 ps
CPU time 57.34 seconds
Started Feb 25 02:43:47 PM PST 24
Finished Feb 25 02:44:45 PM PST 24
Peak memory 252904 kb
Host smart-859429fb-588d-4c60-af0a-8acd051a5985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535272763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1535272763
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2615631557
Short name T120
Test name
Test status
Simulation time 16053724061 ps
CPU time 46.39 seconds
Started Feb 25 02:43:58 PM PST 24
Finished Feb 25 02:44:45 PM PST 24
Peak memory 251952 kb
Host smart-cf9ca91f-88d8-496f-b2de-dff98261184b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615631557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2615631557
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2446861520
Short name T152
Test name
Test status
Simulation time 1689934716 ps
CPU time 10.41 seconds
Started Feb 25 02:43:51 PM PST 24
Finished Feb 25 02:44:02 PM PST 24
Peak memory 240456 kb
Host smart-f46a52ed-8a1a-4f58-b637-5a3ff4a8c8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446861520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2446861520
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.303566046
Short name T785
Test name
Test status
Simulation time 1225324011 ps
CPU time 3.13 seconds
Started Feb 25 02:43:53 PM PST 24
Finished Feb 25 02:43:56 PM PST 24
Peak memory 217140 kb
Host smart-9c74df17-a44c-480f-8c3a-0983607ccef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303566046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.303566046
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.424341405
Short name T970
Test name
Test status
Simulation time 312182720 ps
CPU time 5.32 seconds
Started Feb 25 02:43:43 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 226952 kb
Host smart-01ff47f6-f350-4145-a0a1-31a145078303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424341405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.424341405
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3258326207
Short name T391
Test name
Test status
Simulation time 68965296 ps
CPU time 1.07 seconds
Started Feb 25 02:43:40 PM PST 24
Finished Feb 25 02:43:41 PM PST 24
Peak memory 216120 kb
Host smart-56658fb5-8888-4ed3-894d-10120ca0c4f6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258326207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3258326207
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4151847757
Short name T230
Test name
Test status
Simulation time 42584975036 ps
CPU time 56.24 seconds
Started Feb 25 02:43:52 PM PST 24
Finished Feb 25 02:44:48 PM PST 24
Peak memory 233520 kb
Host smart-889b23a6-a255-4a51-80d6-c2e6f8edf05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151847757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4151847757
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1191319779
Short name T49
Test name
Test status
Simulation time 33418496852 ps
CPU time 5.84 seconds
Started Feb 25 02:43:43 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 232288 kb
Host smart-bbeed341-5893-4c4a-b1fc-00948d7615f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191319779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1191319779
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.1384664178
Short name T711
Test name
Test status
Simulation time 16137260 ps
CPU time 0.83 seconds
Started Feb 25 02:43:42 PM PST 24
Finished Feb 25 02:43:43 PM PST 24
Peak memory 215712 kb
Host smart-8668cb9b-08cc-4306-912e-532adffa2030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384664178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.1384664178
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4113829332
Short name T847
Test name
Test status
Simulation time 574011195 ps
CPU time 3.74 seconds
Started Feb 25 02:43:55 PM PST 24
Finished Feb 25 02:43:59 PM PST 24
Peak memory 221636 kb
Host smart-579f3696-7680-4534-80f7-262ccc1a8e96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4113829332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4113829332
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2444563445
Short name T291
Test name
Test status
Simulation time 10926581572 ps
CPU time 56.82 seconds
Started Feb 25 02:43:45 PM PST 24
Finished Feb 25 02:44:42 PM PST 24
Peak memory 215832 kb
Host smart-ba9a640a-afd9-4ee4-b36e-ee4f7632fcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444563445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2444563445
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.383491657
Short name T579
Test name
Test status
Simulation time 12201300098 ps
CPU time 25.03 seconds
Started Feb 25 02:43:39 PM PST 24
Finished Feb 25 02:44:05 PM PST 24
Peak memory 215896 kb
Host smart-9d1f8df0-a7ce-49e3-aed4-86c5703c039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383491657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.383491657
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3346424039
Short name T332
Test name
Test status
Simulation time 175096717 ps
CPU time 2.7 seconds
Started Feb 25 02:43:45 PM PST 24
Finished Feb 25 02:43:48 PM PST 24
Peak memory 215868 kb
Host smart-c5aa3872-8a69-4b16-8215-502d8f478d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346424039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3346424039
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2598514421
Short name T573
Test name
Test status
Simulation time 55474434 ps
CPU time 0.97 seconds
Started Feb 25 02:43:43 PM PST 24
Finished Feb 25 02:43:44 PM PST 24
Peak memory 205968 kb
Host smart-d25d17fb-0693-420e-82e4-c9c0d1cc00d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598514421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2598514421
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.178336476
Short name T341
Test name
Test status
Simulation time 2413548477 ps
CPU time 5.07 seconds
Started Feb 25 02:43:46 PM PST 24
Finished Feb 25 02:43:51 PM PST 24
Peak memory 234876 kb
Host smart-b8af08b4-9962-44cb-8f9c-54c4e6ac02a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178336476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.178336476
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1630879511
Short name T696
Test name
Test status
Simulation time 107317109 ps
CPU time 0.75 seconds
Started Feb 25 02:43:48 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 204528 kb
Host smart-6e50e3de-e92a-4ff5-9516-68b14ecd4a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630879511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1630879511
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4015655587
Short name T691
Test name
Test status
Simulation time 110928982 ps
CPU time 2.38 seconds
Started Feb 25 02:43:46 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 232968 kb
Host smart-c7f5cedc-83c7-4728-9f49-35d5ad2afa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015655587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4015655587
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2026215289
Short name T46
Test name
Test status
Simulation time 55874820 ps
CPU time 0.78 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:45 PM PST 24
Peak memory 204608 kb
Host smart-531d3be3-f6a8-4363-881b-b6d77905c92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026215289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2026215289
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.856218423
Short name T58
Test name
Test status
Simulation time 4375720020 ps
CPU time 58.11 seconds
Started Feb 25 02:43:50 PM PST 24
Finished Feb 25 02:44:49 PM PST 24
Peak memory 248708 kb
Host smart-a4882a87-77a4-4c13-b757-ef6c84b7d3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856218423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.856218423
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2472080101
Short name T831
Test name
Test status
Simulation time 74179655382 ps
CPU time 244.28 seconds
Started Feb 25 02:43:53 PM PST 24
Finished Feb 25 02:47:57 PM PST 24
Peak memory 255932 kb
Host smart-ea0b90d1-5f04-4089-8e51-e3dae290bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472080101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2472080101
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3638359252
Short name T150
Test name
Test status
Simulation time 51521635090 ps
CPU time 111.02 seconds
Started Feb 25 02:43:55 PM PST 24
Finished Feb 25 02:45:46 PM PST 24
Peak memory 252708 kb
Host smart-c23958bd-556a-4140-b512-811b791ba124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638359252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3638359252
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2696828552
Short name T915
Test name
Test status
Simulation time 1897604446 ps
CPU time 10.27 seconds
Started Feb 25 02:43:54 PM PST 24
Finished Feb 25 02:44:05 PM PST 24
Peak memory 236916 kb
Host smart-0049effa-b509-4b53-843f-4af0712ac1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696828552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2696828552
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.672164603
Short name T684
Test name
Test status
Simulation time 2405232101 ps
CPU time 8.75 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:53 PM PST 24
Peak memory 232776 kb
Host smart-9852014e-96d3-410e-80dc-0afcc3f77ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672164603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.672164603
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3239143722
Short name T476
Test name
Test status
Simulation time 1823918750 ps
CPU time 5.54 seconds
Started Feb 25 02:43:45 PM PST 24
Finished Feb 25 02:43:51 PM PST 24
Peak memory 232996 kb
Host smart-f4a818e7-fac2-4cfb-ab18-3fc589cd7d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239143722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3239143722
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1835043403
Short name T876
Test name
Test status
Simulation time 30717245 ps
CPU time 1.07 seconds
Started Feb 25 02:43:54 PM PST 24
Finished Feb 25 02:43:56 PM PST 24
Peak memory 216124 kb
Host smart-32e11071-894b-4beb-a29d-535f3a5e563c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835043403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1835043403
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3171946871
Short name T886
Test name
Test status
Simulation time 7863639121 ps
CPU time 9.72 seconds
Started Feb 25 02:43:46 PM PST 24
Finished Feb 25 02:43:56 PM PST 24
Peak memory 224116 kb
Host smart-2ead76b0-dc90-4776-9d91-f6de6ae69a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171946871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3171946871
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2273974334
Short name T860
Test name
Test status
Simulation time 2092501445 ps
CPU time 4.25 seconds
Started Feb 25 02:43:46 PM PST 24
Finished Feb 25 02:43:51 PM PST 24
Peak memory 233116 kb
Host smart-6f78a8a8-a67f-469f-86d5-09af0c234488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273974334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2273974334
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.1398875929
Short name T38
Test name
Test status
Simulation time 16889215 ps
CPU time 0.75 seconds
Started Feb 25 02:43:48 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 215708 kb
Host smart-17811aa4-7f8e-40cc-90ce-2f91901a7578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398875929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.1398875929
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.622492845
Short name T443
Test name
Test status
Simulation time 4406787656 ps
CPU time 6.75 seconds
Started Feb 25 02:43:49 PM PST 24
Finished Feb 25 02:43:57 PM PST 24
Peak memory 220288 kb
Host smart-4a9986f8-a434-4ecf-b0a9-c8d8035af791
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=622492845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.622492845
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1501868433
Short name T134
Test name
Test status
Simulation time 3416466946 ps
CPU time 63.72 seconds
Started Feb 25 02:44:03 PM PST 24
Finished Feb 25 02:45:07 PM PST 24
Peak memory 251208 kb
Host smart-e077dc22-8def-4f37-83a9-11735c690da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501868433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1501868433
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.826254682
Short name T474
Test name
Test status
Simulation time 3468770190 ps
CPU time 15.46 seconds
Started Feb 25 02:43:47 PM PST 24
Finished Feb 25 02:44:03 PM PST 24
Peak memory 215912 kb
Host smart-49e76bbb-2564-4f71-aed5-082804569565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826254682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.826254682
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.391806393
Short name T903
Test name
Test status
Simulation time 18990911287 ps
CPU time 8.64 seconds
Started Feb 25 02:43:53 PM PST 24
Finished Feb 25 02:44:02 PM PST 24
Peak memory 215896 kb
Host smart-f80cc498-8c23-4d9e-a126-15507478981a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391806393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.391806393
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1626438317
Short name T881
Test name
Test status
Simulation time 68963871 ps
CPU time 2.53 seconds
Started Feb 25 02:43:49 PM PST 24
Finished Feb 25 02:43:52 PM PST 24
Peak memory 215780 kb
Host smart-b45f7c18-114e-49a8-8e7d-8e099c7ea054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626438317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1626438317
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4167413135
Short name T936
Test name
Test status
Simulation time 27848528 ps
CPU time 0.73 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:45 PM PST 24
Peak memory 204936 kb
Host smart-8f28921a-26a6-4217-a450-89629237e876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167413135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4167413135
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.997388351
Short name T264
Test name
Test status
Simulation time 6619391553 ps
CPU time 13.46 seconds
Started Feb 25 02:43:53 PM PST 24
Finished Feb 25 02:44:07 PM PST 24
Peak memory 217720 kb
Host smart-7683c1ac-d25e-415a-8c98-645f529a4a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997388351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.997388351
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1049049635
Short name T824
Test name
Test status
Simulation time 16443052 ps
CPU time 0.82 seconds
Started Feb 25 02:43:58 PM PST 24
Finished Feb 25 02:43:59 PM PST 24
Peak memory 204548 kb
Host smart-e97501ba-2308-4e8e-b734-72d8768fb6c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049049635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1049049635
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.189002235
Short name T149
Test name
Test status
Simulation time 174830019 ps
CPU time 2.75 seconds
Started Feb 25 02:43:47 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 216016 kb
Host smart-b0af878e-b48e-4fca-96d4-9ba46c0371f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189002235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.189002235
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1387232335
Short name T490
Test name
Test status
Simulation time 20660724 ps
CPU time 0.82 seconds
Started Feb 25 02:43:49 PM PST 24
Finished Feb 25 02:43:50 PM PST 24
Peak memory 205716 kb
Host smart-ea58ae60-2b83-4103-a03b-db65af4fbf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387232335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1387232335
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.123134627
Short name T48
Test name
Test status
Simulation time 1463467666 ps
CPU time 14.05 seconds
Started Feb 25 02:43:44 PM PST 24
Finished Feb 25 02:43:58 PM PST 24
Peak memory 240384 kb
Host smart-851c37c6-1ccf-493b-8072-ca29934a49fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123134627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.123134627
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4239636691
Short name T340
Test name
Test status
Simulation time 25760074527 ps
CPU time 64.23 seconds
Started Feb 25 02:43:53 PM PST 24
Finished Feb 25 02:44:57 PM PST 24
Peak memory 234692 kb
Host smart-f52861c4-5056-45cf-a3b0-5225e02fcbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239636691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4239636691
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.178757705
Short name T932
Test name
Test status
Simulation time 4920777227 ps
CPU time 11.68 seconds
Started Feb 25 02:43:45 PM PST 24
Finished Feb 25 02:43:57 PM PST 24
Peak memory 248264 kb
Host smart-2c116b6f-e759-4168-af87-95fb68ef66b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178757705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.178757705
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1100046987
Short name T188
Test name
Test status
Simulation time 5137324963 ps
CPU time 6.6 seconds
Started Feb 25 02:43:53 PM PST 24
Finished Feb 25 02:44:00 PM PST 24
Peak memory 217308 kb
Host smart-f0eb5562-daf4-4d03-b295-96b6fe60e9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100046987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1100046987
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3578557760
Short name T261
Test name
Test status
Simulation time 1329185009 ps
CPU time 7.38 seconds
Started Feb 25 02:43:52 PM PST 24
Finished Feb 25 02:44:00 PM PST 24
Peak memory 235164 kb
Host smart-e6e31639-c0c5-4abd-b1b6-c2066501de11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578557760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3578557760
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1233516260
Short name T633
Test name
Test status
Simulation time 43195266 ps
CPU time 1.09 seconds
Started Feb 25 02:43:48 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 216172 kb
Host smart-55685d02-0a85-48d5-a0d3-da55925c476a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233516260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1233516260
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2156001554
Short name T979
Test name
Test status
Simulation time 9726417293 ps
CPU time 28.73 seconds
Started Feb 25 02:43:50 PM PST 24
Finished Feb 25 02:44:19 PM PST 24
Peak memory 233116 kb
Host smart-fc358622-72b4-4bbe-85cb-4e452aefbb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156001554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2156001554
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1938995506
Short name T83
Test name
Test status
Simulation time 36944340616 ps
CPU time 19.91 seconds
Started Feb 25 02:43:53 PM PST 24
Finished Feb 25 02:44:13 PM PST 24
Peak memory 232852 kb
Host smart-39d32168-4a95-4c83-8e3b-5cd277e002c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938995506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1938995506
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.2035225652
Short name T508
Test name
Test status
Simulation time 18549764 ps
CPU time 0.77 seconds
Started Feb 25 02:43:52 PM PST 24
Finished Feb 25 02:43:53 PM PST 24
Peak memory 215580 kb
Host smart-6b56fa91-51dc-49fe-b65c-f286e99b1b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035225652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2035225652
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2627658780
Short name T129
Test name
Test status
Simulation time 735384539 ps
CPU time 5.2 seconds
Started Feb 25 02:43:58 PM PST 24
Finished Feb 25 02:44:04 PM PST 24
Peak memory 221632 kb
Host smart-69d3078b-8063-4c16-b0f8-5e27252eebb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2627658780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2627658780
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.937226719
Short name T426
Test name
Test status
Simulation time 19096363588 ps
CPU time 28.06 seconds
Started Feb 25 02:43:48 PM PST 24
Finished Feb 25 02:44:16 PM PST 24
Peak memory 215936 kb
Host smart-a59544dd-cbc6-4140-b6c8-542c1b581ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937226719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.937226719
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3765941009
Short name T81
Test name
Test status
Simulation time 1164962419 ps
CPU time 1.94 seconds
Started Feb 25 02:43:54 PM PST 24
Finished Feb 25 02:43:56 PM PST 24
Peak memory 206064 kb
Host smart-e4e0e0b6-ba69-4cf1-ba34-03f104a2dd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765941009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3765941009
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2597537957
Short name T477
Test name
Test status
Simulation time 159332783 ps
CPU time 2.07 seconds
Started Feb 25 02:43:50 PM PST 24
Finished Feb 25 02:43:53 PM PST 24
Peak memory 215860 kb
Host smart-43da2d4a-05e9-473d-bd17-3cc3aeda7710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597537957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2597537957
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.409551716
Short name T735
Test name
Test status
Simulation time 51372612 ps
CPU time 0.76 seconds
Started Feb 25 02:44:03 PM PST 24
Finished Feb 25 02:44:04 PM PST 24
Peak memory 204776 kb
Host smart-58f577f5-df5a-4147-9775-a4dbf9edafbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409551716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.409551716
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1742189865
Short name T636
Test name
Test status
Simulation time 820850261 ps
CPU time 6.28 seconds
Started Feb 25 02:43:50 PM PST 24
Finished Feb 25 02:43:57 PM PST 24
Peak memory 235772 kb
Host smart-214d8478-d4f2-4e68-b255-3d80bc64c140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742189865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1742189865
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1783049518
Short name T901
Test name
Test status
Simulation time 13667459 ps
CPU time 0.74 seconds
Started Feb 25 02:42:59 PM PST 24
Finished Feb 25 02:43:00 PM PST 24
Peak memory 203980 kb
Host smart-2fcb7ac2-ada1-48c2-98d1-6a646163812f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783049518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
783049518
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4081625049
Short name T773
Test name
Test status
Simulation time 1134745474 ps
CPU time 3.01 seconds
Started Feb 25 02:43:07 PM PST 24
Finished Feb 25 02:43:10 PM PST 24
Peak memory 223996 kb
Host smart-4aeb70ef-742c-4246-a16f-6fb532400d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081625049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4081625049
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3302178742
Short name T857
Test name
Test status
Simulation time 21365110 ps
CPU time 0.79 seconds
Started Feb 25 02:43:00 PM PST 24
Finished Feb 25 02:43:02 PM PST 24
Peak memory 205696 kb
Host smart-d10bf362-c3dc-4c74-b369-aea27eb50c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302178742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3302178742
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3773076904
Short name T718
Test name
Test status
Simulation time 25034325539 ps
CPU time 55.74 seconds
Started Feb 25 02:43:02 PM PST 24
Finished Feb 25 02:43:58 PM PST 24
Peak memory 256672 kb
Host smart-b12e9576-434e-4235-b4d8-3f10c99be118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773076904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3773076904
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1949183140
Short name T257
Test name
Test status
Simulation time 2899902219 ps
CPU time 32.4 seconds
Started Feb 25 02:42:54 PM PST 24
Finished Feb 25 02:43:26 PM PST 24
Peak memory 232316 kb
Host smart-896b1306-c678-4230-915a-fa8b64371dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949183140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1949183140
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1525080611
Short name T678
Test name
Test status
Simulation time 10682528623 ps
CPU time 25.4 seconds
Started Feb 25 02:43:06 PM PST 24
Finished Feb 25 02:43:32 PM PST 24
Peak memory 247184 kb
Host smart-24de0f50-9087-438e-bff2-13a7c6a4ff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525080611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1525080611
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.575834073
Short name T455
Test name
Test status
Simulation time 690869786 ps
CPU time 4.17 seconds
Started Feb 25 02:43:08 PM PST 24
Finished Feb 25 02:43:13 PM PST 24
Peak memory 232220 kb
Host smart-d7808166-5d93-4824-a86e-5e8404b39fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575834073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.575834073
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.62718024
Short name T184
Test name
Test status
Simulation time 4023631798 ps
CPU time 6.87 seconds
Started Feb 25 02:43:02 PM PST 24
Finished Feb 25 02:43:09 PM PST 24
Peak memory 232384 kb
Host smart-dacc65a8-582d-4c05-b36b-a612029b8bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62718024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.62718024
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3224103150
Short name T23
Test name
Test status
Simulation time 18029524 ps
CPU time 1.04 seconds
Started Feb 25 02:42:48 PM PST 24
Finished Feb 25 02:42:49 PM PST 24
Peak memory 217380 kb
Host smart-d7216a6f-1cb5-4fde-bdbc-14367f1266da
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224103150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3224103150
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.161149701
Short name T28
Test name
Test status
Simulation time 2360946126 ps
CPU time 5.93 seconds
Started Feb 25 02:43:02 PM PST 24
Finished Feb 25 02:43:08 PM PST 24
Peak memory 237096 kb
Host smart-f4f39386-6059-4dd9-836a-04af544f512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161149701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
161149701
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2193347338
Short name T278
Test name
Test status
Simulation time 213667296 ps
CPU time 2.84 seconds
Started Feb 25 02:43:05 PM PST 24
Finished Feb 25 02:43:08 PM PST 24
Peak memory 233320 kb
Host smart-04df9412-5148-4972-835e-624913afea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193347338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2193347338
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2231629132
Short name T699
Test name
Test status
Simulation time 19085781 ps
CPU time 0.76 seconds
Started Feb 25 02:42:53 PM PST 24
Finished Feb 25 02:42:54 PM PST 24
Peak memory 215708 kb
Host smart-9863599b-2341-4b4d-8af0-a03f11431f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231629132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2231629132
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4117820117
Short name T841
Test name
Test status
Simulation time 1107305917 ps
CPU time 5.48 seconds
Started Feb 25 02:43:00 PM PST 24
Finished Feb 25 02:43:07 PM PST 24
Peak memory 219348 kb
Host smart-33de4c5f-9b7d-4a9a-b776-98f66d0dfce9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4117820117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4117820117
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1034682079
Short name T45
Test name
Test status
Simulation time 123212000 ps
CPU time 1.11 seconds
Started Feb 25 02:43:07 PM PST 24
Finished Feb 25 02:43:08 PM PST 24
Peak memory 235116 kb
Host smart-6f0a02f9-e8d1-419f-92f2-3b1edcd38973
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034682079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1034682079
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4113529972
Short name T138
Test name
Test status
Simulation time 21892685960 ps
CPU time 328.68 seconds
Started Feb 25 02:43:00 PM PST 24
Finished Feb 25 02:48:29 PM PST 24
Peak memory 288744 kb
Host smart-b82b7a21-cb82-4c69-b5f7-81385db146e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113529972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4113529972
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.155999454
Short name T796
Test name
Test status
Simulation time 539544648 ps
CPU time 3.49 seconds
Started Feb 25 02:42:49 PM PST 24
Finished Feb 25 02:42:53 PM PST 24
Peak memory 215668 kb
Host smart-cb8d2608-a013-4c65-ae6a-e40dbe157d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155999454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.155999454
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2288802547
Short name T506
Test name
Test status
Simulation time 7359256086 ps
CPU time 25.79 seconds
Started Feb 25 02:42:49 PM PST 24
Finished Feb 25 02:43:15 PM PST 24
Peak memory 216884 kb
Host smart-d7c52e53-88ae-423f-84c3-beab29cd6e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288802547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2288802547
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1250928891
Short name T755
Test name
Test status
Simulation time 87926072 ps
CPU time 1.12 seconds
Started Feb 25 02:43:00 PM PST 24
Finished Feb 25 02:43:01 PM PST 24
Peak memory 207440 kb
Host smart-08350ef2-36f6-4f6f-ad80-5b21c720db3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250928891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1250928891
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1103710150
Short name T513
Test name
Test status
Simulation time 391315616 ps
CPU time 0.77 seconds
Started Feb 25 02:42:49 PM PST 24
Finished Feb 25 02:42:50 PM PST 24
Peak memory 204820 kb
Host smart-d9166008-86aa-4514-ad8c-ab4acaa4313f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103710150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1103710150
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.668586445
Short name T710
Test name
Test status
Simulation time 1356318098 ps
CPU time 6.63 seconds
Started Feb 25 02:43:00 PM PST 24
Finished Feb 25 02:43:08 PM PST 24
Peak memory 224092 kb
Host smart-2cc843d8-f2ae-49a6-a025-4614990bc773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668586445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.668586445
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4160144598
Short name T458
Test name
Test status
Simulation time 32559459 ps
CPU time 0.78 seconds
Started Feb 25 02:44:02 PM PST 24
Finished Feb 25 02:44:03 PM PST 24
Peak memory 204528 kb
Host smart-c5d006de-4f2d-422b-a10b-cdbaeea73ae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160144598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4160144598
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.196509021
Short name T179
Test name
Test status
Simulation time 1184362976 ps
CPU time 2.66 seconds
Started Feb 25 02:43:58 PM PST 24
Finished Feb 25 02:44:01 PM PST 24
Peak memory 223720 kb
Host smart-30dc6314-478e-4bec-9a99-57d31911a915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196509021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.196509021
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1901542668
Short name T951
Test name
Test status
Simulation time 63354908 ps
CPU time 0.79 seconds
Started Feb 25 02:43:50 PM PST 24
Finished Feb 25 02:43:51 PM PST 24
Peak memory 204652 kb
Host smart-72bb5dd5-b80a-4551-a144-3cfa1502a38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901542668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1901542668
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1537412474
Short name T228
Test name
Test status
Simulation time 18923646479 ps
CPU time 174.96 seconds
Started Feb 25 02:44:06 PM PST 24
Finished Feb 25 02:47:02 PM PST 24
Peak memory 273332 kb
Host smart-b160213c-bbef-4797-af8f-87d63be10dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537412474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1537412474
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.692119167
Short name T219
Test name
Test status
Simulation time 21473294537 ps
CPU time 84.19 seconds
Started Feb 25 02:44:08 PM PST 24
Finished Feb 25 02:45:34 PM PST 24
Peak memory 256600 kb
Host smart-be20e09a-d061-46a7-8a2c-969826164cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692119167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.692119167
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2733995292
Short name T643
Test name
Test status
Simulation time 2748735118 ps
CPU time 9.68 seconds
Started Feb 25 02:44:00 PM PST 24
Finished Feb 25 02:44:10 PM PST 24
Peak memory 224088 kb
Host smart-ed115f57-18ab-4097-a7af-5074dd9f02d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733995292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2733995292
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1129743881
Short name T193
Test name
Test status
Simulation time 4207847857 ps
CPU time 6.43 seconds
Started Feb 25 02:44:07 PM PST 24
Finished Feb 25 02:44:14 PM PST 24
Peak memory 224056 kb
Host smart-8f20dd89-1e44-4818-8eba-4172e6dde828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129743881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1129743881
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1910585437
Short name T779
Test name
Test status
Simulation time 42916340389 ps
CPU time 29.24 seconds
Started Feb 25 02:44:02 PM PST 24
Finished Feb 25 02:44:31 PM PST 24
Peak memory 238900 kb
Host smart-3071ef9c-61bd-4665-9620-3941c577ee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910585437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1910585437
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3209924260
Short name T815
Test name
Test status
Simulation time 53484408408 ps
CPU time 15.03 seconds
Started Feb 25 02:44:02 PM PST 24
Finished Feb 25 02:44:17 PM PST 24
Peak memory 217008 kb
Host smart-4fa874ec-5795-46b4-9425-9e6a1fbc195c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209924260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3209924260
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3331377564
Short name T590
Test name
Test status
Simulation time 16425029500 ps
CPU time 11.04 seconds
Started Feb 25 02:44:03 PM PST 24
Finished Feb 25 02:44:14 PM PST 24
Peak memory 224128 kb
Host smart-af16da50-e25d-40c6-9f55-4cc7c97465e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331377564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3331377564
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3621036827
Short name T683
Test name
Test status
Simulation time 700704591 ps
CPU time 3.56 seconds
Started Feb 25 02:44:00 PM PST 24
Finished Feb 25 02:44:04 PM PST 24
Peak memory 216128 kb
Host smart-a5184af9-ff10-45b3-bff9-67d70ceb640f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3621036827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3621036827
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2018202194
Short name T66
Test name
Test status
Simulation time 249368197888 ps
CPU time 925.8 seconds
Started Feb 25 02:44:00 PM PST 24
Finished Feb 25 02:59:25 PM PST 24
Peak memory 289744 kb
Host smart-9a771cab-20ae-4cda-9b57-f3832c88f932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018202194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2018202194
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1282682134
Short name T104
Test name
Test status
Simulation time 17743460040 ps
CPU time 30.61 seconds
Started Feb 25 02:43:48 PM PST 24
Finished Feb 25 02:44:19 PM PST 24
Peak memory 215888 kb
Host smart-7f9970f7-17ba-4f3f-85d2-05ed72d5e897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282682134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1282682134
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3434624138
Short name T487
Test name
Test status
Simulation time 1906116607 ps
CPU time 3.33 seconds
Started Feb 25 02:43:50 PM PST 24
Finished Feb 25 02:43:53 PM PST 24
Peak memory 207612 kb
Host smart-23b61301-1320-467b-bfd9-4304ad16716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434624138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3434624138
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2846487428
Short name T550
Test name
Test status
Simulation time 380557268 ps
CPU time 0.83 seconds
Started Feb 25 02:43:58 PM PST 24
Finished Feb 25 02:43:59 PM PST 24
Peak memory 204700 kb
Host smart-15dc7f1f-2f7e-45d5-8421-a591dd3b3237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846487428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2846487428
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.9382045
Short name T868
Test name
Test status
Simulation time 139772347 ps
CPU time 0.91 seconds
Started Feb 25 02:43:48 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 204928 kb
Host smart-3e10d35e-fee6-448e-8ebe-651d4bd15744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9382045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.9382045
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.216216084
Short name T814
Test name
Test status
Simulation time 49181843709 ps
CPU time 29.8 seconds
Started Feb 25 02:44:05 PM PST 24
Finished Feb 25 02:44:36 PM PST 24
Peak memory 237628 kb
Host smart-5cba17a7-f6ed-494a-8337-a24ef9ac401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216216084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.216216084
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3500910312
Short name T698
Test name
Test status
Simulation time 52914089 ps
CPU time 0.75 seconds
Started Feb 25 02:44:01 PM PST 24
Finished Feb 25 02:44:02 PM PST 24
Peak memory 204548 kb
Host smart-f3ebd8c0-3cc4-40cd-8a8c-c941994760c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500910312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3500910312
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2759326197
Short name T335
Test name
Test status
Simulation time 242886878 ps
CPU time 3.01 seconds
Started Feb 25 02:44:05 PM PST 24
Finished Feb 25 02:44:10 PM PST 24
Peak memory 233372 kb
Host smart-af0d26c9-6aba-495c-8539-654befe0dfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759326197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2759326197
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3789944760
Short name T598
Test name
Test status
Simulation time 20023182 ps
CPU time 0.79 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:44:05 PM PST 24
Peak memory 205724 kb
Host smart-20ffa838-2f7b-4581-9175-d3893c4db8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789944760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3789944760
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1939954803
Short name T489
Test name
Test status
Simulation time 16622287777 ps
CPU time 108.14 seconds
Started Feb 25 02:44:03 PM PST 24
Finished Feb 25 02:45:51 PM PST 24
Peak memory 254860 kb
Host smart-09766c46-5d1f-4160-944a-68751f370faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939954803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1939954803
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.800380483
Short name T214
Test name
Test status
Simulation time 32375895879 ps
CPU time 98.7 seconds
Started Feb 25 02:44:02 PM PST 24
Finished Feb 25 02:45:41 PM PST 24
Peak memory 248816 kb
Host smart-8d092a76-0a2b-4bc0-95c1-1a19c91541bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800380483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.800380483
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.542898104
Short name T772
Test name
Test status
Simulation time 41704275179 ps
CPU time 48.88 seconds
Started Feb 25 02:43:59 PM PST 24
Finished Feb 25 02:44:48 PM PST 24
Peak memory 245700 kb
Host smart-6bc46eed-c010-4f80-87bd-7094fa6197ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542898104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.542898104
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3627463772
Short name T182
Test name
Test status
Simulation time 5324779386 ps
CPU time 7.6 seconds
Started Feb 25 02:43:59 PM PST 24
Finished Feb 25 02:44:07 PM PST 24
Peak memory 233200 kb
Host smart-4b7e0d2c-0bae-42af-99ea-c05d00b79281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627463772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3627463772
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3264732718
Short name T173
Test name
Test status
Simulation time 2656300451 ps
CPU time 9.81 seconds
Started Feb 25 02:44:11 PM PST 24
Finished Feb 25 02:44:21 PM PST 24
Peak memory 240424 kb
Host smart-fef57d58-7c6d-4627-98f1-5d6937c1b97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264732718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3264732718
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1342697584
Short name T980
Test name
Test status
Simulation time 8864982275 ps
CPU time 24.06 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:44:29 PM PST 24
Peak memory 227568 kb
Host smart-019116b4-3276-44e9-b406-ba29f25098cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342697584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1342697584
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1233376143
Short name T708
Test name
Test status
Simulation time 4172431215 ps
CPU time 16.97 seconds
Started Feb 25 02:43:58 PM PST 24
Finished Feb 25 02:44:15 PM PST 24
Peak memory 239476 kb
Host smart-bbc32d0f-3d7f-40fe-a008-3a633e885a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233376143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1233376143
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2368302334
Short name T827
Test name
Test status
Simulation time 373447427 ps
CPU time 3.44 seconds
Started Feb 25 02:44:05 PM PST 24
Finished Feb 25 02:44:09 PM PST 24
Peak memory 219576 kb
Host smart-4bae2955-9210-4f08-9c9f-98b82b4b8c8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2368302334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2368302334
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2807373408
Short name T569
Test name
Test status
Simulation time 16313415044 ps
CPU time 52.24 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:44:56 PM PST 24
Peak memory 250984 kb
Host smart-6a9b35a2-b5f3-4b6e-97a6-442159bba548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807373408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2807373408
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2754640427
Short name T739
Test name
Test status
Simulation time 4025464070 ps
CPU time 19.07 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:44:24 PM PST 24
Peak memory 215888 kb
Host smart-0d611de7-aaec-444b-a1e6-d679f66f8a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754640427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2754640427
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3702403754
Short name T394
Test name
Test status
Simulation time 343943434 ps
CPU time 2.85 seconds
Started Feb 25 02:44:11 PM PST 24
Finished Feb 25 02:44:14 PM PST 24
Peak memory 215736 kb
Host smart-6e896f64-30fb-48ba-8f29-a2e5f40d7b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702403754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3702403754
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3233576730
Short name T297
Test name
Test status
Simulation time 117422012 ps
CPU time 1.85 seconds
Started Feb 25 02:44:01 PM PST 24
Finished Feb 25 02:44:03 PM PST 24
Peak memory 216880 kb
Host smart-8b28a376-d1af-484a-b6ed-27f37f00bab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233576730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3233576730
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3981730989
Short name T769
Test name
Test status
Simulation time 17953026 ps
CPU time 0.69 seconds
Started Feb 25 02:43:57 PM PST 24
Finished Feb 25 02:43:58 PM PST 24
Peak memory 204828 kb
Host smart-4be9b1ed-51e7-4fc2-83bb-ee5384c7bebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981730989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3981730989
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1165238114
Short name T324
Test name
Test status
Simulation time 2099258428 ps
CPU time 8.83 seconds
Started Feb 25 02:44:01 PM PST 24
Finished Feb 25 02:44:11 PM PST 24
Peak memory 232412 kb
Host smart-a18272ec-fa5a-4c35-9411-84925292a787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165238114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1165238114
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.739044970
Short name T869
Test name
Test status
Simulation time 22132490 ps
CPU time 0.74 seconds
Started Feb 25 02:43:59 PM PST 24
Finished Feb 25 02:44:00 PM PST 24
Peak memory 204892 kb
Host smart-50d0c790-3636-426c-9275-fec7426761fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739044970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.739044970
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2663915530
Short name T488
Test name
Test status
Simulation time 3084881223 ps
CPU time 3.44 seconds
Started Feb 25 02:44:01 PM PST 24
Finished Feb 25 02:44:05 PM PST 24
Peak memory 233280 kb
Host smart-23bc5247-1ea4-4012-b3d6-ed71b1219133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663915530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2663915530
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2956122736
Short name T707
Test name
Test status
Simulation time 14725231 ps
CPU time 0.81 seconds
Started Feb 25 02:44:02 PM PST 24
Finished Feb 25 02:44:03 PM PST 24
Peak memory 204696 kb
Host smart-22752d73-5a3f-400c-a543-b6d5a164dd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956122736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2956122736
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2324274893
Short name T223
Test name
Test status
Simulation time 78580633674 ps
CPU time 393.63 seconds
Started Feb 25 02:44:00 PM PST 24
Finished Feb 25 02:50:34 PM PST 24
Peak memory 265764 kb
Host smart-356a8846-fed9-41a9-b327-637b6183bf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324274893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2324274893
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1708964191
Short name T216
Test name
Test status
Simulation time 1894116918 ps
CPU time 40.9 seconds
Started Feb 25 02:44:02 PM PST 24
Finished Feb 25 02:44:44 PM PST 24
Peak memory 253064 kb
Host smart-4a78a1a9-f1d6-4ba2-9532-93cfdc5b6e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708964191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1708964191
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2565306114
Short name T433
Test name
Test status
Simulation time 50059143506 ps
CPU time 133.15 seconds
Started Feb 25 02:44:02 PM PST 24
Finished Feb 25 02:46:15 PM PST 24
Peak memory 251044 kb
Host smart-063811e0-f5cd-459e-978d-78016fbc58a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565306114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2565306114
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1655318071
Short name T961
Test name
Test status
Simulation time 6448137415 ps
CPU time 25.18 seconds
Started Feb 25 02:44:00 PM PST 24
Finished Feb 25 02:44:26 PM PST 24
Peak memory 233712 kb
Host smart-be1c3e46-4e4f-4e2d-8b35-cb0ccec5811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655318071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1655318071
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2005148668
Short name T162
Test name
Test status
Simulation time 1357183157 ps
CPU time 6.01 seconds
Started Feb 25 02:43:59 PM PST 24
Finished Feb 25 02:44:05 PM PST 24
Peak memory 234008 kb
Host smart-3fa32ef8-31f0-4ff7-b576-e7bd95bc24d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005148668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2005148668
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3555702879
Short name T263
Test name
Test status
Simulation time 4357371715 ps
CPU time 16.87 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:44:21 PM PST 24
Peak memory 235660 kb
Host smart-50fed531-d9db-4c80-88f7-3548af82f64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555702879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3555702879
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2423287655
Short name T233
Test name
Test status
Simulation time 1757165989 ps
CPU time 6.42 seconds
Started Feb 25 02:44:00 PM PST 24
Finished Feb 25 02:44:06 PM PST 24
Peak memory 236604 kb
Host smart-1728a805-a6af-48af-b3c9-68a5afbf01ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423287655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2423287655
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3092361122
Short name T366
Test name
Test status
Simulation time 12927443138 ps
CPU time 15.62 seconds
Started Feb 25 02:44:01 PM PST 24
Finished Feb 25 02:44:16 PM PST 24
Peak memory 223604 kb
Host smart-d355d818-8e13-4691-81ef-613edae51546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092361122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3092361122
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1421853611
Short name T619
Test name
Test status
Simulation time 1150062172 ps
CPU time 5.44 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:17 PM PST 24
Peak memory 222252 kb
Host smart-970f4d3e-af58-4a33-a42e-bfefc8ef5b04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1421853611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1421853611
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3312526332
Short name T137
Test name
Test status
Simulation time 72807664032 ps
CPU time 226.94 seconds
Started Feb 25 02:44:07 PM PST 24
Finished Feb 25 02:47:55 PM PST 24
Peak memory 265564 kb
Host smart-8f7eaa52-b8c4-4d7c-a1f1-b764734f3176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312526332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3312526332
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4041235755
Short name T594
Test name
Test status
Simulation time 3934024676 ps
CPU time 38.48 seconds
Started Feb 25 02:43:56 PM PST 24
Finished Feb 25 02:44:35 PM PST 24
Peak memory 215908 kb
Host smart-821d6fd7-4435-440a-8a82-d9c45cd261f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041235755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4041235755
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2542232215
Short name T786
Test name
Test status
Simulation time 3830792098 ps
CPU time 12.23 seconds
Started Feb 25 02:44:02 PM PST 24
Finished Feb 25 02:44:14 PM PST 24
Peak memory 215768 kb
Host smart-64470c4a-d987-4e48-a8a2-1c19d95c790a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542232215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2542232215
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1315557890
Short name T776
Test name
Test status
Simulation time 374594855 ps
CPU time 9.83 seconds
Started Feb 25 02:44:00 PM PST 24
Finished Feb 25 02:44:10 PM PST 24
Peak memory 215892 kb
Host smart-c409d991-fe5a-452a-a765-f1fbcc5d8e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315557890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1315557890
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3299396119
Short name T329
Test name
Test status
Simulation time 95885958 ps
CPU time 0.95 seconds
Started Feb 25 02:44:07 PM PST 24
Finished Feb 25 02:44:09 PM PST 24
Peak memory 204936 kb
Host smart-30d8969d-69ea-42c2-b4f2-9c3c3091224f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299396119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3299396119
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4047150796
Short name T975
Test name
Test status
Simulation time 32307637289 ps
CPU time 23.44 seconds
Started Feb 25 02:43:59 PM PST 24
Finished Feb 25 02:44:23 PM PST 24
Peak memory 232352 kb
Host smart-46f3a728-589f-44d9-98b6-61f6549fafae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047150796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4047150796
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1750603331
Short name T306
Test name
Test status
Simulation time 47165466 ps
CPU time 0.73 seconds
Started Feb 25 02:44:06 PM PST 24
Finished Feb 25 02:44:07 PM PST 24
Peak memory 203988 kb
Host smart-d59ba54c-8356-4270-8225-19546877770f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750603331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1750603331
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1728182164
Short name T912
Test name
Test status
Simulation time 19124391763 ps
CPU time 5.91 seconds
Started Feb 25 02:44:08 PM PST 24
Finished Feb 25 02:44:16 PM PST 24
Peak memory 220044 kb
Host smart-64c97f86-ec78-479f-9f50-939cbaa4e7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728182164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1728182164
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2581309674
Short name T398
Test name
Test status
Simulation time 15702667 ps
CPU time 0.73 seconds
Started Feb 25 02:44:11 PM PST 24
Finished Feb 25 02:44:12 PM PST 24
Peak memory 204660 kb
Host smart-78d9ac76-b1c8-42a7-9167-5ff20ae25710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581309674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2581309674
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.252586823
Short name T270
Test name
Test status
Simulation time 8721650687 ps
CPU time 47.44 seconds
Started Feb 25 02:43:58 PM PST 24
Finished Feb 25 02:44:45 PM PST 24
Peak memory 240560 kb
Host smart-90c45d97-8709-4d43-83d8-9dd2a09f5e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252586823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.252586823
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2028883963
Short name T224
Test name
Test status
Simulation time 2592975218 ps
CPU time 11.29 seconds
Started Feb 25 02:44:06 PM PST 24
Finished Feb 25 02:44:18 PM PST 24
Peak memory 233400 kb
Host smart-5596f296-87b2-423f-a43f-40f54c2a9e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028883963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2028883963
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3905221711
Short name T74
Test name
Test status
Simulation time 15067866317 ps
CPU time 34.53 seconds
Started Feb 25 02:43:58 PM PST 24
Finished Feb 25 02:44:33 PM PST 24
Peak memory 245484 kb
Host smart-6ac3330d-44ab-4baf-8db0-f99c0839351c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905221711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3905221711
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2343533343
Short name T527
Test name
Test status
Simulation time 4147762444 ps
CPU time 6.26 seconds
Started Feb 25 02:44:11 PM PST 24
Finished Feb 25 02:44:17 PM PST 24
Peak memory 232972 kb
Host smart-610262c4-5297-40c1-8c94-104786c93582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343533343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2343533343
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1582866276
Short name T591
Test name
Test status
Simulation time 13061338388 ps
CPU time 22.03 seconds
Started Feb 25 02:44:00 PM PST 24
Finished Feb 25 02:44:22 PM PST 24
Peak memory 248064 kb
Host smart-71e1b738-c174-41e3-9168-76d448d4519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582866276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1582866276
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2642691302
Short name T913
Test name
Test status
Simulation time 668107408 ps
CPU time 5.31 seconds
Started Feb 25 02:44:11 PM PST 24
Finished Feb 25 02:44:16 PM PST 24
Peak memory 217120 kb
Host smart-d3796ef8-8008-479f-a051-c753bff5b648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642691302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2642691302
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1951666872
Short name T389
Test name
Test status
Simulation time 3850492800 ps
CPU time 4.83 seconds
Started Feb 25 02:44:11 PM PST 24
Finished Feb 25 02:44:16 PM PST 24
Peak memory 216852 kb
Host smart-857a0a02-668d-4958-a34d-a737b0d750ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951666872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1951666872
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.187772467
Short name T822
Test name
Test status
Simulation time 123257008 ps
CPU time 3.72 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:44:08 PM PST 24
Peak memory 221520 kb
Host smart-2b7f13f7-10d6-40ae-9f21-48ebafb51e15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=187772467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.187772467
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1007208335
Short name T756
Test name
Test status
Simulation time 41284091142 ps
CPU time 96.66 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:45:41 PM PST 24
Peak memory 256732 kb
Host smart-7908e51a-f7da-4c69-bdcb-f23119bd6598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007208335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1007208335
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.515419363
Short name T385
Test name
Test status
Simulation time 6135231367 ps
CPU time 27.08 seconds
Started Feb 25 02:44:08 PM PST 24
Finished Feb 25 02:44:37 PM PST 24
Peak memory 215892 kb
Host smart-c55ddf93-9712-44da-8d47-c68752a92d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515419363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.515419363
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3083425656
Short name T838
Test name
Test status
Simulation time 6506793651 ps
CPU time 13.54 seconds
Started Feb 25 02:44:07 PM PST 24
Finished Feb 25 02:44:21 PM PST 24
Peak memory 215908 kb
Host smart-86634f4e-e3e1-4068-9f7b-4a782453692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083425656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3083425656
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3944933315
Short name T640
Test name
Test status
Simulation time 149585071 ps
CPU time 1.73 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:44:07 PM PST 24
Peak memory 207804 kb
Host smart-bdb8b86a-661b-4957-97a2-9e5810b0aa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944933315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3944933315
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2375726634
Short name T349
Test name
Test status
Simulation time 107225851 ps
CPU time 0.77 seconds
Started Feb 25 02:43:58 PM PST 24
Finished Feb 25 02:43:59 PM PST 24
Peak memory 204924 kb
Host smart-7d00adf5-ed3f-4a39-b2e2-4712a5ab51b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375726634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2375726634
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1952618537
Short name T956
Test name
Test status
Simulation time 17704966188 ps
CPU time 15.09 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:44:19 PM PST 24
Peak memory 221108 kb
Host smart-0e49f954-10e4-47c9-ae10-63c97f7998b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952618537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1952618537
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3382675504
Short name T620
Test name
Test status
Simulation time 13861109 ps
CPU time 0.74 seconds
Started Feb 25 02:44:07 PM PST 24
Finished Feb 25 02:44:09 PM PST 24
Peak memory 203972 kb
Host smart-cc2063ba-47a4-4579-8e74-1911ab50b1db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382675504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3382675504
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.487041759
Short name T119
Test name
Test status
Simulation time 3319677268 ps
CPU time 4.06 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:44:20 PM PST 24
Peak memory 217632 kb
Host smart-620eedf5-5abb-4526-8e6e-2cef1316a1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487041759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.487041759
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2812367717
Short name T693
Test name
Test status
Simulation time 13860089 ps
CPU time 0.81 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:11 PM PST 24
Peak memory 205704 kb
Host smart-3d1a6897-0981-412c-ac65-b8351e971e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812367717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2812367717
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2592842547
Short name T76
Test name
Test status
Simulation time 85715182226 ps
CPU time 134.79 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:46:26 PM PST 24
Peak memory 256996 kb
Host smart-0661017e-dae6-4545-b87f-8d0847fe1098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592842547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2592842547
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2528084635
Short name T453
Test name
Test status
Simulation time 2975038079 ps
CPU time 51.71 seconds
Started Feb 25 02:44:09 PM PST 24
Finished Feb 25 02:45:02 PM PST 24
Peak memory 250972 kb
Host smart-f391a65f-8ecc-4b0c-a7b0-75bc273e1b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528084635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2528084635
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2831400585
Short name T267
Test name
Test status
Simulation time 1449277099 ps
CPU time 8.67 seconds
Started Feb 25 02:44:12 PM PST 24
Finished Feb 25 02:44:21 PM PST 24
Peak memory 221896 kb
Host smart-30b85b69-4755-43a2-b3fd-517db2231fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831400585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2831400585
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2949716491
Short name T266
Test name
Test status
Simulation time 2196120863 ps
CPU time 6.29 seconds
Started Feb 25 02:44:06 PM PST 24
Finished Feb 25 02:44:14 PM PST 24
Peak memory 233248 kb
Host smart-bd312f9f-1a20-43f6-b0f8-12ca7f55a92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949716491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2949716491
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2104635803
Short name T561
Test name
Test status
Simulation time 2702225852 ps
CPU time 10.44 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:21 PM PST 24
Peak memory 223900 kb
Host smart-27b9e5e6-268f-461f-b211-ae39b4a2a8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104635803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2104635803
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2389493938
Short name T207
Test name
Test status
Simulation time 5848581143 ps
CPU time 10.14 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:44:27 PM PST 24
Peak memory 235644 kb
Host smart-457e9e8c-b8f8-462d-bc3f-7ef1e947aea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389493938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2389493938
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4022116438
Short name T780
Test name
Test status
Simulation time 533617672 ps
CPU time 6.22 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:44:23 PM PST 24
Peak memory 233080 kb
Host smart-40c9d913-ac33-4bc6-9b7c-ddb39958aae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022116438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4022116438
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3624723997
Short name T921
Test name
Test status
Simulation time 868739986 ps
CPU time 3.79 seconds
Started Feb 25 02:44:06 PM PST 24
Finished Feb 25 02:44:10 PM PST 24
Peak memory 220852 kb
Host smart-58c14851-3f56-432d-8f58-cd84a713d068
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3624723997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3624723997
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2849098005
Short name T650
Test name
Test status
Simulation time 17393735650 ps
CPU time 43.36 seconds
Started Feb 25 02:44:13 PM PST 24
Finished Feb 25 02:44:56 PM PST 24
Peak memory 215900 kb
Host smart-86239127-2a84-47df-bcb9-1b87c58ec5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849098005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2849098005
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3609004883
Short name T370
Test name
Test status
Simulation time 845350050 ps
CPU time 5.23 seconds
Started Feb 25 02:44:08 PM PST 24
Finished Feb 25 02:44:15 PM PST 24
Peak memory 215816 kb
Host smart-6953d46b-e2cb-4138-9c8b-1bcc7c60c18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609004883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3609004883
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4261283610
Short name T889
Test name
Test status
Simulation time 51771778 ps
CPU time 0.97 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:44:17 PM PST 24
Peak memory 206112 kb
Host smart-dbfe774f-cf88-44a4-a866-65cc0c04d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261283610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4261283610
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1919202112
Short name T80
Test name
Test status
Simulation time 473434976 ps
CPU time 1.15 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:44:17 PM PST 24
Peak memory 205964 kb
Host smart-d3f34a64-6f87-40d0-b6cc-e61a7086f503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919202112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1919202112
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2369605115
Short name T446
Test name
Test status
Simulation time 17855949621 ps
CPU time 37.45 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:44:54 PM PST 24
Peak memory 240476 kb
Host smart-940f572e-9fd4-4685-b84d-d5ffeb7b15ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369605115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2369605115
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1542753863
Short name T540
Test name
Test status
Simulation time 15086975 ps
CPU time 0.75 seconds
Started Feb 25 02:44:06 PM PST 24
Finished Feb 25 02:44:07 PM PST 24
Peak memory 204448 kb
Host smart-acad1150-5894-4ef7-aca1-fc7ed51a4acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542753863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1542753863
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.162640900
Short name T191
Test name
Test status
Simulation time 1053394702 ps
CPU time 3.77 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:44:20 PM PST 24
Peak memory 218008 kb
Host smart-6795c5c5-3355-42a6-9647-9ff08e0d2707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162640900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.162640900
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3895375864
Short name T625
Test name
Test status
Simulation time 14076587 ps
CPU time 0.75 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:11 PM PST 24
Peak memory 205680 kb
Host smart-94326455-3bc9-44c2-a207-7a7444d3c514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895375864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3895375864
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2566350745
Short name T161
Test name
Test status
Simulation time 278934396329 ps
CPU time 388.35 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:50:39 PM PST 24
Peak memory 264984 kb
Host smart-fcbffc45-831b-4e77-8561-977a33d030ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566350745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2566350745
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3244169442
Short name T816
Test name
Test status
Simulation time 16022337997 ps
CPU time 103.8 seconds
Started Feb 25 02:44:11 PM PST 24
Finished Feb 25 02:45:55 PM PST 24
Peak memory 238024 kb
Host smart-0ae514cc-7100-4c7a-afee-ae8b8baaa1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244169442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3244169442
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.871992253
Short name T945
Test name
Test status
Simulation time 70752168318 ps
CPU time 246.01 seconds
Started Feb 25 02:44:08 PM PST 24
Finished Feb 25 02:48:16 PM PST 24
Peak memory 256928 kb
Host smart-65f8a118-0e2d-4069-a5b0-6b209cd300eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871992253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.871992253
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4146937541
Short name T632
Test name
Test status
Simulation time 11593655161 ps
CPU time 14.95 seconds
Started Feb 25 02:44:14 PM PST 24
Finished Feb 25 02:44:29 PM PST 24
Peak memory 240124 kb
Host smart-12545215-3f68-4b77-b7be-53f4cc81a961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146937541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4146937541
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2201329341
Short name T705
Test name
Test status
Simulation time 1224018281 ps
CPU time 5.46 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:16 PM PST 24
Peak memory 232948 kb
Host smart-81972201-ae8c-4924-9025-04b331341899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201329341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2201329341
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2687250871
Short name T762
Test name
Test status
Simulation time 43142609924 ps
CPU time 22.87 seconds
Started Feb 25 02:44:08 PM PST 24
Finished Feb 25 02:44:32 PM PST 24
Peak memory 223544 kb
Host smart-c19027b6-e836-434f-bae4-507d916f3ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687250871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2687250871
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2983997666
Short name T867
Test name
Test status
Simulation time 5018186183 ps
CPU time 19.25 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:30 PM PST 24
Peak memory 239732 kb
Host smart-927b9bf9-0c8b-4f47-be25-d34073c01422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983997666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2983997666
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3528748008
Short name T271
Test name
Test status
Simulation time 24047385378 ps
CPU time 19.89 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:44:25 PM PST 24
Peak memory 237996 kb
Host smart-e2149b27-7e06-45d9-b269-750820a465b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528748008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3528748008
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.598958525
Short name T799
Test name
Test status
Simulation time 771907256 ps
CPU time 3.4 seconds
Started Feb 25 02:44:05 PM PST 24
Finished Feb 25 02:44:09 PM PST 24
Peak memory 219936 kb
Host smart-0436d8dc-3517-4d20-87ac-3722b97b53d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=598958525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.598958525
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2494124519
Short name T360
Test name
Test status
Simulation time 3016520147 ps
CPU time 11.62 seconds
Started Feb 25 02:44:09 PM PST 24
Finished Feb 25 02:44:22 PM PST 24
Peak memory 215904 kb
Host smart-def3ef3a-4872-4c33-be35-8151cdca0bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494124519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2494124519
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3416247923
Short name T318
Test name
Test status
Simulation time 1860687440 ps
CPU time 5.99 seconds
Started Feb 25 02:44:05 PM PST 24
Finished Feb 25 02:44:13 PM PST 24
Peak memory 215788 kb
Host smart-b556bc29-032c-44b5-992d-9582907f9935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416247923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3416247923
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3004527169
Short name T68
Test name
Test status
Simulation time 372066582 ps
CPU time 4.61 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:15 PM PST 24
Peak memory 215924 kb
Host smart-07ebc7f2-de17-466b-8858-6274da09c315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004527169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3004527169
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3691514890
Short name T144
Test name
Test status
Simulation time 28276571 ps
CPU time 0.76 seconds
Started Feb 25 02:44:08 PM PST 24
Finished Feb 25 02:44:09 PM PST 24
Peak memory 204932 kb
Host smart-1d1eab1a-f769-4af4-ab4a-32f74f8963b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691514890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3691514890
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1086503402
Short name T703
Test name
Test status
Simulation time 11202219486 ps
CPU time 22.93 seconds
Started Feb 25 02:44:04 PM PST 24
Finished Feb 25 02:44:27 PM PST 24
Peak memory 234832 kb
Host smart-d835c3a3-ad00-45fb-bb97-bf312b7bcb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086503402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1086503402
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1460781944
Short name T700
Test name
Test status
Simulation time 13099673 ps
CPU time 0.71 seconds
Started Feb 25 02:44:19 PM PST 24
Finished Feb 25 02:44:20 PM PST 24
Peak memory 204564 kb
Host smart-7ab614e9-cefb-405b-9469-8125643cf84d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460781944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1460781944
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3340053269
Short name T541
Test name
Test status
Simulation time 164857759 ps
CPU time 2.3 seconds
Started Feb 25 02:44:12 PM PST 24
Finished Feb 25 02:44:15 PM PST 24
Peak memory 232968 kb
Host smart-631cd9b8-906d-438c-bde7-05b6d7d4825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340053269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3340053269
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2462275114
Short name T966
Test name
Test status
Simulation time 60979013 ps
CPU time 0.78 seconds
Started Feb 25 02:44:05 PM PST 24
Finished Feb 25 02:44:07 PM PST 24
Peak memory 204652 kb
Host smart-f0523110-ebf9-49d3-aaf7-356292330827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462275114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2462275114
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2575645940
Short name T31
Test name
Test status
Simulation time 174494012255 ps
CPU time 218.22 seconds
Started Feb 25 02:44:09 PM PST 24
Finished Feb 25 02:47:48 PM PST 24
Peak memory 248704 kb
Host smart-44caaac5-d918-451b-9558-5bbd96314562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575645940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2575645940
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1273435751
Short name T771
Test name
Test status
Simulation time 117843562272 ps
CPU time 422.46 seconds
Started Feb 25 02:44:09 PM PST 24
Finished Feb 25 02:51:12 PM PST 24
Peak memory 249764 kb
Host smart-6ceb7b4e-96b7-41f1-ad08-f9621eb6f859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273435751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1273435751
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2362848044
Short name T468
Test name
Test status
Simulation time 122095080727 ps
CPU time 203.9 seconds
Started Feb 25 02:44:26 PM PST 24
Finished Feb 25 02:47:50 PM PST 24
Peak memory 265148 kb
Host smart-8a26b0d0-3a7a-4901-8ee5-6b40bc787b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362848044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2362848044
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1136985206
Short name T891
Test name
Test status
Simulation time 3172123925 ps
CPU time 21.06 seconds
Started Feb 25 02:44:05 PM PST 24
Finished Feb 25 02:44:26 PM PST 24
Peak memory 239856 kb
Host smart-9c107a31-8430-4442-ad3c-2eaf11e00250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136985206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1136985206
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4224244809
Short name T669
Test name
Test status
Simulation time 62603797 ps
CPU time 2.33 seconds
Started Feb 25 02:44:05 PM PST 24
Finished Feb 25 02:44:09 PM PST 24
Peak memory 232208 kb
Host smart-e2d02ded-406f-47c0-8e2a-d4bf66d4a632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224244809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4224244809
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3525741287
Short name T308
Test name
Test status
Simulation time 5975192320 ps
CPU time 19.15 seconds
Started Feb 25 02:44:05 PM PST 24
Finished Feb 25 02:44:26 PM PST 24
Peak memory 238528 kb
Host smart-87d69052-af7c-4654-8dce-459221433966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525741287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3525741287
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3378661058
Short name T52
Test name
Test status
Simulation time 4555853095 ps
CPU time 14.83 seconds
Started Feb 25 02:44:09 PM PST 24
Finished Feb 25 02:44:25 PM PST 24
Peak memory 227464 kb
Host smart-cc37ae6c-7146-4443-acd4-97f52b5227e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378661058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3378661058
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1541419448
Short name T906
Test name
Test status
Simulation time 46527494690 ps
CPU time 35 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:46 PM PST 24
Peak memory 232132 kb
Host smart-d6d1ccee-b6f1-4452-843f-62ab78d2fe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541419448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1541419448
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1136686578
Short name T12
Test name
Test status
Simulation time 1364905562 ps
CPU time 3.56 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:15 PM PST 24
Peak memory 219520 kb
Host smart-4266b9f3-4442-4248-8604-8c47836e5cd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1136686578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1136686578
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1198907713
Short name T321
Test name
Test status
Simulation time 274322724 ps
CPU time 1.14 seconds
Started Feb 25 02:44:17 PM PST 24
Finished Feb 25 02:44:18 PM PST 24
Peak memory 206120 kb
Host smart-b668a5a5-acbf-4f08-9248-e0e5b6f4c23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198907713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1198907713
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.599758418
Short name T294
Test name
Test status
Simulation time 971321614 ps
CPU time 14.08 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:24 PM PST 24
Peak memory 215836 kb
Host smart-02a80079-78b0-44f2-9b5d-08102b2a6040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599758418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.599758418
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3700444954
Short name T307
Test name
Test status
Simulation time 11858046851 ps
CPU time 10.65 seconds
Started Feb 25 02:44:07 PM PST 24
Finished Feb 25 02:44:19 PM PST 24
Peak memory 217120 kb
Host smart-b2721b5e-a653-41cb-93b6-b0f75ef3d39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700444954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3700444954
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.370207153
Short name T493
Test name
Test status
Simulation time 210375006 ps
CPU time 2.31 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:44:19 PM PST 24
Peak memory 216984 kb
Host smart-298eb732-deb1-4354-a338-6718caab587c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370207153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.370207153
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1531610646
Short name T7
Test name
Test status
Simulation time 23108017 ps
CPU time 0.73 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:11 PM PST 24
Peak memory 204916 kb
Host smart-db38cce7-7464-4d21-ad9d-95aeaa793533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531610646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1531610646
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.620349548
Short name T737
Test name
Test status
Simulation time 15141790443 ps
CPU time 11.82 seconds
Started Feb 25 02:44:10 PM PST 24
Finished Feb 25 02:44:22 PM PST 24
Peak memory 233220 kb
Host smart-6018f70a-166a-48c3-a96b-42f0d7c0ff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620349548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.620349548
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2216680460
Short name T914
Test name
Test status
Simulation time 13499299 ps
CPU time 0.78 seconds
Started Feb 25 02:44:18 PM PST 24
Finished Feb 25 02:44:19 PM PST 24
Peak memory 204540 kb
Host smart-44478c66-a4b7-4b3c-b230-adaa37061b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216680460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2216680460
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3914224938
Short name T567
Test name
Test status
Simulation time 577714896 ps
CPU time 3.07 seconds
Started Feb 25 02:44:15 PM PST 24
Finished Feb 25 02:44:18 PM PST 24
Peak memory 218100 kb
Host smart-836606df-4e3f-43b0-8c79-625f1eda9c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914224938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3914224938
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.383650487
Short name T303
Test name
Test status
Simulation time 17922251 ps
CPU time 0.77 seconds
Started Feb 25 02:44:26 PM PST 24
Finished Feb 25 02:44:27 PM PST 24
Peak memory 204652 kb
Host smart-392ec1b0-c10f-47fd-ae77-ce4a21140ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383650487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.383650487
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2673122024
Short name T720
Test name
Test status
Simulation time 61764399584 ps
CPU time 50.01 seconds
Started Feb 25 02:44:19 PM PST 24
Finished Feb 25 02:45:09 PM PST 24
Peak memory 220688 kb
Host smart-b7706c4f-c68e-4e76-b7cc-c416a7a55abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673122024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2673122024
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1445375922
Short name T123
Test name
Test status
Simulation time 25040631479 ps
CPU time 113.4 seconds
Started Feb 25 02:44:23 PM PST 24
Finished Feb 25 02:46:17 PM PST 24
Peak memory 251332 kb
Host smart-3d4fc96a-a733-439d-89d9-91b2ff009897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445375922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1445375922
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3582811135
Short name T882
Test name
Test status
Simulation time 17254607683 ps
CPU time 29.85 seconds
Started Feb 25 02:44:31 PM PST 24
Finished Feb 25 02:45:01 PM PST 24
Peak memory 248904 kb
Host smart-ebf0bcae-781d-4203-950c-ecee5779a408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582811135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3582811135
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1198972757
Short name T147
Test name
Test status
Simulation time 237800034 ps
CPU time 3.7 seconds
Started Feb 25 02:44:19 PM PST 24
Finished Feb 25 02:44:23 PM PST 24
Peak memory 234560 kb
Host smart-c94db408-3023-43c5-a9e1-a213cb9a57ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198972757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1198972757
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1525127418
Short name T888
Test name
Test status
Simulation time 1538438194 ps
CPU time 6.62 seconds
Started Feb 25 02:44:14 PM PST 24
Finished Feb 25 02:44:21 PM PST 24
Peak memory 233812 kb
Host smart-e26fc4e3-3725-436d-b7b8-9be63552cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525127418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1525127418
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1768603830
Short name T942
Test name
Test status
Simulation time 2495274323 ps
CPU time 7.65 seconds
Started Feb 25 02:44:17 PM PST 24
Finished Feb 25 02:44:25 PM PST 24
Peak memory 232276 kb
Host smart-7a9229b1-fa34-47a3-886b-60fa756a02bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768603830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1768603830
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3416069990
Short name T404
Test name
Test status
Simulation time 1438186286 ps
CPU time 3.39 seconds
Started Feb 25 02:44:21 PM PST 24
Finished Feb 25 02:44:25 PM PST 24
Peak memory 233084 kb
Host smart-46b6c895-e2a1-49fe-9277-41a1b87ab8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416069990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3416069990
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1815869279
Short name T811
Test name
Test status
Simulation time 5919605493 ps
CPU time 6.03 seconds
Started Feb 25 02:44:16 PM PST 24
Finished Feb 25 02:44:22 PM PST 24
Peak memory 221884 kb
Host smart-2972ae97-4d3f-4d64-a386-70db26450322
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1815869279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1815869279
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3630439124
Short name T853
Test name
Test status
Simulation time 12975310485 ps
CPU time 47.59 seconds
Started Feb 25 02:44:20 PM PST 24
Finished Feb 25 02:45:08 PM PST 24
Peak memory 215860 kb
Host smart-4e6c340f-d8c0-4be1-88c3-22e2029e77bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630439124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3630439124
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1935425700
Short name T655
Test name
Test status
Simulation time 1804756122 ps
CPU time 4.85 seconds
Started Feb 25 02:44:15 PM PST 24
Finished Feb 25 02:44:20 PM PST 24
Peak memory 207688 kb
Host smart-557b5220-d2bb-494f-877c-c71db7ade3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935425700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1935425700
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2005103611
Short name T9
Test name
Test status
Simulation time 108673995 ps
CPU time 2.38 seconds
Started Feb 25 02:44:14 PM PST 24
Finished Feb 25 02:44:16 PM PST 24
Peak memory 215808 kb
Host smart-2cae732c-92e1-4ef7-9fff-3217094a6468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005103611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2005103611
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.441775383
Short name T833
Test name
Test status
Simulation time 40129358 ps
CPU time 0.75 seconds
Started Feb 25 02:44:19 PM PST 24
Finished Feb 25 02:44:20 PM PST 24
Peak memory 204948 kb
Host smart-34d3fff3-0650-4f1b-868f-3596de2edc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441775383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.441775383
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2461852935
Short name T330
Test name
Test status
Simulation time 4961329055 ps
CPU time 12.05 seconds
Started Feb 25 02:44:15 PM PST 24
Finished Feb 25 02:44:27 PM PST 24
Peak memory 233404 kb
Host smart-3db554f1-01fe-4ece-89bb-de79484131c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461852935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2461852935
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3919036237
Short name T375
Test name
Test status
Simulation time 22277892 ps
CPU time 0.72 seconds
Started Feb 25 02:44:18 PM PST 24
Finished Feb 25 02:44:19 PM PST 24
Peak memory 204560 kb
Host smart-1de3bdcc-898d-4e21-92ff-7464b1aa90f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919036237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3919036237
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3322843804
Short name T713
Test name
Test status
Simulation time 147011304 ps
CPU time 3.81 seconds
Started Feb 25 02:44:19 PM PST 24
Finished Feb 25 02:44:23 PM PST 24
Peak memory 233140 kb
Host smart-1ce04e74-87db-4109-b48e-516a8f72b2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322843804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3322843804
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1966928773
Short name T682
Test name
Test status
Simulation time 49973118 ps
CPU time 0.8 seconds
Started Feb 25 02:44:24 PM PST 24
Finished Feb 25 02:44:26 PM PST 24
Peak memory 205712 kb
Host smart-1590f866-134b-478b-a92d-a9eaa28a7d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966928773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1966928773
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3370772463
Short name T157
Test name
Test status
Simulation time 257767465663 ps
CPU time 296.28 seconds
Started Feb 25 02:44:18 PM PST 24
Finished Feb 25 02:49:14 PM PST 24
Peak memory 256948 kb
Host smart-4c7887bb-5765-4334-bc6e-1120cd5bc0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370772463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3370772463
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4254855429
Short name T778
Test name
Test status
Simulation time 6347823163 ps
CPU time 60.43 seconds
Started Feb 25 02:44:19 PM PST 24
Finished Feb 25 02:45:20 PM PST 24
Peak memory 235684 kb
Host smart-aaa9ddeb-93ef-4b32-9ac7-c8d8fd2ac20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254855429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4254855429
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.695574212
Short name T515
Test name
Test status
Simulation time 20135361829 ps
CPU time 27.95 seconds
Started Feb 25 02:44:32 PM PST 24
Finished Feb 25 02:45:00 PM PST 24
Peak memory 240288 kb
Host smart-72a582e9-b27c-4fdd-8697-75ced0a0132c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695574212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.695574212
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3977908136
Short name T558
Test name
Test status
Simulation time 1768469060 ps
CPU time 6.65 seconds
Started Feb 25 02:44:19 PM PST 24
Finished Feb 25 02:44:26 PM PST 24
Peak memory 216120 kb
Host smart-d2755241-a276-4308-9e58-806fdca4c430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977908136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3977908136
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.729560436
Short name T812
Test name
Test status
Simulation time 5680996772 ps
CPU time 11.16 seconds
Started Feb 25 02:44:24 PM PST 24
Finished Feb 25 02:44:35 PM PST 24
Peak memory 232336 kb
Host smart-1687cac8-90d4-474f-a6ae-0b5416999c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729560436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.729560436
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3256896273
Short name T599
Test name
Test status
Simulation time 16790974966 ps
CPU time 29.89 seconds
Started Feb 25 02:44:29 PM PST 24
Finished Feb 25 02:45:00 PM PST 24
Peak memory 237900 kb
Host smart-caa169bc-2950-45ab-bd74-32e3f4cc8b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256896273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3256896273
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2611006247
Short name T345
Test name
Test status
Simulation time 5070903655 ps
CPU time 21.01 seconds
Started Feb 25 02:44:32 PM PST 24
Finished Feb 25 02:44:53 PM PST 24
Peak memory 237700 kb
Host smart-572803da-d85e-4d92-8056-93de109c1d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611006247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2611006247
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3846897513
Short name T820
Test name
Test status
Simulation time 2092271233 ps
CPU time 7.14 seconds
Started Feb 25 02:44:26 PM PST 24
Finished Feb 25 02:44:33 PM PST 24
Peak memory 219336 kb
Host smart-c72bea68-a686-45b3-a20c-966a65de8c29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3846897513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3846897513
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4210426401
Short name T422
Test name
Test status
Simulation time 8666841341 ps
CPU time 17.85 seconds
Started Feb 25 02:44:18 PM PST 24
Finished Feb 25 02:44:36 PM PST 24
Peak memory 215824 kb
Host smart-e5201f83-cc1e-4956-9a17-5e9daaef2472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210426401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4210426401
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4239712551
Short name T671
Test name
Test status
Simulation time 1124028326 ps
CPU time 7.42 seconds
Started Feb 25 02:44:20 PM PST 24
Finished Feb 25 02:44:28 PM PST 24
Peak memory 207636 kb
Host smart-0b6c2701-ccbc-4c1b-9267-940d1debb4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239712551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4239712551
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2298082230
Short name T595
Test name
Test status
Simulation time 36673266 ps
CPU time 1.04 seconds
Started Feb 25 02:44:14 PM PST 24
Finished Feb 25 02:44:16 PM PST 24
Peak memory 206852 kb
Host smart-dfa90647-759d-4ecc-b4d2-9dffff225143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298082230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2298082230
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.864607750
Short name T617
Test name
Test status
Simulation time 86584618 ps
CPU time 0.81 seconds
Started Feb 25 02:44:31 PM PST 24
Finished Feb 25 02:44:32 PM PST 24
Peak memory 204936 kb
Host smart-4e25f377-7362-4753-b949-9f0395322dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864607750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.864607750
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3662772416
Short name T163
Test name
Test status
Simulation time 1905869528 ps
CPU time 10.95 seconds
Started Feb 25 02:44:18 PM PST 24
Finished Feb 25 02:44:29 PM PST 24
Peak memory 223024 kb
Host smart-ff160d1a-39ac-4f4d-a226-c1766f47c5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662772416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3662772416
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.415120550
Short name T334
Test name
Test status
Simulation time 16287868 ps
CPU time 0.73 seconds
Started Feb 25 02:44:26 PM PST 24
Finished Feb 25 02:44:27 PM PST 24
Peak memory 204528 kb
Host smart-b34e5dfb-5e43-4a10-9527-abe78d9ff0cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415120550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.415120550
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.4086173362
Short name T645
Test name
Test status
Simulation time 169476484 ps
CPU time 2.43 seconds
Started Feb 25 02:44:19 PM PST 24
Finished Feb 25 02:44:22 PM PST 24
Peak memory 232936 kb
Host smart-14a02f21-ad22-4bb1-9967-ea5d092aeb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086173362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.4086173362
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.4174439418
Short name T764
Test name
Test status
Simulation time 53701129 ps
CPU time 0.76 seconds
Started Feb 25 02:44:18 PM PST 24
Finished Feb 25 02:44:19 PM PST 24
Peak memory 205008 kb
Host smart-9a4f4bc5-2409-4cbf-97d9-ee125eda8e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174439418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4174439418
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2288609586
Short name T159
Test name
Test status
Simulation time 52147897823 ps
CPU time 121.71 seconds
Started Feb 25 02:44:20 PM PST 24
Finished Feb 25 02:46:22 PM PST 24
Peak memory 267960 kb
Host smart-22b554c8-2528-4096-864b-0986a2cc5332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288609586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2288609586
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4016724884
Short name T908
Test name
Test status
Simulation time 13161329170 ps
CPU time 56.88 seconds
Started Feb 25 02:44:24 PM PST 24
Finished Feb 25 02:45:21 PM PST 24
Peak memory 252404 kb
Host smart-541038a2-6929-49f6-9c91-62ac7561adc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016724884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4016724884
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1614124927
Short name T807
Test name
Test status
Simulation time 1702692917 ps
CPU time 17.47 seconds
Started Feb 25 02:44:21 PM PST 24
Finished Feb 25 02:44:39 PM PST 24
Peak memory 240364 kb
Host smart-ef3c5578-6cc8-46b0-9b8c-3361f690fb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614124927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1614124927
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3975895496
Short name T413
Test name
Test status
Simulation time 1100364064 ps
CPU time 5.52 seconds
Started Feb 25 02:44:20 PM PST 24
Finished Feb 25 02:44:26 PM PST 24
Peak memory 232760 kb
Host smart-20daaa23-d9e1-4b18-b12e-bb27de688192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975895496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3975895496
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.994301425
Short name T189
Test name
Test status
Simulation time 779103712 ps
CPU time 5.23 seconds
Started Feb 25 02:44:21 PM PST 24
Finished Feb 25 02:44:26 PM PST 24
Peak memory 223960 kb
Host smart-cbe2dc40-69bd-4c93-9e35-5b07423c8637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994301425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.994301425
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3480492107
Short name T722
Test name
Test status
Simulation time 1079596036 ps
CPU time 3.73 seconds
Started Feb 25 02:44:29 PM PST 24
Finished Feb 25 02:44:34 PM PST 24
Peak memory 218216 kb
Host smart-5318c659-09f5-48a4-b31a-71f42e779060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480492107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3480492107
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2302462541
Short name T806
Test name
Test status
Simulation time 3708254360 ps
CPU time 5.67 seconds
Started Feb 25 02:44:20 PM PST 24
Finished Feb 25 02:44:26 PM PST 24
Peak memory 233652 kb
Host smart-7e595a42-fc52-4a80-b18d-9fe02de4e4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302462541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2302462541
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1197963807
Short name T909
Test name
Test status
Simulation time 2620617325 ps
CPU time 4.77 seconds
Started Feb 25 02:44:18 PM PST 24
Finished Feb 25 02:44:23 PM PST 24
Peak memory 221740 kb
Host smart-7b76e69d-7a64-4612-94c9-8e61372842eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1197963807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1197963807
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4086127765
Short name T940
Test name
Test status
Simulation time 67443233 ps
CPU time 0.97 seconds
Started Feb 25 02:44:19 PM PST 24
Finished Feb 25 02:44:20 PM PST 24
Peak memory 205008 kb
Host smart-2d31a446-df13-43fd-8ae9-6777cafeb98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086127765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4086127765
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3392105670
Short name T861
Test name
Test status
Simulation time 1871017052 ps
CPU time 3.21 seconds
Started Feb 25 02:44:26 PM PST 24
Finished Feb 25 02:44:30 PM PST 24
Peak memory 215712 kb
Host smart-151b7578-1acd-4d6d-bee9-e1ed056c51a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392105670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3392105670
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2646924946
Short name T344
Test name
Test status
Simulation time 35790769372 ps
CPU time 26.79 seconds
Started Feb 25 02:44:23 PM PST 24
Finished Feb 25 02:44:50 PM PST 24
Peak memory 215888 kb
Host smart-7f0cbe05-612a-4fe7-9af6-4492242b4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646924946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2646924946
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.793777210
Short name T674
Test name
Test status
Simulation time 43809082 ps
CPU time 2.88 seconds
Started Feb 25 02:44:24 PM PST 24
Finished Feb 25 02:44:26 PM PST 24
Peak memory 207620 kb
Host smart-8db43132-8558-45cd-bb88-6346a6bfd726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793777210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.793777210
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1798508192
Short name T872
Test name
Test status
Simulation time 286603781 ps
CPU time 0.82 seconds
Started Feb 25 02:44:21 PM PST 24
Finished Feb 25 02:44:22 PM PST 24
Peak memory 204884 kb
Host smart-d8fe232c-aaa0-430f-b3a8-50c31a29c0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798508192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1798508192
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.508103364
Short name T879
Test name
Test status
Simulation time 12812723478 ps
CPU time 12.43 seconds
Started Feb 25 02:44:18 PM PST 24
Finished Feb 25 02:44:31 PM PST 24
Peak memory 235928 kb
Host smart-011952ba-8719-482a-a461-ec51d4055b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508103364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.508103364
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2607217442
Short name T403
Test name
Test status
Simulation time 27583679 ps
CPU time 0.72 seconds
Started Feb 25 02:43:06 PM PST 24
Finished Feb 25 02:43:07 PM PST 24
Peak memory 204876 kb
Host smart-7f299491-0723-4b96-b69e-f8d540e309b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607217442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
607217442
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3602182035
Short name T900
Test name
Test status
Simulation time 92205883 ps
CPU time 2.99 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:43:15 PM PST 24
Peak memory 233740 kb
Host smart-2c9835b4-786d-497c-9899-f472ee219117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602182035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3602182035
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1187308954
Short name T890
Test name
Test status
Simulation time 57108473 ps
CPU time 0.85 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:11 PM PST 24
Peak memory 205680 kb
Host smart-b451895c-22c9-459b-8a8e-49be5b1ceaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187308954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1187308954
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.418650423
Short name T175
Test name
Test status
Simulation time 12465986269 ps
CPU time 58.92 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:44:09 PM PST 24
Peak memory 248744 kb
Host smart-cc6af497-86b2-4d9d-89c4-e99179341389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418650423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.418650423
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2755878707
Short name T53
Test name
Test status
Simulation time 8678470365 ps
CPU time 56.24 seconds
Started Feb 25 02:43:05 PM PST 24
Finished Feb 25 02:44:02 PM PST 24
Peak memory 221116 kb
Host smart-0b4bda83-1172-4205-9171-c4f04b7ca554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755878707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2755878707
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1374703250
Short name T768
Test name
Test status
Simulation time 6056231092 ps
CPU time 16.85 seconds
Started Feb 25 02:43:06 PM PST 24
Finished Feb 25 02:43:23 PM PST 24
Peak memory 244496 kb
Host smart-9c4d5387-7187-4bfb-a7c4-2c9d6f8a29ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374703250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1374703250
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.933946464
Short name T187
Test name
Test status
Simulation time 139137830 ps
CPU time 3.15 seconds
Started Feb 25 02:43:03 PM PST 24
Finished Feb 25 02:43:07 PM PST 24
Peak memory 233672 kb
Host smart-541b32ab-f824-49d6-a535-7d2c5b76de28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933946464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.933946464
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1355010185
Short name T553
Test name
Test status
Simulation time 1743504562 ps
CPU time 3.75 seconds
Started Feb 25 02:43:03 PM PST 24
Finished Feb 25 02:43:07 PM PST 24
Peak memory 232328 kb
Host smart-5d432714-75df-453f-9a22-964881e50507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355010185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1355010185
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.659338516
Short name T388
Test name
Test status
Simulation time 85098654 ps
CPU time 1.09 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:11 PM PST 24
Peak memory 216120 kb
Host smart-e4bcf874-7430-453e-aeeb-b42d9dbe3e25
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659338516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.659338516
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.267367746
Short name T393
Test name
Test status
Simulation time 338566592 ps
CPU time 2.6 seconds
Started Feb 25 02:43:02 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 232172 kb
Host smart-dd9f420f-6ad5-455e-b9a6-7e79ce1ad6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267367746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
267367746
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1507004542
Short name T926
Test name
Test status
Simulation time 621156051 ps
CPU time 10.7 seconds
Started Feb 25 02:43:06 PM PST 24
Finished Feb 25 02:43:17 PM PST 24
Peak memory 248420 kb
Host smart-da9a7e29-3abb-4db9-947a-e949a0ddeb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507004542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1507004542
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.3086042616
Short name T978
Test name
Test status
Simulation time 45017712 ps
CPU time 0.7 seconds
Started Feb 25 02:43:07 PM PST 24
Finished Feb 25 02:43:08 PM PST 24
Peak memory 215708 kb
Host smart-832b5a1f-d3a9-4852-adc5-fc5539ed14a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086042616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.3086042616
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.700534135
Short name T127
Test name
Test status
Simulation time 546708516 ps
CPU time 3.38 seconds
Started Feb 25 02:43:15 PM PST 24
Finished Feb 25 02:43:18 PM PST 24
Peak memory 220016 kb
Host smart-ae4f08e5-3498-401c-a7f6-809672c3d2d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=700534135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.700534135
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1652610080
Short name T43
Test name
Test status
Simulation time 73883839 ps
CPU time 1.03 seconds
Started Feb 25 02:43:04 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 235108 kb
Host smart-93caa40e-1251-409e-a377-3b9c63a007bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652610080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1652610080
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.433383757
Short name T20
Test name
Test status
Simulation time 38699380209 ps
CPU time 293.41 seconds
Started Feb 25 02:43:09 PM PST 24
Finished Feb 25 02:48:02 PM PST 24
Peak memory 264672 kb
Host smart-221907d4-f889-4e54-af5b-a8b60f580761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433383757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.433383757
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2595724354
Short name T424
Test name
Test status
Simulation time 7146001608 ps
CPU time 23.14 seconds
Started Feb 25 02:43:06 PM PST 24
Finished Feb 25 02:43:30 PM PST 24
Peak memory 215840 kb
Host smart-941191e8-7fe5-44ed-9499-5bdba7d58f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595724354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2595724354
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3355673869
Short name T302
Test name
Test status
Simulation time 294760754 ps
CPU time 2.3 seconds
Started Feb 25 02:43:02 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 207356 kb
Host smart-f22d794d-76ab-4e0d-a300-9386144a021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355673869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3355673869
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3892495493
Short name T309
Test name
Test status
Simulation time 98466346 ps
CPU time 1.59 seconds
Started Feb 25 02:43:00 PM PST 24
Finished Feb 25 02:43:02 PM PST 24
Peak memory 207728 kb
Host smart-5285dcbc-92ab-405f-a2ec-56d8632d2848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892495493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3892495493
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2274400379
Short name T304
Test name
Test status
Simulation time 143679237 ps
CPU time 0.9 seconds
Started Feb 25 02:43:09 PM PST 24
Finished Feb 25 02:43:10 PM PST 24
Peak memory 204936 kb
Host smart-b843c48b-5302-474d-b487-5eb725479eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274400379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2274400379
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2420140515
Short name T383
Test name
Test status
Simulation time 397954896 ps
CPU time 6.67 seconds
Started Feb 25 02:43:01 PM PST 24
Finished Feb 25 02:43:09 PM PST 24
Peak memory 240500 kb
Host smart-e2b12ffc-766f-48f7-bc23-e00137f20a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420140515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2420140515
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.822670038
Short name T863
Test name
Test status
Simulation time 38655402 ps
CPU time 0.78 seconds
Started Feb 25 02:44:36 PM PST 24
Finished Feb 25 02:44:37 PM PST 24
Peak memory 203924 kb
Host smart-44fb3a4d-80b9-4f67-bbd1-84e553a333fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822670038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.822670038
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.944380712
Short name T963
Test name
Test status
Simulation time 331907035 ps
CPU time 2.96 seconds
Started Feb 25 02:44:35 PM PST 24
Finished Feb 25 02:44:39 PM PST 24
Peak memory 216072 kb
Host smart-ef31a78b-94aa-4623-92b6-968c2edfb8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944380712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.944380712
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2968928782
Short name T850
Test name
Test status
Simulation time 29728055 ps
CPU time 0.74 seconds
Started Feb 25 02:44:18 PM PST 24
Finished Feb 25 02:44:19 PM PST 24
Peak memory 204660 kb
Host smart-55ac3141-a175-41fd-ac28-afea2c2960a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968928782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2968928782
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3269674772
Short name T967
Test name
Test status
Simulation time 1061253721 ps
CPU time 14.65 seconds
Started Feb 25 02:44:29 PM PST 24
Finished Feb 25 02:44:44 PM PST 24
Peak memory 234240 kb
Host smart-c46150ee-295a-4e82-a7e5-dc33834880fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269674772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3269674772
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1584882738
Short name T234
Test name
Test status
Simulation time 16000774383 ps
CPU time 110.94 seconds
Started Feb 25 02:44:33 PM PST 24
Finished Feb 25 02:46:24 PM PST 24
Peak memory 253976 kb
Host smart-4f8f411f-cb13-4717-8e05-e2e6473c3408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584882738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1584882738
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.211088430
Short name T794
Test name
Test status
Simulation time 757595002693 ps
CPU time 199.38 seconds
Started Feb 25 02:44:27 PM PST 24
Finished Feb 25 02:47:46 PM PST 24
Peak memory 266172 kb
Host smart-6f64295c-00e9-43c6-a759-6246d0d8bede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211088430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.211088430
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4181845845
Short name T855
Test name
Test status
Simulation time 1118662811 ps
CPU time 14.16 seconds
Started Feb 25 02:44:37 PM PST 24
Finished Feb 25 02:44:51 PM PST 24
Peak memory 256340 kb
Host smart-b75f54c4-bba0-4678-80e4-0d6d3fb02c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181845845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4181845845
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.18662272
Short name T268
Test name
Test status
Simulation time 1286826500 ps
CPU time 4.12 seconds
Started Feb 25 02:44:29 PM PST 24
Finished Feb 25 02:44:33 PM PST 24
Peak memory 233252 kb
Host smart-0211afae-899c-45d7-8703-3de580a95cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18662272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.18662272
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3357241239
Short name T792
Test name
Test status
Simulation time 242192066 ps
CPU time 3.59 seconds
Started Feb 25 02:44:37 PM PST 24
Finished Feb 25 02:44:41 PM PST 24
Peak memory 218532 kb
Host smart-911d5c20-44f2-429b-8adf-c12de484e52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357241239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3357241239
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2654626770
Short name T835
Test name
Test status
Simulation time 547667728 ps
CPU time 6.03 seconds
Started Feb 25 02:44:29 PM PST 24
Finished Feb 25 02:44:35 PM PST 24
Peak memory 232864 kb
Host smart-48974804-a7bc-4d9c-9ebe-da4ac994f353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654626770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2654626770
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3026071962
Short name T380
Test name
Test status
Simulation time 4361632089 ps
CPU time 8.32 seconds
Started Feb 25 02:44:32 PM PST 24
Finished Feb 25 02:44:40 PM PST 24
Peak memory 233272 kb
Host smart-43add831-7368-484e-9700-57a879644a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026071962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3026071962
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3697722228
Short name T452
Test name
Test status
Simulation time 380783065 ps
CPU time 3.85 seconds
Started Feb 25 02:44:30 PM PST 24
Finished Feb 25 02:44:34 PM PST 24
Peak memory 218132 kb
Host smart-af7dfd45-9545-4fd8-a640-0eb1ca6169f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3697722228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3697722228
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3085106906
Short name T641
Test name
Test status
Simulation time 277536747 ps
CPU time 0.83 seconds
Started Feb 25 02:44:32 PM PST 24
Finished Feb 25 02:44:33 PM PST 24
Peak memory 204748 kb
Host smart-6763764c-7421-4560-a28b-2d3a7662ac18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085106906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3085106906
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.534615337
Short name T290
Test name
Test status
Simulation time 21594744751 ps
CPU time 38.55 seconds
Started Feb 25 02:44:27 PM PST 24
Finished Feb 25 02:45:07 PM PST 24
Peak memory 215892 kb
Host smart-04fa9573-e7b1-4452-ac40-c8ddeb148d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534615337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.534615337
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.839984658
Short name T359
Test name
Test status
Simulation time 15579811817 ps
CPU time 7.27 seconds
Started Feb 25 02:44:25 PM PST 24
Finished Feb 25 02:44:32 PM PST 24
Peak memory 215880 kb
Host smart-ea64e5e3-3890-4a9b-aff6-27fa68123c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839984658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.839984658
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1928144353
Short name T910
Test name
Test status
Simulation time 329943215 ps
CPU time 1.56 seconds
Started Feb 25 02:44:36 PM PST 24
Finished Feb 25 02:44:37 PM PST 24
Peak memory 215636 kb
Host smart-d7fe7663-07a1-43ea-a073-2d8668d28ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928144353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1928144353
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1018812960
Short name T362
Test name
Test status
Simulation time 52875709 ps
CPU time 0.77 seconds
Started Feb 25 02:44:31 PM PST 24
Finished Feb 25 02:44:32 PM PST 24
Peak memory 204944 kb
Host smart-958af32d-5a5a-474e-8f2d-994892de1727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018812960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1018812960
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1687789040
Short name T582
Test name
Test status
Simulation time 2256112214 ps
CPU time 9.06 seconds
Started Feb 25 02:44:25 PM PST 24
Finished Feb 25 02:44:35 PM PST 24
Peak memory 218204 kb
Host smart-2f7c0411-e079-415b-81b6-71c31822d6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687789040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1687789040
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.728651178
Short name T751
Test name
Test status
Simulation time 13944002 ps
CPU time 0.74 seconds
Started Feb 25 02:44:29 PM PST 24
Finished Feb 25 02:44:30 PM PST 24
Peak memory 204548 kb
Host smart-5657140e-d819-44e8-a7c4-131e6739ade6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728651178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.728651178
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.417259568
Short name T185
Test name
Test status
Simulation time 159502668 ps
CPU time 2.65 seconds
Started Feb 25 02:44:30 PM PST 24
Finished Feb 25 02:44:33 PM PST 24
Peak memory 233200 kb
Host smart-20d362e1-40a4-43ca-97b1-c7b51e37daf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417259568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.417259568
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2285720504
Short name T585
Test name
Test status
Simulation time 37209105 ps
CPU time 0.75 seconds
Started Feb 25 02:44:23 PM PST 24
Finished Feb 25 02:44:24 PM PST 24
Peak memory 205008 kb
Host smart-6f23d93e-b88b-47dc-9156-bc02aa2df706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285720504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2285720504
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3857728076
Short name T429
Test name
Test status
Simulation time 2979096581 ps
CPU time 16.54 seconds
Started Feb 25 02:44:35 PM PST 24
Finished Feb 25 02:44:52 PM PST 24
Peak memory 224120 kb
Host smart-89cf661a-d888-4890-a8d2-81c24427f446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857728076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3857728076
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1387250451
Short name T121
Test name
Test status
Simulation time 14107944342 ps
CPU time 41.83 seconds
Started Feb 25 02:44:35 PM PST 24
Finished Feb 25 02:45:17 PM PST 24
Peak memory 233416 kb
Host smart-4a001d0f-efc9-488b-9596-cce44728a61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387250451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1387250451
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3086205635
Short name T65
Test name
Test status
Simulation time 200758157148 ps
CPU time 318.48 seconds
Started Feb 25 02:44:27 PM PST 24
Finished Feb 25 02:49:47 PM PST 24
Peak memory 253792 kb
Host smart-71625c1f-deb4-49e0-ab9c-ef402a822620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086205635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3086205635
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2462313826
Short name T145
Test name
Test status
Simulation time 7634133413 ps
CPU time 31.82 seconds
Started Feb 25 02:44:33 PM PST 24
Finished Feb 25 02:45:05 PM PST 24
Peak memory 237464 kb
Host smart-bcda368f-8e9b-409b-9dd0-6f92ff3887ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462313826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2462313826
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.520329324
Short name T629
Test name
Test status
Simulation time 10749764775 ps
CPU time 11.5 seconds
Started Feb 25 02:44:29 PM PST 24
Finished Feb 25 02:44:41 PM PST 24
Peak memory 233160 kb
Host smart-8e212489-faae-4de8-8ac6-7879aa7475dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520329324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.520329324
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3528506227
Short name T571
Test name
Test status
Simulation time 7348271631 ps
CPU time 18.63 seconds
Started Feb 25 02:44:32 PM PST 24
Finished Feb 25 02:44:50 PM PST 24
Peak memory 236216 kb
Host smart-acdf88f0-df02-4725-b7da-bed5c26149bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528506227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3528506227
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2050601235
Short name T454
Test name
Test status
Simulation time 17376799110 ps
CPU time 10.71 seconds
Started Feb 25 02:44:33 PM PST 24
Finished Feb 25 02:44:44 PM PST 24
Peak memory 240124 kb
Host smart-f9be58d1-248a-4d47-8e93-868290ec9278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050601235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2050601235
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3811099144
Short name T84
Test name
Test status
Simulation time 6412738852 ps
CPU time 13.33 seconds
Started Feb 25 02:44:29 PM PST 24
Finished Feb 25 02:44:43 PM PST 24
Peak memory 216520 kb
Host smart-d896de1d-c631-4358-8312-c914bad46fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811099144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3811099144
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3999372087
Short name T783
Test name
Test status
Simulation time 4547228810 ps
CPU time 5.55 seconds
Started Feb 25 02:44:34 PM PST 24
Finished Feb 25 02:44:40 PM PST 24
Peak memory 219932 kb
Host smart-5269bf6a-8f88-430b-a48c-86d622525cbc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3999372087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3999372087
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3222145730
Short name T968
Test name
Test status
Simulation time 43472255149 ps
CPU time 401.36 seconds
Started Feb 25 02:44:27 PM PST 24
Finished Feb 25 02:51:08 PM PST 24
Peak memory 281492 kb
Host smart-576c95aa-3f03-469d-b8f2-2f8689673b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222145730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3222145730
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4175087275
Short name T288
Test name
Test status
Simulation time 2995396432 ps
CPU time 22.12 seconds
Started Feb 25 02:44:30 PM PST 24
Finished Feb 25 02:44:52 PM PST 24
Peak memory 215856 kb
Host smart-a4b49233-a737-4aa3-9046-4ce174950ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175087275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4175087275
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2344834171
Short name T929
Test name
Test status
Simulation time 7041287276 ps
CPU time 13.77 seconds
Started Feb 25 02:44:29 PM PST 24
Finished Feb 25 02:44:43 PM PST 24
Peak memory 215888 kb
Host smart-e614a94c-7c4a-42a9-8691-a740bf79c718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344834171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2344834171
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2183626068
Short name T686
Test name
Test status
Simulation time 57409262 ps
CPU time 1.52 seconds
Started Feb 25 02:44:25 PM PST 24
Finished Feb 25 02:44:27 PM PST 24
Peak memory 216008 kb
Host smart-33cba948-b2c5-463e-9a52-59432f62f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183626068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2183626068
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3744069845
Short name T687
Test name
Test status
Simulation time 412158813 ps
CPU time 0.94 seconds
Started Feb 25 02:44:26 PM PST 24
Finished Feb 25 02:44:27 PM PST 24
Peak memory 205964 kb
Host smart-30258382-56c3-4b17-864b-ecb2c3f4df2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744069845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3744069845
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3387415920
Short name T893
Test name
Test status
Simulation time 6006495564 ps
CPU time 16.43 seconds
Started Feb 25 02:44:34 PM PST 24
Finished Feb 25 02:44:51 PM PST 24
Peak memory 233428 kb
Host smart-75ca472c-4266-4005-ab78-b0628f11f5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387415920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3387415920
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3944244332
Short name T314
Test name
Test status
Simulation time 11655985 ps
CPU time 0.71 seconds
Started Feb 25 02:44:27 PM PST 24
Finished Feb 25 02:44:28 PM PST 24
Peak memory 204536 kb
Host smart-4caab31e-1d0e-42ed-acc1-ef8fd29a4fcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944244332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3944244332
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3471222050
Short name T438
Test name
Test status
Simulation time 175322956 ps
CPU time 4.09 seconds
Started Feb 25 02:44:27 PM PST 24
Finished Feb 25 02:44:33 PM PST 24
Peak memory 233420 kb
Host smart-ae39c18a-8e93-4495-a4cc-1af0fde54f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471222050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3471222050
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3874984711
Short name T925
Test name
Test status
Simulation time 44710996 ps
CPU time 0.74 seconds
Started Feb 25 02:44:36 PM PST 24
Finished Feb 25 02:44:37 PM PST 24
Peak memory 204728 kb
Host smart-fb99f20e-1bdf-4177-bc7d-c81cdf062d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874984711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3874984711
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2366559489
Short name T616
Test name
Test status
Simulation time 2484609088 ps
CPU time 36.55 seconds
Started Feb 25 02:44:35 PM PST 24
Finished Feb 25 02:45:12 PM PST 24
Peak memory 239604 kb
Host smart-b7b4f20e-6218-4bde-9bb4-3762c2097020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366559489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2366559489
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2953373380
Short name T578
Test name
Test status
Simulation time 57311950434 ps
CPU time 123.64 seconds
Started Feb 25 02:44:30 PM PST 24
Finished Feb 25 02:46:34 PM PST 24
Peak memory 253980 kb
Host smart-6cae38a5-450c-4b89-974b-d4de5c1626a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953373380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2953373380
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1234017036
Short name T560
Test name
Test status
Simulation time 25017115504 ps
CPU time 39.77 seconds
Started Feb 25 02:44:34 PM PST 24
Finished Feb 25 02:45:14 PM PST 24
Peak memory 233660 kb
Host smart-7d9b0906-847f-46a7-8828-ad392def196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234017036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1234017036
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2623258156
Short name T131
Test name
Test status
Simulation time 14174020155 ps
CPU time 32.28 seconds
Started Feb 25 02:44:36 PM PST 24
Finished Feb 25 02:45:08 PM PST 24
Peak memory 232328 kb
Host smart-68b26f72-e4f3-42a9-a629-d053785942b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623258156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2623258156
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.569296217
Short name T436
Test name
Test status
Simulation time 24129852571 ps
CPU time 11.93 seconds
Started Feb 25 02:44:28 PM PST 24
Finished Feb 25 02:44:41 PM PST 24
Peak memory 233952 kb
Host smart-4925d0a5-a590-4738-9065-60e37316ee4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569296217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.569296217
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2031897281
Short name T846
Test name
Test status
Simulation time 8533403427 ps
CPU time 10.51 seconds
Started Feb 25 02:44:32 PM PST 24
Finished Feb 25 02:44:43 PM PST 24
Peak memory 240132 kb
Host smart-59c70b96-54eb-44e0-992f-445e5f6832f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031897281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2031897281
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.715811293
Short name T615
Test name
Test status
Simulation time 8114497402 ps
CPU time 27.07 seconds
Started Feb 25 02:44:37 PM PST 24
Finished Feb 25 02:45:05 PM PST 24
Peak memory 238156 kb
Host smart-58873c7f-33e2-4e13-9379-612c2d0cd18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715811293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.715811293
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.232169984
Short name T425
Test name
Test status
Simulation time 64809401460 ps
CPU time 21.54 seconds
Started Feb 25 02:44:36 PM PST 24
Finished Feb 25 02:44:57 PM PST 24
Peak memory 232452 kb
Host smart-74f880ec-e8a6-4005-a1d9-7e4d3e273367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232169984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.232169984
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.533772091
Short name T449
Test name
Test status
Simulation time 3834963936 ps
CPU time 8.02 seconds
Started Feb 25 02:44:28 PM PST 24
Finished Feb 25 02:44:37 PM PST 24
Peak memory 222352 kb
Host smart-3085cb21-18cc-422f-b933-a9c6a3ad79ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=533772091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.533772091
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.388909963
Short name T356
Test name
Test status
Simulation time 3439945149 ps
CPU time 33.18 seconds
Started Feb 25 02:44:26 PM PST 24
Finished Feb 25 02:45:00 PM PST 24
Peak memory 215768 kb
Host smart-b1bfdc95-f9e1-4f0d-9451-2e320351d66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388909963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.388909963
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4248638901
Short name T845
Test name
Test status
Simulation time 2580111567 ps
CPU time 15.1 seconds
Started Feb 25 02:44:28 PM PST 24
Finished Feb 25 02:44:44 PM PST 24
Peak memory 215908 kb
Host smart-9de13fb8-9d55-4ac0-b69c-23326a4685a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248638901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4248638901
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.53445461
Short name T507
Test name
Test status
Simulation time 252775034 ps
CPU time 6.31 seconds
Started Feb 25 02:44:33 PM PST 24
Finished Feb 25 02:44:40 PM PST 24
Peak memory 215952 kb
Host smart-0e82aa0e-b728-484b-aa6b-c4d8bfe20217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53445461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.53445461
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2771407312
Short name T521
Test name
Test status
Simulation time 36882684 ps
CPU time 0.91 seconds
Started Feb 25 02:44:37 PM PST 24
Finished Feb 25 02:44:38 PM PST 24
Peak memory 205952 kb
Host smart-56933439-4fd3-48d5-a493-ee947522baf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771407312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2771407312
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.129311292
Short name T146
Test name
Test status
Simulation time 1262885201 ps
CPU time 7.19 seconds
Started Feb 25 02:44:25 PM PST 24
Finished Feb 25 02:44:33 PM PST 24
Peak memory 218792 kb
Host smart-87e64394-c655-4206-b6dd-546f23447593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129311292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.129311292
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2863179037
Short name T401
Test name
Test status
Simulation time 43759616 ps
CPU time 0.79 seconds
Started Feb 25 02:44:37 PM PST 24
Finished Feb 25 02:44:38 PM PST 24
Peak memory 204852 kb
Host smart-8436740a-caf1-4d94-9f77-49c110afe66e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863179037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2863179037
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2626716453
Short name T190
Test name
Test status
Simulation time 666178900 ps
CPU time 3.99 seconds
Started Feb 25 02:44:40 PM PST 24
Finished Feb 25 02:44:44 PM PST 24
Peak memory 233136 kb
Host smart-e1522823-c622-4d75-9b3c-c6396404f831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626716453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2626716453
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3583240499
Short name T673
Test name
Test status
Simulation time 19290701 ps
CPU time 0.82 seconds
Started Feb 25 02:44:33 PM PST 24
Finished Feb 25 02:44:35 PM PST 24
Peak memory 205016 kb
Host smart-cc072b36-36d2-4934-99c0-ffee6a3abab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583240499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3583240499
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.642082097
Short name T56
Test name
Test status
Simulation time 6388983684 ps
CPU time 21.19 seconds
Started Feb 25 02:44:41 PM PST 24
Finished Feb 25 02:45:02 PM PST 24
Peak memory 236656 kb
Host smart-9f23636c-20b0-4087-9c14-ce4cab04a36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642082097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.642082097
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2865215277
Short name T626
Test name
Test status
Simulation time 77212232716 ps
CPU time 163.63 seconds
Started Feb 25 02:45:01 PM PST 24
Finished Feb 25 02:47:45 PM PST 24
Peak memory 248764 kb
Host smart-26d93978-2a4e-47a4-b140-663d0a562fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865215277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2865215277
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.4016570779
Short name T581
Test name
Test status
Simulation time 111513522060 ps
CPU time 361.25 seconds
Started Feb 25 02:44:43 PM PST 24
Finished Feb 25 02:50:44 PM PST 24
Peak memory 264920 kb
Host smart-97e06701-7ab8-40f6-a4b8-a023575c89df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016570779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.4016570779
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.465346548
Short name T547
Test name
Test status
Simulation time 53472859167 ps
CPU time 48.55 seconds
Started Feb 25 02:44:34 PM PST 24
Finished Feb 25 02:45:23 PM PST 24
Peak memory 240328 kb
Host smart-c5c911bb-7ea0-4961-9877-60bbd84cd142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465346548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.465346548
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.25619656
Short name T604
Test name
Test status
Simulation time 7355060106 ps
CPU time 4.67 seconds
Started Feb 25 02:44:27 PM PST 24
Finished Feb 25 02:44:33 PM PST 24
Peak memory 217852 kb
Host smart-c6b0c0d9-0fb4-4444-a7e9-7dab699d8cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25619656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.25619656
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2034582094
Short name T589
Test name
Test status
Simulation time 7117459104 ps
CPU time 9.78 seconds
Started Feb 25 02:44:33 PM PST 24
Finished Feb 25 02:44:43 PM PST 24
Peak memory 219872 kb
Host smart-144afe7c-d4ba-46b1-ada5-f0e7d645a917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034582094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2034582094
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2202596555
Short name T242
Test name
Test status
Simulation time 32710963644 ps
CPU time 19.75 seconds
Started Feb 25 02:44:29 PM PST 24
Finished Feb 25 02:44:49 PM PST 24
Peak memory 218848 kb
Host smart-7c1f1435-daec-4ed6-b7d1-84573dd5f031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202596555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2202596555
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1689627424
Short name T754
Test name
Test status
Simulation time 927982026 ps
CPU time 3.32 seconds
Started Feb 25 02:44:30 PM PST 24
Finished Feb 25 02:44:34 PM PST 24
Peak memory 224048 kb
Host smart-4e4ce5c1-ebfd-448a-8ba4-8a9d802cce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689627424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1689627424
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3213057223
Short name T440
Test name
Test status
Simulation time 272900404 ps
CPU time 4 seconds
Started Feb 25 02:44:42 PM PST 24
Finished Feb 25 02:44:46 PM PST 24
Peak memory 218340 kb
Host smart-aa81bd02-da4f-443c-a9f0-3cc4d2f56364
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3213057223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3213057223
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.214080174
Short name T622
Test name
Test status
Simulation time 11586121947 ps
CPU time 51 seconds
Started Feb 25 02:44:40 PM PST 24
Finished Feb 25 02:45:36 PM PST 24
Peak memory 233744 kb
Host smart-ea3fb367-f3c0-4e17-9e68-e4d836a2a9a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214080174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.214080174
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.602192078
Short name T320
Test name
Test status
Simulation time 3102921533 ps
CPU time 5.33 seconds
Started Feb 25 02:44:33 PM PST 24
Finished Feb 25 02:44:38 PM PST 24
Peak memory 216072 kb
Host smart-6ea4db4f-cab1-4588-8b87-e3e03ddd2423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602192078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.602192078
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3684212940
Short name T788
Test name
Test status
Simulation time 6597659757 ps
CPU time 10 seconds
Started Feb 25 02:44:25 PM PST 24
Finished Feb 25 02:44:35 PM PST 24
Peak memory 215756 kb
Host smart-ff518e69-4005-47d5-bac8-2af7e5a265ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684212940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3684212940
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.697183083
Short name T601
Test name
Test status
Simulation time 204133082 ps
CPU time 4.97 seconds
Started Feb 25 02:44:34 PM PST 24
Finished Feb 25 02:44:39 PM PST 24
Peak memory 215764 kb
Host smart-71581145-9a70-401f-8f26-da1dddc36eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697183083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.697183083
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1681950975
Short name T368
Test name
Test status
Simulation time 35416908 ps
CPU time 0.85 seconds
Started Feb 25 02:44:30 PM PST 24
Finished Feb 25 02:44:31 PM PST 24
Peak memory 204880 kb
Host smart-a9693e20-9651-437c-892d-755b764f92e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681950975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1681950975
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.635430914
Short name T467
Test name
Test status
Simulation time 571601012 ps
CPU time 6.3 seconds
Started Feb 25 02:44:39 PM PST 24
Finished Feb 25 02:44:46 PM PST 24
Peak memory 216860 kb
Host smart-18f0717a-fe5e-49e9-8b3c-0dd9572afe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635430914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.635430914
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4233846325
Short name T54
Test name
Test status
Simulation time 57398264 ps
CPU time 0.77 seconds
Started Feb 25 02:44:48 PM PST 24
Finished Feb 25 02:44:49 PM PST 24
Peak memory 204536 kb
Host smart-4d5fb91b-bcf8-43ec-8e99-adf5ecd54969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233846325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4233846325
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2809797619
Short name T628
Test name
Test status
Simulation time 154543320 ps
CPU time 2.5 seconds
Started Feb 25 02:44:42 PM PST 24
Finished Feb 25 02:44:44 PM PST 24
Peak memory 233376 kb
Host smart-7dfa25ec-19b2-4e9f-8193-2e1f069e42d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809797619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2809797619
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2717723605
Short name T364
Test name
Test status
Simulation time 214301865 ps
CPU time 0.76 seconds
Started Feb 25 02:44:46 PM PST 24
Finished Feb 25 02:44:46 PM PST 24
Peak memory 205052 kb
Host smart-4e170c4d-0450-40b3-9f3a-afa1321b36a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717723605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2717723605
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.654411336
Short name T160
Test name
Test status
Simulation time 641751114195 ps
CPU time 220.37 seconds
Started Feb 25 02:44:39 PM PST 24
Finished Feb 25 02:48:20 PM PST 24
Peak memory 267912 kb
Host smart-3c9a5df2-647c-4c51-a052-8a5dc580dec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654411336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.654411336
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1553825467
Short name T519
Test name
Test status
Simulation time 7360774197 ps
CPU time 129.23 seconds
Started Feb 25 02:44:38 PM PST 24
Finished Feb 25 02:46:47 PM PST 24
Peak memory 254524 kb
Host smart-6db3236b-3a35-4d99-9b0c-1683b1726fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553825467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1553825467
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1531854093
Short name T844
Test name
Test status
Simulation time 4745323483 ps
CPU time 26.2 seconds
Started Feb 25 02:44:39 PM PST 24
Finished Feb 25 02:45:05 PM PST 24
Peak memory 240680 kb
Host smart-f21bf236-3ee6-48e5-9701-3de1c7f55735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531854093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1531854093
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3949821064
Short name T379
Test name
Test status
Simulation time 243140053 ps
CPU time 6.65 seconds
Started Feb 25 02:44:36 PM PST 24
Finished Feb 25 02:44:42 PM PST 24
Peak memory 228336 kb
Host smart-ea3ab924-e44e-4393-89b8-cbcf797ffccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949821064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3949821064
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1341193711
Short name T800
Test name
Test status
Simulation time 406313683 ps
CPU time 5.37 seconds
Started Feb 25 02:44:45 PM PST 24
Finished Feb 25 02:44:50 PM PST 24
Peak memory 218988 kb
Host smart-b04fd84c-7de4-4a19-9b37-9e55d92b2a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341193711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1341193711
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2057684881
Short name T765
Test name
Test status
Simulation time 880613717 ps
CPU time 3.17 seconds
Started Feb 25 02:44:37 PM PST 24
Finished Feb 25 02:44:41 PM PST 24
Peak memory 215904 kb
Host smart-fdf39611-bb9a-4ddd-b130-1fb96301299e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057684881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2057684881
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2192120030
Short name T221
Test name
Test status
Simulation time 10729539229 ps
CPU time 29.1 seconds
Started Feb 25 02:44:37 PM PST 24
Finished Feb 25 02:45:06 PM PST 24
Peak memory 229480 kb
Host smart-3b9976a1-e085-491a-a456-e765bf940c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192120030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2192120030
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3171592885
Short name T565
Test name
Test status
Simulation time 253364361 ps
CPU time 3.97 seconds
Started Feb 25 02:44:42 PM PST 24
Finished Feb 25 02:44:46 PM PST 24
Peak memory 224100 kb
Host smart-e2b72150-c616-4be8-b6cf-1570bf69cf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171592885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3171592885
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3036130451
Short name T339
Test name
Test status
Simulation time 12788280384 ps
CPU time 6.05 seconds
Started Feb 25 02:44:34 PM PST 24
Finished Feb 25 02:44:40 PM PST 24
Peak memory 222416 kb
Host smart-09422805-26d0-4ce6-8604-a57bf3071523
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3036130451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3036130451
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2137105765
Short name T140
Test name
Test status
Simulation time 485853647629 ps
CPU time 763.19 seconds
Started Feb 25 02:44:41 PM PST 24
Finished Feb 25 02:57:25 PM PST 24
Peak memory 282592 kb
Host smart-f4cf2665-9224-4c10-9668-1ed0551849f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137105765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2137105765
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2659825052
Short name T668
Test name
Test status
Simulation time 6415044918 ps
CPU time 38.27 seconds
Started Feb 25 02:44:41 PM PST 24
Finished Feb 25 02:45:19 PM PST 24
Peak memory 215860 kb
Host smart-ff1faa9b-8a8f-4fe9-bbc2-42ac4a55ecd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659825052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2659825052
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.64360470
Short name T336
Test name
Test status
Simulation time 33023493575 ps
CPU time 16.02 seconds
Started Feb 25 02:44:38 PM PST 24
Finished Feb 25 02:44:54 PM PST 24
Peak memory 215908 kb
Host smart-47ac0a47-abf5-4fbd-857f-9ce7aa1fadf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64360470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.64360470
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3108712643
Short name T781
Test name
Test status
Simulation time 169681427 ps
CPU time 0.95 seconds
Started Feb 25 02:44:40 PM PST 24
Finished Feb 25 02:44:41 PM PST 24
Peak memory 206012 kb
Host smart-7a01d134-8469-4d9d-92d0-02ffcc3ae4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108712643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3108712643
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3456005367
Short name T832
Test name
Test status
Simulation time 17658077 ps
CPU time 0.76 seconds
Started Feb 25 02:44:37 PM PST 24
Finished Feb 25 02:44:38 PM PST 24
Peak memory 204932 kb
Host smart-69d9dfb6-c1ee-42a3-9b99-73f8033b1718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456005367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3456005367
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2550909331
Short name T537
Test name
Test status
Simulation time 7904157403 ps
CPU time 7.79 seconds
Started Feb 25 02:44:34 PM PST 24
Finished Feb 25 02:44:42 PM PST 24
Peak memory 237552 kb
Host smart-242ad3bf-618a-4ee8-8ad6-c6c503577564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550909331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2550909331
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3740834213
Short name T542
Test name
Test status
Simulation time 13985430 ps
CPU time 0.78 seconds
Started Feb 25 02:44:43 PM PST 24
Finished Feb 25 02:44:44 PM PST 24
Peak memory 204728 kb
Host smart-c5efe7e7-5852-4923-89d1-ef1d8628eaf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740834213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3740834213
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1891226462
Short name T177
Test name
Test status
Simulation time 34842255 ps
CPU time 2.64 seconds
Started Feb 25 02:44:33 PM PST 24
Finished Feb 25 02:44:36 PM PST 24
Peak memory 233152 kb
Host smart-bf5e045e-10fb-4e11-a394-6e6a5ae0e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891226462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1891226462
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2436827636
Short name T689
Test name
Test status
Simulation time 45403222 ps
CPU time 0.72 seconds
Started Feb 25 02:44:34 PM PST 24
Finished Feb 25 02:44:35 PM PST 24
Peak memory 205012 kb
Host smart-2f2fb3f3-8c36-4cbf-9a9f-6e4231d46dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436827636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2436827636
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2781300548
Short name T947
Test name
Test status
Simulation time 5883823144 ps
CPU time 45.46 seconds
Started Feb 25 02:44:50 PM PST 24
Finished Feb 25 02:45:35 PM PST 24
Peak memory 248728 kb
Host smart-ffc93985-b2da-44ac-8f1b-88596b27a54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781300548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2781300548
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2810900361
Short name T545
Test name
Test status
Simulation time 9070859213 ps
CPU time 73.69 seconds
Started Feb 25 02:44:50 PM PST 24
Finished Feb 25 02:46:04 PM PST 24
Peak memory 248848 kb
Host smart-8c8fdb8c-0fe2-4e8c-ad38-180e001ef01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810900361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2810900361
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1195134070
Short name T577
Test name
Test status
Simulation time 22466899701 ps
CPU time 80.47 seconds
Started Feb 25 02:44:42 PM PST 24
Finished Feb 25 02:46:02 PM PST 24
Peak memory 234668 kb
Host smart-6023ef18-f4b3-4d63-a05d-20d97ca26502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195134070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1195134070
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.313463985
Short name T849
Test name
Test status
Simulation time 924458031 ps
CPU time 16.75 seconds
Started Feb 25 02:44:41 PM PST 24
Finished Feb 25 02:44:58 PM PST 24
Peak memory 224044 kb
Host smart-d851d522-f743-43d7-9446-095db721b8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313463985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.313463985
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.475809608
Short name T826
Test name
Test status
Simulation time 241165570 ps
CPU time 4.99 seconds
Started Feb 25 02:44:37 PM PST 24
Finished Feb 25 02:44:42 PM PST 24
Peak memory 234596 kb
Host smart-5b5dccd7-6168-40a8-b422-37b8c374c6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475809608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.475809608
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3991753639
Short name T427
Test name
Test status
Simulation time 2165661565 ps
CPU time 4.72 seconds
Started Feb 25 02:44:41 PM PST 24
Finished Feb 25 02:44:46 PM PST 24
Peak memory 218420 kb
Host smart-f81e3f36-c0c4-4e60-a8a7-b78ec20ba100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991753639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3991753639
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3104375679
Short name T973
Test name
Test status
Simulation time 11396774571 ps
CPU time 34.26 seconds
Started Feb 25 02:44:40 PM PST 24
Finished Feb 25 02:45:15 PM PST 24
Peak memory 231012 kb
Host smart-526117ed-fdd3-4faa-a0cd-bef11a5e5517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104375679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3104375679
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.203794266
Short name T709
Test name
Test status
Simulation time 3068982173 ps
CPU time 9.26 seconds
Started Feb 25 02:44:41 PM PST 24
Finished Feb 25 02:44:51 PM PST 24
Peak memory 216108 kb
Host smart-93325a4e-2cae-4bad-8d39-f6f3dbb575f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203794266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.203794266
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2867249999
Short name T522
Test name
Test status
Simulation time 936021011 ps
CPU time 3.52 seconds
Started Feb 25 02:44:52 PM PST 24
Finished Feb 25 02:44:55 PM PST 24
Peak memory 218292 kb
Host smart-b406f918-ed32-4783-b8ec-5aff82bc17a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2867249999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2867249999
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2571473799
Short name T50
Test name
Test status
Simulation time 61442156 ps
CPU time 1.03 seconds
Started Feb 25 02:44:53 PM PST 24
Finished Feb 25 02:44:54 PM PST 24
Peak memory 205804 kb
Host smart-6cdc419c-6a95-4366-88ce-08287db65297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571473799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2571473799
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1416463450
Short name T59
Test name
Test status
Simulation time 3642030194 ps
CPU time 21.48 seconds
Started Feb 25 02:44:39 PM PST 24
Finished Feb 25 02:45:01 PM PST 24
Peak memory 215908 kb
Host smart-0bb024a5-7f85-4e0e-ba6f-25519ac7ec17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416463450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1416463450
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.559535796
Short name T730
Test name
Test status
Simulation time 8332070986 ps
CPU time 12.09 seconds
Started Feb 25 02:44:39 PM PST 24
Finished Feb 25 02:44:51 PM PST 24
Peak memory 215784 kb
Host smart-43fabe5a-3d6f-4669-8b1c-d9a55d06afbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559535796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.559535796
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2081946474
Short name T316
Test name
Test status
Simulation time 142737881 ps
CPU time 1.92 seconds
Started Feb 25 02:44:40 PM PST 24
Finished Feb 25 02:44:42 PM PST 24
Peak memory 215828 kb
Host smart-a03ecf05-a0da-4045-9f26-64cc6fb2289d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081946474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2081946474
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1781753668
Short name T759
Test name
Test status
Simulation time 295738762 ps
CPU time 1.03 seconds
Started Feb 25 02:44:38 PM PST 24
Finished Feb 25 02:44:39 PM PST 24
Peak memory 205856 kb
Host smart-0af01591-ad82-4169-8496-1a6af1d8974a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781753668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1781753668
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1687216476
Short name T416
Test name
Test status
Simulation time 659892534 ps
CPU time 7.03 seconds
Started Feb 25 02:44:37 PM PST 24
Finished Feb 25 02:44:44 PM PST 24
Peak memory 233136 kb
Host smart-af9dcb74-d22f-4f9d-be98-8680e94f78e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687216476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1687216476
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3196426016
Short name T654
Test name
Test status
Simulation time 13726929 ps
CPU time 0.71 seconds
Started Feb 25 02:44:42 PM PST 24
Finished Feb 25 02:44:42 PM PST 24
Peak memory 204536 kb
Host smart-e91f1524-5ffd-459f-bdcb-15498d560f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196426016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3196426016
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3673034609
Short name T328
Test name
Test status
Simulation time 2988080764 ps
CPU time 5.24 seconds
Started Feb 25 02:44:51 PM PST 24
Finished Feb 25 02:44:57 PM PST 24
Peak memory 218556 kb
Host smart-fae49959-f579-4e15-88ee-1bded2875e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673034609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3673034609
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1615602114
Short name T644
Test name
Test status
Simulation time 70417524 ps
CPU time 0.75 seconds
Started Feb 25 02:44:45 PM PST 24
Finished Feb 25 02:44:46 PM PST 24
Peak memory 205640 kb
Host smart-82bbf315-f7fd-48d2-9b55-94edabcabe6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615602114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1615602114
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2792675967
Short name T965
Test name
Test status
Simulation time 99241304477 ps
CPU time 132.34 seconds
Started Feb 25 02:44:50 PM PST 24
Finished Feb 25 02:47:02 PM PST 24
Peak memory 254048 kb
Host smart-b398e766-7f8c-41d8-9a85-2b091ab7680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792675967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2792675967
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2510415976
Short name T265
Test name
Test status
Simulation time 20311580553 ps
CPU time 92.66 seconds
Started Feb 25 02:44:52 PM PST 24
Finished Feb 25 02:46:25 PM PST 24
Peak memory 248768 kb
Host smart-e3320570-3f79-483a-89d2-8c7da6245336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510415976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2510415976
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1001185406
Short name T237
Test name
Test status
Simulation time 27694823392 ps
CPU time 92.63 seconds
Started Feb 25 02:44:49 PM PST 24
Finished Feb 25 02:46:22 PM PST 24
Peak memory 255272 kb
Host smart-513f29af-63c3-486e-a26e-4648ac6cd140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001185406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1001185406
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1432440817
Short name T602
Test name
Test status
Simulation time 11037503261 ps
CPU time 61.16 seconds
Started Feb 25 02:44:49 PM PST 24
Finished Feb 25 02:45:51 PM PST 24
Peak memory 239868 kb
Host smart-4846d36c-1bb6-4dcf-8163-20a50cb31086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432440817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1432440817
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.354627732
Short name T464
Test name
Test status
Simulation time 2821977105 ps
CPU time 4.65 seconds
Started Feb 25 02:44:49 PM PST 24
Finished Feb 25 02:44:54 PM PST 24
Peak memory 216976 kb
Host smart-a156e92b-d20d-4742-a29f-c5a4bdd65fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354627732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.354627732
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3372837248
Short name T729
Test name
Test status
Simulation time 5777016681 ps
CPU time 11.74 seconds
Started Feb 25 02:44:41 PM PST 24
Finished Feb 25 02:44:53 PM PST 24
Peak memory 231384 kb
Host smart-e049e850-1cbe-4570-9981-fe39f5f2812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372837248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3372837248
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2201366347
Short name T596
Test name
Test status
Simulation time 3029064045 ps
CPU time 6.31 seconds
Started Feb 25 02:44:44 PM PST 24
Finished Feb 25 02:44:50 PM PST 24
Peak memory 217616 kb
Host smart-4d0d7b00-da03-48e0-acc7-9d0501db955f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201366347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2201366347
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3435885041
Short name T732
Test name
Test status
Simulation time 2897067912 ps
CPU time 4.22 seconds
Started Feb 25 02:44:44 PM PST 24
Finished Feb 25 02:44:48 PM PST 24
Peak memory 232708 kb
Host smart-2ae8e90e-6435-4119-97bd-b5cbe3695a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435885041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3435885041
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3624796301
Short name T75
Test name
Test status
Simulation time 1560910338 ps
CPU time 4.31 seconds
Started Feb 25 02:44:51 PM PST 24
Finished Feb 25 02:44:55 PM PST 24
Peak memory 219728 kb
Host smart-8e2d7839-96ac-4dcf-940f-0660766c607e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3624796301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3624796301
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.708804228
Short name T851
Test name
Test status
Simulation time 7797688167 ps
CPU time 37.66 seconds
Started Feb 25 02:44:45 PM PST 24
Finished Feb 25 02:45:23 PM PST 24
Peak memory 236404 kb
Host smart-e8e66e98-9fde-4c0f-b518-042d6fa39c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708804228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.708804228
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3010888731
Short name T747
Test name
Test status
Simulation time 17115459516 ps
CPU time 39.54 seconds
Started Feb 25 02:44:48 PM PST 24
Finished Feb 25 02:45:27 PM PST 24
Peak memory 215824 kb
Host smart-70c5bff0-b030-4775-b7ba-8344a57e5972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010888731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3010888731
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3204597795
Short name T358
Test name
Test status
Simulation time 4039864894 ps
CPU time 4.68 seconds
Started Feb 25 02:44:45 PM PST 24
Finished Feb 25 02:44:50 PM PST 24
Peak memory 216216 kb
Host smart-e00819f0-5a60-4bcd-9501-824f605bfa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204597795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3204597795
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1569300153
Short name T482
Test name
Test status
Simulation time 80893288 ps
CPU time 2.22 seconds
Started Feb 25 02:44:50 PM PST 24
Finished Feb 25 02:44:53 PM PST 24
Peak memory 215792 kb
Host smart-bac6a673-2dc7-4495-9b9b-047ab5e64a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569300153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1569300153
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.624281150
Short name T852
Test name
Test status
Simulation time 31700301 ps
CPU time 0.75 seconds
Started Feb 25 02:44:50 PM PST 24
Finished Feb 25 02:44:51 PM PST 24
Peak memory 204848 kb
Host smart-20073733-0e3d-4aaa-8dcb-1d900410ed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624281150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.624281150
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2348146765
Short name T350
Test name
Test status
Simulation time 35321522038 ps
CPU time 27.05 seconds
Started Feb 25 02:44:55 PM PST 24
Finished Feb 25 02:45:22 PM PST 24
Peak memory 226784 kb
Host smart-1ed30a7c-be15-4e22-8483-8414fce745d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348146765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2348146765
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2428179208
Short name T346
Test name
Test status
Simulation time 11194702 ps
CPU time 0.73 seconds
Started Feb 25 02:44:50 PM PST 24
Finished Feb 25 02:44:51 PM PST 24
Peak memory 203984 kb
Host smart-607e07a4-ee29-4826-a0d2-27ba67909151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428179208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2428179208
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.266342410
Short name T874
Test name
Test status
Simulation time 49429909 ps
CPU time 2.85 seconds
Started Feb 25 02:44:55 PM PST 24
Finished Feb 25 02:44:57 PM PST 24
Peak memory 233136 kb
Host smart-ae4de52f-cfad-4054-b829-aeba07e63a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266342410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.266342410
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.335440092
Short name T300
Test name
Test status
Simulation time 68580088 ps
CPU time 0.82 seconds
Started Feb 25 02:44:48 PM PST 24
Finished Feb 25 02:44:49 PM PST 24
Peak memory 205724 kb
Host smart-f4b54419-6eae-4558-9c91-2703c5adf73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335440092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.335440092
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3237776270
Short name T227
Test name
Test status
Simulation time 966145158 ps
CPU time 10.39 seconds
Started Feb 25 02:44:44 PM PST 24
Finished Feb 25 02:44:55 PM PST 24
Peak memory 232264 kb
Host smart-a7a7d118-899a-49b2-ba40-d29456e40e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237776270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3237776270
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2419291790
Short name T19
Test name
Test status
Simulation time 89027184682 ps
CPU time 318.7 seconds
Started Feb 25 02:44:52 PM PST 24
Finished Feb 25 02:50:10 PM PST 24
Peak memory 251872 kb
Host smart-dcc5709e-a831-4f58-8e0d-671be2f0f38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419291790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2419291790
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3102125805
Short name T357
Test name
Test status
Simulation time 23078302634 ps
CPU time 57.15 seconds
Started Feb 25 02:44:49 PM PST 24
Finished Feb 25 02:45:47 PM PST 24
Peak memory 248152 kb
Host smart-84b9cd78-f268-4908-942f-29cad0fe9e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102125805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3102125805
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2089127433
Short name T283
Test name
Test status
Simulation time 41540140008 ps
CPU time 41.49 seconds
Started Feb 25 02:44:54 PM PST 24
Finished Feb 25 02:45:35 PM PST 24
Peak memory 245276 kb
Host smart-a2101a7d-887a-4760-8f64-cd98ec04ce95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089127433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2089127433
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.250367699
Short name T178
Test name
Test status
Simulation time 635165858 ps
CPU time 4.03 seconds
Started Feb 25 02:44:54 PM PST 24
Finished Feb 25 02:44:58 PM PST 24
Peak memory 224068 kb
Host smart-119931aa-7c47-4b6a-976f-6a9a3a49f6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250367699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.250367699
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.540336228
Short name T661
Test name
Test status
Simulation time 4575545938 ps
CPU time 10.06 seconds
Started Feb 25 02:44:46 PM PST 24
Finished Feb 25 02:44:56 PM PST 24
Peak memory 216760 kb
Host smart-f2b939c7-a28e-4457-9885-2a6417717f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540336228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.540336228
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2803412898
Short name T637
Test name
Test status
Simulation time 7838948040 ps
CPU time 21.13 seconds
Started Feb 25 02:44:41 PM PST 24
Finished Feb 25 02:45:03 PM PST 24
Peak memory 233620 kb
Host smart-cf960dce-74d9-46bf-bfba-ff366bdae72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803412898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2803412898
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.810689305
Short name T608
Test name
Test status
Simulation time 8627897972 ps
CPU time 8.95 seconds
Started Feb 25 02:44:44 PM PST 24
Finished Feb 25 02:44:53 PM PST 24
Peak memory 233804 kb
Host smart-f4f3a4f4-6e33-4697-8d6f-86bc12c2745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810689305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.810689305
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1514038914
Short name T70
Test name
Test status
Simulation time 86692302 ps
CPU time 3.21 seconds
Started Feb 25 02:44:49 PM PST 24
Finished Feb 25 02:44:53 PM PST 24
Peak memory 215996 kb
Host smart-e7a55f04-fa21-401d-8341-4b1b421eb9e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1514038914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1514038914
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2113623034
Short name T139
Test name
Test status
Simulation time 263485343 ps
CPU time 1.11 seconds
Started Feb 25 02:44:49 PM PST 24
Finished Feb 25 02:44:51 PM PST 24
Peak memory 206068 kb
Host smart-a9c5da92-b0e6-4c5b-a169-d6d54d962eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113623034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2113623034
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1257380695
Short name T17
Test name
Test status
Simulation time 3396590702 ps
CPU time 15.59 seconds
Started Feb 25 02:44:41 PM PST 24
Finished Feb 25 02:44:57 PM PST 24
Peak memory 216072 kb
Host smart-79dc6394-a710-43c0-bfbc-2c547fe8208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257380695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1257380695
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2082730279
Short name T470
Test name
Test status
Simulation time 3085556315 ps
CPU time 12.98 seconds
Started Feb 25 02:44:49 PM PST 24
Finished Feb 25 02:45:02 PM PST 24
Peak memory 215800 kb
Host smart-a59724dd-8871-4e3c-9344-d52fd716fb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082730279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2082730279
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2829849918
Short name T524
Test name
Test status
Simulation time 781604463 ps
CPU time 5.32 seconds
Started Feb 25 02:44:49 PM PST 24
Finished Feb 25 02:44:55 PM PST 24
Peak memory 216012 kb
Host smart-19bf5291-5db1-4e14-90d5-2b0c94da5683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829849918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2829849918
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1106997983
Short name T802
Test name
Test status
Simulation time 46148961 ps
CPU time 0.83 seconds
Started Feb 25 02:44:51 PM PST 24
Finished Feb 25 02:44:52 PM PST 24
Peak memory 204908 kb
Host smart-655b3479-3b5b-492b-a2a7-27f36ace3156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106997983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1106997983
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2714045994
Short name T457
Test name
Test status
Simulation time 1020214054 ps
CPU time 13.41 seconds
Started Feb 25 02:45:01 PM PST 24
Finished Feb 25 02:45:15 PM PST 24
Peak memory 233288 kb
Host smart-86dd9735-5615-4526-bd7e-622fca679df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714045994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2714045994
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2284666035
Short name T930
Test name
Test status
Simulation time 12568139 ps
CPU time 0.72 seconds
Started Feb 25 02:44:52 PM PST 24
Finished Feb 25 02:44:53 PM PST 24
Peak memory 204552 kb
Host smart-ccb20e11-b292-4ba3-8a6b-60dfa6d037da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284666035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2284666035
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.540778551
Short name T275
Test name
Test status
Simulation time 148021970 ps
CPU time 2.56 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:45:05 PM PST 24
Peak memory 233344 kb
Host smart-9c16c2f0-9bd2-4342-9933-e89195769203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540778551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.540778551
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.597475493
Short name T939
Test name
Test status
Simulation time 82630856 ps
CPU time 0.77 seconds
Started Feb 25 02:44:48 PM PST 24
Finished Feb 25 02:44:49 PM PST 24
Peak memory 206032 kb
Host smart-f7514e34-0249-4d85-b034-24884b01d455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597475493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.597475493
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3622852877
Short name T151
Test name
Test status
Simulation time 8026964239 ps
CPU time 77.43 seconds
Started Feb 25 02:45:00 PM PST 24
Finished Feb 25 02:46:17 PM PST 24
Peak memory 249688 kb
Host smart-a052f77d-2243-48d4-930d-27fed6ae9166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622852877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3622852877
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1725380278
Short name T209
Test name
Test status
Simulation time 65018219268 ps
CPU time 495.15 seconds
Started Feb 25 02:45:05 PM PST 24
Finished Feb 25 02:53:20 PM PST 24
Peak memory 253248 kb
Host smart-66760e6e-809b-4fce-8b11-b667963c8ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725380278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1725380278
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1885285063
Short name T938
Test name
Test status
Simulation time 15469142802 ps
CPU time 73.26 seconds
Started Feb 25 02:44:52 PM PST 24
Finished Feb 25 02:46:05 PM PST 24
Peak memory 240440 kb
Host smart-25bf5fa9-a468-4234-bec1-3001c506adc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885285063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1885285063
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3331421871
Short name T395
Test name
Test status
Simulation time 2630532682 ps
CPU time 5.53 seconds
Started Feb 25 02:44:52 PM PST 24
Finished Feb 25 02:44:57 PM PST 24
Peak memory 217468 kb
Host smart-61f6cfbb-021a-4ac5-abcb-1f4421eaf1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331421871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3331421871
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1924255295
Short name T500
Test name
Test status
Simulation time 7226602421 ps
CPU time 12.07 seconds
Started Feb 25 02:44:57 PM PST 24
Finished Feb 25 02:45:09 PM PST 24
Peak memory 232308 kb
Host smart-1e040dc1-d3fa-4bda-9358-5665f4a8f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924255295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1924255295
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1343307358
Short name T208
Test name
Test status
Simulation time 11682208358 ps
CPU time 23.36 seconds
Started Feb 25 02:44:40 PM PST 24
Finished Feb 25 02:45:04 PM PST 24
Peak memory 245212 kb
Host smart-c2ea58c2-0f6e-4d9d-9b55-e3d3d0a5babc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343307358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1343307358
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1466809633
Short name T392
Test name
Test status
Simulation time 10143915871 ps
CPU time 12.09 seconds
Started Feb 25 02:44:49 PM PST 24
Finished Feb 25 02:45:01 PM PST 24
Peak memory 227328 kb
Host smart-047b15e7-c60e-4e82-8b90-6a586a4ff2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466809633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1466809633
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2377767512
Short name T701
Test name
Test status
Simulation time 189175491 ps
CPU time 3.6 seconds
Started Feb 25 02:44:57 PM PST 24
Finished Feb 25 02:45:01 PM PST 24
Peak memory 219512 kb
Host smart-72e50b60-fd8c-4b72-bf4d-9fd40fa79506
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2377767512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2377767512
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.138556621
Short name T740
Test name
Test status
Simulation time 21333635096 ps
CPU time 60.08 seconds
Started Feb 25 02:44:45 PM PST 24
Finished Feb 25 02:45:45 PM PST 24
Peak memory 215852 kb
Host smart-fcbc5e8e-cd2d-4819-968a-720454cebe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138556621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.138556621
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3750593286
Short name T638
Test name
Test status
Simulation time 3168294499 ps
CPU time 9.67 seconds
Started Feb 25 02:44:57 PM PST 24
Finished Feb 25 02:45:07 PM PST 24
Peak memory 215844 kb
Host smart-9984345e-531e-40fe-a3b2-6c7b4318dcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750593286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3750593286
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.432898270
Short name T548
Test name
Test status
Simulation time 27762404 ps
CPU time 0.78 seconds
Started Feb 25 02:44:54 PM PST 24
Finished Feb 25 02:44:55 PM PST 24
Peak memory 204948 kb
Host smart-6164fc8a-ca6b-41dd-a981-dda0aa74bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432898270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.432898270
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1951257780
Short name T343
Test name
Test status
Simulation time 140792295 ps
CPU time 1.02 seconds
Started Feb 25 02:44:49 PM PST 24
Finished Feb 25 02:44:51 PM PST 24
Peak memory 205368 kb
Host smart-0dc8c68a-b3b6-46a4-9cc5-933950533f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951257780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1951257780
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1749375986
Short name T593
Test name
Test status
Simulation time 73409085567 ps
CPU time 11.64 seconds
Started Feb 25 02:44:53 PM PST 24
Finished Feb 25 02:45:04 PM PST 24
Peak memory 218800 kb
Host smart-257e0cea-12cb-40e8-9db7-4a7f6d707bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749375986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1749375986
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.113221713
Short name T378
Test name
Test status
Simulation time 33023608 ps
CPU time 0.74 seconds
Started Feb 25 02:44:56 PM PST 24
Finished Feb 25 02:44:56 PM PST 24
Peak memory 204536 kb
Host smart-2366bede-6040-42f1-8265-421bc9f24560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113221713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.113221713
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.216499578
Short name T556
Test name
Test status
Simulation time 274832406 ps
CPU time 3.61 seconds
Started Feb 25 02:44:54 PM PST 24
Finished Feb 25 02:44:58 PM PST 24
Peak memory 219256 kb
Host smart-81518a88-ffca-4cad-8392-d994e03ed98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216499578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.216499578
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.693554858
Short name T716
Test name
Test status
Simulation time 25734296 ps
CPU time 0.76 seconds
Started Feb 25 02:44:56 PM PST 24
Finished Feb 25 02:44:57 PM PST 24
Peak memory 204660 kb
Host smart-45c3f749-4ab5-4bec-8c19-e790e0d4070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693554858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.693554858
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3748061953
Short name T235
Test name
Test status
Simulation time 41366263990 ps
CPU time 118.76 seconds
Started Feb 25 02:44:57 PM PST 24
Finished Feb 25 02:46:56 PM PST 24
Peak memory 238544 kb
Host smart-17cc5c17-ab48-4cc2-8dba-57947ee3edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748061953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3748061953
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2062018458
Short name T431
Test name
Test status
Simulation time 29653685238 ps
CPU time 98.92 seconds
Started Feb 25 02:44:52 PM PST 24
Finished Feb 25 02:46:31 PM PST 24
Peak memory 264496 kb
Host smart-3c527da4-158e-404e-9bfb-35383b058772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062018458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2062018458
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.78932006
Short name T603
Test name
Test status
Simulation time 3965867613 ps
CPU time 50.73 seconds
Started Feb 25 02:44:57 PM PST 24
Finished Feb 25 02:45:48 PM PST 24
Peak memory 240556 kb
Host smart-ba42bd86-c852-4ea0-83cd-34eadcfd3e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78932006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.78932006
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.446616857
Short name T895
Test name
Test status
Simulation time 4461453781 ps
CPU time 22.9 seconds
Started Feb 25 02:44:54 PM PST 24
Finished Feb 25 02:45:17 PM PST 24
Peak memory 246480 kb
Host smart-d3e28434-4c84-4918-8c50-ff2d6497d40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446616857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.446616857
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.891299509
Short name T723
Test name
Test status
Simulation time 663340882 ps
CPU time 4.84 seconds
Started Feb 25 02:44:58 PM PST 24
Finished Feb 25 02:45:03 PM PST 24
Peak memory 233192 kb
Host smart-c3b7d39b-ab07-440b-9f04-a92f6cf872ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891299509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.891299509
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1577750186
Short name T743
Test name
Test status
Simulation time 1309893223 ps
CPU time 5.98 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:45:08 PM PST 24
Peak memory 224088 kb
Host smart-58c78a43-5601-4c03-84bb-b1fdb7aa349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577750186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1577750186
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3192463834
Short name T174
Test name
Test status
Simulation time 816174358 ps
CPU time 4.29 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:45:07 PM PST 24
Peak memory 227688 kb
Host smart-e1c214e0-ca56-4126-88f5-587aa195d254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192463834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3192463834
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1362393438
Short name T148
Test name
Test status
Simulation time 546457031 ps
CPU time 5.24 seconds
Started Feb 25 02:44:57 PM PST 24
Finished Feb 25 02:45:02 PM PST 24
Peak memory 232196 kb
Host smart-c84f8069-6dd0-4c79-9ac0-dc1f30356cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362393438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1362393438
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1384468369
Short name T412
Test name
Test status
Simulation time 117661251 ps
CPU time 3.63 seconds
Started Feb 25 02:44:58 PM PST 24
Finished Feb 25 02:45:02 PM PST 24
Peak memory 222316 kb
Host smart-d5c30e93-4467-4eeb-88ef-a7529ebaa3ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1384468369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1384468369
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2650167710
Short name T896
Test name
Test status
Simulation time 896970900 ps
CPU time 1.15 seconds
Started Feb 25 02:44:56 PM PST 24
Finished Feb 25 02:44:57 PM PST 24
Peak memory 206144 kb
Host smart-5e8ec562-383f-459f-b494-7e7192b6065e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650167710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2650167710
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.63228809
Short name T486
Test name
Test status
Simulation time 2874619764 ps
CPU time 16 seconds
Started Feb 25 02:44:57 PM PST 24
Finished Feb 25 02:45:13 PM PST 24
Peak memory 215648 kb
Host smart-d432acf6-3228-4680-919d-64f10b05bb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63228809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.63228809
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3252508079
Short name T384
Test name
Test status
Simulation time 1111193340 ps
CPU time 8.44 seconds
Started Feb 25 02:44:59 PM PST 24
Finished Feb 25 02:45:08 PM PST 24
Peak memory 215756 kb
Host smart-7b2013b9-060f-4e83-88ae-b7b02cffcf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252508079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3252508079
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2860210541
Short name T317
Test name
Test status
Simulation time 65689277 ps
CPU time 1.14 seconds
Started Feb 25 02:44:59 PM PST 24
Finished Feb 25 02:45:00 PM PST 24
Peak memory 207128 kb
Host smart-61a5b58c-a1c2-4fbd-8155-d0d6e3efeae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860210541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2860210541
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2415899798
Short name T365
Test name
Test status
Simulation time 607017734 ps
CPU time 1.21 seconds
Started Feb 25 02:44:56 PM PST 24
Finished Feb 25 02:44:57 PM PST 24
Peak memory 205988 kb
Host smart-5cc48cf5-d790-427c-97b4-fd37e6c6ba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415899798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2415899798
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3845446758
Short name T168
Test name
Test status
Simulation time 21072182927 ps
CPU time 24.22 seconds
Started Feb 25 02:45:00 PM PST 24
Finished Feb 25 02:45:24 PM PST 24
Peak memory 238992 kb
Host smart-7fa722b2-b929-4127-ad84-a0f530e5bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845446758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3845446758
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.243400035
Short name T35
Test name
Test status
Simulation time 28252970 ps
CPU time 0.7 seconds
Started Feb 25 02:43:09 PM PST 24
Finished Feb 25 02:43:10 PM PST 24
Peak memory 203984 kb
Host smart-4bc4aa88-c667-461d-afc9-8a4d6955f388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243400035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.243400035
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3299213292
Short name T419
Test name
Test status
Simulation time 666866880 ps
CPU time 3.35 seconds
Started Feb 25 02:42:58 PM PST 24
Finished Feb 25 02:43:02 PM PST 24
Peak memory 223996 kb
Host smart-f8980de9-af72-467c-a56f-9d86435a8b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299213292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3299213292
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.582587375
Short name T745
Test name
Test status
Simulation time 50662336 ps
CPU time 0.8 seconds
Started Feb 25 02:42:58 PM PST 24
Finished Feb 25 02:42:59 PM PST 24
Peak memory 205704 kb
Host smart-d2a87d89-6eb0-4e7e-94cf-8cee3fd52b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582587375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.582587375
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3068665094
Short name T862
Test name
Test status
Simulation time 96363130184 ps
CPU time 477.72 seconds
Started Feb 25 02:43:00 PM PST 24
Finished Feb 25 02:50:58 PM PST 24
Peak memory 265084 kb
Host smart-705f685b-455e-488d-9a2b-733bad37420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068665094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3068665094
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2468484303
Short name T236
Test name
Test status
Simulation time 15731424585 ps
CPU time 74.24 seconds
Started Feb 25 02:43:03 PM PST 24
Finished Feb 25 02:44:18 PM PST 24
Peak memory 256380 kb
Host smart-1dbce98d-126b-4275-a156-88b09fd1469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468484303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2468484303
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3565334778
Short name T333
Test name
Test status
Simulation time 15524908860 ps
CPU time 65.13 seconds
Started Feb 25 02:43:01 PM PST 24
Finished Feb 25 02:44:07 PM PST 24
Peak memory 236124 kb
Host smart-9b16779f-8c2d-40ef-af8d-9f8f51ebb9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565334778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3565334778
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4143930135
Short name T836
Test name
Test status
Simulation time 20879114955 ps
CPU time 50.82 seconds
Started Feb 25 02:43:01 PM PST 24
Finished Feb 25 02:43:53 PM PST 24
Peak memory 240432 kb
Host smart-3ef12852-68b9-44b4-ab1b-41d36d0dca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143930135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4143930135
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1267788276
Short name T741
Test name
Test status
Simulation time 570534954 ps
CPU time 5.41 seconds
Started Feb 25 02:43:06 PM PST 24
Finished Feb 25 02:43:12 PM PST 24
Peak memory 217332 kb
Host smart-4691060e-e16a-4ec2-90c6-b7744dca20ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267788276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1267788276
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2607427715
Short name T4
Test name
Test status
Simulation time 2102673641 ps
CPU time 8.78 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:19 PM PST 24
Peak memory 233584 kb
Host smart-3103b86e-5967-4494-af46-0a8a3ed5ae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607427715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2607427715
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2810936357
Short name T805
Test name
Test status
Simulation time 33580863 ps
CPU time 1.08 seconds
Started Feb 25 02:43:04 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 216128 kb
Host smart-52244496-9c2a-481b-9f6a-69c6b9518d0d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810936357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2810936357
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2200510604
Short name T164
Test name
Test status
Simulation time 177326365 ps
CPU time 2.89 seconds
Started Feb 25 02:42:59 PM PST 24
Finished Feb 25 02:43:03 PM PST 24
Peak memory 223752 kb
Host smart-3855929a-ee01-4c75-8314-353fb27b4363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200510604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2200510604
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3023782790
Short name T183
Test name
Test status
Simulation time 34826660 ps
CPU time 2.72 seconds
Started Feb 25 02:43:02 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 232264 kb
Host smart-c1efae9a-1301-43f1-aaab-73a8fd604c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023782790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3023782790
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.3531426980
Short name T635
Test name
Test status
Simulation time 25370729 ps
CPU time 0.72 seconds
Started Feb 25 02:43:11 PM PST 24
Finished Feb 25 02:43:11 PM PST 24
Peak memory 215720 kb
Host smart-f985f6fe-4513-4c7f-846d-378992d8edc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531426980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.3531426980
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3993514878
Short name T839
Test name
Test status
Simulation time 1761822342 ps
CPU time 5.29 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:15 PM PST 24
Peak memory 222236 kb
Host smart-2a9e1305-49de-45ea-8a99-5ffb22416b7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3993514878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3993514878
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.690087606
Short name T44
Test name
Test status
Simulation time 377627928 ps
CPU time 1.16 seconds
Started Feb 25 02:43:06 PM PST 24
Finished Feb 25 02:43:08 PM PST 24
Peak memory 236604 kb
Host smart-8787c0b5-2011-4cb1-bc87-6595a713bdc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690087606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.690087606
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3467319036
Short name T842
Test name
Test status
Simulation time 52666138 ps
CPU time 1.23 seconds
Started Feb 25 02:43:02 PM PST 24
Finished Feb 25 02:43:03 PM PST 24
Peak memory 206352 kb
Host smart-728d765f-63a7-48b1-82bf-c0a9934899b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467319036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3467319036
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3911959144
Short name T505
Test name
Test status
Simulation time 7128222814 ps
CPU time 32.82 seconds
Started Feb 25 02:43:07 PM PST 24
Finished Feb 25 02:43:40 PM PST 24
Peak memory 215892 kb
Host smart-2d2d50cb-366d-4e8a-9d83-52f3754644cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911959144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3911959144
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.48995359
Short name T902
Test name
Test status
Simulation time 1804134683 ps
CPU time 11.55 seconds
Started Feb 25 02:43:01 PM PST 24
Finished Feb 25 02:43:13 PM PST 24
Peak memory 215700 kb
Host smart-c5ee8cd0-7c7f-4172-8e7c-eaff719333b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48995359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.48995359
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4265286965
Short name T402
Test name
Test status
Simulation time 6790180899 ps
CPU time 6.68 seconds
Started Feb 25 02:43:02 PM PST 24
Finished Feb 25 02:43:09 PM PST 24
Peak memory 215860 kb
Host smart-d7b6c593-6d4e-4a3a-a027-57ef279e9327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265286965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4265286965
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2846133172
Short name T369
Test name
Test status
Simulation time 87586027 ps
CPU time 0.74 seconds
Started Feb 25 02:43:04 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 204932 kb
Host smart-5caaf4ee-10c1-458a-a00e-38ef185dd179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846133172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2846133172
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2568559207
Short name T679
Test name
Test status
Simulation time 5363940036 ps
CPU time 20.12 seconds
Started Feb 25 02:42:58 PM PST 24
Finished Feb 25 02:43:19 PM PST 24
Peak memory 240300 kb
Host smart-5bed3fd2-b1fa-4f1a-9891-8134c0625be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568559207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2568559207
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3764761962
Short name T670
Test name
Test status
Simulation time 16693382 ps
CPU time 0.76 seconds
Started Feb 25 02:45:03 PM PST 24
Finished Feb 25 02:45:04 PM PST 24
Peak memory 204404 kb
Host smart-e73aa390-869d-4897-a14e-a3bc26bbcca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764761962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3764761962
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2674194816
Short name T706
Test name
Test status
Simulation time 4660747310 ps
CPU time 6.33 seconds
Started Feb 25 02:44:59 PM PST 24
Finished Feb 25 02:45:05 PM PST 24
Peak memory 234388 kb
Host smart-06f49a41-385d-4981-a9a3-ab254d57732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674194816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2674194816
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1556826669
Short name T659
Test name
Test status
Simulation time 254885668 ps
CPU time 0.75 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:45:03 PM PST 24
Peak memory 205052 kb
Host smart-96e60e06-4670-43d6-8616-7b4c0d49cd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556826669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1556826669
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2534068172
Short name T484
Test name
Test status
Simulation time 102725732687 ps
CPU time 167.25 seconds
Started Feb 25 02:45:03 PM PST 24
Finished Feb 25 02:47:50 PM PST 24
Peak memory 259124 kb
Host smart-8a0efa53-0fab-4ff6-bf6c-61a4888a163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534068172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2534068172
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4223909771
Short name T269
Test name
Test status
Simulation time 11045309986 ps
CPU time 54.7 seconds
Started Feb 25 02:45:04 PM PST 24
Finished Feb 25 02:45:59 PM PST 24
Peak memory 248776 kb
Host smart-4d6bfdd7-348d-459e-98e9-669d48d65acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223909771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4223909771
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3405852575
Short name T804
Test name
Test status
Simulation time 19669682807 ps
CPU time 76.16 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:46:23 PM PST 24
Peak memory 248696 kb
Host smart-aa7eb16d-9d54-428e-9830-e7e21e713817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405852575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3405852575
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1932890586
Short name T829
Test name
Test status
Simulation time 8270541555 ps
CPU time 12.66 seconds
Started Feb 25 02:45:09 PM PST 24
Finished Feb 25 02:45:22 PM PST 24
Peak memory 233048 kb
Host smart-9d466737-ad92-4008-9d4b-741eff00aa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932890586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1932890586
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2706621836
Short name T354
Test name
Test status
Simulation time 1574126763 ps
CPU time 6.78 seconds
Started Feb 25 02:44:55 PM PST 24
Finished Feb 25 02:45:02 PM PST 24
Peak memory 232964 kb
Host smart-caef1cae-8ee4-46fc-b7f3-414396e4bb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706621836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2706621836
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1061994481
Short name T14
Test name
Test status
Simulation time 178902729 ps
CPU time 5.73 seconds
Started Feb 25 02:45:00 PM PST 24
Finished Feb 25 02:45:06 PM PST 24
Peak memory 234316 kb
Host smart-73dc1a5d-9418-452e-99f1-48c2877b7bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061994481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1061994481
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2834543820
Short name T386
Test name
Test status
Simulation time 195525027 ps
CPU time 3.94 seconds
Started Feb 25 02:44:55 PM PST 24
Finished Feb 25 02:44:59 PM PST 24
Peak memory 232948 kb
Host smart-bf8224bb-2ea0-44bd-b09e-f24ee536aaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834543820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2834543820
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.814143105
Short name T73
Test name
Test status
Simulation time 8909516931 ps
CPU time 25.27 seconds
Started Feb 25 02:44:58 PM PST 24
Finished Feb 25 02:45:23 PM PST 24
Peak memory 231008 kb
Host smart-cbb9922e-9585-4764-a41d-79a04918d2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814143105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.814143105
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2001981452
Short name T410
Test name
Test status
Simulation time 241579340 ps
CPU time 3.71 seconds
Started Feb 25 02:45:04 PM PST 24
Finished Feb 25 02:45:08 PM PST 24
Peak memory 218488 kb
Host smart-4d94d7aa-d301-4eb8-9fd1-ded0bd9bbd14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2001981452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2001981452
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1512826210
Short name T761
Test name
Test status
Simulation time 13071182626 ps
CPU time 44.27 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:45:50 PM PST 24
Peak memory 221876 kb
Host smart-8e78986c-c5a6-4c4d-a1df-6621c35a2bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512826210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1512826210
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2219555007
Short name T894
Test name
Test status
Simulation time 5596039155 ps
CPU time 13.12 seconds
Started Feb 25 02:44:59 PM PST 24
Finished Feb 25 02:45:12 PM PST 24
Peak memory 216064 kb
Host smart-858ee450-8dab-40e1-bf0f-e4ed0af27ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219555007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2219555007
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.392691065
Short name T948
Test name
Test status
Simulation time 1119549624 ps
CPU time 4.76 seconds
Started Feb 25 02:44:56 PM PST 24
Finished Feb 25 02:45:01 PM PST 24
Peak memory 215756 kb
Host smart-f9876d7c-42dd-4156-bcd1-e83e3b1258d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392691065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.392691065
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2143069332
Short name T680
Test name
Test status
Simulation time 49682739 ps
CPU time 0.79 seconds
Started Feb 25 02:44:51 PM PST 24
Finished Feb 25 02:44:52 PM PST 24
Peak memory 204964 kb
Host smart-ebf2529e-d533-4599-9c10-2013633ddf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143069332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2143069332
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.961335669
Short name T959
Test name
Test status
Simulation time 45503230 ps
CPU time 0.95 seconds
Started Feb 25 02:44:58 PM PST 24
Finished Feb 25 02:44:59 PM PST 24
Peak memory 205960 kb
Host smart-1cc487c4-c38d-409b-9658-4870f72694cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961335669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.961335669
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1320447119
Short name T957
Test name
Test status
Simulation time 30260927236 ps
CPU time 18.64 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:45:21 PM PST 24
Peak memory 234920 kb
Host smart-32289411-e404-409f-9782-b6f1d3c9d7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320447119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1320447119
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3950667411
Short name T960
Test name
Test status
Simulation time 43310393 ps
CPU time 0.72 seconds
Started Feb 25 02:45:09 PM PST 24
Finished Feb 25 02:45:10 PM PST 24
Peak memory 204540 kb
Host smart-ecc50761-283f-4a5e-8885-802ebfacb674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950667411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3950667411
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2431399218
Short name T770
Test name
Test status
Simulation time 55307344 ps
CPU time 2.39 seconds
Started Feb 25 02:45:05 PM PST 24
Finished Feb 25 02:45:08 PM PST 24
Peak memory 233060 kb
Host smart-c8a6bddb-a5f2-4744-9f47-97d275e114f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431399218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2431399218
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1789107969
Short name T411
Test name
Test status
Simulation time 53215993 ps
CPU time 0.81 seconds
Started Feb 25 02:45:05 PM PST 24
Finished Feb 25 02:45:06 PM PST 24
Peak memory 205676 kb
Host smart-7c3c63a7-9bbe-4855-8d59-856350542f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789107969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1789107969
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.714713603
Short name T516
Test name
Test status
Simulation time 16287227366 ps
CPU time 99.39 seconds
Started Feb 25 02:45:08 PM PST 24
Finished Feb 25 02:46:47 PM PST 24
Peak memory 253528 kb
Host smart-df4ca322-296e-416a-a321-dfad40a5ad99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714713603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.714713603
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2319608771
Short name T238
Test name
Test status
Simulation time 40719497905 ps
CPU time 140.98 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:47:23 PM PST 24
Peak memory 255904 kb
Host smart-457222c1-d1cf-4073-ae3e-8d8f5d15b706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319608771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2319608771
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1560414772
Short name T62
Test name
Test status
Simulation time 151844613805 ps
CPU time 571.35 seconds
Started Feb 25 02:45:04 PM PST 24
Finished Feb 25 02:54:36 PM PST 24
Peak memory 251532 kb
Host smart-abf045d5-1fcd-429e-a590-5d9bdd66b004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560414772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1560414772
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1211873952
Short name T445
Test name
Test status
Simulation time 622669009 ps
CPU time 8.72 seconds
Started Feb 25 02:45:05 PM PST 24
Finished Feb 25 02:45:14 PM PST 24
Peak memory 232236 kb
Host smart-58907194-6a3b-4c40-ad6d-0a0fd7da4be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211873952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1211873952
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.302846385
Short name T195
Test name
Test status
Simulation time 4466970183 ps
CPU time 5.29 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:45:08 PM PST 24
Peak memory 224036 kb
Host smart-f0bee3f6-cf05-4768-b9f8-efa0fad764db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302846385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.302846385
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4059874647
Short name T958
Test name
Test status
Simulation time 404817583 ps
CPU time 4.49 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:45:07 PM PST 24
Peak memory 233104 kb
Host smart-595aacdb-b719-4dc6-8338-5918fd7a8015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059874647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4059874647
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3554213189
Short name T717
Test name
Test status
Simulation time 2879978582 ps
CPU time 10.93 seconds
Started Feb 25 02:45:00 PM PST 24
Finished Feb 25 02:45:12 PM PST 24
Peak memory 233016 kb
Host smart-409431d3-34d3-4d2f-902c-b93a0530f8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554213189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3554213189
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4015008070
Short name T435
Test name
Test status
Simulation time 53111791 ps
CPU time 2.72 seconds
Started Feb 25 02:45:05 PM PST 24
Finished Feb 25 02:45:08 PM PST 24
Peak memory 232536 kb
Host smart-35292d07-26df-4bd1-ba6b-c07eb3e284b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015008070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4015008070
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2355968810
Short name T946
Test name
Test status
Simulation time 1376072533 ps
CPU time 4.01 seconds
Started Feb 25 02:45:05 PM PST 24
Finished Feb 25 02:45:09 PM PST 24
Peak memory 221568 kb
Host smart-e344e448-3ba5-43be-94b2-e23621070693
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2355968810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2355968810
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2644693091
Short name T36
Test name
Test status
Simulation time 33556478 ps
CPU time 0.87 seconds
Started Feb 25 02:45:01 PM PST 24
Finished Feb 25 02:45:02 PM PST 24
Peak memory 204760 kb
Host smart-f0a976c2-e15e-4d2b-bf9f-5afa7e0dacff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644693091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2644693091
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1652046838
Short name T607
Test name
Test status
Simulation time 12074272131 ps
CPU time 36.76 seconds
Started Feb 25 02:45:05 PM PST 24
Finished Feb 25 02:45:42 PM PST 24
Peak memory 215828 kb
Host smart-22a32315-3cf1-4313-b7bd-c245072fad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652046838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1652046838
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4008824281
Short name T520
Test name
Test status
Simulation time 2747562262 ps
CPU time 1.99 seconds
Started Feb 25 02:45:04 PM PST 24
Finished Feb 25 02:45:06 PM PST 24
Peak memory 207456 kb
Host smart-cf951748-76d7-4f74-9a35-c84fb8938f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008824281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4008824281
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3022518009
Short name T418
Test name
Test status
Simulation time 18763314 ps
CPU time 0.94 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:45:07 PM PST 24
Peak memory 206332 kb
Host smart-3e177028-ec17-44b4-ae66-adcffa5fee3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022518009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3022518009
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.172475177
Short name T728
Test name
Test status
Simulation time 34494672 ps
CPU time 0.75 seconds
Started Feb 25 02:45:00 PM PST 24
Finished Feb 25 02:45:01 PM PST 24
Peak memory 204884 kb
Host smart-6b73f7a8-6992-4b7a-8c00-4b38a5151b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172475177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.172475177
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.268267632
Short name T880
Test name
Test status
Simulation time 9481622567 ps
CPU time 20.4 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:45:23 PM PST 24
Peak memory 240528 kb
Host smart-f2d3c3bf-b748-4779-8a81-bf5a68909a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268267632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.268267632
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1381311290
Short name T924
Test name
Test status
Simulation time 64545187 ps
CPU time 0.72 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:45:06 PM PST 24
Peak memory 204564 kb
Host smart-ee3603b0-3b2c-4606-96e9-864a3769c72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381311290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1381311290
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3615389524
Short name T277
Test name
Test status
Simulation time 2597788000 ps
CPU time 3.75 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:45:09 PM PST 24
Peak memory 224120 kb
Host smart-54d06ad4-3739-4a78-afa5-c7fc3d9aa33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615389524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3615389524
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.195875572
Short name T323
Test name
Test status
Simulation time 33933207 ps
CPU time 0.77 seconds
Started Feb 25 02:45:03 PM PST 24
Finished Feb 25 02:45:05 PM PST 24
Peak memory 204700 kb
Host smart-a44b69d4-db57-41ff-a1b6-aa004b491fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195875572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.195875572
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2644106861
Short name T584
Test name
Test status
Simulation time 1605998950 ps
CPU time 14.65 seconds
Started Feb 25 02:45:08 PM PST 24
Finished Feb 25 02:45:23 PM PST 24
Peak memory 224068 kb
Host smart-01ccb9b7-f70f-4b0c-9ffd-b088942b4612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644106861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2644106861
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4210636819
Short name T220
Test name
Test status
Simulation time 8311866135 ps
CPU time 40.91 seconds
Started Feb 25 02:45:07 PM PST 24
Finished Feb 25 02:45:48 PM PST 24
Peak memory 255668 kb
Host smart-bb2c09c7-7273-4596-a034-10ceb6c32fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210636819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4210636819
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.719649883
Short name T919
Test name
Test status
Simulation time 23352965534 ps
CPU time 79.59 seconds
Started Feb 25 02:45:01 PM PST 24
Finished Feb 25 02:46:21 PM PST 24
Peak memory 232408 kb
Host smart-44b1b4b1-ef21-4cd7-8c7b-64acb73e1ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719649883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.719649883
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1398344810
Short name T552
Test name
Test status
Simulation time 4219904502 ps
CPU time 13.41 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:45:19 PM PST 24
Peak memory 246900 kb
Host smart-11ddcb79-5354-4f9f-96e7-77c11ad27bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398344810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1398344810
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2020554873
Short name T260
Test name
Test status
Simulation time 9271175188 ps
CPU time 7.04 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:45:13 PM PST 24
Peak memory 224052 kb
Host smart-26aaf1ff-0309-49ce-8447-0e2f0d58504a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020554873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2020554873
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2488418017
Short name T920
Test name
Test status
Simulation time 78083436454 ps
CPU time 53.63 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:45:56 PM PST 24
Peak memory 235104 kb
Host smart-b1c03e53-ba24-4327-a4eb-319926ef49eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488418017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2488418017
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3976298941
Short name T441
Test name
Test status
Simulation time 111951800335 ps
CPU time 42.61 seconds
Started Feb 25 02:45:05 PM PST 24
Finished Feb 25 02:45:48 PM PST 24
Peak memory 236812 kb
Host smart-d39cef32-e493-4168-9943-bf3443b43afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976298941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3976298941
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1221565910
Short name T859
Test name
Test status
Simulation time 265042177292 ps
CPU time 43.53 seconds
Started Feb 25 02:45:02 PM PST 24
Finished Feb 25 02:45:46 PM PST 24
Peak memory 230928 kb
Host smart-4e5d0b14-8b12-4462-9935-c4b0b42555d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221565910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1221565910
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4124207828
Short name T125
Test name
Test status
Simulation time 741482662 ps
CPU time 4.68 seconds
Started Feb 25 02:45:04 PM PST 24
Finished Feb 25 02:45:09 PM PST 24
Peak memory 219416 kb
Host smart-9c4f6fb9-6483-4ff9-882d-c7c20103088c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4124207828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4124207828
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2353838091
Short name T964
Test name
Test status
Simulation time 178335198 ps
CPU time 1.2 seconds
Started Feb 25 02:45:03 PM PST 24
Finished Feb 25 02:45:04 PM PST 24
Peak memory 206344 kb
Host smart-14ff2244-8dd6-4318-aeb7-45b442494e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353838091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2353838091
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1960908867
Short name T372
Test name
Test status
Simulation time 677652488 ps
CPU time 2.53 seconds
Started Feb 25 02:45:04 PM PST 24
Finished Feb 25 02:45:07 PM PST 24
Peak memory 215796 kb
Host smart-c551fe76-c12d-49ba-8491-3c167d0d7695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960908867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1960908867
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2598703058
Short name T405
Test name
Test status
Simulation time 49057309950 ps
CPU time 28.59 seconds
Started Feb 25 02:45:08 PM PST 24
Finished Feb 25 02:45:37 PM PST 24
Peak memory 215812 kb
Host smart-eda8239d-b0cd-4b0e-b350-3f1154196d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598703058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2598703058
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1924357282
Short name T299
Test name
Test status
Simulation time 26637455 ps
CPU time 1 seconds
Started Feb 25 02:45:07 PM PST 24
Finished Feb 25 02:45:08 PM PST 24
Peak memory 206436 kb
Host smart-173f398b-2f92-49e5-8a4b-846af982e828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924357282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1924357282
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2376246821
Short name T530
Test name
Test status
Simulation time 69957305 ps
CPU time 0.99 seconds
Started Feb 25 02:45:09 PM PST 24
Finished Feb 25 02:45:10 PM PST 24
Peak memory 205952 kb
Host smart-d4fabbb6-8580-4633-b35b-cc4c1d265902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376246821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2376246821
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.90234514
Short name T907
Test name
Test status
Simulation time 1832678880 ps
CPU time 7.14 seconds
Started Feb 25 02:45:03 PM PST 24
Finished Feb 25 02:45:11 PM PST 24
Peak memory 217816 kb
Host smart-0728b9c1-83b6-4337-a4cd-ccb4e1fa2674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90234514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.90234514
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2091250312
Short name T311
Test name
Test status
Simulation time 22764911 ps
CPU time 0.7 seconds
Started Feb 25 02:45:09 PM PST 24
Finished Feb 25 02:45:10 PM PST 24
Peak memory 204812 kb
Host smart-290184ea-26e1-4435-bb66-30a214164a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091250312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2091250312
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3158153631
Short name T167
Test name
Test status
Simulation time 1154246190 ps
CPU time 4.66 seconds
Started Feb 25 02:45:08 PM PST 24
Finished Feb 25 02:45:13 PM PST 24
Peak memory 233720 kb
Host smart-b1723c96-4125-42a0-b2de-a8084a63b2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158153631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3158153631
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4265695982
Short name T301
Test name
Test status
Simulation time 19487248 ps
CPU time 0.79 seconds
Started Feb 25 02:45:08 PM PST 24
Finished Feb 25 02:45:09 PM PST 24
Peak memory 204712 kb
Host smart-9c2c9163-77d3-44be-b740-e3f3476369bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265695982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4265695982
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.801598522
Short name T205
Test name
Test status
Simulation time 7760157586 ps
CPU time 103.81 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:46:50 PM PST 24
Peak memory 256500 kb
Host smart-4bff8141-2df0-461f-a26c-f7e823086faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801598522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.801598522
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1270546682
Short name T225
Test name
Test status
Simulation time 69074374122 ps
CPU time 166.88 seconds
Started Feb 25 02:45:05 PM PST 24
Finished Feb 25 02:47:52 PM PST 24
Peak memory 272616 kb
Host smart-d7241f3e-60b3-4f99-b8a5-4f92be75f9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270546682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1270546682
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.361601704
Short name T156
Test name
Test status
Simulation time 27435433382 ps
CPU time 157.09 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:47:44 PM PST 24
Peak memory 240576 kb
Host smart-779f2009-6b32-4bdc-860e-b51b4fd7ef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361601704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.361601704
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4095460768
Short name T69
Test name
Test status
Simulation time 2895416599 ps
CPU time 7.44 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:45:14 PM PST 24
Peak memory 233208 kb
Host smart-4eae0494-5995-46da-b2c7-d0985dc0da58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095460768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4095460768
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3745160766
Short name T653
Test name
Test status
Simulation time 4832495056 ps
CPU time 17.7 seconds
Started Feb 25 02:45:07 PM PST 24
Finished Feb 25 02:45:25 PM PST 24
Peak memory 239472 kb
Host smart-6c06b7aa-c2c3-43b4-8d17-095d1bed5dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745160766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3745160766
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3751083091
Short name T892
Test name
Test status
Simulation time 6587886909 ps
CPU time 17.12 seconds
Started Feb 25 02:45:06 PM PST 24
Finished Feb 25 02:45:24 PM PST 24
Peak memory 216824 kb
Host smart-cef42028-a478-42b6-ab52-09e6771cbcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751083091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3751083091
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4055353473
Short name T621
Test name
Test status
Simulation time 826647469 ps
CPU time 5.83 seconds
Started Feb 25 02:45:09 PM PST 24
Finished Feb 25 02:45:15 PM PST 24
Peak memory 217000 kb
Host smart-ac930d19-2dec-4031-ba3b-03c05f381082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055353473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4055353473
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.917943215
Short name T580
Test name
Test status
Simulation time 1809776292 ps
CPU time 5.12 seconds
Started Feb 25 02:45:07 PM PST 24
Finished Feb 25 02:45:12 PM PST 24
Peak memory 218396 kb
Host smart-40bb6531-bba2-4164-a0df-8ff431522216
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=917943215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.917943215
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2456505695
Short name T295
Test name
Test status
Simulation time 37065127465 ps
CPU time 68.73 seconds
Started Feb 25 02:45:12 PM PST 24
Finished Feb 25 02:46:20 PM PST 24
Peak memory 248784 kb
Host smart-2963379a-d0a6-4ada-8e39-108eeab69d53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456505695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2456505695
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3206287599
Short name T511
Test name
Test status
Simulation time 5427412708 ps
CPU time 10.73 seconds
Started Feb 25 02:45:10 PM PST 24
Finished Feb 25 02:45:21 PM PST 24
Peak memory 215832 kb
Host smart-62c24edd-9c6f-4c14-b1c6-07136508bd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206287599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3206287599
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.216541649
Short name T352
Test name
Test status
Simulation time 4015441727 ps
CPU time 7.86 seconds
Started Feb 25 02:45:04 PM PST 24
Finished Feb 25 02:45:12 PM PST 24
Peak memory 215744 kb
Host smart-e8fb85c3-b3c6-44df-a663-f8d2fddf2d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216541649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.216541649
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4015456162
Short name T415
Test name
Test status
Simulation time 158683375 ps
CPU time 3.28 seconds
Started Feb 25 02:45:04 PM PST 24
Finished Feb 25 02:45:07 PM PST 24
Peak memory 215796 kb
Host smart-c4371087-c333-43a9-b755-737ca0c5b8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015456162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4015456162
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1615582537
Short name T611
Test name
Test status
Simulation time 1237865067 ps
CPU time 1.05 seconds
Started Feb 25 02:45:04 PM PST 24
Finished Feb 25 02:45:05 PM PST 24
Peak memory 205952 kb
Host smart-22fdf2a0-2c44-42d0-aff7-4782bf62b730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615582537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1615582537
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.4038572268
Short name T803
Test name
Test status
Simulation time 10833451817 ps
CPU time 10.87 seconds
Started Feb 25 02:45:07 PM PST 24
Finished Feb 25 02:45:18 PM PST 24
Peak memory 218644 kb
Host smart-09c86b2b-fcc7-4b24-b7b4-eb7b4eb23f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038572268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.4038572268
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2117850681
Short name T34
Test name
Test status
Simulation time 15852054 ps
CPU time 0.7 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:45:16 PM PST 24
Peak memory 204408 kb
Host smart-8f09ea8a-b88f-4ce8-b3ea-133b85694ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117850681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2117850681
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2651910578
Short name T854
Test name
Test status
Simulation time 683239139 ps
CPU time 4.98 seconds
Started Feb 25 02:45:20 PM PST 24
Finished Feb 25 02:45:25 PM PST 24
Peak memory 224028 kb
Host smart-96d8b6e6-46f7-43d5-9e48-03acbfb54dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651910578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2651910578
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.341985168
Short name T6
Test name
Test status
Simulation time 13910469 ps
CPU time 0.77 seconds
Started Feb 25 02:45:13 PM PST 24
Finished Feb 25 02:45:14 PM PST 24
Peak memory 205680 kb
Host smart-ce9bf757-b9c9-427b-9afa-23ab9348e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341985168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.341985168
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1703116244
Short name T32
Test name
Test status
Simulation time 117435667193 ps
CPU time 116.52 seconds
Started Feb 25 02:45:16 PM PST 24
Finished Feb 25 02:47:12 PM PST 24
Peak memory 256472 kb
Host smart-821cf0be-49ff-4ee2-844e-f2f20871cfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703116244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1703116244
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.934345595
Short name T782
Test name
Test status
Simulation time 4358296535 ps
CPU time 67.16 seconds
Started Feb 25 02:45:19 PM PST 24
Finished Feb 25 02:46:27 PM PST 24
Peak memory 240364 kb
Host smart-01bbddc4-269a-401c-9afa-d3b8de3edee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934345595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.934345595
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1284472040
Short name T21
Test name
Test status
Simulation time 121775185614 ps
CPU time 228.15 seconds
Started Feb 25 02:45:14 PM PST 24
Finished Feb 25 02:49:03 PM PST 24
Peak memory 251464 kb
Host smart-7b54e72f-3cf8-4bd6-bbf0-e9e9913f7f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284472040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1284472040
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2841501111
Short name T738
Test name
Test status
Simulation time 4360115506 ps
CPU time 9.65 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:45:25 PM PST 24
Peak memory 220688 kb
Host smart-f120ca23-5623-4de2-ada4-4743780b8c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841501111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2841501111
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3217011932
Short name T856
Test name
Test status
Simulation time 102265032 ps
CPU time 2.55 seconds
Started Feb 25 02:45:18 PM PST 24
Finished Feb 25 02:45:22 PM PST 24
Peak memory 223368 kb
Host smart-afc04fa7-4169-471a-b0ac-643c46540777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217011932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3217011932
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2397611021
Short name T361
Test name
Test status
Simulation time 14304998932 ps
CPU time 24.61 seconds
Started Feb 25 02:45:18 PM PST 24
Finished Feb 25 02:45:43 PM PST 24
Peak memory 234372 kb
Host smart-f3c0eb60-17d2-4c91-abe6-f36ca6b46be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397611021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2397611021
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3821591318
Short name T15
Test name
Test status
Simulation time 4566139748 ps
CPU time 16.04 seconds
Started Feb 25 02:45:20 PM PST 24
Finished Feb 25 02:45:36 PM PST 24
Peak memory 235248 kb
Host smart-3fd5bd53-0562-41e6-8c01-ce5a17aefc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821591318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3821591318
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2238881125
Short name T818
Test name
Test status
Simulation time 1013278036 ps
CPU time 4.06 seconds
Started Feb 25 02:45:09 PM PST 24
Finished Feb 25 02:45:13 PM PST 24
Peak memory 224056 kb
Host smart-176031c6-b8ce-4783-9c85-929a0adfb516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238881125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2238881125
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.244757140
Short name T583
Test name
Test status
Simulation time 899230124 ps
CPU time 3.68 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:45:19 PM PST 24
Peak memory 219356 kb
Host smart-500aaf33-5985-45b2-8d9a-cce91f0a3226
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=244757140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.244757140
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4158599374
Short name T63
Test name
Test status
Simulation time 103991309744 ps
CPU time 691.73 seconds
Started Feb 25 02:45:16 PM PST 24
Finished Feb 25 02:56:48 PM PST 24
Peak memory 266356 kb
Host smart-e2fce12a-8795-4ff1-bfaf-a97a854476a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158599374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4158599374
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1459588941
Short name T790
Test name
Test status
Simulation time 4368593771 ps
CPU time 18.75 seconds
Started Feb 25 02:45:16 PM PST 24
Finished Feb 25 02:45:35 PM PST 24
Peak memory 215752 kb
Host smart-5762b7f2-42b1-4d4e-a311-91dceeb376aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459588941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1459588941
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1631716034
Short name T534
Test name
Test status
Simulation time 2597965762 ps
CPU time 12.74 seconds
Started Feb 25 02:45:05 PM PST 24
Finished Feb 25 02:45:18 PM PST 24
Peak memory 215896 kb
Host smart-c2f9a301-e30d-47b7-858a-8036540abd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631716034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1631716034
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1705517227
Short name T312
Test name
Test status
Simulation time 298453223 ps
CPU time 7.85 seconds
Started Feb 25 02:45:16 PM PST 24
Finished Feb 25 02:45:24 PM PST 24
Peak memory 215752 kb
Host smart-2e75331a-8ed3-4d96-a965-7058cb62516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705517227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1705517227
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1953903839
Short name T305
Test name
Test status
Simulation time 198967238 ps
CPU time 0.96 seconds
Started Feb 25 02:45:16 PM PST 24
Finished Feb 25 02:45:17 PM PST 24
Peak memory 205912 kb
Host smart-eb296d6f-f599-4cfa-a91b-4665ad9d4daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953903839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1953903839
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3586163245
Short name T657
Test name
Test status
Simulation time 1542161887 ps
CPU time 8.11 seconds
Started Feb 25 02:45:19 PM PST 24
Finished Feb 25 02:45:27 PM PST 24
Peak memory 218640 kb
Host smart-6165e600-4c58-44d6-907d-0da54bf0285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586163245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3586163245
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4066236450
Short name T933
Test name
Test status
Simulation time 60216510 ps
CPU time 0.71 seconds
Started Feb 25 02:45:19 PM PST 24
Finished Feb 25 02:45:20 PM PST 24
Peak memory 204532 kb
Host smart-caeadb5c-f3e0-457c-8ac4-7df5b46d6bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066236450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4066236450
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2937198413
Short name T117
Test name
Test status
Simulation time 1605483845 ps
CPU time 4.34 seconds
Started Feb 25 02:45:17 PM PST 24
Finished Feb 25 02:45:22 PM PST 24
Peak memory 232600 kb
Host smart-24cce22e-c91d-4d59-b219-27d4a70e5694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937198413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2937198413
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.616273263
Short name T676
Test name
Test status
Simulation time 17495855 ps
CPU time 0.78 seconds
Started Feb 25 02:45:14 PM PST 24
Finished Feb 25 02:45:15 PM PST 24
Peak memory 204652 kb
Host smart-83be487e-12fa-4405-b7ff-498e6115cbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616273263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.616273263
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3095670342
Short name T606
Test name
Test status
Simulation time 61082081628 ps
CPU time 287.82 seconds
Started Feb 25 02:45:17 PM PST 24
Finished Feb 25 02:50:05 PM PST 24
Peak memory 256344 kb
Host smart-9cc6be58-76e3-4291-a977-5ed093f525ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095670342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3095670342
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1072418622
Short name T943
Test name
Test status
Simulation time 232265594986 ps
CPU time 229.19 seconds
Started Feb 25 02:45:14 PM PST 24
Finished Feb 25 02:49:04 PM PST 24
Peak memory 253116 kb
Host smart-7e4266ea-59b2-44d1-818f-130d8ade9bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072418622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1072418622
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.955348952
Short name T231
Test name
Test status
Simulation time 43197299047 ps
CPU time 305.62 seconds
Started Feb 25 02:45:22 PM PST 24
Finished Feb 25 02:50:29 PM PST 24
Peak memory 248984 kb
Host smart-c7d2c03d-4edd-4168-9276-55ef2ec6cc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955348952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.955348952
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1208553440
Short name T481
Test name
Test status
Simulation time 2473892250 ps
CPU time 13.28 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:45:29 PM PST 24
Peak memory 247312 kb
Host smart-806a16be-68b4-4fac-b4b3-d185ea333c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208553440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1208553440
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1718399925
Short name T731
Test name
Test status
Simulation time 913121104 ps
CPU time 3.41 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:45:19 PM PST 24
Peak memory 232960 kb
Host smart-6f27763d-1885-4443-bdbc-e5fa54160f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718399925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1718399925
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2640924714
Short name T662
Test name
Test status
Simulation time 7344248670 ps
CPU time 12.48 seconds
Started Feb 25 02:45:14 PM PST 24
Finished Feb 25 02:45:27 PM PST 24
Peak memory 226628 kb
Host smart-b922da3d-2a62-47a8-8579-e7dbb0b42fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640924714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2640924714
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.337807293
Short name T282
Test name
Test status
Simulation time 28240528457 ps
CPU time 11.07 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:45:27 PM PST 24
Peak memory 233040 kb
Host smart-e37f2b40-a8a1-4b7a-945a-495af1547339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337807293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.337807293
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2312315372
Short name T504
Test name
Test status
Simulation time 2085412467 ps
CPU time 8.49 seconds
Started Feb 25 02:45:17 PM PST 24
Finished Feb 25 02:45:26 PM PST 24
Peak memory 233956 kb
Host smart-b7da0480-630b-4290-865c-42b1d0079564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312315372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2312315372
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.4198337867
Short name T331
Test name
Test status
Simulation time 6177860626 ps
CPU time 4.52 seconds
Started Feb 25 02:45:22 PM PST 24
Finished Feb 25 02:45:28 PM PST 24
Peak memory 218444 kb
Host smart-32ed0b7b-e56c-4cb7-b216-de03462610ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4198337867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.4198337867
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.830357333
Short name T840
Test name
Test status
Simulation time 43647916563 ps
CPU time 297.55 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:50:13 PM PST 24
Peak memory 252716 kb
Host smart-307de863-e81a-4943-bc65-d8597ef3a671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830357333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.830357333
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3176833581
Short name T92
Test name
Test status
Simulation time 44000374110 ps
CPU time 58.87 seconds
Started Feb 25 02:45:19 PM PST 24
Finished Feb 25 02:46:18 PM PST 24
Peak memory 215892 kb
Host smart-7fd0fddf-a1bf-4e87-9ee3-2552f0808159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176833581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3176833581
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1129856306
Short name T472
Test name
Test status
Simulation time 11855675635 ps
CPU time 14.48 seconds
Started Feb 25 02:45:20 PM PST 24
Finished Feb 25 02:45:35 PM PST 24
Peak memory 215820 kb
Host smart-279c6b7a-729b-4ca3-bc50-d682162a4fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129856306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1129856306
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2554571941
Short name T665
Test name
Test status
Simulation time 92706010 ps
CPU time 1.23 seconds
Started Feb 25 02:45:17 PM PST 24
Finished Feb 25 02:45:19 PM PST 24
Peak memory 207720 kb
Host smart-2d94f236-4361-40ea-9f9a-7a8980f4f305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554571941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2554571941
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.405642421
Short name T784
Test name
Test status
Simulation time 480817393 ps
CPU time 1.08 seconds
Started Feb 25 02:45:18 PM PST 24
Finished Feb 25 02:45:19 PM PST 24
Peak memory 205952 kb
Host smart-77e085c8-967d-4b92-836c-9516d29d50e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405642421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.405642421
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2047460812
Short name T11
Test name
Test status
Simulation time 8124188202 ps
CPU time 13.27 seconds
Started Feb 25 02:45:17 PM PST 24
Finished Feb 25 02:45:31 PM PST 24
Peak memory 226616 kb
Host smart-84e9edd2-63d6-492b-9595-86653a2b6c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047460812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2047460812
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2323721203
Short name T348
Test name
Test status
Simulation time 47021552 ps
CPU time 0.71 seconds
Started Feb 25 02:45:16 PM PST 24
Finished Feb 25 02:45:17 PM PST 24
Peak memory 204556 kb
Host smart-b49afce3-6ec3-4e72-b9b3-38c91150c52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323721203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2323721203
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1237001470
Short name T180
Test name
Test status
Simulation time 401294220 ps
CPU time 2.91 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:45:18 PM PST 24
Peak memory 217356 kb
Host smart-cc13b34b-8c0a-47c5-8bff-d8f5e8612010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237001470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1237001470
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3570088968
Short name T71
Test name
Test status
Simulation time 18380937 ps
CPU time 0.76 seconds
Started Feb 25 02:45:17 PM PST 24
Finished Feb 25 02:45:19 PM PST 24
Peak memory 204980 kb
Host smart-39e85502-18c8-4424-bac0-2cc6e6e1db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570088968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3570088968
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.993261784
Short name T417
Test name
Test status
Simulation time 4203193089 ps
CPU time 10.73 seconds
Started Feb 25 02:45:23 PM PST 24
Finished Feb 25 02:45:34 PM PST 24
Peak memory 218540 kb
Host smart-07be90aa-7d6c-4653-bec4-a362b1e54225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993261784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.993261784
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1812576005
Short name T124
Test name
Test status
Simulation time 149446514661 ps
CPU time 285.83 seconds
Started Feb 25 02:45:20 PM PST 24
Finished Feb 25 02:50:06 PM PST 24
Peak memory 253472 kb
Host smart-b0712f96-0f28-4ab1-9782-5a7b31c53e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812576005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1812576005
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1642869757
Short name T695
Test name
Test status
Simulation time 22708245360 ps
CPU time 30.86 seconds
Started Feb 25 02:45:18 PM PST 24
Finished Feb 25 02:45:49 PM PST 24
Peak memory 236180 kb
Host smart-ff8def4f-6100-4bf6-b447-a6e0c41f3001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642869757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1642869757
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2865828914
Short name T170
Test name
Test status
Simulation time 654127594 ps
CPU time 4.54 seconds
Started Feb 25 02:45:19 PM PST 24
Finished Feb 25 02:45:24 PM PST 24
Peak memory 224044 kb
Host smart-e237d1b6-399b-4f96-8e3b-5183c84b994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865828914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2865828914
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3837371658
Short name T692
Test name
Test status
Simulation time 3649980511 ps
CPU time 11.24 seconds
Started Feb 25 02:45:18 PM PST 24
Finished Feb 25 02:45:29 PM PST 24
Peak memory 233404 kb
Host smart-1e9a488b-0995-4d1b-8a06-b58c1f13f390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837371658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3837371658
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1453249070
Short name T165
Test name
Test status
Simulation time 882867282 ps
CPU time 8.71 seconds
Started Feb 25 02:45:21 PM PST 24
Finished Feb 25 02:45:30 PM PST 24
Peak memory 232192 kb
Host smart-7a58dbcb-4e7f-4f7f-b1d1-4de4993ce873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453249070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1453249070
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.382789055
Short name T563
Test name
Test status
Simulation time 59228459 ps
CPU time 2.24 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:45:18 PM PST 24
Peak memory 216472 kb
Host smart-08cf3a8e-d8cc-4c26-93e7-a2ab88cf7a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382789055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.382789055
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.10942871
Short name T367
Test name
Test status
Simulation time 710499667 ps
CPU time 4.41 seconds
Started Feb 25 02:45:14 PM PST 24
Finished Feb 25 02:45:19 PM PST 24
Peak memory 219800 kb
Host smart-92431442-2b1d-43fb-89b8-754ba4f1059e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=10942871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direc
t.10942871
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1618307596
Short name T499
Test name
Test status
Simulation time 3811929541 ps
CPU time 5.86 seconds
Started Feb 25 02:45:17 PM PST 24
Finished Feb 25 02:45:24 PM PST 24
Peak memory 215904 kb
Host smart-3f563a48-e269-4593-878a-8f16af2d8fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618307596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1618307596
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.475588213
Short name T795
Test name
Test status
Simulation time 2803080766 ps
CPU time 15.14 seconds
Started Feb 25 02:45:19 PM PST 24
Finished Feb 25 02:45:34 PM PST 24
Peak memory 215812 kb
Host smart-bd3b34e5-08d6-4779-beba-4b87a23f8e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475588213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.475588213
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1497616453
Short name T597
Test name
Test status
Simulation time 268738315 ps
CPU time 3.2 seconds
Started Feb 25 02:45:17 PM PST 24
Finished Feb 25 02:45:20 PM PST 24
Peak memory 215832 kb
Host smart-55962876-037d-4ff7-a7d2-a497f7977c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497616453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1497616453
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1889102781
Short name T485
Test name
Test status
Simulation time 122473993 ps
CPU time 0.74 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:45:16 PM PST 24
Peak memory 204932 kb
Host smart-687e8f99-f5c9-477b-b334-4b6d2cf664f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889102781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1889102781
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.26712565
Short name T181
Test name
Test status
Simulation time 228209025629 ps
CPU time 41.85 seconds
Started Feb 25 02:45:17 PM PST 24
Finished Feb 25 02:46:00 PM PST 24
Peak memory 248224 kb
Host smart-95e16914-cc96-4b4f-bad5-efd201c41053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26712565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.26712565
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4166253184
Short name T873
Test name
Test status
Simulation time 13892662 ps
CPU time 0.73 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:45:30 PM PST 24
Peak memory 204256 kb
Host smart-6b4d32a0-52c1-4c84-9e18-7793540ca878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166253184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4166253184
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.504496637
Short name T423
Test name
Test status
Simulation time 417715495 ps
CPU time 2.34 seconds
Started Feb 25 02:45:25 PM PST 24
Finished Feb 25 02:45:28 PM PST 24
Peak memory 233388 kb
Host smart-5978c988-9020-4341-841a-2ed434912383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504496637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.504496637
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2347688574
Short name T496
Test name
Test status
Simulation time 133325421 ps
CPU time 0.77 seconds
Started Feb 25 02:45:15 PM PST 24
Finished Feb 25 02:45:16 PM PST 24
Peak memory 204660 kb
Host smart-3ea064db-fec0-41b4-adeb-ff259cc1a361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347688574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2347688574
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1419659513
Short name T955
Test name
Test status
Simulation time 23269958183 ps
CPU time 121.71 seconds
Started Feb 25 02:45:26 PM PST 24
Finished Feb 25 02:47:28 PM PST 24
Peak memory 248756 kb
Host smart-f2c0f4cd-5dc7-4da6-a00d-48509d580366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419659513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1419659513
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4198331514
Short name T898
Test name
Test status
Simulation time 482873329607 ps
CPU time 621.57 seconds
Started Feb 25 02:45:28 PM PST 24
Finished Feb 25 02:55:50 PM PST 24
Peak memory 264424 kb
Host smart-02c5b892-8ae6-4774-94b8-e8e9a9a9bc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198331514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4198331514
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2671889817
Short name T210
Test name
Test status
Simulation time 186423140474 ps
CPU time 278.83 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:50:09 PM PST 24
Peak memory 263636 kb
Host smart-850522c0-78d0-4271-a00b-a76d6be599e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671889817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2671889817
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3830939806
Short name T766
Test name
Test status
Simulation time 1221777742 ps
CPU time 5.39 seconds
Started Feb 25 02:45:24 PM PST 24
Finished Feb 25 02:45:30 PM PST 24
Peak memory 233208 kb
Host smart-ea3bd4e5-e384-42e0-ba0a-c5abe901f68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830939806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3830939806
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1064079733
Short name T272
Test name
Test status
Simulation time 823531497 ps
CPU time 4.32 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:45:34 PM PST 24
Peak memory 217368 kb
Host smart-cc81916b-255f-44de-8d26-119ab64778f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064079733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1064079733
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4162343884
Short name T450
Test name
Test status
Simulation time 183955330 ps
CPU time 2.96 seconds
Started Feb 25 02:45:26 PM PST 24
Finished Feb 25 02:45:29 PM PST 24
Peak memory 224024 kb
Host smart-ec186335-4ab1-46f2-85dc-e92d4a7271e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162343884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4162343884
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.23349920
Short name T592
Test name
Test status
Simulation time 7342859703 ps
CPU time 11.7 seconds
Started Feb 25 02:45:26 PM PST 24
Finished Feb 25 02:45:37 PM PST 24
Peak memory 229536 kb
Host smart-fbc01e13-6948-46ba-aee6-24569bfdb56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23349920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.23349920
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2772768713
Short name T498
Test name
Test status
Simulation time 48744732471 ps
CPU time 10.64 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:45:40 PM PST 24
Peak memory 223920 kb
Host smart-e6bc0719-5f91-4c39-a841-e32e907e8699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772768713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2772768713
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4140025455
Short name T434
Test name
Test status
Simulation time 1383266271 ps
CPU time 5.32 seconds
Started Feb 25 02:45:38 PM PST 24
Finished Feb 25 02:45:43 PM PST 24
Peak memory 218620 kb
Host smart-80ad16fb-7592-43eb-bbed-1538a81c7a93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4140025455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4140025455
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.46962251
Short name T813
Test name
Test status
Simulation time 81036826438 ps
CPU time 273.89 seconds
Started Feb 25 02:45:25 PM PST 24
Finished Feb 25 02:49:59 PM PST 24
Peak memory 285692 kb
Host smart-e7260b41-2476-492e-a839-18a7c0dbfcf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46962251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress
_all.46962251
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3240388096
Short name T475
Test name
Test status
Simulation time 17730918249 ps
CPU time 31.27 seconds
Started Feb 25 02:45:24 PM PST 24
Finished Feb 25 02:45:55 PM PST 24
Peak memory 215908 kb
Host smart-27897ca3-99ee-4294-b3f6-03bc414889b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240388096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3240388096
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2144167792
Short name T479
Test name
Test status
Simulation time 44254106978 ps
CPU time 30.51 seconds
Started Feb 25 02:45:16 PM PST 24
Finished Feb 25 02:45:47 PM PST 24
Peak memory 215880 kb
Host smart-5f877680-c481-446c-98f8-882d281c025b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144167792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2144167792
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1939904038
Short name T373
Test name
Test status
Simulation time 74446977 ps
CPU time 1.28 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:45:31 PM PST 24
Peak memory 207436 kb
Host smart-b9892b51-07ea-4422-8811-0a93c013eb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939904038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1939904038
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1743093147
Short name T1
Test name
Test status
Simulation time 164202158 ps
CPU time 0.87 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:45:31 PM PST 24
Peak memory 204932 kb
Host smart-a7956d2b-18cc-4182-8273-1f614a526d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743093147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1743093147
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3574535870
Short name T501
Test name
Test status
Simulation time 2793217682 ps
CPU time 7.62 seconds
Started Feb 25 02:45:31 PM PST 24
Finished Feb 25 02:45:38 PM PST 24
Peak memory 233456 kb
Host smart-21f825d4-3144-45fe-b03a-e1b7b65de363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574535870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3574535870
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2557203171
Short name T830
Test name
Test status
Simulation time 34148380 ps
CPU time 0.72 seconds
Started Feb 25 02:45:24 PM PST 24
Finished Feb 25 02:45:25 PM PST 24
Peak memory 204596 kb
Host smart-c06a2d4f-d980-4c39-a1a9-bf779653d599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557203171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2557203171
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4258900270
Short name T666
Test name
Test status
Simulation time 6738941851 ps
CPU time 11.73 seconds
Started Feb 25 02:45:26 PM PST 24
Finished Feb 25 02:45:38 PM PST 24
Peak memory 234148 kb
Host smart-537f068c-94f8-47f2-87c5-6f585bf93a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258900270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4258900270
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2801674801
Short name T409
Test name
Test status
Simulation time 21704588 ps
CPU time 0.79 seconds
Started Feb 25 02:45:38 PM PST 24
Finished Feb 25 02:45:39 PM PST 24
Peak memory 204656 kb
Host smart-804010e1-98cc-46c1-b5d5-47326f2d098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801674801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2801674801
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2743629370
Short name T432
Test name
Test status
Simulation time 48220827581 ps
CPU time 60.96 seconds
Started Feb 25 02:45:28 PM PST 24
Finished Feb 25 02:46:30 PM PST 24
Peak memory 233684 kb
Host smart-e5d9e3ac-9ea7-4968-9550-94b200d246ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743629370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2743629370
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2188932693
Short name T652
Test name
Test status
Simulation time 73297728073 ps
CPU time 195.64 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:48:46 PM PST 24
Peak memory 251924 kb
Host smart-5d601285-c654-4676-946a-e8b592b71334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188932693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2188932693
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3620981613
Short name T241
Test name
Test status
Simulation time 18789964733 ps
CPU time 131.57 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:47:41 PM PST 24
Peak memory 232396 kb
Host smart-40d71a7c-f5a6-4f84-aa4b-8c7fb932b85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620981613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3620981613
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3796501152
Short name T286
Test name
Test status
Simulation time 11365065923 ps
CPU time 20.1 seconds
Started Feb 25 02:45:38 PM PST 24
Finished Feb 25 02:45:58 PM PST 24
Peak memory 244180 kb
Host smart-8a0e6ac1-b5a7-49be-bfc0-43a337795331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796501152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3796501152
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.144207091
Short name T194
Test name
Test status
Simulation time 5904560738 ps
CPU time 8.77 seconds
Started Feb 25 02:45:23 PM PST 24
Finished Feb 25 02:45:32 PM PST 24
Peak memory 234556 kb
Host smart-b92031b8-b46b-431a-9106-feb65efa5991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144207091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.144207091
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3884364801
Short name T414
Test name
Test status
Simulation time 1072864909 ps
CPU time 5.27 seconds
Started Feb 25 02:45:31 PM PST 24
Finished Feb 25 02:45:37 PM PST 24
Peak memory 234220 kb
Host smart-ebe92574-08bd-4a76-bff3-ed256c72839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884364801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3884364801
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2637557297
Short name T239
Test name
Test status
Simulation time 7064838456 ps
CPU time 8.94 seconds
Started Feb 25 02:45:39 PM PST 24
Finished Feb 25 02:45:48 PM PST 24
Peak memory 232288 kb
Host smart-f56aede2-16c9-4ce0-a817-f0b2f9b4e4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637557297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2637557297
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2300583349
Short name T969
Test name
Test status
Simulation time 873697943 ps
CPU time 3.71 seconds
Started Feb 25 02:45:31 PM PST 24
Finished Feb 25 02:45:35 PM PST 24
Peak memory 232948 kb
Host smart-ee59ba1c-cd6c-468e-900f-5b9904833170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300583349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2300583349
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1927583543
Short name T742
Test name
Test status
Simulation time 2150397302 ps
CPU time 6.15 seconds
Started Feb 25 02:45:31 PM PST 24
Finished Feb 25 02:45:37 PM PST 24
Peak memory 221564 kb
Host smart-5cbb7344-d704-4b1a-aff4-b12008a162df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1927583543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1927583543
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2469793466
Short name T387
Test name
Test status
Simulation time 59298198 ps
CPU time 0.91 seconds
Started Feb 25 02:45:25 PM PST 24
Finished Feb 25 02:45:26 PM PST 24
Peak memory 204664 kb
Host smart-e0d1068c-e62d-437b-bf65-3ec4589cd21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469793466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2469793466
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3526272442
Short name T928
Test name
Test status
Simulation time 10287208081 ps
CPU time 51.29 seconds
Started Feb 25 02:45:23 PM PST 24
Finished Feb 25 02:46:15 PM PST 24
Peak memory 217812 kb
Host smart-46aca0e0-7c41-460f-9eae-c4c4ce7e51f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526272442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3526272442
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.412803625
Short name T923
Test name
Test status
Simulation time 4995586383 ps
CPU time 9.29 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:45:39 PM PST 24
Peak memory 215880 kb
Host smart-b882fb71-62cb-4cec-bae5-65d0c7d4a982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412803625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.412803625
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2588639215
Short name T704
Test name
Test status
Simulation time 41919750 ps
CPU time 1.44 seconds
Started Feb 25 02:45:26 PM PST 24
Finished Feb 25 02:45:27 PM PST 24
Peak memory 215956 kb
Host smart-2fa9808f-6a94-44fe-8833-a95c403271a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588639215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2588639215
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1143907192
Short name T319
Test name
Test status
Simulation time 1377137138 ps
CPU time 1.15 seconds
Started Feb 25 02:45:31 PM PST 24
Finished Feb 25 02:45:32 PM PST 24
Peak memory 205664 kb
Host smart-0edcd332-6b28-4b79-9ea7-106920665d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143907192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1143907192
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.555834059
Short name T169
Test name
Test status
Simulation time 5013081833 ps
CPU time 9.07 seconds
Started Feb 25 02:45:31 PM PST 24
Finished Feb 25 02:45:41 PM PST 24
Peak memory 233764 kb
Host smart-d50580b8-69e5-47be-8b7a-797d874e86cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555834059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.555834059
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1527742389
Short name T473
Test name
Test status
Simulation time 15680183 ps
CPU time 0.75 seconds
Started Feb 25 02:45:41 PM PST 24
Finished Feb 25 02:45:42 PM PST 24
Peak memory 203984 kb
Host smart-03cc57bf-5b53-4228-b709-7782885cd5d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527742389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1527742389
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3556316222
Short name T675
Test name
Test status
Simulation time 744830444 ps
CPU time 4.72 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:45:35 PM PST 24
Peak memory 232876 kb
Host smart-3bb81f71-6b93-4a78-be0b-1f3d17c4593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556316222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3556316222
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2537832425
Short name T664
Test name
Test status
Simulation time 81547083 ps
CPU time 0.85 seconds
Started Feb 25 02:45:24 PM PST 24
Finished Feb 25 02:45:25 PM PST 24
Peak memory 206028 kb
Host smart-42f6aedb-0df7-4e61-9349-6fdd39706ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537832425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2537832425
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.313716349
Short name T931
Test name
Test status
Simulation time 42567626641 ps
CPU time 29.4 seconds
Started Feb 25 02:45:33 PM PST 24
Finished Feb 25 02:46:03 PM PST 24
Peak memory 232336 kb
Host smart-dae29bc8-6461-4207-8683-e5fd8ae276b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313716349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.313716349
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2509991942
Short name T396
Test name
Test status
Simulation time 9690356877 ps
CPU time 48.06 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:46:17 PM PST 24
Peak memory 224116 kb
Host smart-4183c1ca-0391-4871-88c4-627e10ebf4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509991942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2509991942
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.903088168
Short name T442
Test name
Test status
Simulation time 1656667961 ps
CPU time 13.58 seconds
Started Feb 25 02:45:22 PM PST 24
Finished Feb 25 02:45:36 PM PST 24
Peak memory 232280 kb
Host smart-f98a98c5-e6a6-4887-94ac-9678f8cdaca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903088168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.903088168
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4134181229
Short name T103
Test name
Test status
Simulation time 5356665417 ps
CPU time 11.44 seconds
Started Feb 25 02:45:39 PM PST 24
Finished Feb 25 02:45:51 PM PST 24
Peak memory 236724 kb
Host smart-7833e37c-1505-406c-9941-9fd643255424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134181229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4134181229
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3331881678
Short name T503
Test name
Test status
Simulation time 1320787608 ps
CPU time 13.34 seconds
Started Feb 25 02:45:28 PM PST 24
Finished Feb 25 02:45:41 PM PST 24
Peak memory 248656 kb
Host smart-fefda3e2-039a-48b9-ba48-2a3846aa1b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331881678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3331881678
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.687941342
Short name T510
Test name
Test status
Simulation time 2084982183 ps
CPU time 5.29 seconds
Started Feb 25 02:45:28 PM PST 24
Finished Feb 25 02:45:34 PM PST 24
Peak memory 232928 kb
Host smart-6ae04881-5f41-4cf5-9d04-1faeb5a5c918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687941342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.687941342
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1973522506
Short name T791
Test name
Test status
Simulation time 6774304519 ps
CPU time 11.98 seconds
Started Feb 25 02:45:24 PM PST 24
Finished Feb 25 02:45:36 PM PST 24
Peak memory 238320 kb
Host smart-2a0f55ad-d483-4918-bc8a-1b4daa5eab0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973522506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1973522506
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3942099734
Short name T407
Test name
Test status
Simulation time 348200168 ps
CPU time 3.93 seconds
Started Feb 25 02:45:24 PM PST 24
Finished Feb 25 02:45:28 PM PST 24
Peak memory 219764 kb
Host smart-5636afce-a78c-4f29-b7e7-d49847379d45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3942099734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3942099734
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1807439300
Short name T215
Test name
Test status
Simulation time 23840071666 ps
CPU time 106.87 seconds
Started Feb 25 02:45:39 PM PST 24
Finished Feb 25 02:47:26 PM PST 24
Peak memory 253252 kb
Host smart-9fd399a2-5355-4e76-a074-e32df70a0d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807439300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1807439300
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.59458671
Short name T962
Test name
Test status
Simulation time 10233132025 ps
CPU time 13.43 seconds
Started Feb 25 02:45:28 PM PST 24
Finished Feb 25 02:45:41 PM PST 24
Peak memory 215868 kb
Host smart-7c8e9639-d532-46e4-9669-3711d9c47dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59458671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.59458671
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3775788438
Short name T313
Test name
Test status
Simulation time 8982034519 ps
CPU time 15.62 seconds
Started Feb 25 02:45:27 PM PST 24
Finished Feb 25 02:45:44 PM PST 24
Peak memory 215896 kb
Host smart-8b8e1db5-f710-4323-96c1-d2f7bc2d93b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775788438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3775788438
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2434251985
Short name T430
Test name
Test status
Simulation time 116171322 ps
CPU time 2.18 seconds
Started Feb 25 02:45:25 PM PST 24
Finished Feb 25 02:45:28 PM PST 24
Peak memory 215860 kb
Host smart-4c4f036f-3c2e-4ea5-91f5-390e82a23050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434251985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2434251985
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.918092140
Short name T463
Test name
Test status
Simulation time 215348729 ps
CPU time 0.97 seconds
Started Feb 25 02:45:24 PM PST 24
Finished Feb 25 02:45:25 PM PST 24
Peak memory 205956 kb
Host smart-00aacccd-199c-4a6c-a951-c05d9c8e9896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918092140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.918092140
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.337764954
Short name T646
Test name
Test status
Simulation time 281502206 ps
CPU time 3.18 seconds
Started Feb 25 02:45:26 PM PST 24
Finished Feb 25 02:45:29 PM PST 24
Peak memory 218540 kb
Host smart-f5fdd5dc-3992-4671-96e3-42a85dd029f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337764954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.337764954
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2644362700
Short name T408
Test name
Test status
Simulation time 66608931 ps
CPU time 0.76 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:43:13 PM PST 24
Peak memory 204528 kb
Host smart-92ac917f-480d-4d9a-af29-804b3c34ad67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644362700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
644362700
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2313226258
Short name T587
Test name
Test status
Simulation time 1967586851 ps
CPU time 8.63 seconds
Started Feb 25 02:43:17 PM PST 24
Finished Feb 25 02:43:26 PM PST 24
Peak memory 232552 kb
Host smart-e9a96943-7713-48fa-b7bb-2bee5a7a1c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313226258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2313226258
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2382222682
Short name T899
Test name
Test status
Simulation time 14550756 ps
CPU time 0.79 seconds
Started Feb 25 02:43:14 PM PST 24
Finished Feb 25 02:43:15 PM PST 24
Peak memory 205712 kb
Host smart-952ac25d-f155-465a-aee8-d0e5c4644d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382222682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2382222682
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.472397872
Short name T883
Test name
Test status
Simulation time 1638983824 ps
CPU time 38.03 seconds
Started Feb 25 02:43:11 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 248708 kb
Host smart-4050103a-ea17-4cfe-a034-e2d51ddae89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472397872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.472397872
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2082563521
Short name T555
Test name
Test status
Simulation time 1424535046 ps
CPU time 16.13 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:43:28 PM PST 24
Peak memory 232256 kb
Host smart-a3921f1d-ee92-4a14-80fa-7a5e18d6ee83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082563521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2082563521
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1967942819
Short name T514
Test name
Test status
Simulation time 22559074860 ps
CPU time 19.15 seconds
Started Feb 25 02:43:04 PM PST 24
Finished Feb 25 02:43:24 PM PST 24
Peak memory 234608 kb
Host smart-f91626bf-be21-4e4a-9e51-bf28d02d6140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967942819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1967942819
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1068127492
Short name T543
Test name
Test status
Simulation time 1067663107 ps
CPU time 3.58 seconds
Started Feb 25 02:43:13 PM PST 24
Finished Feb 25 02:43:18 PM PST 24
Peak memory 217148 kb
Host smart-970784b5-e6ac-4059-b8a6-5b2f1b238de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068127492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1068127492
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3366990622
Short name T656
Test name
Test status
Simulation time 28417413 ps
CPU time 1.1 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:43:13 PM PST 24
Peak memory 216120 kb
Host smart-2feef88b-15fd-4209-82e5-76253f82da49
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366990622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3366990622
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.596640367
Short name T376
Test name
Test status
Simulation time 10501157897 ps
CPU time 28.73 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:39 PM PST 24
Peak memory 230712 kb
Host smart-2e0d3b25-07d7-4f82-906c-c4a20726cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596640367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
596640367
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1818338586
Short name T274
Test name
Test status
Simulation time 1920097949 ps
CPU time 5.46 seconds
Started Feb 25 02:43:06 PM PST 24
Finished Feb 25 02:43:12 PM PST 24
Peak memory 239312 kb
Host smart-eea019b6-20a2-4a4a-8f13-1d47df89d579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818338586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1818338586
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.2143689005
Short name T544
Test name
Test status
Simulation time 22006064 ps
CPU time 0.69 seconds
Started Feb 25 02:43:13 PM PST 24
Finished Feb 25 02:43:15 PM PST 24
Peak memory 215712 kb
Host smart-d1c8306e-ef76-4bbc-9416-7d5fe84a1bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143689005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.2143689005
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1658670929
Short name T494
Test name
Test status
Simulation time 1942968362 ps
CPU time 4.79 seconds
Started Feb 25 02:43:08 PM PST 24
Finished Feb 25 02:43:13 PM PST 24
Peak memory 219248 kb
Host smart-67947756-2456-464a-bebf-f2758c9f1a26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1658670929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1658670929
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1421242982
Short name T911
Test name
Test status
Simulation time 32258843923 ps
CPU time 171.9 seconds
Started Feb 25 02:43:08 PM PST 24
Finished Feb 25 02:46:00 PM PST 24
Peak memory 238192 kb
Host smart-2340248f-d13d-4271-b6bd-fab2d9aec0ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421242982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1421242982
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3363084370
Short name T865
Test name
Test status
Simulation time 2035152938 ps
CPU time 29.29 seconds
Started Feb 25 02:43:09 PM PST 24
Finished Feb 25 02:43:39 PM PST 24
Peak memory 215840 kb
Host smart-7134df40-c7e7-414b-aa1d-5374833f7fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363084370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3363084370
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3753748139
Short name T574
Test name
Test status
Simulation time 51675087792 ps
CPU time 36.74 seconds
Started Feb 25 02:43:08 PM PST 24
Finished Feb 25 02:43:45 PM PST 24
Peak memory 215772 kb
Host smart-1fe4e65a-8af4-43e1-8f24-a5a666209c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753748139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3753748139
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2025871463
Short name T758
Test name
Test status
Simulation time 104650826 ps
CPU time 1.55 seconds
Started Feb 25 02:43:14 PM PST 24
Finished Feb 25 02:43:16 PM PST 24
Peak memory 207744 kb
Host smart-7e662014-8b36-4d9e-854e-08dfb69e7bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025871463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2025871463
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1265025300
Short name T469
Test name
Test status
Simulation time 84319946 ps
CPU time 0.96 seconds
Started Feb 25 02:43:15 PM PST 24
Finished Feb 25 02:43:17 PM PST 24
Peak memory 204932 kb
Host smart-39c513ea-60b1-419a-ba52-34cf0793009c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265025300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1265025300
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.254909214
Short name T259
Test name
Test status
Simulation time 469419441 ps
CPU time 7.77 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:43:20 PM PST 24
Peak memory 238148 kb
Host smart-e5f1c7e7-4e0a-4740-bd67-4a983b5a4523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254909214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.254909214
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.721187040
Short name T518
Test name
Test status
Simulation time 20669751 ps
CPU time 0.73 seconds
Started Feb 25 02:43:07 PM PST 24
Finished Feb 25 02:43:08 PM PST 24
Peak memory 203924 kb
Host smart-a1d728a2-e7c6-46eb-9ddf-57e6038a30d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721187040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.721187040
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.383277687
Short name T546
Test name
Test status
Simulation time 1800251675 ps
CPU time 5.56 seconds
Started Feb 25 02:43:14 PM PST 24
Finished Feb 25 02:43:20 PM PST 24
Peak memory 233112 kb
Host smart-6623c201-3c1a-4511-bf67-702c80ef9c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383277687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.383277687
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.823391097
Short name T400
Test name
Test status
Simulation time 15109380 ps
CPU time 0.85 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:43:13 PM PST 24
Peak memory 205836 kb
Host smart-3d9e61b5-882c-4274-b70a-aca211351b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823391097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.823391097
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.374524822
Short name T575
Test name
Test status
Simulation time 94357389444 ps
CPU time 175.43 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:46:07 PM PST 24
Peak memory 267936 kb
Host smart-603b595f-1ed1-4df5-87a9-b1b4869194df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374524822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.374524822
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.505910556
Short name T934
Test name
Test status
Simulation time 23567132392 ps
CPU time 53.89 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:44:07 PM PST 24
Peak memory 250248 kb
Host smart-bd7a89ee-da2f-423d-a93d-5bf5e70bc106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505910556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.505910556
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1473084324
Short name T525
Test name
Test status
Simulation time 13945922745 ps
CPU time 52.99 seconds
Started Feb 25 02:43:11 PM PST 24
Finished Feb 25 02:44:04 PM PST 24
Peak memory 255348 kb
Host smart-2c88559d-5152-4990-bb71-2af484b9b558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473084324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1473084324
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4171923871
Short name T128
Test name
Test status
Simulation time 117769901257 ps
CPU time 34.29 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:44 PM PST 24
Peak memory 249868 kb
Host smart-1ec32a4f-d9ee-4312-a28f-34c093018e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171923871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4171923871
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1207996804
Short name T13
Test name
Test status
Simulation time 5205741212 ps
CPU time 4.11 seconds
Started Feb 25 02:43:06 PM PST 24
Finished Feb 25 02:43:10 PM PST 24
Peak memory 218412 kb
Host smart-2b43e969-7858-411d-83e6-1a2d26dbd3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207996804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1207996804
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.850669877
Short name T949
Test name
Test status
Simulation time 5018815640 ps
CPU time 18.13 seconds
Started Feb 25 02:43:17 PM PST 24
Finished Feb 25 02:43:35 PM PST 24
Peak memory 239236 kb
Host smart-f9d31331-baaf-4fe2-87e0-fd7101459bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850669877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.850669877
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3021368701
Short name T523
Test name
Test status
Simulation time 150480252 ps
CPU time 1.18 seconds
Started Feb 25 02:43:13 PM PST 24
Finished Feb 25 02:43:14 PM PST 24
Peak memory 216120 kb
Host smart-d3034f97-19bb-45dc-bcb3-fc8ce6f5cbb5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021368701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3021368701
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.774457613
Short name T466
Test name
Test status
Simulation time 10436114652 ps
CPU time 19.64 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:43:32 PM PST 24
Peak memory 227260 kb
Host smart-0171e7c3-c51d-41c8-966b-0ba1c174db8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774457613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
774457613
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2284546213
Short name T663
Test name
Test status
Simulation time 26361508833 ps
CPU time 45.24 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:55 PM PST 24
Peak memory 226688 kb
Host smart-b162ddfa-8545-41a4-ae5f-6f739ed4fd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284546213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2284546213
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.3848602396
Short name T631
Test name
Test status
Simulation time 18014617 ps
CPU time 0.74 seconds
Started Feb 25 02:43:08 PM PST 24
Finished Feb 25 02:43:09 PM PST 24
Peak memory 215660 kb
Host smart-391db127-697a-4756-8ef8-bf343e1b3d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848602396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.3848602396
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.430410815
Short name T870
Test name
Test status
Simulation time 2671147498 ps
CPU time 4.42 seconds
Started Feb 25 02:43:17 PM PST 24
Finished Feb 25 02:43:22 PM PST 24
Peak memory 218040 kb
Host smart-9d6801d9-cb47-4077-bd43-0df0696cc09d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=430410815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.430410815
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3648627982
Short name T421
Test name
Test status
Simulation time 89760119029 ps
CPU time 203.16 seconds
Started Feb 25 02:43:15 PM PST 24
Finished Feb 25 02:46:38 PM PST 24
Peak memory 260872 kb
Host smart-4be40eec-0d22-4473-b26a-031432bcc4b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648627982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3648627982
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3732197869
Short name T971
Test name
Test status
Simulation time 6590235888 ps
CPU time 8.13 seconds
Started Feb 25 02:43:05 PM PST 24
Finished Feb 25 02:43:14 PM PST 24
Peak memory 215852 kb
Host smart-8dc2a483-7606-4beb-a1ca-1f2b63290406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732197869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3732197869
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2584226557
Short name T613
Test name
Test status
Simulation time 973276550 ps
CPU time 5.81 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:16 PM PST 24
Peak memory 207660 kb
Host smart-f3999c43-6c8c-4d97-b467-bcdc72495e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584226557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2584226557
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.841088982
Short name T72
Test name
Test status
Simulation time 114605286 ps
CPU time 2.85 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:13 PM PST 24
Peak memory 216916 kb
Host smart-316b3665-e330-4e49-ba14-531b4444f5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841088982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.841088982
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.453879351
Short name T465
Test name
Test status
Simulation time 47998191 ps
CPU time 0.92 seconds
Started Feb 25 02:43:11 PM PST 24
Finished Feb 25 02:43:12 PM PST 24
Peak memory 205984 kb
Host smart-d25cfc69-b298-4d9c-b3cc-2776f934280f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453879351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.453879351
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.337629503
Short name T535
Test name
Test status
Simulation time 412184367 ps
CPU time 4.3 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:14 PM PST 24
Peak memory 224028 kb
Host smart-edf87205-c93f-401e-ae59-e5cc2603aa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337629503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.337629503
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3516274180
Short name T630
Test name
Test status
Simulation time 24292956 ps
CPU time 0.73 seconds
Started Feb 25 02:43:14 PM PST 24
Finished Feb 25 02:43:15 PM PST 24
Peak memory 204008 kb
Host smart-0fe751e1-f9ba-492a-8e0a-65310c2bd80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516274180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
516274180
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4141623946
Short name T315
Test name
Test status
Simulation time 795964626 ps
CPU time 5.36 seconds
Started Feb 25 02:43:11 PM PST 24
Finished Feb 25 02:43:16 PM PST 24
Peak memory 219448 kb
Host smart-1627107d-3008-4f6f-862e-4e1a1f7d6f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141623946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4141623946
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3131711349
Short name T858
Test name
Test status
Simulation time 47879532 ps
CPU time 0.78 seconds
Started Feb 25 02:43:11 PM PST 24
Finished Feb 25 02:43:12 PM PST 24
Peak memory 206032 kb
Host smart-cfb6edf4-09f6-4c65-866d-9845fdba8810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131711349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3131711349
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2230322961
Short name T605
Test name
Test status
Simulation time 51933815258 ps
CPU time 70.38 seconds
Started Feb 25 02:43:13 PM PST 24
Finished Feb 25 02:44:23 PM PST 24
Peak memory 240500 kb
Host smart-72399b40-ce54-4af2-92ac-0e4a5b491f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230322961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2230322961
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4277075607
Short name T677
Test name
Test status
Simulation time 11019545398 ps
CPU time 101.82 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:44:54 PM PST 24
Peak memory 265800 kb
Host smart-33df40f6-b5ad-4e32-b984-3afbc9fc6950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277075607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4277075607
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3444665137
Short name T725
Test name
Test status
Simulation time 40751346697 ps
CPU time 252.09 seconds
Started Feb 25 02:43:11 PM PST 24
Finished Feb 25 02:47:23 PM PST 24
Peak memory 256944 kb
Host smart-b818ca79-3977-4cbd-9dab-18ebb4c17b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444665137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3444665137
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2127946400
Short name T287
Test name
Test status
Simulation time 2871266062 ps
CPU time 10.41 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:43:23 PM PST 24
Peak memory 246472 kb
Host smart-56baa62c-732c-4b1d-a18c-c17f1f629fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127946400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2127946400
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2721467554
Short name T719
Test name
Test status
Simulation time 521344522 ps
CPU time 2.42 seconds
Started Feb 25 02:43:17 PM PST 24
Finished Feb 25 02:43:19 PM PST 24
Peak memory 215840 kb
Host smart-f8ea8272-e9cd-46df-a963-5321bf69cd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721467554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2721467554
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1006605292
Short name T338
Test name
Test status
Simulation time 8471456825 ps
CPU time 28.69 seconds
Started Feb 25 02:43:12 PM PST 24
Finished Feb 25 02:43:41 PM PST 24
Peak memory 232836 kb
Host smart-67faff31-5c0b-4c4d-a3e1-74211a4f34d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006605292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1006605292
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1068010726
Short name T420
Test name
Test status
Simulation time 47370968 ps
CPU time 1.04 seconds
Started Feb 25 02:43:13 PM PST 24
Finished Feb 25 02:43:14 PM PST 24
Peak memory 216116 kb
Host smart-43b77c85-164b-4b4b-989f-c86b616be732
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068010726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1068010726
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1518281391
Short name T218
Test name
Test status
Simulation time 11870592591 ps
CPU time 17.64 seconds
Started Feb 25 02:43:08 PM PST 24
Finished Feb 25 02:43:25 PM PST 24
Peak memory 223996 kb
Host smart-a553f1d0-5274-43dd-8a5b-3509017b82ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518281391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1518281391
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3975746084
Short name T197
Test name
Test status
Simulation time 552754879 ps
CPU time 7 seconds
Started Feb 25 02:43:17 PM PST 24
Finished Feb 25 02:43:24 PM PST 24
Peak memory 232244 kb
Host smart-6406500a-6536-4962-8ff0-6c5063fefca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975746084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3975746084
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.3304343299
Short name T736
Test name
Test status
Simulation time 17688913 ps
CPU time 0.71 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:11 PM PST 24
Peak memory 215728 kb
Host smart-4054b3d4-8540-47a2-b7ab-55fd00aaeb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304343299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.3304343299
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2870572204
Short name T355
Test name
Test status
Simulation time 1155358907 ps
CPU time 6.14 seconds
Started Feb 25 02:43:07 PM PST 24
Finished Feb 25 02:43:13 PM PST 24
Peak memory 221648 kb
Host smart-7b36ae1d-c168-41aa-b6b3-b462a0fbaec7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2870572204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2870572204
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3745538500
Short name T406
Test name
Test status
Simulation time 54039854527 ps
CPU time 360.29 seconds
Started Feb 25 02:43:14 PM PST 24
Finished Feb 25 02:49:15 PM PST 24
Peak memory 250840 kb
Host smart-b3142830-cc32-4b43-921d-4e0032fd1794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745538500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3745538500
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.515365044
Short name T648
Test name
Test status
Simulation time 3043222261 ps
CPU time 16.26 seconds
Started Feb 25 02:43:13 PM PST 24
Finished Feb 25 02:43:29 PM PST 24
Peak memory 215820 kb
Host smart-501411b8-e304-4f34-8dd1-31be48438cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515365044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.515365044
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1807138548
Short name T797
Test name
Test status
Simulation time 686984876 ps
CPU time 5.35 seconds
Started Feb 25 02:43:18 PM PST 24
Finished Feb 25 02:43:24 PM PST 24
Peak memory 215772 kb
Host smart-59796b21-7a34-4fae-9d19-bfe4d8b4c48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807138548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1807138548
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1179795730
Short name T61
Test name
Test status
Simulation time 19908440 ps
CPU time 0.99 seconds
Started Feb 25 02:43:17 PM PST 24
Finished Feb 25 02:43:18 PM PST 24
Peak memory 205916 kb
Host smart-c2ab7add-39d9-434c-9246-229eaed9aef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179795730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1179795730
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3818105340
Short name T82
Test name
Test status
Simulation time 78834220 ps
CPU time 0.92 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:11 PM PST 24
Peak memory 205068 kb
Host smart-5bd9d463-d36a-4a28-a92c-c70ac07148f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818105340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3818105340
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2241578332
Short name T532
Test name
Test status
Simulation time 3171742659 ps
CPU time 9.8 seconds
Started Feb 25 02:43:17 PM PST 24
Finished Feb 25 02:43:27 PM PST 24
Peak memory 220480 kb
Host smart-b55aedf7-b44f-4cc8-848a-e1d35c503cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241578332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2241578332
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3840276156
Short name T536
Test name
Test status
Simulation time 22568253 ps
CPU time 0.75 seconds
Started Feb 25 02:43:19 PM PST 24
Finished Feb 25 02:43:20 PM PST 24
Peak memory 203968 kb
Host smart-d65019a7-aa72-4d1e-ba1e-b40af3e8e88d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840276156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
840276156
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.898125190
Short name T977
Test name
Test status
Simulation time 1286275410 ps
CPU time 4.65 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:43:33 PM PST 24
Peak memory 224040 kb
Host smart-67dece43-b9fa-46c0-bd41-0edd032b7378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898125190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.898125190
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2757607340
Short name T618
Test name
Test status
Simulation time 13782876 ps
CPU time 0.76 seconds
Started Feb 25 02:43:11 PM PST 24
Finished Feb 25 02:43:11 PM PST 24
Peak memory 204664 kb
Host smart-0da80e2d-ae8e-41a9-aa15-661414c5ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757607340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2757607340
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2554727967
Short name T576
Test name
Test status
Simulation time 6271428464 ps
CPU time 58.07 seconds
Started Feb 25 02:43:22 PM PST 24
Finished Feb 25 02:44:20 PM PST 24
Peak memory 240544 kb
Host smart-ce3aa54a-b098-4305-9422-2477fd70beeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554727967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2554727967
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3748267294
Short name T211
Test name
Test status
Simulation time 30470941510 ps
CPU time 140.77 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:45:49 PM PST 24
Peak memory 263460 kb
Host smart-16531a51-f4b4-47f7-a16a-d8dc940a4f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748267294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3748267294
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2140857621
Short name T57
Test name
Test status
Simulation time 161335207520 ps
CPU time 156.47 seconds
Started Feb 25 02:43:33 PM PST 24
Finished Feb 25 02:46:09 PM PST 24
Peak memory 255172 kb
Host smart-a219b082-777d-4802-a0ea-f8568c571898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140857621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2140857621
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2363468779
Short name T284
Test name
Test status
Simulation time 3272977809 ps
CPU time 17.97 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:43:41 PM PST 24
Peak memory 234956 kb
Host smart-f535cbee-7abd-4e40-8f6a-e2604f314d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363468779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2363468779
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.811687116
Short name T279
Test name
Test status
Simulation time 10842831671 ps
CPU time 17.11 seconds
Started Feb 25 02:43:22 PM PST 24
Finished Feb 25 02:43:39 PM PST 24
Peak memory 232760 kb
Host smart-c68aa828-cd8c-4fe2-b4f7-72aa5646b1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811687116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.811687116
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1513867892
Short name T491
Test name
Test status
Simulation time 6204056594 ps
CPU time 15.57 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:43:45 PM PST 24
Peak memory 223988 kb
Host smart-3dd0a9a4-d667-4dd4-956f-23ab6b5c4c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513867892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1513867892
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1387419951
Short name T526
Test name
Test status
Simulation time 165951392 ps
CPU time 1.05 seconds
Started Feb 25 02:43:08 PM PST 24
Finished Feb 25 02:43:09 PM PST 24
Peak memory 216124 kb
Host smart-71790d3f-eea2-49ae-8840-640bb7b674ba
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387419951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1387419951
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2534887179
Short name T509
Test name
Test status
Simulation time 12627433897 ps
CPU time 30.92 seconds
Started Feb 25 02:43:18 PM PST 24
Finished Feb 25 02:43:49 PM PST 24
Peak memory 232312 kb
Host smart-c9888a45-a155-4b61-81be-8c81b58f3f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534887179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2534887179
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1746259096
Short name T262
Test name
Test status
Simulation time 9585253126 ps
CPU time 14.33 seconds
Started Feb 25 02:43:09 PM PST 24
Finished Feb 25 02:43:23 PM PST 24
Peak memory 239304 kb
Host smart-0ad85611-aa73-437a-8d9d-3738b4ba17dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746259096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1746259096
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.447253637
Short name T715
Test name
Test status
Simulation time 18937702 ps
CPU time 0.76 seconds
Started Feb 25 02:43:16 PM PST 24
Finished Feb 25 02:43:17 PM PST 24
Peak memory 215752 kb
Host smart-0f592249-582d-40ad-a5b0-d3241e4365fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447253637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.447253637
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1538948039
Short name T808
Test name
Test status
Simulation time 710286514 ps
CPU time 4.24 seconds
Started Feb 25 02:43:28 PM PST 24
Finished Feb 25 02:43:32 PM PST 24
Peak memory 221048 kb
Host smart-34139d79-e0da-4023-b665-d615e2c60682
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1538948039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1538948039
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.852052376
Short name T141
Test name
Test status
Simulation time 245681627 ps
CPU time 1.09 seconds
Started Feb 25 02:43:21 PM PST 24
Finished Feb 25 02:43:22 PM PST 24
Peak memory 206308 kb
Host smart-75ede0f9-edd1-4821-82c1-66f9c6ce4a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852052376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.852052376
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3850060003
Short name T774
Test name
Test status
Simulation time 2474899083 ps
CPU time 9.8 seconds
Started Feb 25 02:43:15 PM PST 24
Finished Feb 25 02:43:26 PM PST 24
Peak memory 215844 kb
Host smart-32fa1d31-ae07-4868-9f2d-74376e07cea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850060003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3850060003
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.45799182
Short name T712
Test name
Test status
Simulation time 47188318422 ps
CPU time 16.6 seconds
Started Feb 25 02:43:14 PM PST 24
Finished Feb 25 02:43:31 PM PST 24
Peak memory 215840 kb
Host smart-2587f782-ee9d-453d-a742-533cc4f462df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45799182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.45799182
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.326364370
Short name T623
Test name
Test status
Simulation time 72586553 ps
CPU time 1.49 seconds
Started Feb 25 02:43:08 PM PST 24
Finished Feb 25 02:43:10 PM PST 24
Peak memory 215648 kb
Host smart-24749680-9ee8-472c-af3d-60263a69560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326364370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.326364370
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3229727133
Short name T724
Test name
Test status
Simulation time 161777956 ps
CPU time 0.97 seconds
Started Feb 25 02:43:10 PM PST 24
Finished Feb 25 02:43:11 PM PST 24
Peak memory 205960 kb
Host smart-ccf78a4f-fc5e-4a8e-b002-fa74081e1e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229727133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3229727133
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1944451056
Short name T612
Test name
Test status
Simulation time 34752110790 ps
CPU time 52.88 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:44:16 PM PST 24
Peak memory 218928 kb
Host smart-065d937f-4106-4454-8bd5-d4944832a3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944451056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1944451056
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1724867824
Short name T497
Test name
Test status
Simulation time 11138086 ps
CPU time 0.67 seconds
Started Feb 25 02:43:17 PM PST 24
Finished Feb 25 02:43:18 PM PST 24
Peak memory 204584 kb
Host smart-5ab40704-a380-44b5-ba20-75450361f519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724867824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
724867824
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2089839799
Short name T93
Test name
Test status
Simulation time 4492709647 ps
CPU time 5.94 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:31 PM PST 24
Peak memory 233304 kb
Host smart-1ffd8d67-17bf-4082-b94f-8e702f07fee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089839799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2089839799
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.390744089
Short name T702
Test name
Test status
Simulation time 18772221 ps
CPU time 0.77 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:43:30 PM PST 24
Peak memory 204676 kb
Host smart-3af3cac6-b216-4601-bcf8-093c51897688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390744089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.390744089
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1436181220
Short name T153
Test name
Test status
Simulation time 46901488710 ps
CPU time 129.35 seconds
Started Feb 25 02:43:20 PM PST 24
Finished Feb 25 02:45:30 PM PST 24
Peak memory 254016 kb
Host smart-3f1490cf-68d6-4946-b41e-303764a157d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436181220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1436181220
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1253610285
Short name T753
Test name
Test status
Simulation time 109161371659 ps
CPU time 138.07 seconds
Started Feb 25 02:43:20 PM PST 24
Finished Feb 25 02:45:39 PM PST 24
Peak memory 252356 kb
Host smart-734dede4-7056-4553-bb8e-4d480163623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253610285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1253610285
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3462952356
Short name T685
Test name
Test status
Simulation time 16618470858 ps
CPU time 7.92 seconds
Started Feb 25 02:43:25 PM PST 24
Finished Feb 25 02:43:33 PM PST 24
Peak memory 232856 kb
Host smart-7ef4f31c-99e3-4d45-b124-a569625fbe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462952356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3462952356
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2022851840
Short name T843
Test name
Test status
Simulation time 41786517587 ps
CPU time 35.62 seconds
Started Feb 25 02:43:22 PM PST 24
Finished Feb 25 02:43:58 PM PST 24
Peak memory 238320 kb
Host smart-177d77a6-3f30-4f0d-8ee8-ef5b7c346284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022851840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2022851840
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2027056576
Short name T390
Test name
Test status
Simulation time 29460133 ps
CPU time 1.03 seconds
Started Feb 25 02:43:15 PM PST 24
Finished Feb 25 02:43:17 PM PST 24
Peak memory 216084 kb
Host smart-b4fe6534-766a-42e4-bd0b-fafe869f063e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027056576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2027056576
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.296162001
Short name T798
Test name
Test status
Simulation time 2020136257 ps
CPU time 11.95 seconds
Started Feb 25 02:43:18 PM PST 24
Finished Feb 25 02:43:30 PM PST 24
Peak memory 219332 kb
Host smart-e204292c-9f6e-436c-855e-6eb99f1477b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296162001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
296162001
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1448967520
Short name T714
Test name
Test status
Simulation time 4391510023 ps
CPU time 5.59 seconds
Started Feb 25 02:43:17 PM PST 24
Finished Feb 25 02:43:23 PM PST 24
Peak memory 224164 kb
Host smart-459b826d-548d-4544-b538-caedaabcd4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448967520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1448967520
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.407193027
Short name T363
Test name
Test status
Simulation time 16876506 ps
CPU time 0.75 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:43:24 PM PST 24
Peak memory 215724 kb
Host smart-f16f262e-a130-4ebd-80e4-4dfd6b6e48f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407193027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.407193027
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4268579924
Short name T878
Test name
Test status
Simulation time 665116801 ps
CPU time 4.13 seconds
Started Feb 25 02:43:29 PM PST 24
Finished Feb 25 02:43:33 PM PST 24
Peak memory 215844 kb
Host smart-6511c060-d7a2-4309-9dc8-b54ca62a6726
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4268579924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4268579924
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4233177728
Short name T166
Test name
Test status
Simulation time 261895637112 ps
CPU time 459.83 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:51:03 PM PST 24
Peak memory 262504 kb
Host smart-b2b2c9fd-852f-4f5c-b6f9-ca0e7d3cc0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233177728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4233177728
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.408849512
Short name T60
Test name
Test status
Simulation time 16281897512 ps
CPU time 42.52 seconds
Started Feb 25 02:43:18 PM PST 24
Finished Feb 25 02:44:01 PM PST 24
Peak memory 215824 kb
Host smart-c72a454e-3f35-4d1d-8de9-f616910e2a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408849512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.408849512
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.431480406
Short name T837
Test name
Test status
Simulation time 46690656583 ps
CPU time 29.9 seconds
Started Feb 25 02:43:23 PM PST 24
Finished Feb 25 02:43:53 PM PST 24
Peak memory 215820 kb
Host smart-3435a5ca-3284-4695-b62d-a503260f1269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431480406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.431480406
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1147143474
Short name T922
Test name
Test status
Simulation time 199489858 ps
CPU time 1.46 seconds
Started Feb 25 02:43:19 PM PST 24
Finished Feb 25 02:43:21 PM PST 24
Peak memory 215828 kb
Host smart-3443e272-4853-4c64-a163-bcb67b748193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147143474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1147143474
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1527756388
Short name T651
Test name
Test status
Simulation time 46279074 ps
CPU time 0.91 seconds
Started Feb 25 02:43:19 PM PST 24
Finished Feb 25 02:43:20 PM PST 24
Peak memory 204884 kb
Host smart-7d73416a-0cf8-45c9-8a9a-88c850c75bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527756388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1527756388
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.427200765
Short name T904
Test name
Test status
Simulation time 156823018 ps
CPU time 2.28 seconds
Started Feb 25 02:43:21 PM PST 24
Finished Feb 25 02:43:23 PM PST 24
Peak memory 215856 kb
Host smart-3c9d657d-8ff4-4499-8f11-948fbc162382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427200765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.427200765
Directory /workspace/9.spi_device_upload/latest
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