Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6221986	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6435859

1

T1

1

T2

1977

T3

929

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8199854	1			T1	53		T2	657		T3	21
values[0x0]	2227182	1			T2	819		T3	476		T4	12889
values[0x1]	2230809	1			T2	839		T3	449		T4	12937

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4500417	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8157428

1

T1

19

T2

2042

T3

935

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52832	1			T1	2		T3	11		T4	231
valid_sources[0x01]	50544	1			T2	169		T3	5		T4	222
valid_sources[0x02]	51119	1			T1	3		T3	5		T4	269
valid_sources[0x03]	49394	1			T2	1		T3	2		T4	220
valid_sources[0x04]	48269	1			T1	1		T4	218		T5	5
valid_sources[0x05]	47266	1			T3	2		T4	205		T5	2
valid_sources[0x06]	47481	1			T3	1		T4	257		T6	9
valid_sources[0x07]	47103	1			T2	1		T3	5		T4	261
valid_sources[0x08]	56896	1			T3	2		T4	241		T6	7
valid_sources[0x09]	52539	1			T4	275		T5	1		T6	1
valid_sources[0x0a]	48650	1			T2	1		T3	12		T4	222
valid_sources[0x0b]	55068	1			T3	2		T4	253		T5	1
valid_sources[0x0c]	50463	1			T4	244		T5	5		T6	2
valid_sources[0x0d]	45368	1			T1	1		T2	76		T3	6
valid_sources[0x0e]	49763	1			T3	1		T4	260		T5	1
valid_sources[0x0f]	49692	1			T3	1		T4	254		T5	6
valid_sources[0x10]	47883	1			T2	1		T3	7		T4	221
valid_sources[0x11]	52041	1			T2	228		T3	5		T4	252
valid_sources[0x12]	48233	1			T1	1		T3	6		T4	228
valid_sources[0x13]	50017	1			T3	3		T4	254		T5	4
valid_sources[0x14]	45077	1			T3	2		T4	255		T5	4
valid_sources[0x15]	53239	1			T3	1		T4	226		T5	9
valid_sources[0x16]	45904	1			T2	1		T3	1		T4	257
valid_sources[0x17]	48634	1			T3	1		T4	206		T5	1
valid_sources[0x18]	49346	1			T3	3		T4	276		T5	8
valid_sources[0x19]	48032	1			T2	1		T3	7		T4	273
valid_sources[0x1a]	50562	1			T2	2		T3	5		T4	238
valid_sources[0x1b]	54330	1			T3	2		T4	273		T5	2
valid_sources[0x1c]	49609	1			T3	2		T4	285		T6	5
valid_sources[0x1d]	51304	1			T3	3		T4	267		T6	1
valid_sources[0x1e]	49886	1			T3	7		T4	212		T5	4
valid_sources[0x1f]	49895	1			T3	5		T4	288		T5	1
valid_sources[0x20]	53033	1			T4	204		T5	4		T6	6
valid_sources[0x21]	47719	1			T3	6		T4	255		T5	6
valid_sources[0x22]	48549	1			T3	3		T4	227		T5	2
valid_sources[0x23]	46549	1			T2	270		T3	2		T4	239
valid_sources[0x24]	49929	1			T3	6		T4	233		T6	12
valid_sources[0x25]	46754	1			T3	2		T4	218		T6	1
valid_sources[0x26]	53217	1			T2	1		T3	4		T4	258
valid_sources[0x27]	47512	1			T3	4		T4	213		T5	2
valid_sources[0x28]	46078	1			T2	3		T3	2		T4	268
valid_sources[0x29]	51274	1			T3	4		T4	260		T6	2
valid_sources[0x2a]	54095	1			T3	4		T4	240		T5	5
valid_sources[0x2b]	48107	1			T1	1		T2	1		T3	3
valid_sources[0x2c]	47790	1			T3	4		T4	254		T5	9
valid_sources[0x2d]	48859	1			T3	5		T4	219		T5	4
valid_sources[0x2e]	50714	1			T2	1		T3	4		T4	211
valid_sources[0x2f]	52451	1			T1	6		T2	1		T3	3
valid_sources[0x30]	45312	1			T1	3		T2	266		T4	257
valid_sources[0x31]	50305	1			T2	1		T4	266		T5	3
valid_sources[0x32]	50845	1			T3	2		T4	274		T5	8
valid_sources[0x33]	48015	1			T3	6		T4	275		T5	11
valid_sources[0x34]	51111	1			T2	1		T3	2		T4	195
valid_sources[0x35]	46985	1			T3	4		T4	211		T5	4
valid_sources[0x36]	51336	1			T1	2		T2	1		T4	251
valid_sources[0x37]	47930	1			T3	2		T4	270		T5	2
valid_sources[0x38]	45876	1			T3	8		T4	247		T5	6
valid_sources[0x39]	47694	1			T2	34		T3	3		T4	221
valid_sources[0x3a]	50812	1			T4	224		T6	3		T10	516
valid_sources[0x3b]	48212	1			T3	5		T4	244		T5	6
valid_sources[0x3c]	46459	1			T4	276		T5	1		T6	9
valid_sources[0x3d]	49234	1			T3	5		T4	241		T5	4
valid_sources[0x3e]	48337	1			T4	223		T5	1		T7	130
valid_sources[0x3f]	54567	1			T3	1		T4	230		T6	2
valid_sources[0x40]	49150	1			T3	8		T4	225		T5	3
valid_sources[0x41]	50330	1			T3	7		T4	253		T5	3
valid_sources[0x42]	48493	1			T1	1		T3	13		T4	255
valid_sources[0x43]	50647	1			T3	2		T4	173		T6	2
valid_sources[0x44]	47132	1			T3	2		T4	232		T5	9
valid_sources[0x45]	48903	1			T2	1		T3	3		T4	262
valid_sources[0x46]	46654	1			T2	1		T3	3		T4	297
valid_sources[0x47]	49736	1			T3	2		T4	254		T5	5
valid_sources[0x48]	48145	1			T3	5		T4	247		T5	3
valid_sources[0x49]	48677	1			T3	2		T4	231		T5	13
valid_sources[0x4a]	49392	1			T3	1		T4	221		T5	7
valid_sources[0x4b]	52082	1			T3	5		T4	233		T5	12
valid_sources[0x4c]	49163	1			T2	1		T3	2		T4	224
valid_sources[0x4d]	50082	1			T3	5		T4	235		T5	1
valid_sources[0x4e]	50262	1			T3	2		T4	259		T5	4
valid_sources[0x4f]	45562	1			T3	12		T4	248		T5	7
valid_sources[0x50]	48600	1			T2	1		T3	4		T4	247
valid_sources[0x51]	52170	1			T2	2		T3	3		T4	215
valid_sources[0x52]	49554	1			T1	2		T2	1		T3	2
valid_sources[0x53]	56137	1			T2	1		T3	3		T4	248
valid_sources[0x54]	47739	1			T3	3		T4	246		T5	2
valid_sources[0x55]	48627	1			T3	3		T4	282		T5	2
valid_sources[0x56]	48499	1			T2	2		T3	2		T4	267
valid_sources[0x57]	58138	1			T3	2		T4	282		T5	4
valid_sources[0x58]	52601	1			T1	1		T3	6		T4	250
valid_sources[0x59]	49223	1			T1	1		T3	8		T4	248
valid_sources[0x5a]	49465	1			T2	1		T3	3		T4	251
valid_sources[0x5b]	50074	1			T4	283		T6	9		T10	666
valid_sources[0x5c]	51572	1			T2	2		T3	2		T4	264
valid_sources[0x5d]	45631	1			T3	6		T4	226		T5	1
valid_sources[0x5e]	48637	1			T2	1		T3	1		T4	277
valid_sources[0x5f]	49607	1			T2	131		T3	7		T4	218
valid_sources[0x60]	51809	1			T3	4		T4	255		T5	1
valid_sources[0x61]	50125	1			T2	1		T3	1		T4	271
valid_sources[0x62]	47253	1			T1	2		T2	1		T3	5
valid_sources[0x63]	47918	1			T3	6		T4	228		T5	2
valid_sources[0x64]	50079	1			T3	6		T4	277		T5	2
valid_sources[0x65]	49229	1			T4	240		T5	6		T6	3
valid_sources[0x66]	47721	1			T3	1		T4	252		T5	6
valid_sources[0x67]	48197	1			T3	8		T4	270		T5	2
valid_sources[0x68]	47994	1			T3	12		T4	244		T5	3
valid_sources[0x69]	53079	1			T2	1		T4	245		T6	3
valid_sources[0x6a]	53276	1			T1	1		T2	1		T3	5
valid_sources[0x6b]	49547	1			T3	1		T4	255		T5	6
valid_sources[0x6c]	49579	1			T3	4		T4	256		T5	6
valid_sources[0x6d]	48729	1			T3	1		T4	284		T5	9
valid_sources[0x6e]	47838	1			T4	255		T5	1		T6	4
valid_sources[0x6f]	48761	1			T2	1		T3	3		T4	227
valid_sources[0x70]	48024	1			T2	1		T3	6		T4	263
valid_sources[0x71]	46081	1			T1	1		T2	1		T4	226
valid_sources[0x72]	47090	1			T3	1		T4	265		T5	3
valid_sources[0x73]	51563	1			T2	198		T4	236		T5	7
valid_sources[0x74]	45457	1			T2	1		T3	4		T4	268
valid_sources[0x75]	48939	1			T3	6		T4	217		T5	4
valid_sources[0x76]	47893	1			T3	6		T4	227		T5	2
valid_sources[0x77]	49058	1			T3	3		T4	260		T5	5
valid_sources[0x78]	54261	1			T4	207		T5	4		T6	6
valid_sources[0x79]	49468	1			T3	2		T4	235		T5	6
valid_sources[0x7a]	52051	1			T3	9		T4	212		T5	5
valid_sources[0x7b]	48859	1			T3	12		T4	237		T6	2
valid_sources[0x7c]	48990	1			T2	2		T3	2		T4	235
valid_sources[0x7d]	49611	1			T3	1		T4	246		T5	2
valid_sources[0x7e]	49830	1			T2	1		T3	7		T4	191
valid_sources[0x7f]	50137	1			T3	12		T4	233		T5	2
valid_sources[0x80]	51536	1			T3	5		T4	259		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2462877

1

T1

1

T2

328

T3

14

values[0x0]

all_enables

biggest_size

2001821

1

T2

817

T3

473

T4

11537

values[0x1]

all_enables

biggest_size

1971161

1

T2

832

T3

442

T4

11155