Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6240502

1

T1

52

T2

338

T3

17

full_word

6434903

1

T1

1

T2

1977

T3

929

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	12674995	1			T1	53		T2	2315		T3	946
auto[TlIntgErrCmd]	134	1			T85	6		T89	3		T90	6
auto[TlIntgErrData]	136	1			T85	1		T89	9		T90	5
auto[TlIntgErrBoth]	140	1			T85	3		T89	8		T90	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8201580

1

T1

53

T2

657

T3

21

auto[1]

4473825

1

T2

1658

T3

925

T4

25826

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5738440	1			T1	52		T2	329		T3	7
auto[TlIntgErrNone]	partial	auto[1]	501692	1			T2	9		T3	10		T4	3134
auto[TlIntgErrNone]	full_word	auto[0]	2462953	1			T1	1		T2	328		T3	14
auto[TlIntgErrNone]	full_word	auto[1]	3971910	1			T2	1649		T3	915		T4	22692
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T85	3		T89	1		T90	2
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T85	3		T89	1		T90	4
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T89	1		T153	2		T157	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T109	1		T137	1		T158	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T85	1		T89	2		T90	3
auto[TlIntgErrData]	partial	auto[1]	69	1			T89	4		T90	2		T109	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T89	2		T109	1		T159	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T89	1		T137	2		T160	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T85	1		T89	5		T90	4
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T85	2		T89	3		T90	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T90	1		T161	1		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T90	2		T153	1		T135	1