Unified Coverage Report :: Module :: spi_tpm

Module : spi_tpm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.66	99.29	91.20		91.67	96.13	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm	95.66	99.29	91.20		91.67	96.13	100.00

---

Module Instance : tb.dut.u_spi_tpm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.66	99.29	91.20		91.67	96.13	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.68	99.29	84.99		91.67	95.32	92.16

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arbiter	86.14	100.00	70.73			92.86	80.95
u_cmdaddr_buffer	92.67	100.00	76.92			93.75	100.00
u_csb_sync_rst	100.00	100.00	100.00			100.00
u_hw_reg_slice	100.00	100.00					100.00
u_rdfifo_ready	100.00	100.00				100.00
u_sram_fifo	89.11	95.00	78.12			83.33	100.00
u_tpm_rd_buffer	89.74	100.00	69.23			100.00
u_tpm_wr_buffer	96.15	100.00	84.62			100.00	100.00
u_wrfifo_busy_sync	100.00	100.00				100.00
u_wrfifo_release_reqack	87.50	100.00	50.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_tpm

	Line No.	Total	Covered	Percent
TOTAL		282	280	99.29
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
ALWAYS	524	8	8	100.00
ALWAYS	541	3	3	100.00
ALWAYS	554	4	4	100.00
CONT_ASSIGN	563	1	1	100.00
CONT_ASSIGN	565	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
ALWAYS	593	3	3	100.00
ALWAYS	601	4	4	100.00
ALWAYS	609	3	3	100.00
ALWAYS	619	6	6	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
ALWAYS	647	4	4	100.00
CONT_ASSIGN	654	1	1	100.00
ALWAYS	657	4	4	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
ALWAYS	682	6	6	100.00
CONT_ASSIGN	705	1	1	100.00
ALWAYS	708	6	6	100.00
ALWAYS	720	4	4	100.00
ALWAYS	742	3	3	100.00
ALWAYS	750	3	3	100.00
ALWAYS	762	6	6	100.00
ALWAYS	779	6	6	100.00
ALWAYS	795	3	3	100.00
ALWAYS	801	6	6	100.00
ALWAYS	812	4	4	100.00
ALWAYS	822	4	4	100.00
ALWAYS	831	4	4	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
ALWAYS	851	6	6	100.00
ALWAYS	862	6	6	100.00
ALWAYS	872	3	3	100.00
ALWAYS	892	7	7	100.00
ALWAYS	934	15	15	100.00
ALWAYS	1011	3	3	100.00
CONT_ASSIGN	1020	1	1	100.00
ALWAYS	1023	3	3	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1044	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
ALWAYS	1051	3	3	100.00
ALWAYS	1063	4	4	100.00
CONT_ASSIGN	1072	1	1	100.00
ALWAYS	1094	3	3	100.00
ALWAYS	1122	72	71	98.61
CONT_ASSIGN	1375	1	1	100.00
CONT_ASSIGN	1377	1	1	100.00
ALWAYS	1384	6	6	100.00
ALWAYS	1396	8	8	100.00
ALWAYS	1411	6	6	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1430	1	0	0.00
CONT_ASSIGN	1461	1	1	100.00
CONT_ASSIGN	1467	1	1	100.00
ALWAYS	1472	6	6	100.00
ALWAYS	1482	4	4	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1524	1	1	100.00
CONT_ASSIGN	1558	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
334	1	1
348	1	1
373	1	1
491	1	1
492	1	1
520	1	1
524	1	1
525	1	1
526	1	1
528	1	1
529	1	1
530	1	1
531	1	1
532	1	1
			MISSING_ELSE
541	1	1
542	1	1
544	1	1
554	1	1
555	1	1
556	1	1
557	1	1
			MISSING_ELSE
563	1	1
565	1	1
590	1	1
593	1	1
594	1	1
596	1	1
601	1	1
602	1	1
603	1	1
604	1	1
			MISSING_ELSE
609	1	1
610	1	1
612	1	1
619	1	1
620	1	1
621	1	1
623	1	1
624	1	1
625	1	1
			MISSING_ELSE
636	1	1
643	1	1
647	1	1
648	1	1
649	1	1
650	1	1
			MISSING_ELSE
654	1	1
657	1	1
658	1	1
659	1	1
660	1	1
			MISSING_ELSE
664	1	1
666	1	1
679	1	1
682	1	1
683	1	1
684	1	1
685	1	1
686	1	1
687	1	1
			MISSING_ELSE
705	1	1
708	1	1
709	1	1
710	1	1
711	1	1
712	1	1
713	1	1
			MISSING_ELSE
720	1	1
721	1	1
726	1	1
732	1	1
742	1	1
743	1	1
745	1	1
			MISSING_ELSE
750	1	1
751	1	1
753	1	1
762	1	1
763	1	1
764	1	1
765	1	1
773	1	1
774	1	1
			MISSING_ELSE
779	1	1
780	1	1
782	1	1
783	1	1
784	1	1
785	1	1
			MISSING_ELSE
795	2	2
796	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
806	1	1
			MISSING_ELSE
812	1	1
813	1	1
814	1	1
816	1	1
			MISSING_ELSE
822	1	1
823	1	1
824	1	1
825	1	1
			MISSING_ELSE
831	1	1
832	1	1
833	1	1
835	1	1
			MISSING_ELSE
838	1	1
839	1	1
851	1	1
852	1	1
853	1	1
854	1	1
855	1	1
856	1	1
			MISSING_ELSE
862	1	1
863	1	1
864	1	1
865	1	1
866	1	1
867	1	1
			MISSING_ELSE
872	1	1
873	1	1
875	1	1
892	1	1
894	1	1
896	1	1
900	1	1
904	1	1
908	1	1
912	1	1
934	1	1
936	1	1
938	1	1
939	1	1
940	1	1
			MISSING_ELSE
947	1	1
951	1	1
955	1	1
959	1	1
964	1	1
966	1	1
968	1	1
973	1	1
977	1	1
981	1	1
1011	1	1
1012	1	1
1014	1	1
1020	1	1
1023	2	2
1024	1	1
1043	1	1
1044	1	1
1048	1	1
1051	1	1
1052	1	1
1054	1	1
1063	1	1
1064	1	1
1065	1	1
1066	1	1
			MISSING_ELSE
1072	1	1
1094	1	1
1095	1	1
1097	1	1
1122	1	1
1125	1	1
1126	1	1
1128	1	1
1129	1	1
1130	1	1
1132	1	1
1133	1	1
1139	1	1
1141	1	1
1143	1	1
1145	1	1
1146	1	1
1147	1	1
1149	1	1
1157	0	1
			MISSING_ELSE
1164	1	1
1166	1	1
1168	1	1
1169	1	1
			MISSING_ELSE
1173	1	1
1174	1	1
			MISSING_ELSE
1178	1	1
1179	1	1
1182	1	1
1187	1	1
1188	1	1
			MISSING_ELSE
1190	1	1
1193	1	1
1194	1	1
1197	1	1
1200	1	1
1205	1	1
1206	1	1
			MISSING_ELSE
			MISSING_ELSE
1211	1	1
1212	1	1
1217	1	1
1221	1	1
			MISSING_ELSE
1227	1	1
1228	1	1
1231	1	1
1232	1	1
			MISSING_ELSE
1236	1	1
1239	1	1
			MISSING_ELSE
1244	1	1
1245	1	1
1247	1	1
1249	1	1
1250	1	1
1251	1	1
1252	1	1
1253	1	1
1254	1	1
			==> MISSING_ELSE
			MISSING_ELSE
1260	1	1
1262	1	1
1263	1	1
1265	1	1
1266	1	1
			MISSING_ELSE
1271	1	1
1272	1	1
1276	1	1
1277	1	1
			MISSING_ELSE
1282	1	1
1285	1	1
1287	1	1
1288	1	1
			MISSING_ELSE
1294	1	1
1295	1	1
1296	1	1
			==> MISSING_ELSE
1301	1	1
1302	1	1
1303	1	1
			MISSING_ELSE
1375	1	1
1377	1	1
1384	1	1
1385	1	1
1386	1	1
1387	1	1
1388	1	1
1389	1	1
			MISSING_ELSE
1396	1	1
1397	1	1
1398	1	1
1402	1	1
1403	1	1
1404	1	1
1405	1	1
1406	1	1
			MISSING_ELSE
1411	1	1
1412	1	1
1413	1	1
1419	1	1
1420	1	1
1421	1	1
			MISSING_ELSE
1427	1	1
1430	0	1
1461	1	1
1467	1	1
1472	1	1
1473	1	1
1474	1	1
1475	1	1
1476	1	1
1477	1	1
			MISSING_ELSE
1482	1	1
1483	1	1
1484	1	1
1485	1	1
			MISSING_ELSE
1491	1	1
1492	1	1
1524	1	1
1558	1	1

---

Cond Coverage for Module : spi_tpm

	Total	Covered	Percent
Conditions	216	197	91.20
Logical	216	197	91.20
Non-Logical	0	0
Event	0	0

 LINE       563
 EXPRESSION ((cmdaddr_bitcnt == 5'b0) && (sck_st_q == StIdle))
             ------------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'b0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (sck_st_q == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       565
 EXPRESSION (cmdaddr_bitcnt == 5'h1d)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       590
 EXPRESSION (cmdaddr_bitcnt == 5'h1f)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       643
 EXPRESSION (isck_p2s_sent && (isck_data_sel == SelHwReg))
             ------1------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       643
 SUB-EXPRESSION (isck_data_sel == SelHwReg)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       654
 EXPRESSION (wrdata_bitcnt == 3'h7)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       710
 EXPRESSION (sck_cmdaddr_wvalid && (cmd_type == Write))
             ---------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       710
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T2,T3,T4

 LINE       743
 EXPRESSION (check_locality && (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr)))
             -------1------    ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T6,T7

 LINE       743
 SUB-EXPRESSION (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr))
                 ---------------1---------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T7,T10

 LINE       743
 SUB-EXPRESSION (addr[23:16] == TpmAddr)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       765
 EXPRESSION (((!sys_clk_tpm_cfg.tpm_mode)) && check_hw_reg && (cmd_type == Read) && is_tpm_reg_q && ((!invalid_locality)) && ((!sys_clk_tpm_cfg.hw_reg_dis)))
             --------------1--------------    ------2-----    ---------3--------    ------4-----    ----------5----------    ---------------6---------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T16,T29,T30
1	0	1	1	1	1	Covered	T4,T6,T7
1	1	0	1	1	1	Covered	T4,T7,T10
1	1	1	0	1	1	Covered	T4,T7,T10
1	1	1	1	0	1	Covered	T4,T6,T7
1	1	1	1	1	0	Covered	T4,T7,T10
1	1	1	1	1	1	Covered	T4,T6,T7

 LINE       765
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T6,T7

 LINE       783
 EXPRESSION (TpmReturnByHwAddr[i][11:2] == addr[11:2])
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       804
 EXPRESSION (check_locality && is_tpm_reg_d)
             -------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T6,T7

 LINE       806
 EXPRESSION ((addr[15:12] < 4'(spi_device_reg_pkg::NumLocality)) ? 1'b0 : 1'b1)
             -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T6,T7

 LINE       833
 EXPRESSION ((isck_p2s_sent && sck_rddata_shift_en) || (sck_wrfifo_wvalid && wrdata_shift_en))
             -------------------1------------------    -------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10

 LINE       833
 SUB-EXPRESSION (isck_p2s_sent && sck_rddata_shift_en)
                 ------1------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T7,T10

 LINE       833
 SUB-EXPRESSION (sck_wrfifo_wvalid && wrdata_shift_en)
                 --------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Not Covered
1	1	Covered	T4,T7,T10

 LINE       839
 EXPRESSION (xfer_bytes_q == xfer_size)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       855
 EXPRESSION (sys_rdfifo_wvalid_i & sys_rdfifo_wready_o)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T4,T7,T10

 LINE       866
 EXPRESSION (sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             ----------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       939
 EXPRESSION (((!invalid_locality)) && (4'(i) == locality))
             ----------1----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       939
 SUB-EXPRESSION (4'(i) == locality)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       964
 EXPRESSION (((!invalid_locality)) && sys_active_locality[locality[2:0]])
             ----------1----------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       1020
 EXPRESSION (isck_p2s_valid && (isck_p2s_bitcnt == '0))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       1020
 SUB-EXPRESSION (isck_p2s_bitcnt == '0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       1048
 EXPRESSION (isck_p2s_sent && (isck_data_sel == SelRdFifo))
             ------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T7,T10

 LINE       1048
 SUB-EXPRESSION (isck_data_sel == SelRdFifo)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       1072
 EXPRESSION (((&sck_rdfifo_idx)) && (isck_data_sel == SelRdFifo) && sck_p2s_valid && (isck_p2s_bitcnt == 3'b1))
             ---------1---------    --------------2-------------    ------3------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T4,T7,T10
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T4,T7,T10
1	1	1	1	Covered	T4,T7,T10

 LINE       1072
 SUB-EXPRESSION (isck_data_sel == SelRdFifo)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       1072
 SUB-EXPRESSION (isck_p2s_bitcnt == 3'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       1145
 EXPRESSION (cmdaddr_bitcnt == 5'h07)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       1173
 EXPRESSION (cmdaddr_bitcnt == 5'h1b)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T6,T7

 LINE       1178
 EXPRESSION ((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Read))
             ------------1------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T6,T7

 LINE       1178
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'h1f)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T6,T7

 LINE       1178
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T4,T6,T7

 LINE       1179
 EXPRESSION (((!is_tpm_reg_q)) || sys_clk_tpm_cfg.tpm_mode)
             --------1--------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T16,T29,T30
1	0	Covered	T4,T7,T10

 LINE       1187
 EXPRESSION (sck_cmdaddr_wdepth == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T4,T7,T10

 LINE       1194
 EXPRESSION (invalid_locality && sys_clk_tpm_cfg.invalid_locality)
             --------1-------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T6,T7

 LINE       1205
 EXPRESSION (sck_cmdaddr_wdepth == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T4,T7,T10

 LINE       1211
 EXPRESSION ((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Write))
             ------------1------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T7,T10

 LINE       1211
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'h1f)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T6,T7

 LINE       1211
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T7,T10

 LINE       1212
 EXPRESSION (((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))
             ----------1---------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T10,T16
1	1	Covered	T4,T7,T10

 LINE       1231
 EXPRESSION ((cmd_type == Read) && ((!sck_rdfifo_cmd_pending)) && ((~|sck_cmdaddr_wdepth)))
             ---------1--------    -------------2-------------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T10
1	0	1	Covered	T4,T7,T10
1	1	0	Covered	T4,T7,T10
1	1	1	Covered	T4,T7,T10

 LINE       1231
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T4,T7,T10

 LINE       1236
 EXPRESSION (isck_p2s_sent && (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))))
             ------1------    ---------------------------------------------------------------2---------------------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       1236
 SUB-EXPRESSION (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth))))
                 ------------------------1-----------------------    ------------------------------------2------------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T10
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10

 LINE       1236
 SUB-EXPRESSION ((cmd_type == Read) && enough_payload_in_rdfifo)
                 ---------1--------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       1236
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T4,T7,T10

 LINE       1236
 SUB-EXPRESSION ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))
                 ---------1---------    ----------2---------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T10
1	0	1	Covered	T4,T7,T10
1	1	0	Covered	T4,T10,T16
1	1	1	Covered	T4,T7,T10

 LINE       1236
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T4,T7,T10

 LINE       1249
 EXPRESSION ((cmd_type == Read) && is_hw_reg)
             ---------1--------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T6,T7

 LINE       1249
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T4,T6,T7

 LINE       1251
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T4,T7,T10

 LINE       1253
 EXPRESSION (cmd_type == Write)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T7,T10

 LINE       1265
 EXPRESSION (isck_p2s_sent && xfer_size_met)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       1276
 EXPRESSION (isck_p2s_sent && xfer_size_met)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Covered	T4,T6,T7
1	1	Covered	T6,T7,T9

 LINE       1285
 EXPRESSION (sck_wrfifo_wvalid && xfer_size_met)
             --------1--------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       1294
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T7

 LINE       1301
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T4,T6,T7

 LINE       1388
 EXPRESSION (sys_cmdaddr.rnw & sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             -------1-------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T10
1	0	1	Not Covered
1	1	0	Covered	T4,T7,T10
1	1	1	Covered	T4,T7,T10

 LINE       1398
 EXPRESSION (cmdaddr_bitcnt == 5'h0f)
            ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T6,T7

 LINE       1403
 EXPRESSION (sck_cmdaddr_wvalid && (cmd_type == Read))
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       1403
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T6,T7

 LINE       1405
 EXPRESSION (isck_p2s_sent && xfer_size_met && (sck_st_q == StReadFifo))
             ------1------    ------2------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T10
1	0	1	Covered	T4,T7,T10
1	1	0	Covered	T4,T6,T7
1	1	1	Covered	T4,T7,T10

 LINE       1405
 SUB-EXPRESSION (sck_st_q == StReadFifo)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T7,T10

 LINE       1413
 EXPRESSION (sys_csb_deasserted_pulse & ((!sys_rdfifo_sync_clr)))
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T1,T4,T6
1	1	Covered	T4,T7,T10

 LINE       1420
 EXPRESSION (sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             ----------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       1427
 EXPRESSION (sys_csb_deasserted_pulse & ((!sys_rdfifo_sync_clr)))
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T1,T4,T6
1	1	Covered	T4,T7,T10

 LINE       1461
 EXPRESSION (sys_rdfifo_wvalid_i & ((!sys_rdfifo_wready_o)))
             ---------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T10
1	1	Not Covered

 LINE       1467
 EXPRESSION (enough_payload_in_rdfifo && ((sck_st_q == StReadFifo) || (sck_st_q == StStartByte)))
             ------------1-----------    ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T7,T10
1	1	Covered	T4,T7,T10

 LINE       1467
 SUB-EXPRESSION ((sck_st_q == StReadFifo) || (sck_st_q == StStartByte))
                 ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T7,T10

 LINE       1467
 SUB-EXPRESSION (sck_st_q == StReadFifo)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       1467
 SUB-EXPRESSION (sck_st_q == StStartByte)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       1474
 EXPRESSION (sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo])
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T4,T7,T10

 LINE       1484
 EXPRESSION (sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo])
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T4,T7,T10

 LINE       1491
 EXPRESSION (rdfifo_active && ((!sck_rdfifo_req_pending)) && ((!sck_rdfifo_full)))
             ------1------    -------------2-------------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T7,T10
1	1	0	Covered	T4,T7,T10
1	1	1	Covered	T4,T7,T10

---

FSM Coverage for Module : spi_tpm

Summary for FSM :: sck_st_q

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	12	11	91.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: sck_st_q

---

states	Line No.	Covered	Tests
StAddr	1147	Covered	T4,T6,T7
StEnd	1157	Covered	T4,T6,T7
StIdle	1142	Covered	T1,T2,T3
StInvalid	1197	Covered	T4,T6,T7
StReadFifo	1252	Covered	T4,T7,T10
StReadHwReg	1250	Covered	T4,T6,T7
StStartByte	1193	Covered	T4,T6,T7
StWait	1182	Covered	T4,T7,T10
StWrite	1254	Covered	T4,T7,T10

transitions	Line No.	Covered	Tests
StAddr->StInvalid	1197	Covered	T4,T6,T7
StAddr->StStartByte	1193	Covered	T4,T6,T7
StAddr->StWait	1182	Covered	T4,T7,T10
StIdle->StAddr	1147	Covered	T4,T6,T7
StIdle->StEnd	1157	Not Covered
StReadFifo->StEnd	1266	Covered	T4,T7,T10
StReadHwReg->StEnd	1277	Covered	T6,T7,T9
StStartByte->StReadFifo	1252	Covered	T4,T7,T10
StStartByte->StReadHwReg	1250	Covered	T4,T6,T7
StStartByte->StWrite	1254	Covered	T4,T7,T10
StWait->StStartByte	1239	Covered	T4,T7,T10
StWrite->StEnd	1288	Covered	T4,T7,T10

---

Branch Coverage for Module : spi_tpm

	Line No.	Total	Covered	Percent
Branches		155	149	96.13
IF	524	3	3	100.00
IF	541	2	2	100.00
IF	554	3	3	100.00
IF	593	2	2	100.00
IF	601	3	3	100.00
IF	609	2	2	100.00
IF	619	4	4	100.00
IF	647	3	3	100.00
IF	657	3	3	100.00
IF	682	4	4	100.00
IF	708	4	4	100.00
CASE	721	3	3	100.00
IF	743	2	2	100.00
IF	750	2	2	100.00
IF	762	3	3	100.00
IF	783	2	2	100.00
IF	795	2	2	100.00
IF	801	4	4	100.00
IF	812	3	3	100.00
IF	822	3	3	100.00
IF	831	3	3	100.00
IF	851	4	4	100.00
IF	862	4	4	100.00
IF	872	2	2	100.00
CASE	894	6	5	83.33
CASE	936	11	10	90.91
IF	1011	2	2	100.00
IF	1023	2	2	100.00
IF	1051	2	2	100.00
IF	1063	3	3	100.00
IF	1094	2	2	100.00
CASE	1141	37	33	89.19
IF	1384	4	4	100.00
IF	1396	5	5	100.00
IF	1411	4	4	100.00
IF	1472	4	4	100.00
IF	1482	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	524	if ((!sys_rst_ni))
-2-:	528	if (sys_csb_asserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	541	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	554	if ((!rst_ni))
-2-:	556	if (cmdaddr_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	593	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	601	if ((!rst_ni))
-2-:	603	if (cmdaddr_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	609	if (cmdaddr_shift_en)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	619	if ((!rst_ni))
-2-:	621	if (isck_fifoaddr_latch)
-3-:	624	if (isck_fifoaddr_inc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	647	if ((!rst_ni))
-2-:	649	if (wrdata_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	657	if ((!rst_ni))
-2-:	659	if (wrdata_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	682	if ((!sys_rst_ni))
-2-:	684	if (sys_wrfifo_release_i)
-3-:	686	if (sys_wrfifo_release_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T7,T10
0	0	1	Covered	T4,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	708	if ((!sys_rst_ni))
-2-:	710	if ((sck_cmdaddr_wvalid && (cmd_type == Write)))
-3-:	712	if (sck_wrfifo_release_req)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T7,T10
0	0	1	Covered	T4,T7,T10
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	721	case (1'b1)

Branches:

-1-	Status	Tests
check_locality	Covered	T4,T6,T7
check_hw_reg	Covered	T4,T6,T7
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	743	if ((check_locality && (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr))))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	762	if ((!rst_ni))
-2-:	765	if (((((((!sys_clk_tpm_cfg.tpm_mode) && check_hw_reg) && (cmd_type == Read)) && is_tpm_reg_q) && (!invalid_locality)) && (!sys_clk_tpm_cfg.hw_reg_dis)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	783	if ((TpmReturnByHwAddr[i][11:2] == addr[11:2]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	795	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	801	if ((!rst_ni))
-2-:	804	if ((check_locality && is_tpm_reg_d))
-3-:	806	((addr[15:12] < 4'(spi_device_reg_pkg::NumLocality))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T4,T6,T7
0	1	0	Covered	T4,T6,T7
0	0	-	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	812	if ((!rst_ni))
-2-:	814	if (latch_cmd_type)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	822	if ((!rst_ni))
-2-:	824	if (latch_xfer_size)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	831	if ((!rst_ni))
-2-:	833	if (((isck_p2s_sent && sck_rddata_shift_en) || (sck_wrfifo_wvalid && wrdata_shift_en)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	851	if ((!sys_rst_ni))
-2-:	853	if (sys_csb_asserted_pulse)
-3-:	855	if ((sys_rdfifo_wvalid_i & sys_rdfifo_wready_o))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T6
0	0	1	Covered	T4,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	862	if ((!sys_rst_ni))
-2-:	864	if (sys_csb_asserted_pulse)
-3-:	866	if ((sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T6
0	0	1	Covered	T4,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	872	if ((!sys_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	894	case (isck_data_sel)

Branches:

-1-	Status	Tests
SelWait	Covered	T1,T2,T3
SelStart	Covered	T4,T6,T7
SelInvalid	Covered	T4,T6,T7
SelHwReg	Covered	T4,T6,T7
SelRdFifo	Covered	T4,T7,T10
default	Not Covered

	LineNo.	Expression
-1-:	936	case (isck_hw_reg_idx)
-2-:	964	if (((!invalid_locality) && sys_active_locality[locality[2:0]]))

Branches:

-1-	-2-	Status	Tests
RegAccess	-	Covered	T1,T2,T3
RegIntEn	-	Covered	T4,T6,T7
RegIntVect	-	Covered	T4,T6,T7
RegIntSts	-	Covered	T4,T6,T7
RegIntfCap	-	Covered	T32,T83,T84
RegSts	1	Covered	T4,T6,T7
RegSts	0	Covered	T4,T6,T7
RegHashStart	-	Covered	T4,T6,T7
RegId	-	Covered	T4,T6,T9
RegRid	-	Covered	T4,T6,T7
default	-	Not Covered

	LineNo.	Expression
-1-:	1011	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	1023	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	1051	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	1063	if ((!rst_ni))
-2-:	1065	if (isck_rd_byte_sent)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	1094	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	1141	case (sck_st_q)
-2-:	1145	if ((cmdaddr_bitcnt == 5'h07))
-3-:	1146	if (sys_clk_tpm_en)
-4-:	1166	if ((cmdaddr_bitcnt >= 5'h18))
-5-:	1173	if ((cmdaddr_bitcnt == 5'h1b))
-6-:	1178	if (((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Read)))
-7-:	1179	if (((!is_tpm_reg_q) || sys_clk_tpm_cfg.tpm_mode))
-8-:	1187	if ((sck_cmdaddr_wdepth == '0))
-9-:	1190	if (is_hw_reg)
-10-:	1194	if ((invalid_locality && sys_clk_tpm_cfg.invalid_locality))
-11-:	1205	if ((sck_cmdaddr_wdepth == '0))
-12-:	1211	if (((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Write)))
-13-:	1212	if (((!sck_wrfifo_busy) && (~|sck_cmdaddr_wdepth)))
-14-:	1231	if ((((cmd_type == Read) && (!sck_rdfifo_cmd_pending)) && (~|sck_cmdaddr_wdepth)))
-15-:	1236	if ((isck_p2s_sent && (((cmd_type == Read) && enough_payload_in_rdfifo) || (((cmd_type == Write) && (!sck_wrfifo_busy)) && (~|sck_cmdaddr_wdepth)))))
-16-:	1247	if (isck_p2s_sent)
-17-:	1249	if (((cmd_type == Read) && is_hw_reg))
-18-:	1251	if ((cmd_type == Read))
-19-:	1253	if ((cmd_type == Write))
-20-:	1265	if ((isck_p2s_sent && xfer_size_met))
-21-:	1276	if ((isck_p2s_sent && xfer_size_met))
-22-:	1285	if ((sck_wrfifo_wvalid && xfer_size_met))
-23-:	1294	if ((cmd_type == Read))
-24-:	1301	if ((cmd_type == Read))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	Status	Tests
StIdle	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StIdle	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StAddr	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StAddr	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StAddr	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StAddr	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StAddr	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T10
StAddr	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T10
StAddr	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StAddr	-	-	-	-	1	0	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StAddr	-	-	-	-	1	0	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T10
StAddr	-	-	-	-	1	0	-	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T10
StAddr	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StAddr	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T10
StAddr	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T10
StAddr	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StWait	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T10
StWait	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T10
StWait	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T10
StWait	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T10
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T4,T6,T7
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	Covered	T4,T7,T10
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	Covered	T4,T7,T10
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	Not Covered
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StReadFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T7,T10
StReadFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T7,T10
StReadHwReg	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T6,T7,T9
StReadHwReg	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T4,T6,T7
StWrite	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T7,T10
StWrite	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T7,T10
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T6,T7
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StEnd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T7
StEnd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T7,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	1384	if ((!sys_rst_ni))
-2-:	1386	if (sys_csb_deasserted_pulse)
-3-:	1388	if (((sys_cmdaddr.rnw & sys_cmdaddr_rvalid_o) & sys_cmdaddr_rready_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T6
0	0	1	Covered	T4,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1396	if ((!sys_rst_ni))
-2-:	1398	if ((cmdaddr_bitcnt == 5'h0f))
-3-:	1403	if ((sck_cmdaddr_wvalid && (cmd_type == Read)))
-4-:	1405	if (((isck_p2s_sent && xfer_size_met) && (sck_st_q == StReadFifo)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T4,T6,T7
0	0	1	-	Covered	T4,T7,T10
0	0	0	1	Covered	T4,T7,T10
0	0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	1411	if ((!sys_rst_ni))
-2-:	1413	if ((sys_csb_deasserted_pulse & (!sys_rdfifo_sync_clr)))
-3-:	1420	if ((sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T7,T10
0	0	1	Covered	T4,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1472	if ((!rst_ni))
-2-:	1474	if ((sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo]))
-3-:	1476	if (sck_sram_rvalid[SramRdFifo])

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T7,T10
0	0	1	Covered	T4,T7,T10
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	1482	if ((!rst_ni))
-2-:	1484	if ((sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo]))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
0	0	Covered	T4,T6,T7

---

Assert Coverage for Module : spi_tpm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CmdAddrAvailable_A	183944557	72902	0	0
CmdAddrBitCntInAddrSt_A	183944557	811168	0	0
CmdAddrInfo_A	183944557	80861	0	0
CmdPowerof2_A	939	939	0	0
DataFifoLessThan64_A	939	939	0	0
DataSelKnown_A	183945476	42823660	0	0
HwRegCondition2_a	183944557	17827	0	0
HwRegCondition_A	183944557	101396	0	0
HwRegIdxKnown_A	183945476	42823660	0	0
LocalityLatchCondition_A	183944557	101396	0	0
RdFifoDepthPoT_A	939	939	0	0
RdFifoNumBytesPoT_A	939	939	0	0
RdPowerof2_A	939	939	0	0
SckFifoAddrLatchCondition_A	183944557	101396	0	0
TpmRegSizeMatch_A	939	939	0	0
WrDepthSpec_A	939	939	0	0
WrFifoAvailable_A	183944557	643064	0	0

CmdAddrAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	72902	0	0
T4	791679	573	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	318	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	862	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	571	0	0
T18	0	289	0	0
T19	0	436	0	0
T28	0	215	0	0
T29	0	566	0	0
T30	0	359	0	0
T47	0	12	0	0

CmdAddrBitCntInAddrSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	811168	0	0
T4	791679	5232	0	0
T5	19513	0	0	0
T6	99763	3224	0	0
T7	107130	2976	0	0
T8	144	16	0	0
T9	116799	3784	0	0
T10	176201	8560	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	4568	0	0
T18	0	2704	0	0
T28	0	2192	0	0
T29	0	4528	0	0

CmdAddrInfo_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	80861	0	0
T4	791679	425	0	0
T5	19513	0	0	0
T6	99763	403	0	0
T7	107130	282	0	0
T8	144	2	0	0
T9	116799	473	0	0
T10	176201	840	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	389	0	0
T18	0	200	0	0
T28	0	200	0	0
T29	0	421	0	0

CmdPowerof2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

DataFifoLessThan64_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

DataSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183945476	42823660	0	0
T4	791680	219736	0	0
T5	19514	0	0	0
T6	99764	90808	0	0
T7	107131	103792	0	0
T8	145	144	0	0
T9	116800	111831	0	0
T10	176202	338400	0	0
T11	44607	0	0	0
T12	146285	0	0	0
T13	474333	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

HwRegCondition2_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	17827	0	0
T4	791679	44	0	0
T5	19513	0	0	0
T6	99763	268	0	0
T7	107130	20	0	0
T8	144	2	0	0
T9	116799	315	0	0
T10	176201	129	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T18	0	31	0	0
T19	0	26	0	0
T27	0	32	0	0
T28	0	20	0	0

HwRegCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	101396	0	0
T4	791679	654	0	0
T5	19513	0	0	0
T6	99763	403	0	0
T7	107130	372	0	0
T8	144	2	0	0
T9	116799	473	0	0
T10	176201	1070	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	571	0	0
T18	0	338	0	0
T28	0	274	0	0
T29	0	566	0	0

HwRegIdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183945476	42823660	0	0
T4	791680	219736	0	0
T5	19514	0	0	0
T6	99764	90808	0	0
T7	107131	103792	0	0
T8	145	144	0	0
T9	116800	111831	0	0
T10	176202	338400	0	0
T11	44607	0	0	0
T12	146285	0	0	0
T13	474333	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

LocalityLatchCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	101396	0	0
T4	791679	654	0	0
T5	19513	0	0	0
T6	99763	403	0	0
T7	107130	372	0	0
T8	144	2	0	0
T9	116799	473	0	0
T10	176201	1070	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	571	0	0
T18	0	338	0	0
T28	0	274	0	0
T29	0	566	0	0

RdFifoDepthPoT_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

RdFifoNumBytesPoT_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

RdPowerof2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SckFifoAddrLatchCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	101396	0	0
T4	791679	654	0	0
T5	19513	0	0	0
T6	99763	403	0	0
T7	107130	372	0	0
T8	144	2	0	0
T9	116799	473	0	0
T10	176201	1070	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	571	0	0
T18	0	338	0	0
T28	0	274	0	0
T29	0	566	0	0

TpmRegSizeMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WrDepthSpec_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WrFifoAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	643064	0	0
T4	791679	5480	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	3135	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	8152	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	5013	0	0
T18	0	3300	0	0
T19	0	4254	0	0
T28	0	2291	0	0
T29	0	4864	0	0
T30	0	3523	0	0
T47	0	212	0	0