Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Covered	T4,T7,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T13
1	0	Covered	T4,T10,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T4,T10,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	931239224	745289421	0	0
CheckNGreaterZero_A	2817	2817	0	0
GntImpliesReady_A	931239224	4237977	0	0
GntImpliesValid_A	931239224	4237977	0	0
GrantKnown_A	931239224	745289421	0	0
IdxKnown_A	931239224	745289421	0	0
IndexIsCorrect_A	931239224	4237977	0	0
LockArbDecision_A	931239224	0	0	0
NoReadyValidNoGrant_A	931239224	0	0	0
ReadyAndValidImplyGrant_A	931239224	4237977	0	0
ReqAndReadyImplyGrant_A	931239224	4237977	0	0
ReqImpliesValid_A	931239224	4237977	0	0
ReqStaysHighUntilGranted0_M	931239224	0	0	0
RoundRobin_A	931239224	5	0	939
ValidKnown_A	931239224	745289421	0	0
gen_data_port_assertion.DataFlow_A	931239224	4237977	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	745289421	0	0
T1	1405	1317	0	0
T2	203291	203212	0	0
T3	892358	892292	0	0
T4	1752164	948595	0	0
T5	125036	105186	0	0
T6	841497	732722	0	0
T7	848008	737486	0	0
T8	1619	1413	0	0
T9	478882	357056	0	0
T10	856522	982472	0	0
T11	89212	44306	0	0
T12	146284	146284	0	0
T13	474332	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2817	2817	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	4237977	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	1752164	25848	0	0
T5	125036	832	0	0
T6	841497	0	0	0
T7	848008	6672	0	0
T8	1619	0	0	0
T9	478882	0	0	0
T10	856522	51832	0	0
T11	141833	832	0	0
T12	292568	832	0	0
T13	948664	15179	0	0
T16	0	11442	0	0
T18	0	4242	0	0
T19	0	8627	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T47	0	231	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	4237977	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	1752164	25848	0	0
T5	125036	832	0	0
T6	841497	0	0	0
T7	848008	6672	0	0
T8	1619	0	0	0
T9	478882	0	0	0
T10	856522	51832	0	0
T11	141833	832	0	0
T12	292568	832	0	0
T13	948664	15179	0	0
T16	0	11442	0	0
T18	0	4242	0	0
T19	0	8627	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T47	0	231	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	745289421	0	0
T1	1405	1317	0	0
T2	203291	203212	0	0
T3	892358	892292	0	0
T4	1752164	948595	0	0
T5	125036	105186	0	0
T6	841497	732722	0	0
T7	848008	737486	0	0
T8	1619	1413	0	0
T9	478882	357056	0	0
T10	856522	982472	0	0
T11	89212	44306	0	0
T12	146284	146284	0	0
T13	474332	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	745289421	0	0
T1	1405	1317	0	0
T2	203291	203212	0	0
T3	892358	892292	0	0
T4	1752164	948595	0	0
T5	125036	105186	0	0
T6	841497	732722	0	0
T7	848008	737486	0	0
T8	1619	1413	0	0
T9	478882	357056	0	0
T10	856522	982472	0	0
T11	89212	44306	0	0
T12	146284	146284	0	0
T13	474332	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	4237977	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	1752164	25848	0	0
T5	125036	832	0	0
T6	841497	0	0	0
T7	848008	6672	0	0
T8	1619	0	0	0
T9	478882	0	0	0
T10	856522	51832	0	0
T11	141833	832	0	0
T12	292568	832	0	0
T13	948664	15179	0	0
T16	0	11442	0	0
T18	0	4242	0	0
T19	0	8627	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T47	0	231	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	4237977	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	1752164	25848	0	0
T5	125036	832	0	0
T6	841497	0	0	0
T7	848008	6672	0	0
T8	1619	0	0	0
T9	478882	0	0	0
T10	856522	51832	0	0
T11	141833	832	0	0
T12	292568	832	0	0
T13	948664	15179	0	0
T16	0	11442	0	0
T18	0	4242	0	0
T19	0	8627	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T47	0	231	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	4237977	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	1752164	25848	0	0
T5	125036	832	0	0
T6	841497	0	0	0
T7	848008	6672	0	0
T8	1619	0	0	0
T9	478882	0	0	0
T10	856522	51832	0	0
T11	141833	832	0	0
T12	292568	832	0	0
T13	948664	15179	0	0
T16	0	11442	0	0
T18	0	4242	0	0
T19	0	8627	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T47	0	231	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	4237977	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	1752164	25848	0	0
T5	125036	832	0	0
T6	841497	0	0	0
T7	848008	6672	0	0
T8	1619	0	0	0
T9	478882	0	0	0
T10	856522	51832	0	0
T11	141833	832	0	0
T12	292568	832	0	0
T13	948664	15179	0	0
T16	0	11442	0	0
T18	0	4242	0	0
T19	0	8627	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T47	0	231	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	5	0	939
T20	106636	1	0	1
T22	0	1	0	0
T38	140470	0	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	10451	0	0	1
T52	20678	0	0	1
T53	95237	0	0	1
T54	116086	0	0	1
T55	3638	0	0	1
T56	1695	0	0	1
T57	46673	0	0	1
T58	1578	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	745289421	0	0
T1	1405	1317	0	0
T2	203291	203212	0	0
T3	892358	892292	0	0
T4	1752164	948595	0	0
T5	125036	105186	0	0
T6	841497	732722	0	0
T7	848008	737486	0	0
T8	1619	1413	0	0
T9	478882	357056	0	0
T10	856522	982472	0	0
T11	89212	44306	0	0
T12	146284	146284	0	0
T13	474332	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	931239224	4237977	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	1752164	25848	0	0
T5	125036	832	0	0
T6	841497	0	0	0
T7	848008	6672	0	0
T8	1619	0	0	0
T9	478882	0	0	0
T10	856522	51832	0	0
T11	141833	832	0	0
T12	292568	832	0	0
T13	948664	15179	0	0
T16	0	11442	0	0
T18	0	4242	0	0
T19	0	8627	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T47	0	231	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Covered	T4,T7,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T7,T10
0	0	1	Unreachable
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	183944557	42823660	0	0
CheckNGreaterZero_A	939	939	0	0
GntImpliesReady_A	183944557	949894	0	0
GntImpliesValid_A	183944557	949894	0	0
GrantKnown_A	183944557	42823660	0	0
IdxKnown_A	183944557	42823660	0	0
IndexIsCorrect_A	183944557	949894	0	0
LockArbDecision_A	183944557	0	0	0
NoReadyValidNoGrant_A	183944557	0	0	0
ReadyAndValidImplyGrant_A	183944557	949894	0	0
ReqAndReadyImplyGrant_A	183944557	949894	0	0
ReqImpliesValid_A	183944557	949894	0	0
ReqStaysHighUntilGranted0_M	183944557	0	0	0
RoundRobin_A	183944557	0	0	0
ValidKnown_A	183944557	42823660	0	0
gen_data_port_assertion.DataFlow_A	183944557	949894	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	42823660	0	0
T4	791679	219736	0	0
T5	19513	0	0	0
T6	99763	90808	0	0
T7	107130	103792	0	0
T8	144	144	0	0
T9	116799	111831	0	0
T10	176201	338400	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	949894	0	0
T4	791679	7726	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	4557	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	11541	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	7688	0	0
T18	0	4242	0	0
T19	0	6436	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T47	0	231	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	949894	0	0
T4	791679	7726	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	4557	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	11541	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	7688	0	0
T18	0	4242	0	0
T19	0	6436	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T47	0	231	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	42823660	0	0
T4	791679	219736	0	0
T5	19513	0	0	0
T6	99763	90808	0	0
T7	107130	103792	0	0
T8	144	144	0	0
T9	116799	111831	0	0
T10	176201	338400	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	42823660	0	0
T4	791679	219736	0	0
T5	19513	0	0	0
T6	99763	90808	0	0
T7	107130	103792	0	0
T8	144	144	0	0
T9	116799	111831	0	0
T10	176201	338400	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	949894	0	0
T4	791679	7726	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	4557	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	11541	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	7688	0	0
T18	0	4242	0	0
T19	0	6436	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T47	0	231	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	949894	0	0
T4	791679	7726	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	4557	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	11541	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	7688	0	0
T18	0	4242	0	0
T19	0	6436	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T47	0	231	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	949894	0	0
T4	791679	7726	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	4557	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	11541	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	7688	0	0
T18	0	4242	0	0
T19	0	6436	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T47	0	231	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	949894	0	0
T4	791679	7726	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	4557	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	11541	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	7688	0	0
T18	0	4242	0	0
T19	0	6436	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T47	0	231	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	42823660	0	0
T4	791679	219736	0	0
T5	19513	0	0	0
T6	99763	90808	0	0
T7	107130	103792	0	0
T8	144	144	0	0
T9	116799	111831	0	0
T10	176201	338400	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	949894	0	0
T4	791679	7726	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	4557	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	11541	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	7688	0	0
T18	0	4242	0	0
T19	0	6436	0	0
T28	0	3273	0	0
T29	0	7558	0	0
T30	0	4958	0	0
T47	0	231	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T13
1	0	Covered	T4,T10,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T4,T10,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T10,T13
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	183944557	139200466	0	0
CheckNGreaterZero_A	939	939	0	0
GntImpliesReady_A	183944557	668105	0	0
GntImpliesValid_A	183944557	668105	0	0
GrantKnown_A	183944557	139200466	0	0
IdxKnown_A	183944557	139200466	0	0
IndexIsCorrect_A	183944557	668105	0	0
LockArbDecision_A	183944557	0	0	0
NoReadyValidNoGrant_A	183944557	0	0	0
ReadyAndValidImplyGrant_A	183944557	668105	0	0
ReqAndReadyImplyGrant_A	183944557	668105	0	0
ReqImpliesValid_A	183944557	668105	0	0
ReqStaysHighUntilGranted0_M	183944557	0	0	0
RoundRobin_A	183944557	0	0	0
ValidKnown_A	183944557	139200466	0	0
gen_data_port_assertion.DataFlow_A	183944557	668105	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	668105	0	0
T4	791679	1831	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	4315	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	4949	0	0
T19	0	2191	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T59	0	2879	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	668105	0	0
T4	791679	1831	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	4315	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	4949	0	0
T19	0	2191	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T59	0	2879	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	668105	0	0
T4	791679	1831	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	4315	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	4949	0	0
T19	0	2191	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T59	0	2879	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	668105	0	0
T4	791679	1831	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	4315	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	4949	0	0
T19	0	2191	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T59	0	2879	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	668105	0	0
T4	791679	1831	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	4315	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	4949	0	0
T19	0	2191	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T59	0	2879	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	668105	0	0
T4	791679	1831	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	4315	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	4949	0	0
T19	0	2191	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T59	0	2879	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	668105	0	0
T4	791679	1831	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	4315	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	4949	0	0
T19	0	2191	0	0
T26	0	15807	0	0
T27	0	5498	0	0
T31	0	12108	0	0
T32	0	1892	0	0
T34	0	11734	0	0
T59	0	2879	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	563350110	563265295	0	0
CheckNGreaterZero_A	939	939	0	0
GntImpliesReady_A	563350110	2619978	0	0
GntImpliesValid_A	563350110	2619978	0	0
GrantKnown_A	563350110	563265295	0	0
IdxKnown_A	563350110	563265295	0	0
IndexIsCorrect_A	563350110	2619978	0	0
LockArbDecision_A	563350110	0	0	0
NoReadyValidNoGrant_A	563350110	0	0	0
ReadyAndValidImplyGrant_A	563350110	2619978	0	0
ReqAndReadyImplyGrant_A	563350110	2619978	0	0
ReqImpliesValid_A	563350110	2619978	0	0
ReqStaysHighUntilGranted0_M	563350110	0	0	0
RoundRobin_A	563350110	5	0	939
ValidKnown_A	563350110	563265295	0	0
gen_data_port_assertion.DataFlow_A	563350110	2619978	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	563265295	0	0
T1	1405	1317	0	0
T2	75658	75579	0	0
T3	670150	670084	0	0
T4	168806	168799	0	0
T5	86010	85950	0	0
T6	641971	641914	0	0
T7	633748	633694	0	0
T8	1331	1269	0	0
T9	245284	245225	0	0
T10	504120	504082	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	2619978	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	168806	16291	0	0
T5	86010	832	0	0
T6	641971	0	0	0
T7	633748	2115	0	0
T8	1331	0	0	0
T9	245284	0	0	0
T10	504120	35976	0	0
T11	52621	832	0	0
T12	0	832	0	0
T13	0	10230	0	0
T16	0	3754	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	2619978	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	168806	16291	0	0
T5	86010	832	0	0
T6	641971	0	0	0
T7	633748	2115	0	0
T8	1331	0	0	0
T9	245284	0	0	0
T10	504120	35976	0	0
T11	52621	832	0	0
T12	0	832	0	0
T13	0	10230	0	0
T16	0	3754	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	563265295	0	0
T1	1405	1317	0	0
T2	75658	75579	0	0
T3	670150	670084	0	0
T4	168806	168799	0	0
T5	86010	85950	0	0
T6	641971	641914	0	0
T7	633748	633694	0	0
T8	1331	1269	0	0
T9	245284	245225	0	0
T10	504120	504082	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	563265295	0	0
T1	1405	1317	0	0
T2	75658	75579	0	0
T3	670150	670084	0	0
T4	168806	168799	0	0
T5	86010	85950	0	0
T6	641971	641914	0	0
T7	633748	633694	0	0
T8	1331	1269	0	0
T9	245284	245225	0	0
T10	504120	504082	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	2619978	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	168806	16291	0	0
T5	86010	832	0	0
T6	641971	0	0	0
T7	633748	2115	0	0
T8	1331	0	0	0
T9	245284	0	0	0
T10	504120	35976	0	0
T11	52621	832	0	0
T12	0	832	0	0
T13	0	10230	0	0
T16	0	3754	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	2619978	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	168806	16291	0	0
T5	86010	832	0	0
T6	641971	0	0	0
T7	633748	2115	0	0
T8	1331	0	0	0
T9	245284	0	0	0
T10	504120	35976	0	0
T11	52621	832	0	0
T12	0	832	0	0
T13	0	10230	0	0
T16	0	3754	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	2619978	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	168806	16291	0	0
T5	86010	832	0	0
T6	641971	0	0	0
T7	633748	2115	0	0
T8	1331	0	0	0
T9	245284	0	0	0
T10	504120	35976	0	0
T11	52621	832	0	0
T12	0	832	0	0
T13	0	10230	0	0
T16	0	3754	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	2619978	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	168806	16291	0	0
T5	86010	832	0	0
T6	641971	0	0	0
T7	633748	2115	0	0
T8	1331	0	0	0
T9	245284	0	0	0
T10	504120	35976	0	0
T11	52621	832	0	0
T12	0	832	0	0
T13	0	10230	0	0
T16	0	3754	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	5	0	939
T20	106636	1	0	1
T22	0	1	0	0
T38	140470	0	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	10451	0	0	1
T52	20678	0	0	1
T53	95237	0	0	1
T54	116086	0	0	1
T55	3638	0	0	1
T56	1695	0	0	1
T57	46673	0	0	1
T58	1578	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	563265295	0	0
T1	1405	1317	0	0
T2	75658	75579	0	0
T3	670150	670084	0	0
T4	168806	168799	0	0
T5	86010	85950	0	0
T6	641971	641914	0	0
T7	633748	633694	0	0
T8	1331	1269	0	0
T9	245284	245225	0	0
T10	504120	504082	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	2619978	0	0
T2	75658	1600	0	0
T3	670150	832	0	0
T4	168806	16291	0	0
T5	86010	832	0	0
T6	641971	0	0	0
T7	633748	2115	0	0
T8	1331	0	0	0
T9	245284	0	0	0
T10	504120	35976	0	0
T11	52621	832	0	0
T12	0	832	0	0
T13	0	10230	0	0
T16	0	3754	0	0