Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
3671 |
0 |
0 |
T85 |
11168 |
2 |
0 |
0 |
T86 |
3351 |
12 |
0 |
0 |
T87 |
5733 |
41 |
0 |
0 |
T88 |
15706 |
215 |
0 |
0 |
T89 |
19537 |
2 |
0 |
0 |
T91 |
8457 |
6 |
0 |
0 |
T92 |
2755 |
130 |
0 |
0 |
T98 |
10208 |
262 |
0 |
0 |
T106 |
9261 |
6 |
0 |
0 |
T107 |
5729 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1646 |
0 |
0 |
T100 |
11290 |
17 |
0 |
0 |
T106 |
9261 |
20 |
0 |
0 |
T107 |
5729 |
1 |
0 |
0 |
T119 |
9648 |
3 |
0 |
0 |
T131 |
7821 |
41 |
0 |
0 |
T132 |
21613 |
76 |
0 |
0 |
T133 |
14379 |
68 |
0 |
0 |
T134 |
20898 |
59 |
0 |
0 |
T135 |
105481 |
122 |
0 |
0 |
T136 |
70386 |
93 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1545 |
0 |
0 |
T100 |
11290 |
10 |
0 |
0 |
T106 |
9261 |
12 |
0 |
0 |
T107 |
5729 |
5 |
0 |
0 |
T119 |
9648 |
9 |
0 |
0 |
T131 |
7821 |
30 |
0 |
0 |
T132 |
21613 |
35 |
0 |
0 |
T133 |
14379 |
56 |
0 |
0 |
T134 |
20898 |
74 |
0 |
0 |
T135 |
105481 |
107 |
0 |
0 |
T136 |
70386 |
69 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
2031 |
0 |
0 |
T100 |
11290 |
32 |
0 |
0 |
T106 |
9261 |
8 |
0 |
0 |
T119 |
9648 |
16 |
0 |
0 |
T131 |
7821 |
13 |
0 |
0 |
T132 |
21613 |
32 |
0 |
0 |
T133 |
14379 |
53 |
0 |
0 |
T134 |
20898 |
104 |
0 |
0 |
T135 |
105481 |
279 |
0 |
0 |
T136 |
70386 |
108 |
0 |
0 |
T137 |
100808 |
185 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
8921 |
0 |
0 |
T100 |
11290 |
110 |
0 |
0 |
T106 |
9261 |
118 |
0 |
0 |
T107 |
5729 |
1 |
0 |
0 |
T119 |
9648 |
50 |
0 |
0 |
T131 |
7821 |
50 |
0 |
0 |
T132 |
21613 |
79 |
0 |
0 |
T133 |
14379 |
37 |
0 |
0 |
T134 |
20898 |
51 |
0 |
0 |
T135 |
105481 |
1120 |
0 |
0 |
T136 |
70386 |
1243 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
10686 |
0 |
0 |
T100 |
11290 |
219 |
0 |
0 |
T106 |
9261 |
259 |
0 |
0 |
T107 |
5729 |
10 |
0 |
0 |
T119 |
9648 |
50 |
0 |
0 |
T131 |
7821 |
26 |
0 |
0 |
T132 |
21613 |
121 |
0 |
0 |
T133 |
14379 |
27 |
0 |
0 |
T134 |
20898 |
95 |
0 |
0 |
T135 |
105481 |
1854 |
0 |
0 |
T136 |
70386 |
1326 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
10075 |
0 |
0 |
T100 |
11290 |
117 |
0 |
0 |
T106 |
9261 |
14 |
0 |
0 |
T107 |
5729 |
110 |
0 |
0 |
T119 |
9648 |
104 |
0 |
0 |
T131 |
7821 |
26 |
0 |
0 |
T132 |
21613 |
67 |
0 |
0 |
T133 |
14379 |
46 |
0 |
0 |
T134 |
20898 |
77 |
0 |
0 |
T135 |
105481 |
1956 |
0 |
0 |
T136 |
70386 |
969 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
9755 |
0 |
0 |
T100 |
11290 |
131 |
0 |
0 |
T106 |
9261 |
112 |
0 |
0 |
T107 |
5729 |
33 |
0 |
0 |
T119 |
9648 |
9 |
0 |
0 |
T131 |
7821 |
29 |
0 |
0 |
T132 |
21613 |
91 |
0 |
0 |
T133 |
14379 |
45 |
0 |
0 |
T134 |
20898 |
33 |
0 |
0 |
T135 |
105481 |
1912 |
0 |
0 |
T136 |
70386 |
1446 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
10477 |
0 |
0 |
T100 |
11290 |
225 |
0 |
0 |
T106 |
9261 |
14 |
0 |
0 |
T107 |
5729 |
63 |
0 |
0 |
T119 |
9648 |
103 |
0 |
0 |
T131 |
7821 |
15 |
0 |
0 |
T132 |
21613 |
40 |
0 |
0 |
T133 |
14379 |
22 |
0 |
0 |
T134 |
20898 |
99 |
0 |
0 |
T135 |
105481 |
1984 |
0 |
0 |
T136 |
70386 |
1476 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
9648 |
0 |
0 |
T88 |
15706 |
4 |
0 |
0 |
T100 |
11290 |
16 |
0 |
0 |
T106 |
9261 |
23 |
0 |
0 |
T107 |
5729 |
73 |
0 |
0 |
T131 |
7821 |
22 |
0 |
0 |
T132 |
21613 |
73 |
0 |
0 |
T133 |
14379 |
49 |
0 |
0 |
T134 |
20898 |
48 |
0 |
0 |
T135 |
105481 |
1976 |
0 |
0 |
T136 |
70386 |
1170 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
9070 |
0 |
0 |
T100 |
11290 |
144 |
0 |
0 |
T106 |
9261 |
137 |
0 |
0 |
T107 |
5729 |
1 |
0 |
0 |
T119 |
9648 |
145 |
0 |
0 |
T131 |
7821 |
29 |
0 |
0 |
T132 |
21613 |
68 |
0 |
0 |
T133 |
14379 |
34 |
0 |
0 |
T134 |
20898 |
81 |
0 |
0 |
T135 |
105481 |
1594 |
0 |
0 |
T136 |
70386 |
895 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
9218 |
0 |
0 |
T100 |
11290 |
145 |
0 |
0 |
T106 |
9261 |
163 |
0 |
0 |
T119 |
9648 |
55 |
0 |
0 |
T131 |
7821 |
25 |
0 |
0 |
T132 |
21613 |
38 |
0 |
0 |
T133 |
14379 |
21 |
0 |
0 |
T134 |
20898 |
46 |
0 |
0 |
T135 |
105481 |
1692 |
0 |
0 |
T136 |
70386 |
1134 |
0 |
0 |
T137 |
100808 |
2164 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4464 |
0 |
0 |
T100 |
11290 |
83 |
0 |
0 |
T106 |
9261 |
62 |
0 |
0 |
T107 |
5729 |
5 |
0 |
0 |
T119 |
9648 |
17 |
0 |
0 |
T131 |
7821 |
16 |
0 |
0 |
T132 |
21613 |
50 |
0 |
0 |
T133 |
14379 |
47 |
0 |
0 |
T134 |
20898 |
63 |
0 |
0 |
T135 |
105481 |
855 |
0 |
0 |
T136 |
70386 |
437 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4613 |
0 |
0 |
T100 |
11290 |
23 |
0 |
0 |
T106 |
9261 |
71 |
0 |
0 |
T119 |
9648 |
35 |
0 |
0 |
T131 |
7821 |
12 |
0 |
0 |
T132 |
21613 |
101 |
0 |
0 |
T133 |
14379 |
27 |
0 |
0 |
T134 |
20898 |
76 |
0 |
0 |
T135 |
105481 |
606 |
0 |
0 |
T136 |
70386 |
556 |
0 |
0 |
T137 |
100808 |
790 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4693 |
0 |
0 |
T100 |
11290 |
104 |
0 |
0 |
T106 |
9261 |
14 |
0 |
0 |
T107 |
5729 |
12 |
0 |
0 |
T119 |
9648 |
30 |
0 |
0 |
T131 |
7821 |
14 |
0 |
0 |
T132 |
21613 |
43 |
0 |
0 |
T133 |
14379 |
52 |
0 |
0 |
T134 |
20898 |
108 |
0 |
0 |
T135 |
105481 |
785 |
0 |
0 |
T136 |
70386 |
419 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
5046 |
0 |
0 |
T100 |
11290 |
48 |
0 |
0 |
T106 |
9261 |
111 |
0 |
0 |
T107 |
5729 |
50 |
0 |
0 |
T119 |
9648 |
77 |
0 |
0 |
T131 |
7821 |
31 |
0 |
0 |
T132 |
21613 |
70 |
0 |
0 |
T133 |
14379 |
22 |
0 |
0 |
T134 |
20898 |
98 |
0 |
0 |
T135 |
105481 |
773 |
0 |
0 |
T136 |
70386 |
523 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4759 |
0 |
0 |
T100 |
11290 |
10 |
0 |
0 |
T106 |
9261 |
83 |
0 |
0 |
T107 |
5729 |
20 |
0 |
0 |
T119 |
9648 |
46 |
0 |
0 |
T132 |
21613 |
74 |
0 |
0 |
T133 |
14379 |
17 |
0 |
0 |
T134 |
20898 |
50 |
0 |
0 |
T135 |
105481 |
675 |
0 |
0 |
T136 |
70386 |
706 |
0 |
0 |
T137 |
100808 |
691 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
5158 |
0 |
0 |
T100 |
11290 |
111 |
0 |
0 |
T106 |
9261 |
76 |
0 |
0 |
T107 |
5729 |
37 |
0 |
0 |
T119 |
9648 |
15 |
0 |
0 |
T131 |
7821 |
5 |
0 |
0 |
T132 |
21613 |
64 |
0 |
0 |
T133 |
14379 |
61 |
0 |
0 |
T134 |
20898 |
103 |
0 |
0 |
T135 |
105481 |
557 |
0 |
0 |
T136 |
70386 |
477 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4751 |
0 |
0 |
T100 |
11290 |
123 |
0 |
0 |
T106 |
9261 |
12 |
0 |
0 |
T107 |
5729 |
9 |
0 |
0 |
T119 |
9648 |
94 |
0 |
0 |
T131 |
7821 |
36 |
0 |
0 |
T132 |
21613 |
65 |
0 |
0 |
T133 |
14379 |
76 |
0 |
0 |
T134 |
20898 |
75 |
0 |
0 |
T135 |
105481 |
754 |
0 |
0 |
T136 |
70386 |
625 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4549 |
0 |
0 |
T100 |
11290 |
120 |
0 |
0 |
T106 |
9261 |
59 |
0 |
0 |
T107 |
5729 |
20 |
0 |
0 |
T119 |
9648 |
70 |
0 |
0 |
T131 |
7821 |
1 |
0 |
0 |
T132 |
21613 |
55 |
0 |
0 |
T133 |
14379 |
47 |
0 |
0 |
T134 |
20898 |
86 |
0 |
0 |
T135 |
105481 |
557 |
0 |
0 |
T136 |
70386 |
461 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4842 |
0 |
0 |
T100 |
11290 |
117 |
0 |
0 |
T106 |
9261 |
20 |
0 |
0 |
T119 |
9648 |
81 |
0 |
0 |
T131 |
7821 |
7 |
0 |
0 |
T132 |
21613 |
85 |
0 |
0 |
T133 |
14379 |
50 |
0 |
0 |
T134 |
20898 |
113 |
0 |
0 |
T135 |
105481 |
721 |
0 |
0 |
T136 |
70386 |
604 |
0 |
0 |
T137 |
100808 |
866 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
5561 |
0 |
0 |
T100 |
11290 |
45 |
0 |
0 |
T106 |
9261 |
74 |
0 |
0 |
T107 |
5729 |
37 |
0 |
0 |
T119 |
9648 |
22 |
0 |
0 |
T131 |
7821 |
18 |
0 |
0 |
T132 |
21613 |
140 |
0 |
0 |
T133 |
14379 |
55 |
0 |
0 |
T134 |
20898 |
64 |
0 |
0 |
T135 |
105481 |
942 |
0 |
0 |
T136 |
70386 |
512 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4678 |
0 |
0 |
T100 |
11290 |
89 |
0 |
0 |
T106 |
9261 |
51 |
0 |
0 |
T107 |
5729 |
37 |
0 |
0 |
T119 |
9648 |
79 |
0 |
0 |
T131 |
7821 |
49 |
0 |
0 |
T132 |
21613 |
76 |
0 |
0 |
T133 |
14379 |
34 |
0 |
0 |
T134 |
20898 |
47 |
0 |
0 |
T135 |
105481 |
881 |
0 |
0 |
T136 |
70386 |
566 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
5006 |
0 |
0 |
T100 |
11290 |
9 |
0 |
0 |
T106 |
9261 |
62 |
0 |
0 |
T107 |
5729 |
5 |
0 |
0 |
T119 |
9648 |
49 |
0 |
0 |
T131 |
7821 |
9 |
0 |
0 |
T132 |
21613 |
58 |
0 |
0 |
T133 |
14379 |
40 |
0 |
0 |
T134 |
20898 |
57 |
0 |
0 |
T135 |
105481 |
852 |
0 |
0 |
T136 |
70386 |
557 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4979 |
0 |
0 |
T100 |
11290 |
9 |
0 |
0 |
T106 |
9261 |
72 |
0 |
0 |
T107 |
5729 |
17 |
0 |
0 |
T119 |
9648 |
27 |
0 |
0 |
T131 |
7821 |
2 |
0 |
0 |
T132 |
21613 |
69 |
0 |
0 |
T133 |
14379 |
30 |
0 |
0 |
T134 |
20898 |
59 |
0 |
0 |
T135 |
105481 |
940 |
0 |
0 |
T136 |
70386 |
599 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4411 |
0 |
0 |
T100 |
11290 |
102 |
0 |
0 |
T106 |
9261 |
75 |
0 |
0 |
T107 |
5729 |
6 |
0 |
0 |
T119 |
9648 |
35 |
0 |
0 |
T131 |
7821 |
10 |
0 |
0 |
T132 |
21613 |
61 |
0 |
0 |
T133 |
14379 |
10 |
0 |
0 |
T134 |
20898 |
60 |
0 |
0 |
T135 |
105481 |
632 |
0 |
0 |
T136 |
70386 |
376 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4983 |
0 |
0 |
T100 |
11290 |
64 |
0 |
0 |
T106 |
9261 |
56 |
0 |
0 |
T119 |
9648 |
28 |
0 |
0 |
T131 |
7821 |
16 |
0 |
0 |
T132 |
21613 |
79 |
0 |
0 |
T133 |
14379 |
39 |
0 |
0 |
T134 |
20898 |
128 |
0 |
0 |
T135 |
105481 |
787 |
0 |
0 |
T136 |
70386 |
586 |
0 |
0 |
T137 |
100808 |
938 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
5492 |
0 |
0 |
T100 |
11290 |
116 |
0 |
0 |
T106 |
9261 |
78 |
0 |
0 |
T107 |
5729 |
25 |
0 |
0 |
T119 |
9648 |
62 |
0 |
0 |
T131 |
7821 |
26 |
0 |
0 |
T132 |
21613 |
64 |
0 |
0 |
T133 |
14379 |
29 |
0 |
0 |
T134 |
20898 |
102 |
0 |
0 |
T135 |
105481 |
817 |
0 |
0 |
T136 |
70386 |
503 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4786 |
0 |
0 |
T100 |
11290 |
84 |
0 |
0 |
T106 |
9261 |
13 |
0 |
0 |
T107 |
5729 |
28 |
0 |
0 |
T119 |
9648 |
70 |
0 |
0 |
T131 |
7821 |
18 |
0 |
0 |
T132 |
21613 |
69 |
0 |
0 |
T133 |
14379 |
44 |
0 |
0 |
T134 |
20898 |
85 |
0 |
0 |
T135 |
105481 |
720 |
0 |
0 |
T136 |
70386 |
701 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4969 |
0 |
0 |
T100 |
11290 |
62 |
0 |
0 |
T106 |
9261 |
68 |
0 |
0 |
T107 |
5729 |
2 |
0 |
0 |
T119 |
9648 |
88 |
0 |
0 |
T131 |
7821 |
31 |
0 |
0 |
T132 |
21613 |
68 |
0 |
0 |
T133 |
14379 |
38 |
0 |
0 |
T134 |
20898 |
69 |
0 |
0 |
T135 |
105481 |
787 |
0 |
0 |
T136 |
70386 |
407 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
5244 |
0 |
0 |
T100 |
11290 |
6 |
0 |
0 |
T106 |
9261 |
27 |
0 |
0 |
T107 |
5729 |
7 |
0 |
0 |
T119 |
9648 |
105 |
0 |
0 |
T131 |
7821 |
39 |
0 |
0 |
T132 |
21613 |
106 |
0 |
0 |
T133 |
14379 |
17 |
0 |
0 |
T134 |
20898 |
95 |
0 |
0 |
T135 |
105481 |
909 |
0 |
0 |
T136 |
70386 |
546 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4436 |
0 |
0 |
T100 |
11290 |
42 |
0 |
0 |
T106 |
9261 |
79 |
0 |
0 |
T107 |
5729 |
33 |
0 |
0 |
T119 |
9648 |
5 |
0 |
0 |
T131 |
7821 |
51 |
0 |
0 |
T132 |
21613 |
23 |
0 |
0 |
T133 |
14379 |
41 |
0 |
0 |
T134 |
20898 |
50 |
0 |
0 |
T135 |
105481 |
888 |
0 |
0 |
T136 |
70386 |
555 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4933 |
0 |
0 |
T100 |
11290 |
66 |
0 |
0 |
T106 |
9261 |
3 |
0 |
0 |
T107 |
5729 |
37 |
0 |
0 |
T119 |
9648 |
48 |
0 |
0 |
T131 |
7821 |
22 |
0 |
0 |
T132 |
21613 |
54 |
0 |
0 |
T133 |
14379 |
2 |
0 |
0 |
T134 |
20898 |
113 |
0 |
0 |
T135 |
105481 |
895 |
0 |
0 |
T136 |
70386 |
438 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4865 |
0 |
0 |
T100 |
11290 |
17 |
0 |
0 |
T106 |
9261 |
75 |
0 |
0 |
T107 |
5729 |
5 |
0 |
0 |
T119 |
9648 |
35 |
0 |
0 |
T131 |
7821 |
24 |
0 |
0 |
T132 |
21613 |
64 |
0 |
0 |
T133 |
14379 |
34 |
0 |
0 |
T134 |
20898 |
52 |
0 |
0 |
T135 |
105481 |
868 |
0 |
0 |
T136 |
70386 |
597 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4615 |
0 |
0 |
T100 |
11290 |
47 |
0 |
0 |
T106 |
9261 |
108 |
0 |
0 |
T107 |
5729 |
3 |
0 |
0 |
T119 |
9648 |
85 |
0 |
0 |
T131 |
7821 |
44 |
0 |
0 |
T132 |
21613 |
71 |
0 |
0 |
T133 |
14379 |
67 |
0 |
0 |
T134 |
20898 |
53 |
0 |
0 |
T135 |
105481 |
813 |
0 |
0 |
T136 |
70386 |
404 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4748 |
0 |
0 |
T100 |
11290 |
88 |
0 |
0 |
T106 |
9261 |
16 |
0 |
0 |
T107 |
5729 |
31 |
0 |
0 |
T119 |
9648 |
55 |
0 |
0 |
T131 |
7821 |
8 |
0 |
0 |
T132 |
21613 |
76 |
0 |
0 |
T133 |
14379 |
31 |
0 |
0 |
T134 |
20898 |
45 |
0 |
0 |
T135 |
105481 |
726 |
0 |
0 |
T136 |
70386 |
638 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1977 |
0 |
0 |
T100 |
11290 |
28 |
0 |
0 |
T106 |
9261 |
24 |
0 |
0 |
T107 |
5729 |
5 |
0 |
0 |
T119 |
9648 |
19 |
0 |
0 |
T131 |
7821 |
21 |
0 |
0 |
T132 |
21613 |
143 |
0 |
0 |
T133 |
14379 |
42 |
0 |
0 |
T134 |
20898 |
51 |
0 |
0 |
T135 |
105481 |
137 |
0 |
0 |
T136 |
70386 |
139 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1781 |
0 |
0 |
T100 |
11290 |
29 |
0 |
0 |
T106 |
9261 |
19 |
0 |
0 |
T107 |
5729 |
8 |
0 |
0 |
T119 |
9648 |
21 |
0 |
0 |
T131 |
7821 |
16 |
0 |
0 |
T132 |
21613 |
107 |
0 |
0 |
T133 |
14379 |
31 |
0 |
0 |
T134 |
20898 |
53 |
0 |
0 |
T135 |
105481 |
159 |
0 |
0 |
T136 |
70386 |
110 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1842 |
0 |
0 |
T100 |
11290 |
17 |
0 |
0 |
T106 |
9261 |
21 |
0 |
0 |
T107 |
5729 |
3 |
0 |
0 |
T119 |
9648 |
9 |
0 |
0 |
T131 |
7821 |
12 |
0 |
0 |
T132 |
21613 |
37 |
0 |
0 |
T133 |
14379 |
39 |
0 |
0 |
T134 |
20898 |
81 |
0 |
0 |
T135 |
105481 |
174 |
0 |
0 |
T136 |
70386 |
94 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1830 |
0 |
0 |
T100 |
11290 |
28 |
0 |
0 |
T106 |
9261 |
16 |
0 |
0 |
T107 |
5729 |
4 |
0 |
0 |
T119 |
9648 |
6 |
0 |
0 |
T131 |
7821 |
18 |
0 |
0 |
T132 |
21613 |
64 |
0 |
0 |
T133 |
14379 |
50 |
0 |
0 |
T134 |
20898 |
102 |
0 |
0 |
T135 |
105481 |
184 |
0 |
0 |
T136 |
70386 |
110 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
2368 |
0 |
0 |
T88 |
15706 |
4 |
0 |
0 |
T100 |
11290 |
13 |
0 |
0 |
T106 |
9261 |
32 |
0 |
0 |
T107 |
5729 |
4 |
0 |
0 |
T131 |
7821 |
14 |
0 |
0 |
T132 |
21613 |
35 |
0 |
0 |
T133 |
14379 |
42 |
0 |
0 |
T134 |
20898 |
93 |
0 |
0 |
T135 |
105481 |
235 |
0 |
0 |
T136 |
70386 |
165 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
4145 |
0 |
0 |
T27 |
425867 |
17 |
0 |
0 |
T31 |
668230 |
0 |
0 |
0 |
T32 |
123751 |
0 |
0 |
0 |
T33 |
333093 |
0 |
0 |
0 |
T40 |
17446 |
0 |
0 |
0 |
T41 |
49902 |
0 |
0 |
0 |
T42 |
103481 |
0 |
0 |
0 |
T43 |
14986 |
0 |
0 |
0 |
T138 |
0 |
10 |
0 |
0 |
T139 |
0 |
25 |
0 |
0 |
T140 |
0 |
30 |
0 |
0 |
T141 |
0 |
15 |
0 |
0 |
T142 |
0 |
14 |
0 |
0 |
T143 |
0 |
22 |
0 |
0 |
T144 |
0 |
21 |
0 |
0 |
T145 |
0 |
54 |
0 |
0 |
T146 |
0 |
38 |
0 |
0 |
T147 |
929 |
0 |
0 |
0 |
T148 |
1723 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1788 |
0 |
0 |
T100 |
11290 |
13 |
0 |
0 |
T106 |
9261 |
26 |
0 |
0 |
T107 |
5729 |
5 |
0 |
0 |
T119 |
9648 |
8 |
0 |
0 |
T131 |
7821 |
14 |
0 |
0 |
T132 |
21613 |
31 |
0 |
0 |
T133 |
14379 |
37 |
0 |
0 |
T134 |
20898 |
80 |
0 |
0 |
T135 |
105481 |
175 |
0 |
0 |
T136 |
70386 |
129 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1885 |
0 |
0 |
T100 |
11290 |
16 |
0 |
0 |
T106 |
9261 |
22 |
0 |
0 |
T119 |
9648 |
4 |
0 |
0 |
T131 |
7821 |
51 |
0 |
0 |
T132 |
21613 |
62 |
0 |
0 |
T133 |
14379 |
43 |
0 |
0 |
T134 |
20898 |
57 |
0 |
0 |
T135 |
105481 |
191 |
0 |
0 |
T136 |
70386 |
111 |
0 |
0 |
T137 |
100808 |
184 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1605 |
0 |
0 |
T100 |
11290 |
25 |
0 |
0 |
T106 |
9261 |
15 |
0 |
0 |
T119 |
9648 |
8 |
0 |
0 |
T131 |
7821 |
38 |
0 |
0 |
T132 |
21613 |
93 |
0 |
0 |
T133 |
14379 |
43 |
0 |
0 |
T134 |
20898 |
66 |
0 |
0 |
T135 |
105481 |
96 |
0 |
0 |
T136 |
70386 |
77 |
0 |
0 |
T137 |
100808 |
123 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1599 |
0 |
0 |
T100 |
11290 |
23 |
0 |
0 |
T106 |
9261 |
14 |
0 |
0 |
T119 |
9648 |
2 |
0 |
0 |
T131 |
7821 |
41 |
0 |
0 |
T132 |
21613 |
33 |
0 |
0 |
T133 |
14379 |
55 |
0 |
0 |
T134 |
20898 |
122 |
0 |
0 |
T135 |
105481 |
119 |
0 |
0 |
T136 |
70386 |
103 |
0 |
0 |
T137 |
100808 |
99 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1570 |
0 |
0 |
T94 |
11091 |
12 |
0 |
0 |
T100 |
11290 |
24 |
0 |
0 |
T106 |
9261 |
17 |
0 |
0 |
T119 |
9648 |
8 |
0 |
0 |
T131 |
7821 |
13 |
0 |
0 |
T132 |
21613 |
97 |
0 |
0 |
T133 |
14379 |
59 |
0 |
0 |
T134 |
20898 |
48 |
0 |
0 |
T135 |
105481 |
104 |
0 |
0 |
T136 |
70386 |
94 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1574 |
0 |
0 |
T100 |
11290 |
20 |
0 |
0 |
T106 |
9261 |
10 |
0 |
0 |
T107 |
5729 |
3 |
0 |
0 |
T119 |
9648 |
10 |
0 |
0 |
T131 |
7821 |
9 |
0 |
0 |
T132 |
21613 |
100 |
0 |
0 |
T133 |
14379 |
32 |
0 |
0 |
T134 |
20898 |
91 |
0 |
0 |
T135 |
105481 |
101 |
0 |
0 |
T136 |
70386 |
69 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
2595 |
0 |
0 |
T100 |
11290 |
18 |
0 |
0 |
T106 |
9261 |
6 |
0 |
0 |
T107 |
5729 |
19 |
0 |
0 |
T119 |
9648 |
28 |
0 |
0 |
T131 |
7821 |
42 |
0 |
0 |
T132 |
21613 |
106 |
0 |
0 |
T133 |
14379 |
43 |
0 |
0 |
T134 |
20898 |
121 |
0 |
0 |
T135 |
105481 |
275 |
0 |
0 |
T136 |
70386 |
184 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1693 |
0 |
0 |
T100 |
11290 |
17 |
0 |
0 |
T106 |
9261 |
20 |
0 |
0 |
T107 |
5729 |
3 |
0 |
0 |
T119 |
9648 |
6 |
0 |
0 |
T131 |
7821 |
36 |
0 |
0 |
T132 |
21613 |
47 |
0 |
0 |
T133 |
14379 |
71 |
0 |
0 |
T134 |
20898 |
115 |
0 |
0 |
T135 |
105481 |
109 |
0 |
0 |
T136 |
70386 |
114 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
2811 |
0 |
0 |
T100 |
11290 |
27 |
0 |
0 |
T106 |
9261 |
38 |
0 |
0 |
T107 |
5729 |
14 |
0 |
0 |
T119 |
9648 |
27 |
0 |
0 |
T131 |
7821 |
17 |
0 |
0 |
T132 |
21613 |
78 |
0 |
0 |
T133 |
14379 |
37 |
0 |
0 |
T134 |
20898 |
36 |
0 |
0 |
T135 |
105481 |
431 |
0 |
0 |
T136 |
70386 |
219 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1771 |
0 |
0 |
T100 |
11290 |
18 |
0 |
0 |
T106 |
9261 |
16 |
0 |
0 |
T107 |
5729 |
16 |
0 |
0 |
T119 |
9648 |
7 |
0 |
0 |
T131 |
7821 |
12 |
0 |
0 |
T132 |
21613 |
50 |
0 |
0 |
T133 |
14379 |
54 |
0 |
0 |
T134 |
20898 |
55 |
0 |
0 |
T135 |
105481 |
159 |
0 |
0 |
T136 |
70386 |
119 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1699 |
0 |
0 |
T100 |
11290 |
20 |
0 |
0 |
T106 |
9261 |
17 |
0 |
0 |
T119 |
9648 |
1 |
0 |
0 |
T131 |
7821 |
44 |
0 |
0 |
T132 |
21613 |
117 |
0 |
0 |
T133 |
14379 |
62 |
0 |
0 |
T134 |
20898 |
125 |
0 |
0 |
T135 |
105481 |
108 |
0 |
0 |
T136 |
70386 |
68 |
0 |
0 |
T137 |
100808 |
92 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1638 |
0 |
0 |
T100 |
11290 |
13 |
0 |
0 |
T106 |
9261 |
13 |
0 |
0 |
T107 |
5729 |
4 |
0 |
0 |
T119 |
9648 |
3 |
0 |
0 |
T131 |
7821 |
31 |
0 |
0 |
T132 |
21613 |
34 |
0 |
0 |
T133 |
14379 |
72 |
0 |
0 |
T134 |
20898 |
87 |
0 |
0 |
T135 |
105481 |
128 |
0 |
0 |
T136 |
70386 |
80 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1557 |
0 |
0 |
T100 |
11290 |
19 |
0 |
0 |
T106 |
9261 |
13 |
0 |
0 |
T107 |
5729 |
12 |
0 |
0 |
T119 |
9648 |
3 |
0 |
0 |
T131 |
7821 |
5 |
0 |
0 |
T132 |
21613 |
59 |
0 |
0 |
T133 |
14379 |
58 |
0 |
0 |
T134 |
20898 |
33 |
0 |
0 |
T135 |
105481 |
121 |
0 |
0 |
T136 |
70386 |
52 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1627 |
0 |
0 |
T100 |
11290 |
1 |
0 |
0 |
T106 |
9261 |
16 |
0 |
0 |
T107 |
5729 |
7 |
0 |
0 |
T119 |
9648 |
4 |
0 |
0 |
T131 |
7821 |
20 |
0 |
0 |
T132 |
21613 |
68 |
0 |
0 |
T133 |
14379 |
78 |
0 |
0 |
T134 |
20898 |
62 |
0 |
0 |
T135 |
105481 |
135 |
0 |
0 |
T136 |
70386 |
73 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1658 |
0 |
0 |
T88 |
15706 |
8 |
0 |
0 |
T100 |
11290 |
14 |
0 |
0 |
T106 |
9261 |
17 |
0 |
0 |
T107 |
5729 |
1 |
0 |
0 |
T131 |
7821 |
44 |
0 |
0 |
T132 |
21613 |
59 |
0 |
0 |
T133 |
14379 |
39 |
0 |
0 |
T134 |
20898 |
63 |
0 |
0 |
T135 |
105481 |
112 |
0 |
0 |
T136 |
70386 |
85 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565489795 |
1594 |
0 |
0 |
T100 |
11290 |
17 |
0 |
0 |
T106 |
9261 |
15 |
0 |
0 |
T107 |
5729 |
2 |
0 |
0 |
T119 |
9648 |
5 |
0 |
0 |
T131 |
7821 |
16 |
0 |
0 |
T132 |
21613 |
49 |
0 |
0 |
T133 |
14379 |
60 |
0 |
0 |
T134 |
20898 |
82 |
0 |
0 |
T135 |
105481 |
113 |
0 |
0 |
T136 |
70386 |
87 |
0 |
0 |