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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 98.38 94.43 98.61 89.36 97.08 95.82 98.22


Total test records in report: 1114
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T1024 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1505597766 Feb 29 01:00:33 PM PST 24 Feb 29 01:00:33 PM PST 24 24411163 ps
T1025 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1999668065 Feb 29 01:00:15 PM PST 24 Feb 29 01:00:33 PM PST 24 2524816123 ps
T154 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1165079293 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:37 PM PST 24 647800531 ps
T1026 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2853521768 Feb 29 01:00:36 PM PST 24 Feb 29 01:00:36 PM PST 24 14717909 ps
T155 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.491031794 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:54 PM PST 24 4042614808 ps
T1027 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.606932182 Feb 29 01:00:25 PM PST 24 Feb 29 01:00:29 PM PST 24 49883375 ps
T156 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4234582653 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:46 PM PST 24 3368555396 ps
T118 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.278790373 Feb 29 01:00:15 PM PST 24 Feb 29 01:00:18 PM PST 24 69944137 ps
T1028 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2095773986 Feb 29 01:00:13 PM PST 24 Feb 29 01:00:14 PM PST 24 20053798 ps
T94 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1120117837 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:35 PM PST 24 462237864 ps
T136 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2275979970 Feb 29 01:00:34 PM PST 24 Feb 29 01:00:50 PM PST 24 3199450974 ps
T1029 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3001683356 Feb 29 01:00:35 PM PST 24 Feb 29 01:00:36 PM PST 24 16910390 ps
T1030 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1716683066 Feb 29 01:00:34 PM PST 24 Feb 29 01:00:34 PM PST 24 22341626 ps
T1031 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3694000930 Feb 29 01:00:33 PM PST 24 Feb 29 01:00:33 PM PST 24 15343675 ps
T1032 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3073501378 Feb 29 01:00:14 PM PST 24 Feb 29 01:00:15 PM PST 24 24330752 ps
T1033 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3235400062 Feb 29 01:00:28 PM PST 24 Feb 29 01:00:30 PM PST 24 24554038 ps
T1034 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2235494936 Feb 29 01:00:38 PM PST 24 Feb 29 01:00:39 PM PST 24 17914551 ps
T119 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2761947505 Feb 29 01:00:27 PM PST 24 Feb 29 01:00:30 PM PST 24 402111016 ps
T120 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1745732962 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:35 PM PST 24 140895540 ps
T1035 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1816284620 Feb 29 01:00:13 PM PST 24 Feb 29 01:00:29 PM PST 24 858549573 ps
T137 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2772101732 Feb 29 01:00:09 PM PST 24 Feb 29 01:00:32 PM PST 24 10081007975 ps
T121 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1890616330 Feb 29 01:00:16 PM PST 24 Feb 29 01:00:40 PM PST 24 360922632 ps
T99 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3116968377 Feb 29 01:00:33 PM PST 24 Feb 29 01:00:35 PM PST 24 136430937 ps
T1036 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3430661658 Feb 29 01:00:27 PM PST 24 Feb 29 01:00:28 PM PST 24 11433082 ps
T1037 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2749097519 Feb 29 01:00:21 PM PST 24 Feb 29 01:00:22 PM PST 24 87020093 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1103214898 Feb 29 01:00:27 PM PST 24 Feb 29 01:00:32 PM PST 24 317453465 ps
T1039 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3006888424 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:32 PM PST 24 40916550 ps
T1040 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3459099176 Feb 29 01:00:30 PM PST 24 Feb 29 01:00:32 PM PST 24 33679396 ps
T1041 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3609464528 Feb 29 01:00:14 PM PST 24 Feb 29 01:00:17 PM PST 24 321233126 ps
T122 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2294007179 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:34 PM PST 24 27271567 ps
T123 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.442640973 Feb 29 01:00:11 PM PST 24 Feb 29 01:00:13 PM PST 24 38211572 ps
T1042 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1694312160 Feb 29 01:00:29 PM PST 24 Feb 29 01:00:30 PM PST 24 33978881 ps
T1043 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2684551974 Feb 29 01:00:25 PM PST 24 Feb 29 01:00:27 PM PST 24 162422287 ps
T1044 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.927806158 Feb 29 01:00:09 PM PST 24 Feb 29 01:00:33 PM PST 24 370932345 ps
T1045 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1891287308 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:38 PM PST 24 202864097 ps
T1046 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3456780796 Feb 29 01:00:27 PM PST 24 Feb 29 01:00:30 PM PST 24 418041439 ps
T1047 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2907032671 Feb 29 01:00:35 PM PST 24 Feb 29 01:00:36 PM PST 24 15802277 ps
T1048 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2890863347 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:33 PM PST 24 100800803 ps
T101 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2020463281 Feb 29 01:00:14 PM PST 24 Feb 29 01:00:16 PM PST 24 147368160 ps
T81 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2927054041 Feb 29 01:00:11 PM PST 24 Feb 29 01:00:13 PM PST 24 87980676 ps
T1049 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3512209642 Feb 29 01:00:24 PM PST 24 Feb 29 01:00:27 PM PST 24 38914869 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1588582726 Feb 29 01:00:15 PM PST 24 Feb 29 01:00:30 PM PST 24 268610619 ps
T96 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.854683945 Feb 29 01:00:10 PM PST 24 Feb 29 01:00:11 PM PST 24 62305359 ps
T1051 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.280444810 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:33 PM PST 24 49442132 ps
T1052 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3629166112 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:33 PM PST 24 413769251 ps
T1053 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2168936240 Feb 29 01:00:27 PM PST 24 Feb 29 01:00:29 PM PST 24 52217659 ps
T1054 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1351789510 Feb 29 01:00:34 PM PST 24 Feb 29 01:00:34 PM PST 24 38402356 ps
T1055 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3825489429 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:33 PM PST 24 79255127 ps
T97 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2737234885 Feb 29 01:00:29 PM PST 24 Feb 29 01:00:34 PM PST 24 117256577 ps
T1056 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1657355251 Feb 29 01:00:11 PM PST 24 Feb 29 01:00:51 PM PST 24 2704966990 ps
T1057 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.291276974 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:34 PM PST 24 27211226 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.719395516 Feb 29 01:00:12 PM PST 24 Feb 29 01:00:14 PM PST 24 36075423 ps
T1059 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1439521222 Feb 29 01:00:26 PM PST 24 Feb 29 01:00:39 PM PST 24 1069816708 ps
T1060 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3967114258 Feb 29 01:00:34 PM PST 24 Feb 29 01:00:35 PM PST 24 13121366 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1673573736 Feb 29 01:00:11 PM PST 24 Feb 29 01:00:20 PM PST 24 325625194 ps
T1062 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3349915634 Feb 29 01:00:27 PM PST 24 Feb 29 01:00:30 PM PST 24 128420973 ps
T1063 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.902188962 Feb 29 01:00:12 PM PST 24 Feb 29 01:00:16 PM PST 24 1784347247 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1681863531 Feb 29 01:00:11 PM PST 24 Feb 29 01:00:15 PM PST 24 199469213 ps
T82 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2556534870 Feb 29 01:00:11 PM PST 24 Feb 29 01:00:12 PM PST 24 69225288 ps
T1065 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2554186862 Feb 29 01:00:28 PM PST 24 Feb 29 01:00:32 PM PST 24 293620551 ps
T1066 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.104159153 Feb 29 01:00:12 PM PST 24 Feb 29 01:00:13 PM PST 24 123986580 ps
T104 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2288064311 Feb 29 01:00:28 PM PST 24 Feb 29 01:00:30 PM PST 24 33729905 ps
T1067 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2156871927 Feb 29 01:00:28 PM PST 24 Feb 29 01:00:32 PM PST 24 201765957 ps
T1068 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2263957674 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:32 PM PST 24 37050250 ps
T160 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4070372966 Feb 29 01:00:29 PM PST 24 Feb 29 01:00:48 PM PST 24 1285898248 ps
T1069 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3316571462 Feb 29 01:00:36 PM PST 24 Feb 29 01:00:37 PM PST 24 19671189 ps
T103 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3614115674 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:33 PM PST 24 54798464 ps
T1070 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.243636746 Feb 29 01:00:36 PM PST 24 Feb 29 01:00:40 PM PST 24 629100519 ps
T1071 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.442652729 Feb 29 01:00:13 PM PST 24 Feb 29 01:00:16 PM PST 24 372107044 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1822943432 Feb 29 01:00:11 PM PST 24 Feb 29 01:00:34 PM PST 24 1456366306 ps
T1073 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2450436318 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:32 PM PST 24 13945973 ps
T1074 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4007292483 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:35 PM PST 24 76875332 ps
T1075 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1235780545 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:32 PM PST 24 150957058 ps
T1076 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3958213614 Feb 29 01:00:30 PM PST 24 Feb 29 01:00:32 PM PST 24 256427572 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.549412509 Feb 29 01:00:28 PM PST 24 Feb 29 01:00:30 PM PST 24 1300151672 ps
T1078 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1156000220 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:32 PM PST 24 32493714 ps
T1079 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3587059677 Feb 29 01:00:29 PM PST 24 Feb 29 01:00:47 PM PST 24 1056461133 ps
T1080 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2952818455 Feb 29 01:00:40 PM PST 24 Feb 29 01:00:41 PM PST 24 34659738 ps
T1081 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4102166908 Feb 29 01:00:40 PM PST 24 Feb 29 01:00:42 PM PST 24 248898457 ps
T1082 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1424185005 Feb 29 01:00:36 PM PST 24 Feb 29 01:00:37 PM PST 24 14590501 ps
T1083 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2128539204 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:36 PM PST 24 438784059 ps
T1084 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3008479625 Feb 29 01:00:36 PM PST 24 Feb 29 01:00:38 PM PST 24 109141862 ps
T158 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4078343593 Feb 29 01:00:28 PM PST 24 Feb 29 01:00:45 PM PST 24 5621543446 ps
T1085 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2629268713 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:33 PM PST 24 48157824 ps
T1086 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4257261506 Feb 29 01:00:26 PM PST 24 Feb 29 01:00:41 PM PST 24 708506345 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2277734081 Feb 29 01:00:11 PM PST 24 Feb 29 01:00:14 PM PST 24 157887512 ps
T1088 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.262567168 Feb 29 01:00:11 PM PST 24 Feb 29 01:00:14 PM PST 24 36964375 ps
T1089 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2489994427 Feb 29 01:00:36 PM PST 24 Feb 29 01:00:39 PM PST 24 98840268 ps
T1090 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.682163558 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:32 PM PST 24 31947460 ps
T1091 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.381389809 Feb 29 01:00:33 PM PST 24 Feb 29 01:00:34 PM PST 24 21021735 ps
T1092 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.620921341 Feb 29 01:00:30 PM PST 24 Feb 29 01:00:31 PM PST 24 19373801 ps
T1093 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2830157148 Feb 29 01:00:35 PM PST 24 Feb 29 01:00:38 PM PST 24 429605916 ps
T1094 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2315847192 Feb 29 01:00:15 PM PST 24 Feb 29 01:00:17 PM PST 24 33200427 ps
T1095 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1293749 Feb 29 01:00:35 PM PST 24 Feb 29 01:00:40 PM PST 24 923805576 ps
T105 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4081214553 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:36 PM PST 24 158377075 ps
T1096 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3046041903 Feb 29 01:00:15 PM PST 24 Feb 29 01:00:19 PM PST 24 429340906 ps
T1097 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2911179749 Feb 29 01:00:14 PM PST 24 Feb 29 01:00:20 PM PST 24 1489766891 ps
T1098 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3611270059 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:32 PM PST 24 17000439 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.15651324 Feb 29 01:00:09 PM PST 24 Feb 29 01:00:10 PM PST 24 19993274 ps
T1100 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4173548024 Feb 29 01:00:40 PM PST 24 Feb 29 01:00:41 PM PST 24 19662078 ps
T1101 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4025582405 Feb 29 01:00:31 PM PST 24 Feb 29 01:00:32 PM PST 24 42522553 ps
T1102 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3785691381 Feb 29 01:00:11 PM PST 24 Feb 29 01:00:26 PM PST 24 2534719916 ps
T1103 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2294294636 Feb 29 01:00:32 PM PST 24 Feb 29 01:00:36 PM PST 24 361707922 ps
T1104 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2296286424 Feb 29 01:00:26 PM PST 24 Feb 29 01:00:27 PM PST 24 59450308 ps
T1105 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1780774895 Feb 29 01:00:27 PM PST 24 Feb 29 01:00:31 PM PST 24 59186130 ps
T1106 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1138969914 Feb 29 01:00:14 PM PST 24 Feb 29 01:00:18 PM PST 24 208863615 ps
T1107 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1111589371 Feb 29 01:00:28 PM PST 24 Feb 29 01:00:33 PM PST 24 327368731 ps
T1108 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1645121467 Feb 29 01:00:30 PM PST 24 Feb 29 01:00:33 PM PST 24 302063307 ps
T1109 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1714069810 Feb 29 01:00:26 PM PST 24 Feb 29 01:00:27 PM PST 24 16802285 ps
T1110 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4227689405 Feb 29 01:00:29 PM PST 24 Feb 29 01:00:32 PM PST 24 47630843 ps
T1111 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2831127856 Feb 29 01:00:29 PM PST 24 Feb 29 01:00:30 PM PST 24 19192795 ps
T1112 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3170531986 Feb 29 01:00:36 PM PST 24 Feb 29 01:00:36 PM PST 24 11289280 ps
T1113 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1047434492 Feb 29 01:00:28 PM PST 24 Feb 29 01:00:32 PM PST 24 178377359 ps
T1114 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2090297147 Feb 29 01:00:41 PM PST 24 Feb 29 01:00:42 PM PST 24 89458034 ps

Test location /workspace/coverage/default/9.spi_device_stress_all.2074993286
Short name T10
Test name
Test status
Simulation time 219181312386 ps
CPU time 397.35 seconds
Started Feb 29 01:36:46 PM PST 24
Finished Feb 29 01:43:23 PM PST 24
Peak memory 273612 kb
Host smart-5e3ea574-90a0-45fa-90f9-65d0c28d7ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074993286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2074993286
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3319817849
Short name T12
Test name
Test status
Simulation time 3055874237 ps
CPU time 14.98 seconds
Started Feb 29 01:38:02 PM PST 24
Finished Feb 29 01:38:18 PM PST 24
Peak memory 222712 kb
Host smart-4fb3fdc5-c746-4f65-9a30-82090c8c9aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319817849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3319817849
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2154419389
Short name T26
Test name
Test status
Simulation time 411749456075 ps
CPU time 800.87 seconds
Started Feb 29 01:37:10 PM PST 24
Finished Feb 29 01:50:32 PM PST 24
Peak memory 266364 kb
Host smart-a55d6ad4-fef5-479f-8efe-554093cb85f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154419389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2154419389
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2536741623
Short name T106
Test name
Test status
Simulation time 402657714 ps
CPU time 2.55 seconds
Started Feb 29 01:00:16 PM PST 24
Finished Feb 29 01:00:19 PM PST 24
Peak memory 216496 kb
Host smart-d9ead3df-e107-465b-8462-249cd0ac4b01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536741623 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2536741623
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1362107036
Short name T195
Test name
Test status
Simulation time 136091361350 ps
CPU time 307.21 seconds
Started Feb 29 01:38:19 PM PST 24
Finished Feb 29 01:43:26 PM PST 24
Peak memory 272796 kb
Host smart-497fa04f-4902-401e-97f7-d1270789c233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362107036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1362107036
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1668459457
Short name T31
Test name
Test status
Simulation time 69609589774 ps
CPU time 513.17 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:47:37 PM PST 24
Peak memory 265576 kb
Host smart-38591bc8-2ce0-4fd7-8ec1-eb861d366720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668459457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1668459457
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1530947551
Short name T457
Test name
Test status
Simulation time 16787546 ps
CPU time 0.74 seconds
Started Feb 29 01:35:54 PM PST 24
Finished Feb 29 01:35:55 PM PST 24
Peak memory 216016 kb
Host smart-bd4cbd9c-2e37-43d6-8fc3-a3f088d3b3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530947551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1530947551
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3512141135
Short name T38
Test name
Test status
Simulation time 127699956490 ps
CPU time 164.49 seconds
Started Feb 29 01:38:24 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 256084 kb
Host smart-780f46ec-150d-4ce6-b60a-0cd26b06becf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512141135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3512141135
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3846750711
Short name T69
Test name
Test status
Simulation time 64913105 ps
CPU time 1.13 seconds
Started Feb 29 01:35:53 PM PST 24
Finished Feb 29 01:35:55 PM PST 24
Peak memory 235300 kb
Host smart-b24cfefe-7d57-4cb5-99fb-1a5a60fdb409
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846750711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3846750711
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.913969462
Short name T145
Test name
Test status
Simulation time 511905875787 ps
CPU time 382.3 seconds
Started Feb 29 01:37:37 PM PST 24
Finished Feb 29 01:43:59 PM PST 24
Peak memory 300852 kb
Host smart-869dd6da-2d6d-45b1-a269-76e38062d361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913969462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.913969462
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3830394590
Short name T78
Test name
Test status
Simulation time 1130349698 ps
CPU time 5.26 seconds
Started Feb 29 01:36:42 PM PST 24
Finished Feb 29 01:36:47 PM PST 24
Peak memory 222540 kb
Host smart-ffef12b4-e814-4660-8b2b-936db91636f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3830394590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3830394590
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2303135364
Short name T36
Test name
Test status
Simulation time 7239682284 ps
CPU time 133.85 seconds
Started Feb 29 01:37:41 PM PST 24
Finished Feb 29 01:39:55 PM PST 24
Peak memory 264956 kb
Host smart-1fdf4cd0-8849-4a6e-a24b-980070a905ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303135364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2303135364
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3000319965
Short name T89
Test name
Test status
Simulation time 424746449 ps
CPU time 11.04 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:43 PM PST 24
Peak memory 215272 kb
Host smart-6dead3b7-5f4c-4329-b21f-b97ca3430b65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000319965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3000319965
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3198304270
Short name T20
Test name
Test status
Simulation time 10663649973 ps
CPU time 119.83 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:39:56 PM PST 24
Peak memory 255888 kb
Host smart-36acf6bb-86b9-4f8c-b2b6-38d1f838c429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198304270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3198304270
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.456015479
Short name T126
Test name
Test status
Simulation time 30912083430 ps
CPU time 117.45 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:39:41 PM PST 24
Peak memory 270256 kb
Host smart-28dc6b1a-74d7-465c-b3bd-7007d28e28a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456015479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.456015479
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4213308881
Short name T95
Test name
Test status
Simulation time 60378839 ps
CPU time 4.41 seconds
Started Feb 29 01:00:12 PM PST 24
Finished Feb 29 01:00:17 PM PST 24
Peak memory 215308 kb
Host smart-3e146081-e833-4b58-a647-07cbdb87c406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213308881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
213308881
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2146618946
Short name T114
Test name
Test status
Simulation time 47919000 ps
CPU time 1.92 seconds
Started Feb 29 01:00:29 PM PST 24
Finished Feb 29 01:00:31 PM PST 24
Peak memory 207024 kb
Host smart-9f6ba2ed-9e26-4b87-9629-a3489ba4f348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146618946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2146618946
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4214679540
Short name T37
Test name
Test status
Simulation time 311831546299 ps
CPU time 452.7 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:44:17 PM PST 24
Peak memory 267848 kb
Host smart-7da03b0a-04b7-46fb-9945-43116978e1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214679540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4214679540
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1750206372
Short name T364
Test name
Test status
Simulation time 386089144 ps
CPU time 1.01 seconds
Started Feb 29 01:36:46 PM PST 24
Finished Feb 29 01:36:47 PM PST 24
Peak memory 217820 kb
Host smart-70e5b99f-b7d4-4b02-a343-7d4b05ddc112
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750206372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1750206372
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.678363377
Short name T197
Test name
Test status
Simulation time 210939454310 ps
CPU time 441.04 seconds
Started Feb 29 01:38:10 PM PST 24
Finished Feb 29 01:45:33 PM PST 24
Peak memory 273652 kb
Host smart-b79c55a1-3bd4-4a9b-944b-1a935563bf1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678363377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.678363377
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3098598873
Short name T162
Test name
Test status
Simulation time 252095506916 ps
CPU time 871.8 seconds
Started Feb 29 01:38:30 PM PST 24
Finished Feb 29 01:53:02 PM PST 24
Peak memory 264220 kb
Host smart-3a66c780-931b-4541-a7f5-6e67a728239c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098598873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3098598873
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1619592586
Short name T201
Test name
Test status
Simulation time 2165986704 ps
CPU time 24.36 seconds
Started Feb 29 01:37:41 PM PST 24
Finished Feb 29 01:38:05 PM PST 24
Peak memory 240108 kb
Host smart-9e24fa62-428b-41a5-919f-0ecdf57552b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619592586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1619592586
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2870159421
Short name T34
Test name
Test status
Simulation time 304513577044 ps
CPU time 363.91 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:45:46 PM PST 24
Peak memory 266644 kb
Host smart-f67570a7-42e1-4e63-8576-ee989fe8fa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870159421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2870159421
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3275104138
Short name T178
Test name
Test status
Simulation time 11220315757 ps
CPU time 114.69 seconds
Started Feb 29 01:36:46 PM PST 24
Finished Feb 29 01:38:42 PM PST 24
Peak memory 266072 kb
Host smart-6d74fa47-852e-49c5-88f4-cf1ff79429c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275104138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3275104138
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1561574390
Short name T261
Test name
Test status
Simulation time 70936687864 ps
CPU time 615.38 seconds
Started Feb 29 01:37:00 PM PST 24
Finished Feb 29 01:47:15 PM PST 24
Peak memory 296140 kb
Host smart-71a33e2c-1d4d-4df0-b310-ab6f99bbfb84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561574390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1561574390
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4135240858
Short name T371
Test name
Test status
Simulation time 14535186 ps
CPU time 0.71 seconds
Started Feb 29 01:35:58 PM PST 24
Finished Feb 29 01:36:00 PM PST 24
Peak memory 204844 kb
Host smart-c98d1782-204e-41a0-b3fd-689bcce85c23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135240858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
135240858
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1594783394
Short name T18
Test name
Test status
Simulation time 1801298278 ps
CPU time 18.59 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:38:02 PM PST 24
Peak memory 216148 kb
Host smart-8a441dc6-17f7-408e-b2fd-599230e15f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594783394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1594783394
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4081214553
Short name T105
Test name
Test status
Simulation time 158377075 ps
CPU time 3.82 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 215412 kb
Host smart-b669aa56-cf4e-4d47-8553-2cd3eb99e9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081214553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
081214553
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4078343593
Short name T158
Test name
Test status
Simulation time 5621543446 ps
CPU time 17.66 seconds
Started Feb 29 01:00:28 PM PST 24
Finished Feb 29 01:00:45 PM PST 24
Peak memory 215460 kb
Host smart-c8bda536-4c42-4db4-9ba4-933dfc90d1e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078343593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.4078343593
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3154459282
Short name T287
Test name
Test status
Simulation time 68637305789 ps
CPU time 176.02 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:40:37 PM PST 24
Peak memory 256448 kb
Host smart-7aad0c35-3c18-4336-8c7c-829f830a535a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154459282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3154459282
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1172288347
Short name T146
Test name
Test status
Simulation time 152671944443 ps
CPU time 615.88 seconds
Started Feb 29 01:35:54 PM PST 24
Finished Feb 29 01:46:10 PM PST 24
Peak memory 286500 kb
Host smart-de605311-9d1b-43ec-8197-d044e79d7d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172288347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1172288347
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3719529486
Short name T187
Test name
Test status
Simulation time 12877272498 ps
CPU time 24.71 seconds
Started Feb 29 01:37:02 PM PST 24
Finished Feb 29 01:37:27 PM PST 24
Peak memory 238580 kb
Host smart-0ea1bb7a-c04f-4af8-9fa0-792f0de85076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719529486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3719529486
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1192715563
Short name T175
Test name
Test status
Simulation time 868182356913 ps
CPU time 646.67 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:49:41 PM PST 24
Peak memory 281828 kb
Host smart-56cf8f77-c37b-4ce8-8b05-e08dd10ab3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192715563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1192715563
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1781672859
Short name T138
Test name
Test status
Simulation time 22652829337 ps
CPU time 85.13 seconds
Started Feb 29 01:39:13 PM PST 24
Finished Feb 29 01:40:38 PM PST 24
Peak memory 253300 kb
Host smart-da624157-e3d8-46b5-b124-e6eb954c485a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781672859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1781672859
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1590949899
Short name T88
Test name
Test status
Simulation time 327227903 ps
CPU time 3.97 seconds
Started Feb 29 01:00:30 PM PST 24
Finished Feb 29 01:00:35 PM PST 24
Peak memory 215564 kb
Host smart-565a4a7a-4894-40c4-9574-9a68588ddba0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590949899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1590949899
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4128260219
Short name T161
Test name
Test status
Simulation time 413097223 ps
CPU time 5.95 seconds
Started Feb 29 01:00:10 PM PST 24
Finished Feb 29 01:00:16 PM PST 24
Peak memory 215272 kb
Host smart-fc4bdfcf-e57b-4bf3-86d7-dc18b9c6d396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128260219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4128260219
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2882191062
Short name T275
Test name
Test status
Simulation time 46912119174 ps
CPU time 244.2 seconds
Started Feb 29 01:36:00 PM PST 24
Finished Feb 29 01:40:05 PM PST 24
Peak memory 255168 kb
Host smart-3ff18345-cd45-4c99-9d4d-c379138a2269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882191062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2882191062
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2396686750
Short name T274
Test name
Test status
Simulation time 18781580649 ps
CPU time 77.82 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:38:03 PM PST 24
Peak memory 269220 kb
Host smart-946c8eb2-c101-4b19-b9ad-e8c1fb5fcd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396686750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2396686750
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1988096866
Short name T286
Test name
Test status
Simulation time 21860218043 ps
CPU time 204.22 seconds
Started Feb 29 01:37:01 PM PST 24
Finished Feb 29 01:40:27 PM PST 24
Peak memory 255348 kb
Host smart-a8d7184b-5077-4b44-9900-e2757d5ca6bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988096866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1988096866
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.129300413
Short name T271
Test name
Test status
Simulation time 20228406813 ps
CPU time 131.49 seconds
Started Feb 29 01:37:39 PM PST 24
Finished Feb 29 01:39:51 PM PST 24
Peak memory 265044 kb
Host smart-bdbc68ae-1b41-4729-bc33-9676dd3b91da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129300413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.129300413
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3715218826
Short name T35
Test name
Test status
Simulation time 120967111608 ps
CPU time 27.14 seconds
Started Feb 29 01:39:27 PM PST 24
Finished Feb 29 01:39:55 PM PST 24
Peak memory 232632 kb
Host smart-6fc535fb-85fc-4ee2-a11d-dbfbbd33d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715218826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3715218826
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3199937514
Short name T79
Test name
Test status
Simulation time 21889712 ps
CPU time 0.95 seconds
Started Feb 29 01:00:14 PM PST 24
Finished Feb 29 01:00:15 PM PST 24
Peak memory 206680 kb
Host smart-0fa019b8-2a24-4844-b89e-cf355dfb6f28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199937514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3199937514
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2020463281
Short name T101
Test name
Test status
Simulation time 147368160 ps
CPU time 1.98 seconds
Started Feb 29 01:00:14 PM PST 24
Finished Feb 29 01:00:16 PM PST 24
Peak memory 215340 kb
Host smart-e82cabfa-c144-47fc-affa-ea0ebf22cd7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020463281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
020463281
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1999668065
Short name T1025
Test name
Test status
Simulation time 2524816123 ps
CPU time 16.78 seconds
Started Feb 29 01:00:15 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 207332 kb
Host smart-d79912d9-9b2b-4072-8b25-1a41784de662
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999668065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1999668065
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1657355251
Short name T1056
Test name
Test status
Simulation time 2704966990 ps
CPU time 40.23 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:51 PM PST 24
Peak memory 207264 kb
Host smart-19e6aabc-e11a-4c14-a250-d2b1aeb4ba72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657355251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1657355251
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2556534870
Short name T82
Test name
Test status
Simulation time 69225288 ps
CPU time 1.01 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:12 PM PST 24
Peak memory 206968 kb
Host smart-3dff61b0-52b5-46be-8e5d-a14a804922de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556534870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2556534870
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3609464528
Short name T1041
Test name
Test status
Simulation time 321233126 ps
CPU time 2.8 seconds
Started Feb 29 01:00:14 PM PST 24
Finished Feb 29 01:00:17 PM PST 24
Peak memory 216468 kb
Host smart-d4b48184-1c8b-4bc3-98b6-72b23aa97012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609464528 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3609464528
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2303210507
Short name T115
Test name
Test status
Simulation time 221945795 ps
CPU time 1.87 seconds
Started Feb 29 01:00:09 PM PST 24
Finished Feb 29 01:00:11 PM PST 24
Peak memory 215408 kb
Host smart-061e07ba-18ac-4b01-a8b6-d5b7ff060bfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303210507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
303210507
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.15651324
Short name T1099
Test name
Test status
Simulation time 19993274 ps
CPU time 0.77 seconds
Started Feb 29 01:00:09 PM PST 24
Finished Feb 29 01:00:10 PM PST 24
Peak memory 203132 kb
Host smart-8e198d2c-fd93-4c48-9286-fe76b58a1712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15651324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.15651324
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2428873732
Short name T117
Test name
Test status
Simulation time 21792451 ps
CPU time 1.64 seconds
Started Feb 29 01:00:13 PM PST 24
Finished Feb 29 01:00:15 PM PST 24
Peak memory 215324 kb
Host smart-0d9c18ae-de95-4f61-8647-aca729d71964
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428873732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2428873732
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.697647773
Short name T1011
Test name
Test status
Simulation time 11428967 ps
CPU time 0.65 seconds
Started Feb 29 01:00:10 PM PST 24
Finished Feb 29 01:00:11 PM PST 24
Peak memory 203020 kb
Host smart-bb48a565-5228-488f-8c10-a82be3cd751d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697647773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.697647773
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.902188962
Short name T1063
Test name
Test status
Simulation time 1784347247 ps
CPU time 3.11 seconds
Started Feb 29 01:00:12 PM PST 24
Finished Feb 29 01:00:16 PM PST 24
Peak memory 215220 kb
Host smart-4eaa400c-f87a-419c-8543-667d2dc19281
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902188962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.902188962
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1673573736
Short name T1061
Test name
Test status
Simulation time 325625194 ps
CPU time 8.74 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:20 PM PST 24
Peak memory 207164 kb
Host smart-9967f4e1-fd1e-4905-a66a-00271649fe9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673573736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1673573736
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.927806158
Short name T1044
Test name
Test status
Simulation time 370932345 ps
CPU time 24.03 seconds
Started Feb 29 01:00:09 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 207188 kb
Host smart-f9e7401b-7f64-46de-91cd-028ccf1f7b0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927806158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.927806158
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2393738821
Short name T107
Test name
Test status
Simulation time 58481231 ps
CPU time 1.73 seconds
Started Feb 29 01:00:12 PM PST 24
Finished Feb 29 01:00:14 PM PST 24
Peak memory 215452 kb
Host smart-990d3936-3e28-46e4-a2c3-e52e1b4c639f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393738821 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2393738821
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.442640973
Short name T123
Test name
Test status
Simulation time 38211572 ps
CPU time 2.39 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:13 PM PST 24
Peak memory 215400 kb
Host smart-bcb62271-6707-4a2c-b119-0530b2b7280d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442640973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.442640973
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.201956875
Short name T1017
Test name
Test status
Simulation time 23788262 ps
CPU time 0.66 seconds
Started Feb 29 01:00:12 PM PST 24
Finished Feb 29 01:00:13 PM PST 24
Peak memory 202936 kb
Host smart-bb2dbadc-0489-47aa-9cbe-22158ed6aee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201956875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.201956875
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.442652729
Short name T1071
Test name
Test status
Simulation time 372107044 ps
CPU time 1.84 seconds
Started Feb 29 01:00:13 PM PST 24
Finished Feb 29 01:00:16 PM PST 24
Peak memory 215356 kb
Host smart-953b637a-a58b-42df-b121-593aa4c93035
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442652729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.442652729
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4042135683
Short name T1013
Test name
Test status
Simulation time 40251099 ps
CPU time 0.67 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:11 PM PST 24
Peak memory 203000 kb
Host smart-a8ba388a-d0cc-474e-bc30-c5717e22f4b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042135683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4042135683
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1681863531
Short name T1064
Test name
Test status
Simulation time 199469213 ps
CPU time 4.3 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:15 PM PST 24
Peak memory 215068 kb
Host smart-fb5b04ef-3d63-4293-a620-91aa2c064aca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681863531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1681863531
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.854683945
Short name T96
Test name
Test status
Simulation time 62305359 ps
CPU time 1.76 seconds
Started Feb 29 01:00:10 PM PST 24
Finished Feb 29 01:00:11 PM PST 24
Peak memory 215488 kb
Host smart-3d2e77ca-acb9-4de2-af33-647db011cac5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854683945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.854683945
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2772101732
Short name T137
Test name
Test status
Simulation time 10081007975 ps
CPU time 22.92 seconds
Started Feb 29 01:00:09 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 215472 kb
Host smart-f53c70fc-563a-4cac-bb4f-27aad983d128
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772101732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2772101732
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.549412509
Short name T1077
Test name
Test status
Simulation time 1300151672 ps
CPU time 2.54 seconds
Started Feb 29 01:00:28 PM PST 24
Finished Feb 29 01:00:30 PM PST 24
Peak memory 216364 kb
Host smart-72c31b9b-27f9-4733-845f-ba602095abc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549412509 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.549412509
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3825489429
Short name T1055
Test name
Test status
Simulation time 79255127 ps
CPU time 0.76 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 203104 kb
Host smart-4d346ada-cd02-46c3-ad19-cbb5ddfe38a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825489429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3825489429
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3273116390
Short name T133
Test name
Test status
Simulation time 575211443 ps
CPU time 3.46 seconds
Started Feb 29 01:00:30 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 215384 kb
Host smart-dc93fb81-cc18-4792-9d7c-0a460986900a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273116390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3273116390
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2288064311
Short name T104
Test name
Test status
Simulation time 33729905 ps
CPU time 2.28 seconds
Started Feb 29 01:00:28 PM PST 24
Finished Feb 29 01:00:30 PM PST 24
Peak memory 215432 kb
Host smart-d16be7b2-42ea-4bac-9226-67854a93e01e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288064311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2288064311
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4257261506
Short name T1086
Test name
Test status
Simulation time 708506345 ps
CPU time 15.7 seconds
Started Feb 29 01:00:26 PM PST 24
Finished Feb 29 01:00:41 PM PST 24
Peak memory 215360 kb
Host smart-d732ca60-850b-4a7b-ab82-78fddc96ab0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257261506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4257261506
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2294294636
Short name T1103
Test name
Test status
Simulation time 361707922 ps
CPU time 4.15 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 216972 kb
Host smart-32c98c24-4f17-4dc4-93a9-8c827d40c3d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294294636 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2294294636
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.748599350
Short name T111
Test name
Test status
Simulation time 57648470 ps
CPU time 1.2 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 207072 kb
Host smart-c2af9b72-bee2-48d1-bbe0-dc5ffb660c50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748599350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.748599350
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2831127856
Short name T1111
Test name
Test status
Simulation time 19192795 ps
CPU time 0.67 seconds
Started Feb 29 01:00:29 PM PST 24
Finished Feb 29 01:00:30 PM PST 24
Peak memory 203088 kb
Host smart-2d935fad-a188-4f82-8359-23a689dac361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831127856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2831127856
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3958213614
Short name T1076
Test name
Test status
Simulation time 256427572 ps
CPU time 1.97 seconds
Started Feb 29 01:00:30 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 207164 kb
Host smart-e486f9e8-580c-4095-84bb-7c41983071b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958213614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3958213614
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2626729182
Short name T87
Test name
Test status
Simulation time 59750701 ps
CPU time 1.98 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 207256 kb
Host smart-d33cfb01-7828-4617-9b24-18ff2e8f8f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626729182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2626729182
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.124626525
Short name T135
Test name
Test status
Simulation time 2344028875 ps
CPU time 23.07 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:51 PM PST 24
Peak memory 215480 kb
Host smart-c417111e-c009-421a-b200-aa72da8f0327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124626525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.124626525
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2890863347
Short name T1048
Test name
Test status
Simulation time 100800803 ps
CPU time 1.82 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 215328 kb
Host smart-15c74357-cdd6-4e73-84e5-78171f3ef434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890863347 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2890863347
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4007292483
Short name T1074
Test name
Test status
Simulation time 76875332 ps
CPU time 2.06 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:35 PM PST 24
Peak memory 207184 kb
Host smart-98623a74-e7d5-4859-8bce-ff706384e6a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007292483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4007292483
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.620921341
Short name T1092
Test name
Test status
Simulation time 19373801 ps
CPU time 0.72 seconds
Started Feb 29 01:00:30 PM PST 24
Finished Feb 29 01:00:31 PM PST 24
Peak memory 203368 kb
Host smart-ecf52b81-c312-4f56-bb16-3909a0c662ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620921341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.620921341
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3101329417
Short name T1016
Test name
Test status
Simulation time 152576698 ps
CPU time 3.91 seconds
Started Feb 29 01:00:29 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 215048 kb
Host smart-bb3c418c-8dcb-4e9b-b3c2-c48ec859d7e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101329417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3101329417
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1772317948
Short name T1021
Test name
Test status
Simulation time 235981945 ps
CPU time 4.11 seconds
Started Feb 29 01:00:33 PM PST 24
Finished Feb 29 01:00:37 PM PST 24
Peak memory 216800 kb
Host smart-fb1d59d1-b12b-4094-ad0e-74c2cdd644fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772317948 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1772317948
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2294007179
Short name T122
Test name
Test status
Simulation time 27271567 ps
CPU time 1.78 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 206984 kb
Host smart-645af928-42b2-4bde-a60e-a7f582afbfed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294007179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2294007179
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.682163558
Short name T1090
Test name
Test status
Simulation time 31947460 ps
CPU time 0.74 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 203136 kb
Host smart-851fa0e8-e100-43b6-88d6-33cede0a5c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682163558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.682163558
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3751764044
Short name T131
Test name
Test status
Simulation time 325977437 ps
CPU time 2.08 seconds
Started Feb 29 01:00:30 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 215120 kb
Host smart-f9f821cb-1efe-480c-9b20-cde7618ef5a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751764044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3751764044
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2502492145
Short name T108
Test name
Test status
Simulation time 144630944 ps
CPU time 2.88 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 215424 kb
Host smart-96af6532-3323-4a23-90df-bb4935d8e545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502492145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2502492145
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2275979970
Short name T136
Test name
Test status
Simulation time 3199450974 ps
CPU time 15.94 seconds
Started Feb 29 01:00:34 PM PST 24
Finished Feb 29 01:00:50 PM PST 24
Peak memory 215548 kb
Host smart-67e54656-8046-443f-af42-311e425dccd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275979970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2275979970
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.243636746
Short name T1070
Test name
Test status
Simulation time 629100519 ps
CPU time 4 seconds
Started Feb 29 01:00:36 PM PST 24
Finished Feb 29 01:00:40 PM PST 24
Peak memory 216560 kb
Host smart-895c94e6-c1ec-44aa-9ea6-9b5649fe515f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243636746 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.243636746
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.381389809
Short name T1091
Test name
Test status
Simulation time 21021735 ps
CPU time 1.36 seconds
Started Feb 29 01:00:33 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 207116 kb
Host smart-177fa67c-11cb-4ab7-8867-2f3f6798e8e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381389809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.381389809
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3967114258
Short name T1060
Test name
Test status
Simulation time 13121366 ps
CPU time 0.75 seconds
Started Feb 29 01:00:34 PM PST 24
Finished Feb 29 01:00:35 PM PST 24
Peak memory 203132 kb
Host smart-90a6c452-e272-46cf-b6c9-e4d9ae744d10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967114258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3967114258
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.231292752
Short name T1012
Test name
Test status
Simulation time 167671804 ps
CPU time 3.9 seconds
Started Feb 29 01:00:29 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 207252 kb
Host smart-c7ebc7af-bcb3-412d-836d-ca02f5453e00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231292752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.231292752
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2629547195
Short name T92
Test name
Test status
Simulation time 114883128 ps
CPU time 2.26 seconds
Started Feb 29 01:00:39 PM PST 24
Finished Feb 29 01:00:41 PM PST 24
Peak memory 215468 kb
Host smart-07b8f47d-90bc-41dc-a476-0f016c7d589f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629547195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2629547195
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1891287308
Short name T1045
Test name
Test status
Simulation time 202864097 ps
CPU time 6.34 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:38 PM PST 24
Peak memory 215928 kb
Host smart-6ccf07d0-06f2-491b-9708-da36945984fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891287308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1891287308
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2489994427
Short name T1089
Test name
Test status
Simulation time 98840268 ps
CPU time 2.54 seconds
Started Feb 29 01:00:36 PM PST 24
Finished Feb 29 01:00:39 PM PST 24
Peak memory 216500 kb
Host smart-d93aff5d-8ba8-4efa-bdf6-711d3c52b5b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489994427 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2489994427
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3008479625
Short name T1084
Test name
Test status
Simulation time 109141862 ps
CPU time 1.88 seconds
Started Feb 29 01:00:36 PM PST 24
Finished Feb 29 01:00:38 PM PST 24
Peak memory 207080 kb
Host smart-7d5787c6-66a8-4469-a7be-0889c84767a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008479625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3008479625
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1351789510
Short name T1054
Test name
Test status
Simulation time 38402356 ps
CPU time 0.74 seconds
Started Feb 29 01:00:34 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 203100 kb
Host smart-7d51f5e7-2720-412f-930c-5e4bbe1a6705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351789510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1351789510
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4227689405
Short name T1110
Test name
Test status
Simulation time 47630843 ps
CPU time 2.88 seconds
Started Feb 29 01:00:29 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 214996 kb
Host smart-084898b1-2733-4b1e-bbda-cbd2289865a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227689405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4227689405
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1421399672
Short name T98
Test name
Test status
Simulation time 106367977 ps
CPU time 3.41 seconds
Started Feb 29 01:00:40 PM PST 24
Finished Feb 29 01:00:44 PM PST 24
Peak memory 216464 kb
Host smart-d706a750-9582-47d7-bdca-4e85dde82fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421399672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1421399672
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3260311299
Short name T90
Test name
Test status
Simulation time 404804931 ps
CPU time 13.08 seconds
Started Feb 29 01:00:30 PM PST 24
Finished Feb 29 01:00:43 PM PST 24
Peak memory 215460 kb
Host smart-21459746-b9c6-4f51-aa42-76484640e0be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260311299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3260311299
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1371244313
Short name T86
Test name
Test status
Simulation time 93132626 ps
CPU time 2.62 seconds
Started Feb 29 01:00:34 PM PST 24
Finished Feb 29 01:00:37 PM PST 24
Peak memory 216464 kb
Host smart-ece63c26-d9f3-4161-8db7-a2705f12dbf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371244313 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1371244313
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3629166112
Short name T1052
Test name
Test status
Simulation time 413769251 ps
CPU time 2.75 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 207200 kb
Host smart-3e42345c-43ec-4441-a70c-0f58a8ef379f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629166112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3629166112
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3006888424
Short name T1039
Test name
Test status
Simulation time 40916550 ps
CPU time 0.7 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 203088 kb
Host smart-8bb64df7-3af5-4021-b61c-c09a37cd4709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006888424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3006888424
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3459099176
Short name T1040
Test name
Test status
Simulation time 33679396 ps
CPU time 1.86 seconds
Started Feb 29 01:00:30 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 207228 kb
Host smart-75d3631d-1857-4d40-a117-4fc61364d03f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459099176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3459099176
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2737234885
Short name T97
Test name
Test status
Simulation time 117256577 ps
CPU time 4.07 seconds
Started Feb 29 01:00:29 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 215628 kb
Host smart-b13eb997-4b8d-4e95-a5ba-479ac1f34c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737234885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2737234885
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3062870636
Short name T85
Test name
Test status
Simulation time 111710509 ps
CPU time 7.24 seconds
Started Feb 29 01:00:33 PM PST 24
Finished Feb 29 01:00:40 PM PST 24
Peak memory 221716 kb
Host smart-fa54db01-32cc-4b4f-b599-b7d3a630da66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062870636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3062870636
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1383411069
Short name T100
Test name
Test status
Simulation time 116405519 ps
CPU time 3.03 seconds
Started Feb 29 01:00:33 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 216572 kb
Host smart-19a08ec4-6076-41ff-9889-0f5790bb3994
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383411069 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1383411069
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4102166908
Short name T1081
Test name
Test status
Simulation time 248898457 ps
CPU time 1.83 seconds
Started Feb 29 01:00:40 PM PST 24
Finished Feb 29 01:00:42 PM PST 24
Peak memory 207096 kb
Host smart-0c313588-eea2-43de-a187-e3ff798a033c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102166908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4102166908
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2450436318
Short name T1073
Test name
Test status
Simulation time 13945973 ps
CPU time 0.74 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 203164 kb
Host smart-7d955e78-8733-4b99-92f7-1dbec195d990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450436318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2450436318
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1474145449
Short name T1023
Test name
Test status
Simulation time 181527625 ps
CPU time 4.39 seconds
Started Feb 29 01:00:35 PM PST 24
Finished Feb 29 01:00:39 PM PST 24
Peak memory 215396 kb
Host smart-b356d5cb-6985-467d-a5d0-fdead8b32aff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474145449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1474145449
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2876786956
Short name T102
Test name
Test status
Simulation time 208453509 ps
CPU time 2.15 seconds
Started Feb 29 01:00:33 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 215416 kb
Host smart-c6959110-1e6d-4e80-ab1b-efe946c2f9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876786956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2876786956
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.491031794
Short name T155
Test name
Test status
Simulation time 4042614808 ps
CPU time 21.99 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:54 PM PST 24
Peak memory 215728 kb
Host smart-d4642209-c044-4313-9797-2bc6390a6de3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491031794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.491031794
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2830157148
Short name T1093
Test name
Test status
Simulation time 429605916 ps
CPU time 2.73 seconds
Started Feb 29 01:00:35 PM PST 24
Finished Feb 29 01:00:38 PM PST 24
Peak memory 216400 kb
Host smart-01c01578-09be-4c11-b2d6-cbd2e11836a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830157148 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2830157148
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1745732962
Short name T120
Test name
Test status
Simulation time 140895540 ps
CPU time 3.04 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:35 PM PST 24
Peak memory 215376 kb
Host smart-3bd46dfd-7f1d-46af-a8c8-9f640889cab6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745732962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1745732962
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2629268713
Short name T1085
Test name
Test status
Simulation time 48157824 ps
CPU time 0.75 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 203432 kb
Host smart-73738b94-fca5-4c93-a541-796b61034224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629268713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2629268713
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.280444810
Short name T1051
Test name
Test status
Simulation time 49442132 ps
CPU time 1.68 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 207232 kb
Host smart-db25d10a-9129-474b-bf82-589ff253f7a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280444810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.280444810
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1120117837
Short name T94
Test name
Test status
Simulation time 462237864 ps
CPU time 3.12 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:35 PM PST 24
Peak memory 216472 kb
Host smart-8112389c-ccf0-4987-8768-34f0f2276756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120117837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1120117837
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4234582653
Short name T156
Test name
Test status
Simulation time 3368555396 ps
CPU time 13.79 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:46 PM PST 24
Peak memory 215440 kb
Host smart-778c02d5-439d-4966-bfcb-90567b9669ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234582653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4234582653
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2090297147
Short name T1114
Test name
Test status
Simulation time 89458034 ps
CPU time 1.65 seconds
Started Feb 29 01:00:41 PM PST 24
Finished Feb 29 01:00:42 PM PST 24
Peak memory 215332 kb
Host smart-f5b60535-746e-4833-bc43-9d41aee94592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090297147 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2090297147
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3512209642
Short name T1049
Test name
Test status
Simulation time 38914869 ps
CPU time 2.53 seconds
Started Feb 29 01:00:24 PM PST 24
Finished Feb 29 01:00:27 PM PST 24
Peak memory 215400 kb
Host smart-f02548ef-a124-47f0-b0cb-6509f564c689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512209642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3512209642
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1424185005
Short name T1082
Test name
Test status
Simulation time 14590501 ps
CPU time 0.76 seconds
Started Feb 29 01:00:36 PM PST 24
Finished Feb 29 01:00:37 PM PST 24
Peak memory 203096 kb
Host smart-90c07b5a-457c-4e1e-ab16-b01f50700850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424185005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1424185005
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1293749
Short name T1095
Test name
Test status
Simulation time 923805576 ps
CPU time 4.19 seconds
Started Feb 29 01:00:35 PM PST 24
Finished Feb 29 01:00:40 PM PST 24
Peak memory 215548 kb
Host smart-de35a04f-2c86-427a-879d-64cb12ef1d72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi
_device_same_csr_outstanding.1293749
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3116968377
Short name T99
Test name
Test status
Simulation time 136430937 ps
CPU time 1.82 seconds
Started Feb 29 01:00:33 PM PST 24
Finished Feb 29 01:00:35 PM PST 24
Peak memory 215408 kb
Host smart-0350c42e-2dcd-4910-8ee3-2bf6a3ef79e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116968377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3116968377
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1165079293
Short name T154
Test name
Test status
Simulation time 647800531 ps
CPU time 6.23 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:37 PM PST 24
Peak memory 215348 kb
Host smart-c793ea1e-b613-4303-a66e-0c9a4861b4a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165079293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1165079293
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3785691381
Short name T1102
Test name
Test status
Simulation time 2534719916 ps
CPU time 15.55 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:26 PM PST 24
Peak memory 207416 kb
Host smart-74ccfd07-0645-496e-a05a-910b49462d89
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785691381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3785691381
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2647701484
Short name T112
Test name
Test status
Simulation time 2541060506 ps
CPU time 13.07 seconds
Started Feb 29 01:00:13 PM PST 24
Finished Feb 29 01:00:27 PM PST 24
Peak memory 206804 kb
Host smart-d17dc600-5ca1-466a-a5ab-1b63597c8882
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647701484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2647701484
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2927054041
Short name T81
Test name
Test status
Simulation time 87980676 ps
CPU time 1.15 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:13 PM PST 24
Peak memory 215376 kb
Host smart-22c3a21e-d17b-46ec-8cb2-d6958f0ea647
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927054041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2927054041
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2277734081
Short name T1087
Test name
Test status
Simulation time 157887512 ps
CPU time 1.34 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:14 PM PST 24
Peak memory 207172 kb
Host smart-c8fc4da3-2299-4f17-842b-1505f2361190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277734081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
277734081
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.719395516
Short name T1058
Test name
Test status
Simulation time 36075423 ps
CPU time 0.69 seconds
Started Feb 29 01:00:12 PM PST 24
Finished Feb 29 01:00:14 PM PST 24
Peak memory 203248 kb
Host smart-eef2338c-2c74-4312-a056-e0f914c8381b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719395516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.719395516
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2335961300
Short name T113
Test name
Test status
Simulation time 64241471 ps
CPU time 2.11 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:13 PM PST 24
Peak memory 215452 kb
Host smart-8c0c6736-cb9d-4f63-8694-80b8e5776069
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335961300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2335961300
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2342241152
Short name T1010
Test name
Test status
Simulation time 14147007 ps
CPU time 0.7 seconds
Started Feb 29 01:00:12 PM PST 24
Finished Feb 29 01:00:14 PM PST 24
Peak memory 203544 kb
Host smart-5f447313-3245-4509-b0e6-922fe145af94
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342241152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2342241152
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1502987651
Short name T1020
Test name
Test status
Simulation time 149088724 ps
CPU time 4.12 seconds
Started Feb 29 01:00:07 PM PST 24
Finished Feb 29 01:00:12 PM PST 24
Peak memory 207176 kb
Host smart-c2e91aa3-515e-4fef-ab15-41dc1bc05e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502987651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1502987651
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1413374760
Short name T159
Test name
Test status
Simulation time 205063692 ps
CPU time 13.6 seconds
Started Feb 29 01:00:13 PM PST 24
Finished Feb 29 01:00:27 PM PST 24
Peak memory 215696 kb
Host smart-5a23a27e-b6fc-4cbb-826c-50a65a62f7db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413374760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1413374760
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2853521768
Short name T1026
Test name
Test status
Simulation time 14717909 ps
CPU time 0.69 seconds
Started Feb 29 01:00:36 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 203060 kb
Host smart-65bc5e85-016f-4cd7-a636-a199958ec34a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853521768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2853521768
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3974904955
Short name T1003
Test name
Test status
Simulation time 20062665 ps
CPU time 0.72 seconds
Started Feb 29 01:00:35 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 202948 kb
Host smart-35220b22-b4b9-4687-a38b-d0a14c72c2a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974904955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3974904955
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3001683356
Short name T1029
Test name
Test status
Simulation time 16910390 ps
CPU time 0.75 seconds
Started Feb 29 01:00:35 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 203100 kb
Host smart-68f7d5a6-46c0-43e6-af5c-1f8b8fc3e891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001683356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3001683356
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2692249753
Short name T1015
Test name
Test status
Simulation time 28569900 ps
CPU time 0.78 seconds
Started Feb 29 01:00:35 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 203312 kb
Host smart-ee70e1fe-a3ab-4a19-943f-45698279867e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692249753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2692249753
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1716683066
Short name T1030
Test name
Test status
Simulation time 22341626 ps
CPU time 0.75 seconds
Started Feb 29 01:00:34 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 203156 kb
Host smart-6f4b9f06-335e-404f-a95e-e052db4f31e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716683066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1716683066
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.19454925
Short name T1019
Test name
Test status
Simulation time 23455259 ps
CPU time 0.74 seconds
Started Feb 29 01:00:35 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 203136 kb
Host smart-78623839-53cd-40d9-a244-acdb3292fb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19454925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.19454925
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3694000930
Short name T1031
Test name
Test status
Simulation time 15343675 ps
CPU time 0.76 seconds
Started Feb 29 01:00:33 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 203368 kb
Host smart-988cf8d4-30fa-451d-8f36-3e547ee70860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694000930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3694000930
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3170531986
Short name T1112
Test name
Test status
Simulation time 11289280 ps
CPU time 0.74 seconds
Started Feb 29 01:00:36 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 203360 kb
Host smart-aee2eae5-4961-4ad9-aa1a-ef4463fce2da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170531986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3170531986
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4173548024
Short name T1100
Test name
Test status
Simulation time 19662078 ps
CPU time 0.71 seconds
Started Feb 29 01:00:40 PM PST 24
Finished Feb 29 01:00:41 PM PST 24
Peak memory 202972 kb
Host smart-4f9325e2-bf94-4c1d-87b4-9c6e92088611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173548024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4173548024
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1694312160
Short name T1042
Test name
Test status
Simulation time 33978881 ps
CPU time 0.75 seconds
Started Feb 29 01:00:29 PM PST 24
Finished Feb 29 01:00:30 PM PST 24
Peak memory 203092 kb
Host smart-7f7947dd-d291-407a-83ab-539836c34dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694312160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1694312160
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1816284620
Short name T1035
Test name
Test status
Simulation time 858549573 ps
CPU time 15.72 seconds
Started Feb 29 01:00:13 PM PST 24
Finished Feb 29 01:00:29 PM PST 24
Peak memory 215372 kb
Host smart-ee515a18-a7d4-4d5d-b9d3-f8dabe0f93b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816284620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1816284620
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1822943432
Short name T1072
Test name
Test status
Simulation time 1456366306 ps
CPU time 21.55 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 207160 kb
Host smart-6aa2135d-3b7f-4338-adef-2b44aaff65a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822943432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1822943432
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.104159153
Short name T1066
Test name
Test status
Simulation time 123986580 ps
CPU time 1.22 seconds
Started Feb 29 01:00:12 PM PST 24
Finished Feb 29 01:00:13 PM PST 24
Peak memory 207180 kb
Host smart-c046575b-0bd8-4bac-84bc-9f7c46d0adfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104159153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.104159153
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2593516455
Short name T1018
Test name
Test status
Simulation time 1846662094 ps
CPU time 3.68 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:16 PM PST 24
Peak memory 216516 kb
Host smart-eaa47d7d-fc13-4dc7-87e2-93f74f80b2f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593516455 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2593516455
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.262567168
Short name T1088
Test name
Test status
Simulation time 36964375 ps
CPU time 2.37 seconds
Started Feb 29 01:00:11 PM PST 24
Finished Feb 29 01:00:14 PM PST 24
Peak memory 215332 kb
Host smart-477c1ae7-13fd-4d82-ba22-90c6aa151e11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262567168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.262567168
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2315847192
Short name T1094
Test name
Test status
Simulation time 33200427 ps
CPU time 0.78 seconds
Started Feb 29 01:00:15 PM PST 24
Finished Feb 29 01:00:17 PM PST 24
Peak memory 202956 kb
Host smart-aa345e72-6183-45de-b0d8-1ea7e0c00e78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315847192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
315847192
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.278790373
Short name T118
Test name
Test status
Simulation time 69944137 ps
CPU time 2.47 seconds
Started Feb 29 01:00:15 PM PST 24
Finished Feb 29 01:00:18 PM PST 24
Peak memory 214908 kb
Host smart-66c9c592-6a72-4830-b766-17622ac10c89
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278790373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.278790373
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2095773986
Short name T1028
Test name
Test status
Simulation time 20053798 ps
CPU time 0.69 seconds
Started Feb 29 01:00:13 PM PST 24
Finished Feb 29 01:00:14 PM PST 24
Peak memory 203108 kb
Host smart-d5f34267-545d-4125-9e4c-dddd3cef9662
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095773986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2095773986
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3412832244
Short name T132
Test name
Test status
Simulation time 900640952 ps
CPU time 5.08 seconds
Started Feb 29 01:00:15 PM PST 24
Finished Feb 29 01:00:20 PM PST 24
Peak memory 215120 kb
Host smart-8d1428e4-8789-4356-9ea9-e755815ae2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412832244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3412832244
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1138969914
Short name T1106
Test name
Test status
Simulation time 208863615 ps
CPU time 4.01 seconds
Started Feb 29 01:00:14 PM PST 24
Finished Feb 29 01:00:18 PM PST 24
Peak memory 215480 kb
Host smart-6ecabce0-51e7-4fa5-bb4e-4ceaa711561f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138969914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
138969914
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3239265921
Short name T157
Test name
Test status
Simulation time 788982844 ps
CPU time 12.88 seconds
Started Feb 29 01:00:09 PM PST 24
Finished Feb 29 01:00:22 PM PST 24
Peak memory 215272 kb
Host smart-b3f91e50-cd64-406f-975f-40a6e0458734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239265921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3239265921
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3611270059
Short name T1098
Test name
Test status
Simulation time 17000439 ps
CPU time 0.72 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 202964 kb
Host smart-16b9b503-c3bb-483d-ad77-9d6042878d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611270059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3611270059
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3633475917
Short name T1002
Test name
Test status
Simulation time 16155569 ps
CPU time 0.77 seconds
Started Feb 29 01:00:34 PM PST 24
Finished Feb 29 01:00:35 PM PST 24
Peak memory 203464 kb
Host smart-4ae82c73-88b3-49a6-b71f-c9d9d4d8c327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633475917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3633475917
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1077747201
Short name T1009
Test name
Test status
Simulation time 87771620 ps
CPU time 0.71 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:28 PM PST 24
Peak memory 203156 kb
Host smart-b6bc74d2-31c1-40e6-99ab-9f8d5b2c210e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077747201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1077747201
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1156000220
Short name T1078
Test name
Test status
Simulation time 32493714 ps
CPU time 0.7 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 203092 kb
Host smart-878a49b2-9e7a-4321-aeb0-d9de874b292b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156000220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1156000220
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1235780545
Short name T1075
Test name
Test status
Simulation time 150957058 ps
CPU time 0.72 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 203024 kb
Host smart-5f2da630-f1a9-4f4e-b8b6-8a67d52914b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235780545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1235780545
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2199868222
Short name T1008
Test name
Test status
Simulation time 67910886 ps
CPU time 0.71 seconds
Started Feb 29 01:00:33 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 203464 kb
Host smart-2b34cbfd-2342-4898-806a-45ec2ba50bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199868222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2199868222
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.639474310
Short name T1000
Test name
Test status
Simulation time 45312312 ps
CPU time 0.73 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 203084 kb
Host smart-12f5d3af-ed18-47ff-b533-08610067be06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639474310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.639474310
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3430661658
Short name T1036
Test name
Test status
Simulation time 11433082 ps
CPU time 0.68 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:28 PM PST 24
Peak memory 203016 kb
Host smart-3956171a-62df-4915-a6ce-60b29ca4e76d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430661658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3430661658
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.771176747
Short name T997
Test name
Test status
Simulation time 11293349 ps
CPU time 0.71 seconds
Started Feb 29 01:00:36 PM PST 24
Finished Feb 29 01:00:37 PM PST 24
Peak memory 203356 kb
Host smart-00a12fbd-a38b-4ca2-a963-834188747203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771176747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.771176747
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3352214183
Short name T1022
Test name
Test status
Simulation time 21046811 ps
CPU time 0.73 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 203104 kb
Host smart-f1e3db94-3a85-4ce2-b311-5997bd146a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352214183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3352214183
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1588582726
Short name T1050
Test name
Test status
Simulation time 268610619 ps
CPU time 13.72 seconds
Started Feb 29 01:00:15 PM PST 24
Finished Feb 29 01:00:30 PM PST 24
Peak memory 207160 kb
Host smart-0b6e797a-0b8e-4756-a8a0-8bb7de7a9c79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588582726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1588582726
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1890616330
Short name T121
Test name
Test status
Simulation time 360922632 ps
CPU time 23.47 seconds
Started Feb 29 01:00:16 PM PST 24
Finished Feb 29 01:00:40 PM PST 24
Peak memory 207120 kb
Host smart-485c8188-0a08-4a55-afe5-1cff1eb199a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890616330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1890616330
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1909904060
Short name T80
Test name
Test status
Simulation time 77198147 ps
CPU time 0.95 seconds
Started Feb 29 01:00:16 PM PST 24
Finished Feb 29 01:00:18 PM PST 24
Peak memory 206164 kb
Host smart-5c59c7dd-78f9-4446-9232-1b30610b1730
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909904060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1909904060
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1780774895
Short name T1105
Test name
Test status
Simulation time 59186130 ps
CPU time 3.99 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:31 PM PST 24
Peak memory 217864 kb
Host smart-fc60f5a2-31a2-4117-81b5-363b130e045e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780774895 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1780774895
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3046041903
Short name T1096
Test name
Test status
Simulation time 429340906 ps
CPU time 2.6 seconds
Started Feb 29 01:00:15 PM PST 24
Finished Feb 29 01:00:19 PM PST 24
Peak memory 215368 kb
Host smart-4794f591-6956-4aa9-b72e-946c390adf61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046041903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
046041903
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3073501378
Short name T1032
Test name
Test status
Simulation time 24330752 ps
CPU time 0.75 seconds
Started Feb 29 01:00:14 PM PST 24
Finished Feb 29 01:00:15 PM PST 24
Peak memory 203372 kb
Host smart-8ef970ee-ad8e-4bed-908e-72c2de16e6da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073501378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
073501378
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2749097519
Short name T1037
Test name
Test status
Simulation time 87020093 ps
CPU time 1.7 seconds
Started Feb 29 01:00:21 PM PST 24
Finished Feb 29 01:00:22 PM PST 24
Peak memory 215364 kb
Host smart-be0d9626-86b6-410b-a9ea-11eebab2f61f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749097519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2749097519
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.440240111
Short name T1001
Test name
Test status
Simulation time 16596508 ps
CPU time 0.72 seconds
Started Feb 29 01:00:17 PM PST 24
Finished Feb 29 01:00:18 PM PST 24
Peak memory 203064 kb
Host smart-cbf387e0-f222-4849-b04e-3ca4358d6a0f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440240111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.440240111
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1103214898
Short name T1038
Test name
Test status
Simulation time 317453465 ps
CPU time 4.31 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 215228 kb
Host smart-0d2fb588-0137-45bf-af01-b590e773deee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103214898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1103214898
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2911179749
Short name T1097
Test name
Test status
Simulation time 1489766891 ps
CPU time 5.56 seconds
Started Feb 29 01:00:14 PM PST 24
Finished Feb 29 01:00:20 PM PST 24
Peak memory 215408 kb
Host smart-4ac5d6f5-fff0-4621-92eb-9904fc50dfad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911179749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
911179749
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.65533123
Short name T109
Test name
Test status
Simulation time 1131187426 ps
CPU time 7.31 seconds
Started Feb 29 01:00:12 PM PST 24
Finished Feb 29 01:00:20 PM PST 24
Peak memory 215436 kb
Host smart-bde7c485-6558-4f72-abd8-565c2c6e9137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65533123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_t
l_intg_err.65533123
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2907032671
Short name T1047
Test name
Test status
Simulation time 15802277 ps
CPU time 0.77 seconds
Started Feb 29 01:00:35 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 203076 kb
Host smart-bf42a533-e1af-4a6d-8df5-2383a6ba9799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907032671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2907032671
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3017130569
Short name T1007
Test name
Test status
Simulation time 27915046 ps
CPU time 0.75 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 203104 kb
Host smart-93915af2-9565-44c9-82d5-96b942e7a5f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017130569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3017130569
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2117275197
Short name T1004
Test name
Test status
Simulation time 15368716 ps
CPU time 0.73 seconds
Started Feb 29 01:00:30 PM PST 24
Finished Feb 29 01:00:31 PM PST 24
Peak memory 203172 kb
Host smart-6d9ebbaa-5708-4d1b-817f-a791b9cc119e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117275197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2117275197
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2832112951
Short name T998
Test name
Test status
Simulation time 15133325 ps
CPU time 0.68 seconds
Started Feb 29 01:00:35 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 203056 kb
Host smart-294d3110-dd33-4170-828f-0cb75b442fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832112951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2832112951
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3316571462
Short name T1069
Test name
Test status
Simulation time 19671189 ps
CPU time 0.79 seconds
Started Feb 29 01:00:36 PM PST 24
Finished Feb 29 01:00:37 PM PST 24
Peak memory 203084 kb
Host smart-349125bb-7b85-4fd3-a2c5-28bfe0cb9b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316571462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3316571462
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2263957674
Short name T1068
Test name
Test status
Simulation time 37050250 ps
CPU time 0.73 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 203092 kb
Host smart-47f25d32-3037-4cea-b09e-6b4a08622712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263957674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2263957674
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1505597766
Short name T1024
Test name
Test status
Simulation time 24411163 ps
CPU time 0.77 seconds
Started Feb 29 01:00:33 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 203452 kb
Host smart-61d610df-2c27-4e75-b6cf-4b0adbb549ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505597766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1505597766
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2952818455
Short name T1080
Test name
Test status
Simulation time 34659738 ps
CPU time 0.71 seconds
Started Feb 29 01:00:40 PM PST 24
Finished Feb 29 01:00:41 PM PST 24
Peak memory 203096 kb
Host smart-884dd871-34df-4101-ba8b-d13a20e35a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952818455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2952818455
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2235494936
Short name T1034
Test name
Test status
Simulation time 17914551 ps
CPU time 0.71 seconds
Started Feb 29 01:00:38 PM PST 24
Finished Feb 29 01:00:39 PM PST 24
Peak memory 203436 kb
Host smart-42426b31-6ad2-45fa-a6bc-95ac19c6aecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235494936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2235494936
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1385839467
Short name T1014
Test name
Test status
Simulation time 22628529 ps
CPU time 0.71 seconds
Started Feb 29 01:00:42 PM PST 24
Finished Feb 29 01:00:43 PM PST 24
Peak memory 203328 kb
Host smart-345eee9d-af10-43b4-81f7-0545ee828537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385839467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1385839467
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.606932182
Short name T1027
Test name
Test status
Simulation time 49883375 ps
CPU time 3.6 seconds
Started Feb 29 01:00:25 PM PST 24
Finished Feb 29 01:00:29 PM PST 24
Peak memory 217520 kb
Host smart-8007fef7-3d93-40f5-87bf-eca6aec41c5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606932182 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.606932182
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2761947505
Short name T119
Test name
Test status
Simulation time 402111016 ps
CPU time 2.72 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:30 PM PST 24
Peak memory 215332 kb
Host smart-ff86208d-efa0-40b2-be39-53014b631866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761947505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
761947505
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1714069810
Short name T1109
Test name
Test status
Simulation time 16802285 ps
CPU time 0.73 seconds
Started Feb 29 01:00:26 PM PST 24
Finished Feb 29 01:00:27 PM PST 24
Peak memory 203100 kb
Host smart-168e439d-40c8-4d2a-8bad-e004c7e21ba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714069810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
714069810
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2836342840
Short name T134
Test name
Test status
Simulation time 870819387 ps
CPU time 4.36 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 215556 kb
Host smart-34f3c1e0-5023-415a-88ba-4c44780e1265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836342840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2836342840
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3614115674
Short name T103
Test name
Test status
Simulation time 54798464 ps
CPU time 1.8 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 215592 kb
Host smart-fe1f4e8d-576b-4cff-90d1-b91a5853f72b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614115674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
614115674
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3587059677
Short name T1079
Test name
Test status
Simulation time 1056461133 ps
CPU time 18.18 seconds
Started Feb 29 01:00:29 PM PST 24
Finished Feb 29 01:00:47 PM PST 24
Peak memory 215320 kb
Host smart-0d6c4611-c73c-4a0f-91f2-916124038b28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587059677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3587059677
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.465441536
Short name T91
Test name
Test status
Simulation time 469897210 ps
CPU time 2.78 seconds
Started Feb 29 01:00:26 PM PST 24
Finished Feb 29 01:00:29 PM PST 24
Peak memory 216516 kb
Host smart-fadab2a5-ad14-4ad9-a383-0c1357d9d368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465441536 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.465441536
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2168936240
Short name T1053
Test name
Test status
Simulation time 52217659 ps
CPU time 1.84 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:29 PM PST 24
Peak memory 215272 kb
Host smart-0af0651f-a0c5-4939-948a-3b508e9ff042
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168936240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
168936240
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4025582405
Short name T1101
Test name
Test status
Simulation time 42522553 ps
CPU time 0.72 seconds
Started Feb 29 01:00:31 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 203144 kb
Host smart-494ab2f2-816d-4a2b-b691-09f371d66e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025582405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
025582405
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1047434492
Short name T1113
Test name
Test status
Simulation time 178377359 ps
CPU time 3.92 seconds
Started Feb 29 01:00:28 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 207220 kb
Host smart-69d29c82-b968-4160-a764-3b1171e4a24d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047434492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1047434492
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2128539204
Short name T1083
Test name
Test status
Simulation time 438784059 ps
CPU time 3.12 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:36 PM PST 24
Peak memory 216444 kb
Host smart-8a3074d0-def5-4def-8620-318e2c568cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128539204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
128539204
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1439521222
Short name T1059
Test name
Test status
Simulation time 1069816708 ps
CPU time 12.94 seconds
Started Feb 29 01:00:26 PM PST 24
Finished Feb 29 01:00:39 PM PST 24
Peak memory 215360 kb
Host smart-a7345580-4ca4-4613-a8ea-a4e7a66a60c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439521222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1439521222
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2156871927
Short name T1067
Test name
Test status
Simulation time 201765957 ps
CPU time 3.46 seconds
Started Feb 29 01:00:28 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 217036 kb
Host smart-a3c538da-92ef-40a1-a965-9ba6ea747455
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156871927 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2156871927
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3456780796
Short name T1046
Test name
Test status
Simulation time 418041439 ps
CPU time 2.87 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:30 PM PST 24
Peak memory 207128 kb
Host smart-8edcb2df-5015-4cef-81ea-157727e6c276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456780796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
456780796
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2296286424
Short name T1104
Test name
Test status
Simulation time 59450308 ps
CPU time 0.79 seconds
Started Feb 29 01:00:26 PM PST 24
Finished Feb 29 01:00:27 PM PST 24
Peak memory 203148 kb
Host smart-46d655ef-1d2d-4a9d-9e5e-fa085fb88238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296286424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
296286424
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2554186862
Short name T1065
Test name
Test status
Simulation time 293620551 ps
CPU time 3.99 seconds
Started Feb 29 01:00:28 PM PST 24
Finished Feb 29 01:00:32 PM PST 24
Peak memory 215368 kb
Host smart-b076ae4b-4219-4d59-94e6-3d729d67b0fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554186862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2554186862
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1645121467
Short name T1108
Test name
Test status
Simulation time 302063307 ps
CPU time 2.49 seconds
Started Feb 29 01:00:30 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 215412 kb
Host smart-90f6fd9a-467a-4a78-acb2-68ba5447e348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645121467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
645121467
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.95423757
Short name T153
Test name
Test status
Simulation time 807454805 ps
CPU time 22.16 seconds
Started Feb 29 01:00:29 PM PST 24
Finished Feb 29 01:00:51 PM PST 24
Peak memory 215832 kb
Host smart-e65381ef-74a8-44a4-8012-d580d9b547a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95423757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_t
l_intg_err.95423757
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3349915634
Short name T1062
Test name
Test status
Simulation time 128420973 ps
CPU time 2.88 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:30 PM PST 24
Peak memory 216636 kb
Host smart-7c3f4f66-2227-48d6-b34e-8ce0c6a634d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349915634 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3349915634
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.968840286
Short name T116
Test name
Test status
Simulation time 68169554 ps
CPU time 2.44 seconds
Started Feb 29 01:00:30 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 207080 kb
Host smart-048fb0ad-1b75-41cd-a50e-7ac6a3da7a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968840286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.968840286
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4180271436
Short name T999
Test name
Test status
Simulation time 65217093 ps
CPU time 0.76 seconds
Started Feb 29 01:00:28 PM PST 24
Finished Feb 29 01:00:29 PM PST 24
Peak memory 203064 kb
Host smart-4bdecdef-c2d9-4485-9077-249afb47f979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180271436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4
180271436
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2410489050
Short name T1005
Test name
Test status
Simulation time 224698445 ps
CPU time 4.06 seconds
Started Feb 29 01:00:27 PM PST 24
Finished Feb 29 01:00:31 PM PST 24
Peak memory 215336 kb
Host smart-09478184-9486-43fc-b828-1a6de6440a4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410489050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2410489050
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1111589371
Short name T1107
Test name
Test status
Simulation time 327368731 ps
CPU time 4.78 seconds
Started Feb 29 01:00:28 PM PST 24
Finished Feb 29 01:00:33 PM PST 24
Peak memory 215324 kb
Host smart-c5259d36-7997-4b3a-ae97-4b1ef11fc94c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111589371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
111589371
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4070372966
Short name T160
Test name
Test status
Simulation time 1285898248 ps
CPU time 18.97 seconds
Started Feb 29 01:00:29 PM PST 24
Finished Feb 29 01:00:48 PM PST 24
Peak memory 223036 kb
Host smart-600fea91-60d6-4f56-8a50-9cf6e3ad9de6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070372966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4070372966
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3235400062
Short name T1033
Test name
Test status
Simulation time 24554038 ps
CPU time 1.82 seconds
Started Feb 29 01:00:28 PM PST 24
Finished Feb 29 01:00:30 PM PST 24
Peak memory 215536 kb
Host smart-e5da0d72-0a32-4ced-ba48-79dec5c701c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235400062 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3235400062
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2684551974
Short name T1043
Test name
Test status
Simulation time 162422287 ps
CPU time 1.89 seconds
Started Feb 29 01:00:25 PM PST 24
Finished Feb 29 01:00:27 PM PST 24
Peak memory 207192 kb
Host smart-fbdd69e0-2718-4a57-a86d-77483ade5a00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684551974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
684551974
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2783451564
Short name T1006
Test name
Test status
Simulation time 14840815 ps
CPU time 0.69 seconds
Started Feb 29 01:00:28 PM PST 24
Finished Feb 29 01:00:29 PM PST 24
Peak memory 203444 kb
Host smart-df2e78df-2210-47f7-9a29-233105f59e3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783451564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
783451564
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.291276974
Short name T1057
Test name
Test status
Simulation time 27211226 ps
CPU time 1.79 seconds
Started Feb 29 01:00:32 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 215348 kb
Host smart-11cce3f2-2298-4cbe-a839-3bfd321bc7d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291276974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.291276974
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3713511752
Short name T608
Test name
Test status
Simulation time 15503793 ps
CPU time 0.71 seconds
Started Feb 29 01:35:57 PM PST 24
Finished Feb 29 01:35:58 PM PST 24
Peak memory 204948 kb
Host smart-a5fa3cf6-c1db-47ea-b95f-6e666826536e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713511752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
713511752
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2565832082
Short name T473
Test name
Test status
Simulation time 1222817461 ps
CPU time 9.2 seconds
Started Feb 29 01:35:54 PM PST 24
Finished Feb 29 01:36:04 PM PST 24
Peak memory 234392 kb
Host smart-492aa15c-3a3a-4ee7-ab08-fe55c8da509c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565832082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2565832082
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.65204162
Short name T833
Test name
Test status
Simulation time 12362786 ps
CPU time 0.76 seconds
Started Feb 29 01:35:40 PM PST 24
Finished Feb 29 01:35:42 PM PST 24
Peak memory 204964 kb
Host smart-ba126019-86d0-4c27-8cd0-f7a7181cabb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65204162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.65204162
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1288718093
Short name T260
Test name
Test status
Simulation time 16453785618 ps
CPU time 157.13 seconds
Started Feb 29 01:35:53 PM PST 24
Finished Feb 29 01:38:31 PM PST 24
Peak memory 268044 kb
Host smart-dce7b6c2-7e9d-4d04-ac02-9b4c7a5c1ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288718093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1288718093
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1916189576
Short name T449
Test name
Test status
Simulation time 2038429306 ps
CPU time 34.65 seconds
Started Feb 29 01:35:52 PM PST 24
Finished Feb 29 01:36:27 PM PST 24
Peak memory 221792 kb
Host smart-e5bf8766-dae6-4928-8eea-128d784031c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916189576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1916189576
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.154198479
Short name T4
Test name
Test status
Simulation time 17402261737 ps
CPU time 175.36 seconds
Started Feb 29 01:35:53 PM PST 24
Finished Feb 29 01:38:49 PM PST 24
Peak memory 262844 kb
Host smart-5c89897f-6e40-4d7d-8483-2888515aa9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154198479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
154198479
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2870904927
Short name T476
Test name
Test status
Simulation time 19892497788 ps
CPU time 26.77 seconds
Started Feb 29 01:35:54 PM PST 24
Finished Feb 29 01:36:21 PM PST 24
Peak memory 235516 kb
Host smart-c1d90625-e22f-48c5-a424-a217edb38721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870904927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2870904927
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2708817787
Short name T604
Test name
Test status
Simulation time 562911401 ps
CPU time 3.53 seconds
Started Feb 29 01:35:55 PM PST 24
Finished Feb 29 01:35:59 PM PST 24
Peak memory 224208 kb
Host smart-e9c84451-e704-4360-87ea-20dad517be99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708817787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2708817787
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2070310382
Short name T596
Test name
Test status
Simulation time 1427882596 ps
CPU time 6.4 seconds
Started Feb 29 01:35:54 PM PST 24
Finished Feb 29 01:36:01 PM PST 24
Peak memory 232512 kb
Host smart-b5d84404-9a18-4c0f-bc7f-39fce8fa8aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070310382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2070310382
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.731070676
Short name T765
Test name
Test status
Simulation time 46329282 ps
CPU time 1.11 seconds
Started Feb 29 01:35:35 PM PST 24
Finished Feb 29 01:35:36 PM PST 24
Peak memory 216556 kb
Host smart-fb213c73-767b-4876-8f71-fedc3d860f61
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731070676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.731070676
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3461973413
Short name T243
Test name
Test status
Simulation time 27036629859 ps
CPU time 10.38 seconds
Started Feb 29 01:35:53 PM PST 24
Finished Feb 29 01:36:03 PM PST 24
Peak memory 240612 kb
Host smart-25ea536f-61fd-4880-9322-e7698f598900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461973413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3461973413
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1956397100
Short name T33
Test name
Test status
Simulation time 25622594781 ps
CPU time 14.08 seconds
Started Feb 29 01:35:57 PM PST 24
Finished Feb 29 01:36:12 PM PST 24
Peak memory 217932 kb
Host smart-967e0757-e99c-45dc-80da-8beefb9d841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956397100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1956397100
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1957628034
Short name T778
Test name
Test status
Simulation time 331320274 ps
CPU time 3.8 seconds
Started Feb 29 01:35:52 PM PST 24
Finished Feb 29 01:35:56 PM PST 24
Peak memory 222420 kb
Host smart-8f1f6e4b-731f-40d0-ba4e-99ddf0d9cf83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957628034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1957628034
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3150570772
Short name T895
Test name
Test status
Simulation time 17507664708 ps
CPU time 14.71 seconds
Started Feb 29 01:35:55 PM PST 24
Finished Feb 29 01:36:10 PM PST 24
Peak memory 216120 kb
Host smart-ad213843-1f1b-41aa-ab03-f6df7f7dfd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150570772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3150570772
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3770529227
Short name T851
Test name
Test status
Simulation time 10118645675 ps
CPU time 27.23 seconds
Started Feb 29 01:35:55 PM PST 24
Finished Feb 29 01:36:23 PM PST 24
Peak memory 215220 kb
Host smart-c0905451-0f48-478c-8d39-66a38c0f0398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770529227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3770529227
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.456829777
Short name T629
Test name
Test status
Simulation time 2011858757 ps
CPU time 17.4 seconds
Started Feb 29 01:35:52 PM PST 24
Finished Feb 29 01:36:09 PM PST 24
Peak memory 216248 kb
Host smart-4baa5291-235d-481a-966b-e25eee08b8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456829777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.456829777
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.738674101
Short name T407
Test name
Test status
Simulation time 90072433 ps
CPU time 0.98 seconds
Started Feb 29 01:35:55 PM PST 24
Finished Feb 29 01:35:57 PM PST 24
Peak memory 206172 kb
Host smart-30c9ec19-581f-4f77-9802-c16285e44f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738674101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.738674101
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3743165889
Short name T773
Test name
Test status
Simulation time 7056716658 ps
CPU time 15.42 seconds
Started Feb 29 01:35:54 PM PST 24
Finished Feb 29 01:36:10 PM PST 24
Peak memory 233116 kb
Host smart-3d86fb2f-634c-4304-833e-edf18c773bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743165889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3743165889
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2421814296
Short name T217
Test name
Test status
Simulation time 1001036544 ps
CPU time 3.53 seconds
Started Feb 29 01:35:56 PM PST 24
Finished Feb 29 01:36:00 PM PST 24
Peak memory 217888 kb
Host smart-b5c39be5-140f-4420-b1da-e22cbb9d8a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421814296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2421814296
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3070543762
Short name T503
Test name
Test status
Simulation time 14684569 ps
CPU time 0.75 seconds
Started Feb 29 01:35:54 PM PST 24
Finished Feb 29 01:35:55 PM PST 24
Peak memory 205076 kb
Host smart-3d98c910-eaf6-43d3-8705-9acac84578f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070543762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3070543762
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3907711279
Short name T995
Test name
Test status
Simulation time 146216319302 ps
CPU time 204.13 seconds
Started Feb 29 01:35:57 PM PST 24
Finished Feb 29 01:39:22 PM PST 24
Peak memory 249016 kb
Host smart-0b0ee71d-4898-4c89-b5a3-3c3cf89e5254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907711279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3907711279
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1964317977
Short name T385
Test name
Test status
Simulation time 47947717962 ps
CPU time 108.41 seconds
Started Feb 29 01:35:57 PM PST 24
Finished Feb 29 01:37:45 PM PST 24
Peak memory 258508 kb
Host smart-d7dd59ef-ce51-4060-a589-842c130f6ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964317977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1964317977
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3326753280
Short name T900
Test name
Test status
Simulation time 23727133002 ps
CPU time 34.43 seconds
Started Feb 29 01:36:01 PM PST 24
Finished Feb 29 01:36:37 PM PST 24
Peak memory 245916 kb
Host smart-d990b3fd-edea-449d-9a19-1c36feafff2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326753280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3326753280
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3889739840
Short name T389
Test name
Test status
Simulation time 54909902 ps
CPU time 2.46 seconds
Started Feb 29 01:35:56 PM PST 24
Finished Feb 29 01:35:59 PM PST 24
Peak memory 233048 kb
Host smart-372a34f0-b1c4-4f9d-a4c1-e91b0e13ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889739840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3889739840
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2294484928
Short name T326
Test name
Test status
Simulation time 890828341 ps
CPU time 5.35 seconds
Started Feb 29 01:35:57 PM PST 24
Finished Feb 29 01:36:02 PM PST 24
Peak memory 234876 kb
Host smart-6b7f6862-9de5-4646-8799-9600309e220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294484928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2294484928
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2701479087
Short name T928
Test name
Test status
Simulation time 26072154 ps
CPU time 1.03 seconds
Started Feb 29 01:35:53 PM PST 24
Finished Feb 29 01:35:54 PM PST 24
Peak memory 216504 kb
Host smart-fa7ef31b-f97f-4798-8c23-299fcae31980
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701479087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2701479087
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4134943578
Short name T790
Test name
Test status
Simulation time 21878774920 ps
CPU time 17.22 seconds
Started Feb 29 01:35:52 PM PST 24
Finished Feb 29 01:36:09 PM PST 24
Peak memory 217548 kb
Host smart-d901b8b1-4ef3-48e4-b624-256573a972c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134943578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4134943578
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1206637850
Short name T794
Test name
Test status
Simulation time 2729458659 ps
CPU time 11.63 seconds
Started Feb 29 01:35:55 PM PST 24
Finished Feb 29 01:36:07 PM PST 24
Peak memory 216232 kb
Host smart-df0ed9af-0100-4ed1-833c-a35e84fab949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206637850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1206637850
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.2169246654
Short name T992
Test name
Test status
Simulation time 29997441 ps
CPU time 0.72 seconds
Started Feb 29 01:35:53 PM PST 24
Finished Feb 29 01:35:53 PM PST 24
Peak memory 216024 kb
Host smart-ff0071a0-ab04-4e44-a5cb-1de6eb732367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169246654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.2169246654
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3217955810
Short name T551
Test name
Test status
Simulation time 2307180898 ps
CPU time 5.06 seconds
Started Feb 29 01:36:00 PM PST 24
Finished Feb 29 01:36:07 PM PST 24
Peak memory 222500 kb
Host smart-26d790b5-f6f8-40a8-8daa-41da634fd9b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3217955810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3217955810
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.981869441
Short name T68
Test name
Test status
Simulation time 35356827 ps
CPU time 1.01 seconds
Started Feb 29 01:36:00 PM PST 24
Finished Feb 29 01:36:02 PM PST 24
Peak memory 235280 kb
Host smart-222f0dd4-4b06-4fcf-a476-2b2ed66704ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981869441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.981869441
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1919080148
Short name T841
Test name
Test status
Simulation time 49167080686 ps
CPU time 387.13 seconds
Started Feb 29 01:36:02 PM PST 24
Finished Feb 29 01:42:29 PM PST 24
Peak memory 262604 kb
Host smart-18cd4cbd-5423-42e2-b218-b079ac7e8b14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919080148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1919080148
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1364854881
Short name T715
Test name
Test status
Simulation time 5247552525 ps
CPU time 22.8 seconds
Started Feb 29 01:35:51 PM PST 24
Finished Feb 29 01:36:14 PM PST 24
Peak memory 216204 kb
Host smart-03a48142-234f-4a94-9291-01de3c92e69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364854881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1364854881
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.421330186
Short name T452
Test name
Test status
Simulation time 34988077782 ps
CPU time 12.27 seconds
Started Feb 29 01:35:52 PM PST 24
Finished Feb 29 01:36:04 PM PST 24
Peak memory 216172 kb
Host smart-37930c82-1a09-41f1-a300-b7fa476fbf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421330186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.421330186
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1898098062
Short name T530
Test name
Test status
Simulation time 270136799 ps
CPU time 1.42 seconds
Started Feb 29 01:35:52 PM PST 24
Finished Feb 29 01:35:54 PM PST 24
Peak memory 207916 kb
Host smart-7104fcd8-12be-4eab-b4bf-227beb311e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898098062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1898098062
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3737027903
Short name T399
Test name
Test status
Simulation time 257714920 ps
CPU time 1.09 seconds
Started Feb 29 01:35:53 PM PST 24
Finished Feb 29 01:35:54 PM PST 24
Peak memory 206196 kb
Host smart-42cc4228-b069-4048-be44-42c73f8c48b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737027903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3737027903
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3408427157
Short name T891
Test name
Test status
Simulation time 1220773901 ps
CPU time 8.51 seconds
Started Feb 29 01:35:52 PM PST 24
Finished Feb 29 01:36:01 PM PST 24
Peak memory 234120 kb
Host smart-b4cf6d41-9d59-4f15-9d7e-e18e05762543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408427157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3408427157
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.514818105
Short name T571
Test name
Test status
Simulation time 11390075 ps
CPU time 0.68 seconds
Started Feb 29 01:36:43 PM PST 24
Finished Feb 29 01:36:43 PM PST 24
Peak memory 204804 kb
Host smart-8d6634df-deca-4d02-b28f-cd7edbccdc92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514818105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.514818105
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1613492678
Short name T988
Test name
Test status
Simulation time 80967548 ps
CPU time 3.05 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:36:48 PM PST 24
Peak memory 234324 kb
Host smart-3c9266f7-3757-48c5-91d8-60374b34e0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613492678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1613492678
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3571976729
Short name T977
Test name
Test status
Simulation time 34577440 ps
CPU time 0.78 seconds
Started Feb 29 01:36:48 PM PST 24
Finished Feb 29 01:36:49 PM PST 24
Peak memory 206436 kb
Host smart-b3620e02-b61a-4744-929d-58c806bbcd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571976729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3571976729
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3812344954
Short name T263
Test name
Test status
Simulation time 95503784234 ps
CPU time 479.86 seconds
Started Feb 29 01:36:47 PM PST 24
Finished Feb 29 01:44:47 PM PST 24
Peak memory 266484 kb
Host smart-193c9940-82a3-48ab-9c27-d94b29d57007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812344954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3812344954
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3034568676
Short name T512
Test name
Test status
Simulation time 871793919 ps
CPU time 13.27 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:36:58 PM PST 24
Peak memory 242240 kb
Host smart-c8994f74-4c00-4600-a1b2-d8ba5f11c099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034568676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3034568676
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2165467819
Short name T762
Test name
Test status
Simulation time 294415868 ps
CPU time 3.77 seconds
Started Feb 29 01:36:46 PM PST 24
Finished Feb 29 01:36:51 PM PST 24
Peak memory 224304 kb
Host smart-48c22589-85b9-48a7-b233-210a2ac6bb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165467819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2165467819
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.236045660
Short name T75
Test name
Test status
Simulation time 5233582455 ps
CPU time 17.32 seconds
Started Feb 29 01:36:47 PM PST 24
Finished Feb 29 01:37:05 PM PST 24
Peak memory 232612 kb
Host smart-d432569a-0995-4bc6-90cc-840957a6bc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236045660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.236045660
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2927855827
Short name T814
Test name
Test status
Simulation time 89719101 ps
CPU time 1.04 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:45 PM PST 24
Peak memory 217784 kb
Host smart-c496b57c-bf5e-4ebf-98d1-fd0d20c80609
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927855827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2927855827
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.84687353
Short name T238
Test name
Test status
Simulation time 12786089175 ps
CPU time 25.38 seconds
Started Feb 29 01:36:46 PM PST 24
Finished Feb 29 01:37:11 PM PST 24
Peak memory 228040 kb
Host smart-24d9135a-0103-486c-a29e-e50b2848aa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84687353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.84687353
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1365034515
Short name T885
Test name
Test status
Simulation time 5593801059 ps
CPU time 16.85 seconds
Started Feb 29 01:36:48 PM PST 24
Finished Feb 29 01:37:05 PM PST 24
Peak memory 233764 kb
Host smart-64dfdaf9-84a9-4c64-a964-b0e55069fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365034515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1365034515
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.1713335172
Short name T465
Test name
Test status
Simulation time 17608993 ps
CPU time 0.72 seconds
Started Feb 29 01:36:46 PM PST 24
Finished Feb 29 01:36:47 PM PST 24
Peak memory 216056 kb
Host smart-3ff33bae-4fa5-4267-ae80-0b9d8501bfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713335172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1713335172
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4358854
Short name T541
Test name
Test status
Simulation time 1418172486 ps
CPU time 6.11 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:50 PM PST 24
Peak memory 218496 kb
Host smart-deb67829-9b36-4cf0-a1fd-461b56331031
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4358854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.4358854
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3001940287
Short name T505
Test name
Test status
Simulation time 698486465 ps
CPU time 1.21 seconds
Started Feb 29 01:36:46 PM PST 24
Finished Feb 29 01:36:48 PM PST 24
Peak memory 207320 kb
Host smart-1a73fb25-f334-4276-bac3-f96b25447bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001940287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3001940287
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1963973255
Short name T493
Test name
Test status
Simulation time 1387926453 ps
CPU time 14.29 seconds
Started Feb 29 01:36:49 PM PST 24
Finished Feb 29 01:37:04 PM PST 24
Peak memory 216136 kb
Host smart-75c6dd05-75d3-45c0-9932-daffd5475466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963973255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1963973255
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3529800969
Short name T311
Test name
Test status
Simulation time 3833577226 ps
CPU time 12.57 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:36:58 PM PST 24
Peak memory 216156 kb
Host smart-bc9579ba-01e7-4e7d-abfa-534eeccd707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529800969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3529800969
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2078193250
Short name T788
Test name
Test status
Simulation time 623233904 ps
CPU time 3.43 seconds
Started Feb 29 01:36:47 PM PST 24
Finished Feb 29 01:36:50 PM PST 24
Peak memory 216272 kb
Host smart-edd212b0-554b-4de1-9839-4508310b2b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078193250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2078193250
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2812294086
Short name T738
Test name
Test status
Simulation time 16722051 ps
CPU time 0.75 seconds
Started Feb 29 01:36:50 PM PST 24
Finished Feb 29 01:36:50 PM PST 24
Peak memory 205232 kb
Host smart-d56cfd9c-370c-44d5-8372-1386c1c53940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812294086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2812294086
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.568514639
Short name T749
Test name
Test status
Simulation time 5310267375 ps
CPU time 19.03 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:37:04 PM PST 24
Peak memory 249220 kb
Host smart-20484149-a1e4-48df-9844-04efb5ea321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568514639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.568514639
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2223415174
Short name T763
Test name
Test status
Simulation time 39325415 ps
CPU time 0.7 seconds
Started Feb 29 01:36:53 PM PST 24
Finished Feb 29 01:36:54 PM PST 24
Peak memory 204828 kb
Host smart-7ed9b4c4-95e4-4ebe-8dbb-6e049000a466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223415174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2223415174
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3350479412
Short name T470
Test name
Test status
Simulation time 453870098 ps
CPU time 2.93 seconds
Started Feb 29 01:36:54 PM PST 24
Finished Feb 29 01:36:57 PM PST 24
Peak memory 233968 kb
Host smart-405bc7f1-1e8e-47ef-aca8-1f1b7783e0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350479412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3350479412
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2481558653
Short name T691
Test name
Test status
Simulation time 14677331 ps
CPU time 0.77 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:45 PM PST 24
Peak memory 205988 kb
Host smart-6ec3b127-ac19-4e28-a79f-9fa769aa25e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481558653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2481558653
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3259164450
Short name T182
Test name
Test status
Simulation time 80840346501 ps
CPU time 20.82 seconds
Started Feb 29 01:36:56 PM PST 24
Finished Feb 29 01:37:17 PM PST 24
Peak memory 218496 kb
Host smart-bcee4481-ba0a-4b96-8a28-cb1dada7235e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259164450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3259164450
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2928451057
Short name T661
Test name
Test status
Simulation time 96151419898 ps
CPU time 209.54 seconds
Started Feb 29 01:36:56 PM PST 24
Finished Feb 29 01:40:26 PM PST 24
Peak memory 250112 kb
Host smart-402fef8f-24db-4bb4-a91c-a901b3853161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928451057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2928451057
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4041623024
Short name T235
Test name
Test status
Simulation time 11525753742 ps
CPU time 30.6 seconds
Started Feb 29 01:36:56 PM PST 24
Finished Feb 29 01:37:27 PM PST 24
Peak memory 223648 kb
Host smart-ca986bc2-87e3-48d6-b657-4aaef2ab4021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041623024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4041623024
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1374101654
Short name T210
Test name
Test status
Simulation time 14058584714 ps
CPU time 25.99 seconds
Started Feb 29 01:36:55 PM PST 24
Finished Feb 29 01:37:21 PM PST 24
Peak memory 233532 kb
Host smart-72285e11-8fc4-488c-a3a5-a799b4b769a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374101654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1374101654
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2285871808
Short name T230
Test name
Test status
Simulation time 987224953 ps
CPU time 6.05 seconds
Started Feb 29 01:36:58 PM PST 24
Finished Feb 29 01:37:04 PM PST 24
Peak memory 218200 kb
Host smart-c69c6819-949f-4686-a190-f8e1ef5a3316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285871808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2285871808
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1093267346
Short name T890
Test name
Test status
Simulation time 4159354637 ps
CPU time 12.06 seconds
Started Feb 29 01:36:55 PM PST 24
Finished Feb 29 01:37:07 PM PST 24
Peak memory 232940 kb
Host smart-49a67d68-24c2-4986-9da6-8539dabc7afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093267346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1093267346
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.328845427
Short name T240
Test name
Test status
Simulation time 1935807747 ps
CPU time 7.09 seconds
Started Feb 29 01:36:53 PM PST 24
Finished Feb 29 01:37:00 PM PST 24
Peak memory 217936 kb
Host smart-86279de4-9a8f-48fc-a47b-41f18de52710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328845427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.328845427
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2244743561
Short name T965
Test name
Test status
Simulation time 24950707198 ps
CPU time 17.82 seconds
Started Feb 29 01:36:52 PM PST 24
Finished Feb 29 01:37:10 PM PST 24
Peak memory 232592 kb
Host smart-a25eaae1-3e14-4b55-8d0f-deacf903b894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244743561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2244743561
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3520297154
Short name T614
Test name
Test status
Simulation time 22591078 ps
CPU time 0.73 seconds
Started Feb 29 01:36:57 PM PST 24
Finished Feb 29 01:36:58 PM PST 24
Peak memory 216032 kb
Host smart-af5797b5-5afd-4a75-9372-461f901b7e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520297154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3520297154
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2489213180
Short name T344
Test name
Test status
Simulation time 324339093 ps
CPU time 3.95 seconds
Started Feb 29 01:36:53 PM PST 24
Finished Feb 29 01:36:58 PM PST 24
Peak memory 218516 kb
Host smart-6cb2acd0-f0d1-4d17-8ced-018019ab2469
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2489213180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2489213180
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2142613634
Short name T343
Test name
Test status
Simulation time 57029061 ps
CPU time 0.91 seconds
Started Feb 29 01:36:53 PM PST 24
Finished Feb 29 01:36:54 PM PST 24
Peak memory 206292 kb
Host smart-fc1b646f-5c4f-4494-a7b3-423d609c53c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142613634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2142613634
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.962729765
Short name T936
Test name
Test status
Simulation time 1322459612 ps
CPU time 9.09 seconds
Started Feb 29 01:36:56 PM PST 24
Finished Feb 29 01:37:06 PM PST 24
Peak memory 216376 kb
Host smart-000ea284-e6c8-4c43-a0e5-b67f3dfb91b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962729765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.962729765
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2156745468
Short name T416
Test name
Test status
Simulation time 19946791058 ps
CPU time 21.56 seconds
Started Feb 29 01:36:58 PM PST 24
Finished Feb 29 01:37:20 PM PST 24
Peak memory 216204 kb
Host smart-ff3e8691-1f40-4f84-9abf-bc2c7054f3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156745468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2156745468
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1004804567
Short name T535
Test name
Test status
Simulation time 269235039 ps
CPU time 2.15 seconds
Started Feb 29 01:36:55 PM PST 24
Finished Feb 29 01:36:57 PM PST 24
Peak memory 216124 kb
Host smart-f13fac9a-ff79-4178-9822-1df936a66737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004804567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1004804567
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.4012662309
Short name T316
Test name
Test status
Simulation time 86573785 ps
CPU time 0.89 seconds
Started Feb 29 01:36:56 PM PST 24
Finished Feb 29 01:36:58 PM PST 24
Peak memory 206248 kb
Host smart-01fd9922-027a-4092-8ee8-a7d2fa6d0732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012662309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4012662309
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.274944392
Short name T884
Test name
Test status
Simulation time 932494752 ps
CPU time 5.27 seconds
Started Feb 29 01:36:57 PM PST 24
Finished Feb 29 01:37:02 PM PST 24
Peak memory 232636 kb
Host smart-7d7b898b-f2e0-4e00-a01d-6768834914a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274944392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.274944392
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3745840106
Short name T645
Test name
Test status
Simulation time 16959353 ps
CPU time 0.71 seconds
Started Feb 29 01:36:57 PM PST 24
Finished Feb 29 01:36:58 PM PST 24
Peak memory 205204 kb
Host smart-9f1d94a2-4262-4b6b-a803-f0df538d2e26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745840106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3745840106
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3304427678
Short name T475
Test name
Test status
Simulation time 4543634099 ps
CPU time 6.67 seconds
Started Feb 29 01:37:02 PM PST 24
Finished Feb 29 01:37:09 PM PST 24
Peak memory 224392 kb
Host smart-20d2eb59-fa82-40d3-b4fd-cb2ba7b01c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304427678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3304427678
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2503639852
Short name T531
Test name
Test status
Simulation time 16031529 ps
CPU time 0.75 seconds
Started Feb 29 01:36:54 PM PST 24
Finished Feb 29 01:36:55 PM PST 24
Peak memory 204952 kb
Host smart-4a8b212a-2df6-405d-8518-9a650658064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503639852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2503639852
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1535695664
Short name T665
Test name
Test status
Simulation time 42478119272 ps
CPU time 70.47 seconds
Started Feb 29 01:37:03 PM PST 24
Finished Feb 29 01:38:13 PM PST 24
Peak memory 256008 kb
Host smart-0a563afc-ae95-4836-abdb-7894f8c148fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535695664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1535695664
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.869883918
Short name T632
Test name
Test status
Simulation time 15093601361 ps
CPU time 33.76 seconds
Started Feb 29 01:36:54 PM PST 24
Finished Feb 29 01:37:28 PM PST 24
Peak memory 221148 kb
Host smart-1d63cf87-7371-4a39-8a59-0110a5f04777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869883918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.869883918
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2298534053
Short name T467
Test name
Test status
Simulation time 9921450279 ps
CPU time 66.88 seconds
Started Feb 29 01:36:55 PM PST 24
Finished Feb 29 01:38:02 PM PST 24
Peak memory 232596 kb
Host smart-dbfec2a6-88c4-4133-9e73-ff009b094367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298534053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2298534053
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2626731399
Short name T543
Test name
Test status
Simulation time 3474809317 ps
CPU time 7.41 seconds
Started Feb 29 01:36:56 PM PST 24
Finished Feb 29 01:37:04 PM PST 24
Peak memory 224332 kb
Host smart-8d9e5a18-bed3-4110-9e90-3741d9764f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626731399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2626731399
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2460687179
Short name T646
Test name
Test status
Simulation time 947634642 ps
CPU time 6.75 seconds
Started Feb 29 01:36:54 PM PST 24
Finished Feb 29 01:37:00 PM PST 24
Peak memory 237328 kb
Host smart-1411a75b-f9aa-4e96-ac46-e2b9d65d1256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460687179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2460687179
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1504475299
Short name T23
Test name
Test status
Simulation time 180682548 ps
CPU time 1.13 seconds
Started Feb 29 01:36:58 PM PST 24
Finished Feb 29 01:36:59 PM PST 24
Peak memory 216584 kb
Host smart-2af522a5-0244-4b0d-8f3c-a2d84b8d1588
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504475299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1504475299
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1888044868
Short name T39
Test name
Test status
Simulation time 6701379310 ps
CPU time 19.59 seconds
Started Feb 29 01:36:56 PM PST 24
Finished Feb 29 01:37:16 PM PST 24
Peak memory 232800 kb
Host smart-10a3dfe7-e4bd-44b9-ac61-6b6e319dfee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888044868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1888044868
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1305758010
Short name T336
Test name
Test status
Simulation time 3503863467 ps
CPU time 10.02 seconds
Started Feb 29 01:36:57 PM PST 24
Finished Feb 29 01:37:07 PM PST 24
Peak memory 224420 kb
Host smart-6164f5a5-de72-4763-ad88-1d28dc0cbecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305758010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1305758010
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.1293389550
Short name T66
Test name
Test status
Simulation time 15112505 ps
CPU time 0.76 seconds
Started Feb 29 01:36:57 PM PST 24
Finished Feb 29 01:36:58 PM PST 24
Peak memory 216024 kb
Host smart-23dec5cb-8449-4932-bfde-75949d5b98c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293389550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.1293389550
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3900169364
Short name T460
Test name
Test status
Simulation time 1921617033 ps
CPU time 4.59 seconds
Started Feb 29 01:36:56 PM PST 24
Finished Feb 29 01:37:01 PM PST 24
Peak memory 222524 kb
Host smart-9e2992cb-bc2c-4634-a310-03d5f7f29eb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3900169364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3900169364
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1149677647
Short name T793
Test name
Test status
Simulation time 34015889511 ps
CPU time 43.14 seconds
Started Feb 29 01:36:56 PM PST 24
Finished Feb 29 01:37:40 PM PST 24
Peak memory 216272 kb
Host smart-895f8a45-7afd-492a-9436-9eff646618dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149677647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1149677647
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3241106211
Short name T412
Test name
Test status
Simulation time 42186073577 ps
CPU time 31.06 seconds
Started Feb 29 01:36:54 PM PST 24
Finished Feb 29 01:37:25 PM PST 24
Peak memory 216208 kb
Host smart-01888231-c866-4f7b-9869-f65a4d3f8997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241106211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3241106211
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.662597856
Short name T329
Test name
Test status
Simulation time 17275202 ps
CPU time 0.75 seconds
Started Feb 29 01:36:54 PM PST 24
Finished Feb 29 01:36:55 PM PST 24
Peak memory 205192 kb
Host smart-5dc0eb53-5b67-4475-957a-b063d777e1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662597856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.662597856
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2820896880
Short name T832
Test name
Test status
Simulation time 145659232 ps
CPU time 0.92 seconds
Started Feb 29 01:36:57 PM PST 24
Finished Feb 29 01:36:58 PM PST 24
Peak memory 206224 kb
Host smart-444822d4-3368-469f-8c94-01c500b083b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820896880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2820896880
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.852724446
Short name T867
Test name
Test status
Simulation time 11255866819 ps
CPU time 11.4 seconds
Started Feb 29 01:37:09 PM PST 24
Finished Feb 29 01:37:21 PM PST 24
Peak memory 237388 kb
Host smart-556683d1-d7a9-40dc-a05f-841f7424e3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852724446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.852724446
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2920556859
Short name T593
Test name
Test status
Simulation time 15202397 ps
CPU time 0.71 seconds
Started Feb 29 01:37:06 PM PST 24
Finished Feb 29 01:37:07 PM PST 24
Peak memory 204832 kb
Host smart-27ecc1a5-515c-4384-8adb-acc0b5371926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920556859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2920556859
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1862393033
Short name T391
Test name
Test status
Simulation time 3264950266 ps
CPU time 12.29 seconds
Started Feb 29 01:36:59 PM PST 24
Finished Feb 29 01:37:12 PM PST 24
Peak memory 234644 kb
Host smart-34be011f-d13c-453e-bb80-2ceb88fb2621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862393033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1862393033
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2741192525
Short name T642
Test name
Test status
Simulation time 19281118 ps
CPU time 0.76 seconds
Started Feb 29 01:37:02 PM PST 24
Finished Feb 29 01:37:03 PM PST 24
Peak memory 206292 kb
Host smart-81acd497-4f71-4e1d-b17a-a4e1c5641bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741192525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2741192525
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2919504117
Short name T204
Test name
Test status
Simulation time 1132783497 ps
CPU time 16.49 seconds
Started Feb 29 01:37:06 PM PST 24
Finished Feb 29 01:37:23 PM PST 24
Peak memory 240620 kb
Host smart-1869e2ff-4e3f-499c-8cc0-c536c9202a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919504117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2919504117
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2837592908
Short name T188
Test name
Test status
Simulation time 41922848160 ps
CPU time 221.9 seconds
Started Feb 29 01:36:59 PM PST 24
Finished Feb 29 01:40:41 PM PST 24
Peak memory 249700 kb
Host smart-4638b4d0-a78e-470b-bae6-6c7756b6d873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837592908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2837592908
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1811329351
Short name T266
Test name
Test status
Simulation time 128409133386 ps
CPU time 428.54 seconds
Started Feb 29 01:36:56 PM PST 24
Finished Feb 29 01:44:05 PM PST 24
Peak memory 255932 kb
Host smart-40bcdca6-02bf-4239-95f3-ce5c9c45e6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811329351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1811329351
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3460023560
Short name T877
Test name
Test status
Simulation time 918006134 ps
CPU time 9.79 seconds
Started Feb 29 01:37:06 PM PST 24
Finished Feb 29 01:37:16 PM PST 24
Peak memory 235876 kb
Host smart-389b653c-e902-4401-afca-1f7f525c172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460023560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3460023560
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4037153799
Short name T787
Test name
Test status
Simulation time 478610359 ps
CPU time 4.77 seconds
Started Feb 29 01:37:00 PM PST 24
Finished Feb 29 01:37:05 PM PST 24
Peak memory 218708 kb
Host smart-eac71d86-7653-4ff0-ad5a-9f0da4650959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037153799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4037153799
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1698610017
Short name T455
Test name
Test status
Simulation time 3580293381 ps
CPU time 12.02 seconds
Started Feb 29 01:37:00 PM PST 24
Finished Feb 29 01:37:12 PM PST 24
Peak memory 232608 kb
Host smart-8571ebb1-0adb-4715-94e1-41f08867925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698610017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1698610017
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.744473554
Short name T434
Test name
Test status
Simulation time 25617540 ps
CPU time 1.01 seconds
Started Feb 29 01:36:55 PM PST 24
Finished Feb 29 01:36:56 PM PST 24
Peak memory 217808 kb
Host smart-fafa018c-b4e6-454c-ac38-c5c3547acef3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744473554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.744473554
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2798214419
Short name T451
Test name
Test status
Simulation time 7720647510 ps
CPU time 11.14 seconds
Started Feb 29 01:37:00 PM PST 24
Finished Feb 29 01:37:11 PM PST 24
Peak memory 233248 kb
Host smart-1db95a77-4f58-40db-a1b1-f117257e2e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798214419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2798214419
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3310041752
Short name T621
Test name
Test status
Simulation time 2858743679 ps
CPU time 6.56 seconds
Started Feb 29 01:36:55 PM PST 24
Finished Feb 29 01:37:02 PM PST 24
Peak memory 234248 kb
Host smart-9e5833f4-4a46-4f61-a8f2-233070ae39f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310041752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3310041752
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.2607878102
Short name T592
Test name
Test status
Simulation time 22591081 ps
CPU time 0.73 seconds
Started Feb 29 01:37:05 PM PST 24
Finished Feb 29 01:37:07 PM PST 24
Peak memory 216032 kb
Host smart-de5fd055-7070-4fb0-8d14-76e8d766d703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607878102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2607878102
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3262781083
Short name T993
Test name
Test status
Simulation time 3563896679 ps
CPU time 4.78 seconds
Started Feb 29 01:36:58 PM PST 24
Finished Feb 29 01:37:03 PM PST 24
Peak memory 222568 kb
Host smart-c702062f-6dd7-48d8-b0b4-00e63b18afab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3262781083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3262781083
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.769278527
Short name T30
Test name
Test status
Simulation time 2380224556 ps
CPU time 25.79 seconds
Started Feb 29 01:37:06 PM PST 24
Finished Feb 29 01:37:32 PM PST 24
Peak memory 216192 kb
Host smart-539c8bf9-b7a2-44d7-ae93-c5fdf860ca21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769278527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.769278527
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4199444507
Short name T740
Test name
Test status
Simulation time 73478827985 ps
CPU time 26.4 seconds
Started Feb 29 01:37:00 PM PST 24
Finished Feb 29 01:37:26 PM PST 24
Peak memory 216224 kb
Host smart-aa722b0c-5790-4c76-b0a9-ebfae91d0f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199444507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4199444507
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.573206075
Short name T802
Test name
Test status
Simulation time 591314623 ps
CPU time 5.18 seconds
Started Feb 29 01:37:06 PM PST 24
Finished Feb 29 01:37:11 PM PST 24
Peak memory 216200 kb
Host smart-4de4e89f-60d2-4d07-a825-f70a0a27da04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573206075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.573206075
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1388302922
Short name T559
Test name
Test status
Simulation time 38780297 ps
CPU time 0.91 seconds
Started Feb 29 01:36:55 PM PST 24
Finished Feb 29 01:36:56 PM PST 24
Peak memory 206224 kb
Host smart-15feae05-545e-44ae-bdf3-a4ca67603eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388302922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1388302922
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3277588487
Short name T252
Test name
Test status
Simulation time 1786959756 ps
CPU time 9.6 seconds
Started Feb 29 01:36:59 PM PST 24
Finished Feb 29 01:37:09 PM PST 24
Peak memory 233504 kb
Host smart-0b0ee49e-93cf-40ef-83d8-3ad54849ecf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277588487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3277588487
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2494078194
Short name T375
Test name
Test status
Simulation time 15559080 ps
CPU time 0.73 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:15 PM PST 24
Peak memory 204120 kb
Host smart-494ab99c-139e-4ef8-a062-9a390ee68cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494078194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2494078194
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1445834065
Short name T676
Test name
Test status
Simulation time 10959698512 ps
CPU time 5.95 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:20 PM PST 24
Peak memory 224340 kb
Host smart-f6716a28-9bb4-4f3d-ac58-5f7e44c1ffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445834065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1445834065
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.768647645
Short name T862
Test name
Test status
Simulation time 51753645 ps
CPU time 0.77 seconds
Started Feb 29 01:36:59 PM PST 24
Finished Feb 29 01:37:00 PM PST 24
Peak memory 204944 kb
Host smart-c5880782-e215-4b56-a924-b9b434cc3aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768647645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.768647645
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2166489094
Short name T198
Test name
Test status
Simulation time 114594086709 ps
CPU time 284.1 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:41:58 PM PST 24
Peak memory 263760 kb
Host smart-09757f7b-76e5-4e03-bca9-3878e2fc7ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166489094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2166489094
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3068859837
Short name T268
Test name
Test status
Simulation time 90347530554 ps
CPU time 156.93 seconds
Started Feb 29 01:37:09 PM PST 24
Finished Feb 29 01:39:48 PM PST 24
Peak memory 254600 kb
Host smart-4986b0e8-6889-4f73-83b9-5bb8acd245a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068859837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3068859837
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.730806638
Short name T494
Test name
Test status
Simulation time 8240967444 ps
CPU time 32.14 seconds
Started Feb 29 01:37:14 PM PST 24
Finished Feb 29 01:37:46 PM PST 24
Peak memory 238408 kb
Host smart-0ed483b2-a181-47bc-9a91-766b1bed75c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730806638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.730806638
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1307233113
Short name T469
Test name
Test status
Simulation time 8966234776 ps
CPU time 9.68 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:24 PM PST 24
Peak memory 217760 kb
Host smart-e389e73f-c8eb-4954-b442-49db54970aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307233113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1307233113
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.26397123
Short name T504
Test name
Test status
Simulation time 4288822714 ps
CPU time 19.88 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:32 PM PST 24
Peak memory 243696 kb
Host smart-cb7530bc-6b0e-4f50-a671-9656927e55a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26397123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.26397123
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1769226704
Short name T403
Test name
Test status
Simulation time 45929624 ps
CPU time 1.05 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:15 PM PST 24
Peak memory 216456 kb
Host smart-ed702523-cf29-40bb-95a0-c8cec93b1983
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769226704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1769226704
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1512015884
Short name T954
Test name
Test status
Simulation time 1644029955 ps
CPU time 3.31 seconds
Started Feb 29 01:37:23 PM PST 24
Finished Feb 29 01:37:26 PM PST 24
Peak memory 232956 kb
Host smart-c73ab19c-b7c0-4a63-b221-da3f4d910ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512015884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1512015884
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1928956288
Short name T564
Test name
Test status
Simulation time 512633139 ps
CPU time 4.58 seconds
Started Feb 29 01:37:10 PM PST 24
Finished Feb 29 01:37:16 PM PST 24
Peak memory 232504 kb
Host smart-4c4f7fd6-bdc4-4137-bf2f-4a900101dc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928956288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1928956288
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.88005993
Short name T870
Test name
Test status
Simulation time 19093842 ps
CPU time 0.75 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:14 PM PST 24
Peak memory 215984 kb
Host smart-ddf3a432-80bd-42d7-942c-ff59833b7372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88005993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.88005993
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3183591643
Short name T462
Test name
Test status
Simulation time 4981939876 ps
CPU time 6.02 seconds
Started Feb 29 01:37:14 PM PST 24
Finished Feb 29 01:37:20 PM PST 24
Peak memory 220656 kb
Host smart-9f039dcd-c982-4f42-834a-b570455b9ca1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3183591643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3183591643
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3517101858
Short name T272
Test name
Test status
Simulation time 294154050968 ps
CPU time 447.07 seconds
Started Feb 29 01:37:11 PM PST 24
Finished Feb 29 01:44:39 PM PST 24
Peak memory 275568 kb
Host smart-03fd49a0-0b9d-423b-a6b1-e799cc998e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517101858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3517101858
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3170637323
Short name T971
Test name
Test status
Simulation time 110156127341 ps
CPU time 43.73 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:58 PM PST 24
Peak memory 216248 kb
Host smart-76292de4-4927-4d0f-a778-f45e8eb12131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170637323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3170637323
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3428323160
Short name T562
Test name
Test status
Simulation time 655825761 ps
CPU time 4.63 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:18 PM PST 24
Peak memory 216084 kb
Host smart-01302684-6abb-46de-ab24-b7dd6a90acd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428323160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3428323160
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3172898631
Short name T916
Test name
Test status
Simulation time 19378329 ps
CPU time 0.87 seconds
Started Feb 29 01:37:13 PM PST 24
Finished Feb 29 01:37:15 PM PST 24
Peak memory 206008 kb
Host smart-4c16adfe-4dbb-4a94-91ab-36d1e58eba07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172898631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3172898631
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.264228484
Short name T410
Test name
Test status
Simulation time 44279613 ps
CPU time 0.8 seconds
Started Feb 29 01:37:13 PM PST 24
Finished Feb 29 01:37:15 PM PST 24
Peak memory 205196 kb
Host smart-1ef85f06-bbee-48d5-898b-020b27a96ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264228484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.264228484
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2377073159
Short name T580
Test name
Test status
Simulation time 3165755118 ps
CPU time 6.8 seconds
Started Feb 29 01:37:17 PM PST 24
Finished Feb 29 01:37:24 PM PST 24
Peak memory 217900 kb
Host smart-12b9c61a-4aeb-4c89-8def-f009992bf752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377073159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2377073159
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4081846231
Short name T627
Test name
Test status
Simulation time 20011100 ps
CPU time 0.7 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 204204 kb
Host smart-5e930757-67dd-46cb-8a8b-e98dd6e6deb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081846231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4081846231
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3288361781
Short name T215
Test name
Test status
Simulation time 58905101 ps
CPU time 2.51 seconds
Started Feb 29 01:37:31 PM PST 24
Finished Feb 29 01:37:33 PM PST 24
Peak memory 216628 kb
Host smart-7015c694-5312-46a3-80b5-511ff5b24af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288361781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3288361781
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4160255155
Short name T409
Test name
Test status
Simulation time 71062418 ps
CPU time 0.78 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:15 PM PST 24
Peak memory 205984 kb
Host smart-a29cadae-aac0-4c8f-99c2-0484e9ca3c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160255155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4160255155
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.89632371
Short name T173
Test name
Test status
Simulation time 28531727736 ps
CPU time 77.5 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:38:43 PM PST 24
Peak memory 240712 kb
Host smart-fa0724c7-ea09-4c8e-8986-eaa0f52e71a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89632371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.89632371
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.927036212
Short name T679
Test name
Test status
Simulation time 2795616022 ps
CPU time 27.91 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:53 PM PST 24
Peak memory 233852 kb
Host smart-cde6ed73-fbc0-4d52-a3d1-4462c3abc729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927036212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.927036212
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2832354002
Short name T280
Test name
Test status
Simulation time 38099566359 ps
CPU time 68.06 seconds
Started Feb 29 01:37:23 PM PST 24
Finished Feb 29 01:38:32 PM PST 24
Peak memory 252888 kb
Host smart-4801b4fa-6f22-4685-aca7-4febc28086be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832354002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2832354002
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1264706180
Short name T2
Test name
Test status
Simulation time 1544051517 ps
CPU time 12.75 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:38 PM PST 24
Peak memory 236372 kb
Host smart-8de0fd97-6d74-4a9e-8894-270cf72b7d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264706180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1264706180
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1094464435
Short name T185
Test name
Test status
Simulation time 12370737167 ps
CPU time 12.3 seconds
Started Feb 29 01:37:14 PM PST 24
Finished Feb 29 01:37:26 PM PST 24
Peak memory 233204 kb
Host smart-49848799-b93d-4053-a7c8-7f4c05411b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094464435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1094464435
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1161077006
Short name T917
Test name
Test status
Simulation time 451851478 ps
CPU time 6.76 seconds
Started Feb 29 01:37:24 PM PST 24
Finished Feb 29 01:37:31 PM PST 24
Peak memory 227932 kb
Host smart-20b0eb79-0533-4ed0-bfc1-c2c85e2981d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161077006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1161077006
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1127294865
Short name T653
Test name
Test status
Simulation time 25544180 ps
CPU time 1 seconds
Started Feb 29 01:37:11 PM PST 24
Finished Feb 29 01:37:12 PM PST 24
Peak memory 217804 kb
Host smart-d03ff54e-90c2-47e8-ad67-a80a4f69bcb9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127294865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1127294865
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1091992536
Short name T808
Test name
Test status
Simulation time 4940631615 ps
CPU time 9.83 seconds
Started Feb 29 01:37:11 PM PST 24
Finished Feb 29 01:37:21 PM PST 24
Peak memory 224264 kb
Host smart-0ef00182-a634-4735-9a7c-08fc46190b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091992536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1091992536
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.133592936
Short name T231
Test name
Test status
Simulation time 1962129858 ps
CPU time 7.94 seconds
Started Feb 29 01:37:13 PM PST 24
Finished Feb 29 01:37:22 PM PST 24
Peak memory 216144 kb
Host smart-5f5dc9df-51aa-4393-a5dc-0029d8772a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133592936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.133592936
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.746702319
Short name T539
Test name
Test status
Simulation time 24569019 ps
CPU time 0.76 seconds
Started Feb 29 01:37:13 PM PST 24
Finished Feb 29 01:37:15 PM PST 24
Peak memory 216012 kb
Host smart-21ffe3f5-0d06-4922-bdeb-8a802d0ed19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746702319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.746702319
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1442699241
Short name T831
Test name
Test status
Simulation time 238490725 ps
CPU time 4.08 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 222488 kb
Host smart-4f6cff70-a030-4e36-b027-2d508f4bc441
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1442699241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1442699241
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2544384804
Short name T927
Test name
Test status
Simulation time 31153036 ps
CPU time 0.91 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 205024 kb
Host smart-ec535545-3285-4968-9440-53cb265ed660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544384804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2544384804
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.183713114
Short name T525
Test name
Test status
Simulation time 2085029930 ps
CPU time 22.56 seconds
Started Feb 29 01:37:14 PM PST 24
Finished Feb 29 01:37:37 PM PST 24
Peak memory 216048 kb
Host smart-6be49446-6497-4084-a0a9-ad2a8546cbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183713114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.183713114
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1745249122
Short name T931
Test name
Test status
Simulation time 432925143 ps
CPU time 2.06 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:15 PM PST 24
Peak memory 215680 kb
Host smart-9fee02b6-ed2d-4af9-8074-54328445e842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745249122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1745249122
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.884614640
Short name T487
Test name
Test status
Simulation time 14543781 ps
CPU time 0.83 seconds
Started Feb 29 01:37:12 PM PST 24
Finished Feb 29 01:37:15 PM PST 24
Peak memory 205220 kb
Host smart-8bc36a8c-5ef8-4695-b812-04ec3186a314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884614640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.884614640
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1907396141
Short name T674
Test name
Test status
Simulation time 147932369 ps
CPU time 0.98 seconds
Started Feb 29 01:37:13 PM PST 24
Finished Feb 29 01:37:15 PM PST 24
Peak memory 205192 kb
Host smart-a1d826e7-8e09-4a9f-bb79-ab048d5e7ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907396141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1907396141
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3094463915
Short name T939
Test name
Test status
Simulation time 4055872504 ps
CPU time 7.96 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:36 PM PST 24
Peak memory 216384 kb
Host smart-cadb3ecb-8c98-47c8-a9ff-d2bf40b18356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094463915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3094463915
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.69708448
Short name T829
Test name
Test status
Simulation time 47758257 ps
CPU time 0.73 seconds
Started Feb 29 01:37:26 PM PST 24
Finished Feb 29 01:37:27 PM PST 24
Peak memory 204844 kb
Host smart-7079f0ca-83cf-4185-a54e-dc77db8236af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69708448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.69708448
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2115044612
Short name T545
Test name
Test status
Simulation time 32367186459 ps
CPU time 10.79 seconds
Started Feb 29 01:37:24 PM PST 24
Finished Feb 29 01:37:35 PM PST 24
Peak memory 219596 kb
Host smart-6a6a1c15-8602-47f8-95f4-86a0286bc050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115044612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2115044612
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2098436193
Short name T306
Test name
Test status
Simulation time 21822914 ps
CPU time 0.84 seconds
Started Feb 29 01:37:26 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 206320 kb
Host smart-80dce7f7-03e2-4b20-8822-6dadcb364012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098436193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2098436193
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4200145492
Short name T149
Test name
Test status
Simulation time 7158137132 ps
CPU time 63.27 seconds
Started Feb 29 01:37:30 PM PST 24
Finished Feb 29 01:38:34 PM PST 24
Peak memory 249020 kb
Host smart-999ca9aa-94a3-4e60-912e-d2296720d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200145492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4200145492
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1798037812
Short name T401
Test name
Test status
Simulation time 6372696784 ps
CPU time 77.59 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:38:46 PM PST 24
Peak memory 249212 kb
Host smart-4a176250-86fc-45bf-87e9-e66d2cd4f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798037812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1798037812
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2440802884
Short name T196
Test name
Test status
Simulation time 7335520292 ps
CPU time 63.71 seconds
Started Feb 29 01:37:24 PM PST 24
Finished Feb 29 01:38:28 PM PST 24
Peak memory 240768 kb
Host smart-e89ab26a-a43b-4d91-a463-88ef0407492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440802884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2440802884
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1560317804
Short name T502
Test name
Test status
Simulation time 1631638259 ps
CPU time 5.66 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:34 PM PST 24
Peak memory 222744 kb
Host smart-88a52ae2-635b-4ed0-865f-fcaa8bd44c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560317804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1560317804
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3838758693
Short name T633
Test name
Test status
Simulation time 1995946938 ps
CPU time 5.33 seconds
Started Feb 29 01:37:31 PM PST 24
Finished Feb 29 01:37:37 PM PST 24
Peak memory 218340 kb
Host smart-6b966aa4-f82f-4777-a8c8-0ca3cd5a0a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838758693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3838758693
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3187464525
Short name T496
Test name
Test status
Simulation time 1750775322 ps
CPU time 9.97 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:35 PM PST 24
Peak memory 240620 kb
Host smart-e71a9c5d-4194-4876-808f-8445ca959622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187464525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3187464525
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1824632675
Short name T25
Test name
Test status
Simulation time 45498118 ps
CPU time 0.99 seconds
Started Feb 29 01:37:26 PM PST 24
Finished Feb 29 01:37:27 PM PST 24
Peak memory 216548 kb
Host smart-59979013-8d3d-44bd-90a2-9bee50dc0762
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824632675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1824632675
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3556779961
Short name T242
Test name
Test status
Simulation time 2084704198 ps
CPU time 9.5 seconds
Started Feb 29 01:37:29 PM PST 24
Finished Feb 29 01:37:39 PM PST 24
Peak memory 249400 kb
Host smart-13d66b4d-473d-47ac-a8a7-c803c5f2073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556779961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3556779961
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.777913076
Short name T806
Test name
Test status
Simulation time 43944902 ps
CPU time 2.67 seconds
Started Feb 29 01:37:23 PM PST 24
Finished Feb 29 01:37:26 PM PST 24
Peak memory 232492 kb
Host smart-de3c6154-c56d-4843-a561-d4f421131783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777913076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.777913076
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2209440756
Short name T940
Test name
Test status
Simulation time 18847815 ps
CPU time 0.73 seconds
Started Feb 29 01:37:29 PM PST 24
Finished Feb 29 01:37:30 PM PST 24
Peak memory 216160 kb
Host smart-c00c24a6-80bf-497c-aff8-63b22f9c2789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209440756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2209440756
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2966209739
Short name T764
Test name
Test status
Simulation time 1170147320 ps
CPU time 6.36 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:32 PM PST 24
Peak memory 221264 kb
Host smart-a48254b0-ad8b-4e0d-8dfa-b81007e2da65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2966209739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2966209739
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2818091519
Short name T73
Test name
Test status
Simulation time 50772941 ps
CPU time 1.09 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 206564 kb
Host smart-826b335a-3e08-418e-9944-619545182b2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818091519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2818091519
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3103087027
Short name T546
Test name
Test status
Simulation time 8059093170 ps
CPU time 12.11 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:37 PM PST 24
Peak memory 216212 kb
Host smart-70ed0759-5c27-41fe-b4c2-c73d2f3b75e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103087027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3103087027
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2590622192
Short name T405
Test name
Test status
Simulation time 1905198824 ps
CPU time 2.44 seconds
Started Feb 29 01:37:24 PM PST 24
Finished Feb 29 01:37:26 PM PST 24
Peak memory 207684 kb
Host smart-6b7aa227-cb61-4d14-b3fd-7468af698910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590622192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2590622192
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1249910553
Short name T446
Test name
Test status
Simulation time 49521091 ps
CPU time 1.19 seconds
Started Feb 29 01:37:26 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 206460 kb
Host smart-a9ec1c2b-b583-4ed2-a5d0-51885a4412dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249910553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1249910553
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2764386394
Short name T703
Test name
Test status
Simulation time 42483753 ps
CPU time 0.95 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:26 PM PST 24
Peak memory 205192 kb
Host smart-7bc38e30-49f3-4b88-9411-e784b045da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764386394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2764386394
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.457899899
Short name T636
Test name
Test status
Simulation time 24305465567 ps
CPU time 21.86 seconds
Started Feb 29 01:37:24 PM PST 24
Finished Feb 29 01:37:46 PM PST 24
Peak memory 234152 kb
Host smart-afbaf2e0-60c9-42a0-9673-539595795771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457899899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.457899899
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1225752132
Short name T147
Test name
Test status
Simulation time 18982494 ps
CPU time 0.76 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:26 PM PST 24
Peak memory 204280 kb
Host smart-5ce71b3f-d930-4a3f-8604-359c118b36f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225752132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1225752132
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1225626721
Short name T259
Test name
Test status
Simulation time 357145103 ps
CPU time 4.33 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:32 PM PST 24
Peak memory 232924 kb
Host smart-986c823d-c8f6-448f-8e62-a1d18cecbe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225626721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1225626721
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2190121822
Short name T456
Test name
Test status
Simulation time 68466987 ps
CPU time 0.85 seconds
Started Feb 29 01:37:26 PM PST 24
Finished Feb 29 01:37:27 PM PST 24
Peak memory 205964 kb
Host smart-0bf42dfa-fce6-460d-91eb-5833c383fa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190121822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2190121822
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1665324614
Short name T324
Test name
Test status
Simulation time 6844798125 ps
CPU time 36.97 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:38:05 PM PST 24
Peak memory 240752 kb
Host smart-ef80a218-1a4f-4ca2-8021-0ae7cdc89b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665324614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1665324614
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1487385067
Short name T339
Test name
Test status
Simulation time 82850772215 ps
CPU time 78.34 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:38:46 PM PST 24
Peak memory 240212 kb
Host smart-3484cf60-6333-4531-9d6b-d9a1c9ea4112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487385067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1487385067
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3386627453
Short name T779
Test name
Test status
Simulation time 6963953538 ps
CPU time 25.57 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:54 PM PST 24
Peak memory 252788 kb
Host smart-a33cf8d3-3215-425c-8edd-90d7c54152b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386627453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3386627453
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1989407520
Short name T979
Test name
Test status
Simulation time 352626785 ps
CPU time 3.98 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 235444 kb
Host smart-cd0ae27b-ee16-45f4-9d9d-f3eba0be8667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989407520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1989407520
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1876679893
Short name T54
Test name
Test status
Simulation time 1209295846 ps
CPU time 5.17 seconds
Started Feb 29 01:37:29 PM PST 24
Finished Feb 29 01:37:35 PM PST 24
Peak memory 224176 kb
Host smart-d3474cc5-b471-44bb-9736-54d8fd2c3a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876679893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1876679893
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.380039239
Short name T24
Test name
Test status
Simulation time 58124662 ps
CPU time 1.11 seconds
Started Feb 29 01:37:26 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 216552 kb
Host smart-c676bfd8-4a18-4363-9376-9938851a0a6f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380039239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.380039239
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3322371189
Short name T882
Test name
Test status
Simulation time 8405413662 ps
CPU time 22.97 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:48 PM PST 24
Peak memory 239000 kb
Host smart-dd899b9a-d532-424c-b95d-e1f506fb2d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322371189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3322371189
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3389791890
Short name T710
Test name
Test status
Simulation time 19312192751 ps
CPU time 11.55 seconds
Started Feb 29 01:37:26 PM PST 24
Finished Feb 29 01:37:37 PM PST 24
Peak memory 224196 kb
Host smart-630b3551-30f2-4c7d-aa34-24c2dea5d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389791890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3389791890
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3685114576
Short name T422
Test name
Test status
Simulation time 46801896 ps
CPU time 0.75 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 215968 kb
Host smart-51e3d872-2a96-4221-82aa-0bd27828a393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685114576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3685114576
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2859161794
Short name T966
Test name
Test status
Simulation time 1409271552 ps
CPU time 3.86 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:32 PM PST 24
Peak memory 222328 kb
Host smart-aebacaa6-e0bf-4167-a1fe-e8a2ca2588c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2859161794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2859161794
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1365299509
Short name T65
Test name
Test status
Simulation time 2261561813 ps
CPU time 32.68 seconds
Started Feb 29 01:37:30 PM PST 24
Finished Feb 29 01:38:03 PM PST 24
Peak memory 222264 kb
Host smart-ef16a6f6-1683-474c-be21-f66c8080e4e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365299509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1365299509
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1694754395
Short name T970
Test name
Test status
Simulation time 2345080994 ps
CPU time 12.54 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:41 PM PST 24
Peak memory 216292 kb
Host smart-5741e573-d9f1-480b-8872-2f5d1f44c9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694754395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1694754395
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3031586595
Short name T538
Test name
Test status
Simulation time 23721890085 ps
CPU time 18.86 seconds
Started Feb 29 01:37:29 PM PST 24
Finished Feb 29 01:37:48 PM PST 24
Peak memory 216304 kb
Host smart-1bf2f9c2-01b9-4dd9-bd7d-8afb681432a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031586595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3031586595
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.130343986
Short name T766
Test name
Test status
Simulation time 436328865 ps
CPU time 2.46 seconds
Started Feb 29 01:37:28 PM PST 24
Finished Feb 29 01:37:31 PM PST 24
Peak memory 207932 kb
Host smart-f2ab3a36-49bc-4e34-84e0-a15dea3f7631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130343986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.130343986
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3141282212
Short name T942
Test name
Test status
Simulation time 78418657 ps
CPU time 0.9 seconds
Started Feb 29 01:37:31 PM PST 24
Finished Feb 29 01:37:32 PM PST 24
Peak memory 205216 kb
Host smart-fc8472aa-b76e-41d3-bce4-5e2ca16e33a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141282212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3141282212
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3906672012
Short name T205
Test name
Test status
Simulation time 10458168203 ps
CPU time 28.44 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:37:57 PM PST 24
Peak memory 222920 kb
Host smart-860af862-dd84-4bc4-8ada-9b21ac46de4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906672012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3906672012
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4081033883
Short name T747
Test name
Test status
Simulation time 38644022 ps
CPU time 0.69 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:37:44 PM PST 24
Peak memory 204764 kb
Host smart-88dc3b08-22a1-45f6-9d42-1c1e193499d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081033883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4081033883
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.580916139
Short name T232
Test name
Test status
Simulation time 1977686828 ps
CPU time 4.19 seconds
Started Feb 29 01:37:30 PM PST 24
Finished Feb 29 01:37:34 PM PST 24
Peak memory 233092 kb
Host smart-5f041cdd-2d1e-4f17-8880-0e22df6b7c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580916139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.580916139
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.596406622
Short name T331
Test name
Test status
Simulation time 49691306 ps
CPU time 0.77 seconds
Started Feb 29 01:37:29 PM PST 24
Finished Feb 29 01:37:30 PM PST 24
Peak memory 204944 kb
Host smart-baea404d-9d6b-422f-8bc6-6c2ee7d3d4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596406622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.596406622
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1677230941
Short name T283
Test name
Test status
Simulation time 83991314097 ps
CPU time 47.13 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:38:15 PM PST 24
Peak memory 232836 kb
Host smart-1dece5ab-ead4-48c8-b08c-ef0778db0d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677230941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1677230941
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3720839046
Short name T443
Test name
Test status
Simulation time 187823882943 ps
CPU time 291.73 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:42:20 PM PST 24
Peak memory 257256 kb
Host smart-3dae92c0-13eb-4e51-9630-67c21f786564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720839046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3720839046
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2646121586
Short name T244
Test name
Test status
Simulation time 415327515305 ps
CPU time 500.11 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:46:03 PM PST 24
Peak memory 256628 kb
Host smart-067aa139-e85b-44f4-b94d-d5ced9470852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646121586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2646121586
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2511621729
Short name T524
Test name
Test status
Simulation time 4525898083 ps
CPU time 14.61 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:40 PM PST 24
Peak memory 240572 kb
Host smart-2cf6634c-49c0-41de-b8fe-57b136d10b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511621729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2511621729
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3571691724
Short name T656
Test name
Test status
Simulation time 667627001 ps
CPU time 5.61 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:37:34 PM PST 24
Peak memory 224260 kb
Host smart-ba28f5fe-8126-4b82-a51d-0abdfe8b5232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571691724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3571691724
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.282700314
Short name T350
Test name
Test status
Simulation time 33601735294 ps
CPU time 38.72 seconds
Started Feb 29 01:37:31 PM PST 24
Finished Feb 29 01:38:10 PM PST 24
Peak memory 240424 kb
Host smart-ccde10a4-113b-4850-be85-e5657421fec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282700314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.282700314
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1654576452
Short name T485
Test name
Test status
Simulation time 85019809 ps
CPU time 1.05 seconds
Started Feb 29 01:37:25 PM PST 24
Finished Feb 29 01:37:26 PM PST 24
Peak memory 216556 kb
Host smart-2e0c4048-bdf6-4be6-b4c9-685a986551f4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654576452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1654576452
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.517915716
Short name T827
Test name
Test status
Simulation time 9381982391 ps
CPU time 7.81 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:37:36 PM PST 24
Peak memory 234552 kb
Host smart-b2b6f2e1-30a5-4ecb-8bab-e9f693dec0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517915716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.517915716
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3360153273
Short name T824
Test name
Test status
Simulation time 8231365248 ps
CPU time 12.82 seconds
Started Feb 29 01:37:29 PM PST 24
Finished Feb 29 01:37:42 PM PST 24
Peak memory 217524 kb
Host smart-b8f2df8b-17c9-4c34-9731-c51b152517c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360153273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3360153273
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.765442826
Short name T341
Test name
Test status
Simulation time 17441466 ps
CPU time 0.73 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 215984 kb
Host smart-cfde7685-df27-46c1-8faa-53bcc2922c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765442826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.765442826
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.332459591
Short name T130
Test name
Test status
Simulation time 295266951 ps
CPU time 3.92 seconds
Started Feb 29 01:37:29 PM PST 24
Finished Feb 29 01:37:33 PM PST 24
Peak memory 219752 kb
Host smart-880c77db-438e-416f-9ba2-b18e14a42ed7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=332459591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.332459591
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1172525598
Short name T746
Test name
Test status
Simulation time 869297794 ps
CPU time 12.44 seconds
Started Feb 29 01:37:26 PM PST 24
Finished Feb 29 01:37:41 PM PST 24
Peak memory 216092 kb
Host smart-05caa2b2-5f45-49bb-86c8-10f1aafeb5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172525598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1172525598
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3836712850
Short name T938
Test name
Test status
Simulation time 590874410 ps
CPU time 4.96 seconds
Started Feb 29 01:37:29 PM PST 24
Finished Feb 29 01:37:34 PM PST 24
Peak memory 216108 kb
Host smart-48f3edc4-766b-4c27-9b5b-a85385dbba64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836712850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3836712850
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1710808032
Short name T617
Test name
Test status
Simulation time 532081162 ps
CPU time 2.48 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:37:31 PM PST 24
Peak memory 216096 kb
Host smart-0d046be6-110f-4e5a-a664-3b9c921bd32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710808032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1710808032
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3681326456
Short name T433
Test name
Test status
Simulation time 156036447 ps
CPU time 0.99 seconds
Started Feb 29 01:37:27 PM PST 24
Finished Feb 29 01:37:29 PM PST 24
Peak memory 205208 kb
Host smart-80aac3e5-dbfe-4730-bd40-ef8da27a0a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681326456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3681326456
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1926601775
Short name T383
Test name
Test status
Simulation time 451752363 ps
CPU time 7.72 seconds
Started Feb 29 01:37:31 PM PST 24
Finished Feb 29 01:37:39 PM PST 24
Peak memory 237396 kb
Host smart-e1dc5519-d979-4bdf-b5ff-3898d267a4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926601775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1926601775
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1751194627
Short name T757
Test name
Test status
Simulation time 36668305 ps
CPU time 0.7 seconds
Started Feb 29 01:37:38 PM PST 24
Finished Feb 29 01:37:39 PM PST 24
Peak memory 204264 kb
Host smart-ce1bbcca-ef1d-43fe-a78e-a5396b44cea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751194627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1751194627
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3283077030
Short name T881
Test name
Test status
Simulation time 893929204 ps
CPU time 4.43 seconds
Started Feb 29 01:37:43 PM PST 24
Finished Feb 29 01:37:48 PM PST 24
Peak memory 224272 kb
Host smart-40f74acc-a7f2-45ad-ae6f-6b95800aa5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283077030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3283077030
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2507455622
Short name T786
Test name
Test status
Simulation time 13439556 ps
CPU time 0.81 seconds
Started Feb 29 01:37:39 PM PST 24
Finished Feb 29 01:37:40 PM PST 24
Peak memory 204988 kb
Host smart-4cdfec34-6342-4725-9b25-635366328b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507455622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2507455622
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3899637156
Short name T19
Test name
Test status
Simulation time 8558433025 ps
CPU time 43.01 seconds
Started Feb 29 01:37:39 PM PST 24
Finished Feb 29 01:38:23 PM PST 24
Peak memory 229832 kb
Host smart-54548f81-7df8-4f8e-af33-0c0647810a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899637156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3899637156
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3283383111
Short name T448
Test name
Test status
Simulation time 41515038659 ps
CPU time 178.55 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:40:39 PM PST 24
Peak memory 249052 kb
Host smart-4ee5222a-a479-4a22-a6c8-3d991ca7cac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283383111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3283383111
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.133875841
Short name T418
Test name
Test status
Simulation time 251727358 ps
CPU time 7.69 seconds
Started Feb 29 01:37:39 PM PST 24
Finished Feb 29 01:37:47 PM PST 24
Peak memory 233304 kb
Host smart-c9c3c282-9558-4fb7-8975-00e91e24e4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133875841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.133875841
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4040539454
Short name T985
Test name
Test status
Simulation time 1540805399 ps
CPU time 2.98 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:37:44 PM PST 24
Peak memory 234088 kb
Host smart-7262aaab-53aa-4712-801e-c52cc4bcb546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040539454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4040539454
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1582334774
Short name T255
Test name
Test status
Simulation time 312205102 ps
CPU time 4.69 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:37:46 PM PST 24
Peak memory 233384 kb
Host smart-6d4b9a13-ea94-4f90-9372-4f706f89b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582334774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1582334774
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.647081753
Short name T959
Test name
Test status
Simulation time 28439470 ps
CPU time 1.09 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:37:42 PM PST 24
Peak memory 216672 kb
Host smart-0a8e5207-2329-49cd-88aa-5512bbc84263
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647081753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.647081753
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1950180799
Short name T623
Test name
Test status
Simulation time 288392439 ps
CPU time 3.67 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:37:47 PM PST 24
Peak memory 233132 kb
Host smart-49677c7f-92ee-4d2b-af22-7ba237340040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950180799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1950180799
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3557687553
Short name T388
Test name
Test status
Simulation time 11221435350 ps
CPU time 31.08 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:38:14 PM PST 24
Peak memory 228624 kb
Host smart-15c98f11-88ae-4c50-a8c4-610a1d6f2fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557687553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3557687553
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.2477034662
Short name T58
Test name
Test status
Simulation time 15812282 ps
CPU time 0.75 seconds
Started Feb 29 01:37:41 PM PST 24
Finished Feb 29 01:37:43 PM PST 24
Peak memory 215628 kb
Host smart-9f9555f7-04ed-4a27-846e-ee5c94694849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477034662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2477034662
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2960415512
Short name T415
Test name
Test status
Simulation time 1042756329 ps
CPU time 3.52 seconds
Started Feb 29 01:37:41 PM PST 24
Finished Feb 29 01:37:44 PM PST 24
Peak memory 217024 kb
Host smart-5cd11be2-3acd-425e-9336-143064066e64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2960415512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2960415512
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4196334737
Short name T719
Test name
Test status
Simulation time 7349902765 ps
CPU time 59.54 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:38:43 PM PST 24
Peak memory 239064 kb
Host smart-f9710d14-ffa0-4424-9cf5-f58b276d0f03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196334737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4196334737
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1041943197
Short name T533
Test name
Test status
Simulation time 5251293397 ps
CPU time 24.25 seconds
Started Feb 29 01:37:41 PM PST 24
Finished Feb 29 01:38:05 PM PST 24
Peak memory 216220 kb
Host smart-4f8eaeb3-bc73-4730-8fee-b97aac627523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041943197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1041943197
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3046295531
Short name T9
Test name
Test status
Simulation time 10220342308 ps
CPU time 10.32 seconds
Started Feb 29 01:37:39 PM PST 24
Finished Feb 29 01:37:49 PM PST 24
Peak memory 216184 kb
Host smart-2968971e-70a0-4cc7-9f30-51c3a717e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046295531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3046295531
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1325720622
Short name T813
Test name
Test status
Simulation time 104977213 ps
CPU time 1.46 seconds
Started Feb 29 01:37:38 PM PST 24
Finished Feb 29 01:37:40 PM PST 24
Peak memory 208004 kb
Host smart-2d3a6431-6ba5-43b1-83cd-a7144e74717b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325720622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1325720622
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.292414199
Short name T947
Test name
Test status
Simulation time 104115969 ps
CPU time 0.76 seconds
Started Feb 29 01:37:39 PM PST 24
Finished Feb 29 01:37:40 PM PST 24
Peak memory 205216 kb
Host smart-b4388b10-64ad-46df-bec6-c80633340957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292414199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.292414199
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.998200189
Short name T372
Test name
Test status
Simulation time 2372389328 ps
CPU time 11.13 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:37:52 PM PST 24
Peak memory 236836 kb
Host smart-3c4ba290-a145-4b77-9222-7a570c521661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998200189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.998200189
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.739990815
Short name T466
Test name
Test status
Simulation time 15008794 ps
CPU time 0.73 seconds
Started Feb 29 01:36:02 PM PST 24
Finished Feb 29 01:36:03 PM PST 24
Peak memory 204840 kb
Host smart-a67da339-c855-4cb7-b4c5-86d1ba17742c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739990815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.739990815
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3763597545
Short name T392
Test name
Test status
Simulation time 282742846 ps
CPU time 4.2 seconds
Started Feb 29 01:35:58 PM PST 24
Finished Feb 29 01:36:02 PM PST 24
Peak memory 233484 kb
Host smart-f9822a63-6c24-41f3-964a-bba3d139a4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763597545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3763597545
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3184581378
Short name T899
Test name
Test status
Simulation time 45030557 ps
CPU time 0.73 seconds
Started Feb 29 01:35:58 PM PST 24
Finished Feb 29 01:36:00 PM PST 24
Peak memory 204892 kb
Host smart-5828dd05-071f-40aa-bf36-7da217a2accc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184581378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3184581378
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2122269432
Short name T680
Test name
Test status
Simulation time 938593474 ps
CPU time 7.05 seconds
Started Feb 29 01:36:01 PM PST 24
Finished Feb 29 01:36:09 PM PST 24
Peak memory 234072 kb
Host smart-3932d5e1-c7ea-4cd3-b1c1-661a69e13e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122269432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2122269432
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1011018808
Short name T907
Test name
Test status
Simulation time 15777485696 ps
CPU time 154.8 seconds
Started Feb 29 01:35:57 PM PST 24
Finished Feb 29 01:38:32 PM PST 24
Peak memory 266188 kb
Host smart-80018ed0-8152-4af5-9e5c-c0e14d1c3280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011018808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1011018808
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1985339765
Short name T941
Test name
Test status
Simulation time 7535553357 ps
CPU time 21.53 seconds
Started Feb 29 01:35:58 PM PST 24
Finished Feb 29 01:36:19 PM PST 24
Peak memory 221104 kb
Host smart-a33c2c70-c2b2-4f90-8494-c4054ed63d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985339765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1985339765
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4229305482
Short name T290
Test name
Test status
Simulation time 3665847315 ps
CPU time 8.96 seconds
Started Feb 29 01:36:02 PM PST 24
Finished Feb 29 01:36:11 PM PST 24
Peak memory 238848 kb
Host smart-833102d8-bf9c-425b-bdc2-047ac5669579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229305482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4229305482
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.463055158
Short name T248
Test name
Test status
Simulation time 181621244 ps
CPU time 4.8 seconds
Started Feb 29 01:36:03 PM PST 24
Finished Feb 29 01:36:07 PM PST 24
Peak memory 234768 kb
Host smart-ec7c93ec-9eee-4a1a-b7a1-56253b4ce6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463055158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.463055158
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.225958024
Short name T969
Test name
Test status
Simulation time 4723316948 ps
CPU time 12.44 seconds
Started Feb 29 01:36:01 PM PST 24
Finished Feb 29 01:36:15 PM PST 24
Peak memory 230068 kb
Host smart-0015224b-c741-4f55-a68d-988281e04e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225958024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.225958024
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1123955403
Short name T386
Test name
Test status
Simulation time 33953896 ps
CPU time 1.12 seconds
Started Feb 29 01:36:00 PM PST 24
Finished Feb 29 01:36:02 PM PST 24
Peak memory 216568 kb
Host smart-63edb3f9-5ac4-419b-84bc-f0f3c5d5e8eb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123955403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1123955403
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2634879105
Short name T611
Test name
Test status
Simulation time 18335099629 ps
CPU time 25.91 seconds
Started Feb 29 01:36:00 PM PST 24
Finished Feb 29 01:36:26 PM PST 24
Peak memory 232644 kb
Host smart-9f4f4d5f-3101-40b5-aefa-b2290fc6349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634879105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2634879105
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3338490965
Short name T826
Test name
Test status
Simulation time 1285809427 ps
CPU time 9.66 seconds
Started Feb 29 01:35:59 PM PST 24
Finished Feb 29 01:36:09 PM PST 24
Peak memory 216208 kb
Host smart-bec28d05-513e-49a2-a25a-b1384bf790e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338490965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3338490965
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2283470199
Short name T67
Test name
Test status
Simulation time 29825476 ps
CPU time 0.72 seconds
Started Feb 29 01:36:01 PM PST 24
Finished Feb 29 01:36:02 PM PST 24
Peak memory 216044 kb
Host smart-48a46fe3-457e-4adf-8e1d-54ccd06d9509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283470199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2283470199
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.310577167
Short name T5
Test name
Test status
Simulation time 1720243287 ps
CPU time 5.31 seconds
Started Feb 29 01:36:01 PM PST 24
Finished Feb 29 01:36:07 PM PST 24
Peak memory 220260 kb
Host smart-b46e5cd9-e069-4b5f-b7ce-f7fc71da4109
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=310577167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.310577167
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1090022058
Short name T71
Test name
Test status
Simulation time 206349156 ps
CPU time 1.21 seconds
Started Feb 29 01:35:59 PM PST 24
Finished Feb 29 01:36:01 PM PST 24
Peak memory 235292 kb
Host smart-c94a3694-fff1-4a39-81e2-ad141f85ebe4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090022058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1090022058
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2672449971
Short name T729
Test name
Test status
Simulation time 43702306 ps
CPU time 1.07 seconds
Started Feb 29 01:35:59 PM PST 24
Finished Feb 29 01:36:00 PM PST 24
Peak memory 206604 kb
Host smart-b8bdd872-9b0e-4404-a76a-d2a10c4ac5f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672449971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2672449971
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2036977600
Short name T805
Test name
Test status
Simulation time 5437767839 ps
CPU time 44.17 seconds
Started Feb 29 01:35:59 PM PST 24
Finished Feb 29 01:36:45 PM PST 24
Peak memory 216224 kb
Host smart-98473b65-80a6-4b07-b739-a60d05cd5f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036977600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2036977600
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1401727276
Short name T577
Test name
Test status
Simulation time 21629940588 ps
CPU time 15.87 seconds
Started Feb 29 01:35:56 PM PST 24
Finished Feb 29 01:36:12 PM PST 24
Peak memory 216156 kb
Host smart-05a67e6b-eb5c-4f0a-b3e9-52c2a414807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401727276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1401727276
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2859906852
Short name T436
Test name
Test status
Simulation time 62751991 ps
CPU time 1.47 seconds
Started Feb 29 01:36:00 PM PST 24
Finished Feb 29 01:36:02 PM PST 24
Peak memory 216108 kb
Host smart-8f3afcc3-36f2-4725-9b9c-58d244875452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859906852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2859906852
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1888235551
Short name T708
Test name
Test status
Simulation time 341636754 ps
CPU time 1.06 seconds
Started Feb 29 01:36:01 PM PST 24
Finished Feb 29 01:36:03 PM PST 24
Peak memory 206244 kb
Host smart-837aec90-e1d7-4f08-8725-996363d5b922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888235551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1888235551
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2793434608
Short name T905
Test name
Test status
Simulation time 3685895726 ps
CPU time 7.95 seconds
Started Feb 29 01:36:00 PM PST 24
Finished Feb 29 01:36:09 PM PST 24
Peak memory 224356 kb
Host smart-91537b64-3563-4c59-856e-c22999129c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793434608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2793434608
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1402684252
Short name T508
Test name
Test status
Simulation time 14407248 ps
CPU time 0.72 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:37:44 PM PST 24
Peak memory 205136 kb
Host smart-b5504bed-34ec-4aea-bf7f-8d335bcb12cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402684252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1402684252
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3416613107
Short name T254
Test name
Test status
Simulation time 2072908359 ps
CPU time 4.18 seconds
Started Feb 29 01:37:38 PM PST 24
Finished Feb 29 01:37:43 PM PST 24
Peak memory 233196 kb
Host smart-6f127c9e-2de4-488d-9bce-e25793e88f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416613107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3416613107
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3734327972
Short name T317
Test name
Test status
Simulation time 26107978 ps
CPU time 0.76 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:37:42 PM PST 24
Peak memory 204924 kb
Host smart-cb5fcc93-72af-4d1d-8656-8f3a6455ba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734327972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3734327972
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1059357864
Short name T957
Test name
Test status
Simulation time 110894497897 ps
CPU time 135.38 seconds
Started Feb 29 01:37:39 PM PST 24
Finished Feb 29 01:39:54 PM PST 24
Peak memory 248104 kb
Host smart-22783afa-706f-4dd0-8536-ef1be16c9496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059357864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1059357864
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1648192897
Short name T704
Test name
Test status
Simulation time 84690129748 ps
CPU time 133.18 seconds
Started Feb 29 01:37:39 PM PST 24
Finished Feb 29 01:39:52 PM PST 24
Peak memory 235288 kb
Host smart-5c052eca-1ed8-4ef3-a1f0-cfa218d32aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648192897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1648192897
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4045579775
Short name T889
Test name
Test status
Simulation time 155296848467 ps
CPU time 302.97 seconds
Started Feb 29 01:37:39 PM PST 24
Finished Feb 29 01:42:43 PM PST 24
Peak memory 257064 kb
Host smart-f348e293-392e-49d8-8d1c-0ea69856dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045579775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4045579775
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_intercept.42433860
Short name T698
Test name
Test status
Simulation time 3384373902 ps
CPU time 6.64 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:37:46 PM PST 24
Peak memory 217452 kb
Host smart-c9cd6a6c-8d75-40e1-b9f5-bb5fad325992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42433860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.42433860
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4071508470
Short name T532
Test name
Test status
Simulation time 713693915 ps
CPU time 7.16 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:37:50 PM PST 24
Peak memory 234548 kb
Host smart-e29e5c98-4821-4bea-bb5b-59f51453c391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071508470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4071508470
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2565646745
Short name T799
Test name
Test status
Simulation time 3200501247 ps
CPU time 11.9 seconds
Started Feb 29 01:37:43 PM PST 24
Finished Feb 29 01:37:55 PM PST 24
Peak memory 233312 kb
Host smart-0b1f72f0-b63a-4d8d-a2ae-9df395b4821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565646745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2565646745
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2001236013
Short name T697
Test name
Test status
Simulation time 111368997 ps
CPU time 2.55 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:37:43 PM PST 24
Peak memory 233428 kb
Host smart-d6b70119-b003-46e2-8983-bdb7b8769fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001236013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2001236013
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2968334735
Short name T40
Test name
Test status
Simulation time 181760119 ps
CPU time 3.87 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:37:47 PM PST 24
Peak memory 222464 kb
Host smart-f21a6fd3-f123-4179-80e3-1048930444bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2968334735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2968334735
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2617710106
Short name T295
Test name
Test status
Simulation time 23807063732 ps
CPU time 56.92 seconds
Started Feb 29 01:37:37 PM PST 24
Finished Feb 29 01:38:34 PM PST 24
Peak memory 216204 kb
Host smart-a9810d1f-6622-4c48-af05-6a9644fdd691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617710106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2617710106
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2907197276
Short name T357
Test name
Test status
Simulation time 15371376432 ps
CPU time 22.99 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:38:04 PM PST 24
Peak memory 216172 kb
Host smart-289880b3-7003-4289-8d7e-b1d777a47d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907197276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2907197276
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.461620781
Short name T996
Test name
Test status
Simulation time 80256042 ps
CPU time 1.45 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:37:45 PM PST 24
Peak memory 216104 kb
Host smart-132eafd1-94bf-47f1-adde-0b225927fb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461620781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.461620781
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4291789071
Short name T300
Test name
Test status
Simulation time 107950185 ps
CPU time 0.94 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:37:44 PM PST 24
Peak memory 206228 kb
Host smart-fa91355b-dea4-47a6-a9fc-c3457425d2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291789071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4291789071
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2897253285
Short name T256
Test name
Test status
Simulation time 1235182910 ps
CPU time 6.04 seconds
Started Feb 29 01:37:43 PM PST 24
Finished Feb 29 01:37:49 PM PST 24
Peak memory 217140 kb
Host smart-026f490b-aa7b-4781-82a4-c3c6749d36b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897253285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2897253285
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2268347480
Short name T924
Test name
Test status
Simulation time 11597641 ps
CPU time 0.71 seconds
Started Feb 29 01:37:55 PM PST 24
Finished Feb 29 01:37:57 PM PST 24
Peak memory 204824 kb
Host smart-4b760110-d425-4a5f-9221-d87775259f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268347480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2268347480
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2446104491
Short name T340
Test name
Test status
Simulation time 59121742 ps
CPU time 2.13 seconds
Started Feb 29 01:37:41 PM PST 24
Finished Feb 29 01:37:44 PM PST 24
Peak memory 216248 kb
Host smart-14370237-f1af-43bb-a143-c78946b31f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446104491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2446104491
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.532971935
Short name T960
Test name
Test status
Simulation time 48127791 ps
CPU time 0.77 seconds
Started Feb 29 01:37:39 PM PST 24
Finished Feb 29 01:37:40 PM PST 24
Peak memory 204940 kb
Host smart-40aa6c6e-bafb-4a76-8456-d2c0762288ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532971935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.532971935
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1067756898
Short name T276
Test name
Test status
Simulation time 25443429775 ps
CPU time 179.67 seconds
Started Feb 29 01:37:54 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 264768 kb
Host smart-5bc68f81-3410-4cf3-9e4f-7b3c10c735e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067756898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1067756898
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2581425808
Short name T751
Test name
Test status
Simulation time 24110701198 ps
CPU time 34.27 seconds
Started Feb 29 01:37:43 PM PST 24
Finished Feb 29 01:38:18 PM PST 24
Peak memory 232600 kb
Host smart-be9de26b-9217-4256-8a36-24ea5f204f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581425808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2581425808
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3296032139
Short name T620
Test name
Test status
Simulation time 14227665638 ps
CPU time 12.55 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:37:52 PM PST 24
Peak memory 219252 kb
Host smart-41c787c2-07bf-4141-89b5-9e0c7c95ec61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296032139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3296032139
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1229126401
Short name T962
Test name
Test status
Simulation time 30113167059 ps
CPU time 31.02 seconds
Started Feb 29 01:37:43 PM PST 24
Finished Feb 29 01:38:14 PM PST 24
Peak memory 232620 kb
Host smart-f0794ef2-2fef-4313-9b95-faa68e3a99eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229126401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1229126401
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2239720739
Short name T742
Test name
Test status
Simulation time 1951473184 ps
CPU time 6.72 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:37:50 PM PST 24
Peak memory 229836 kb
Host smart-d3a72c10-4b74-41e3-865e-a27156adde67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239720739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2239720739
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3366689207
Short name T735
Test name
Test status
Simulation time 3116626902 ps
CPU time 7.3 seconds
Started Feb 29 01:37:41 PM PST 24
Finished Feb 29 01:37:48 PM PST 24
Peak memory 239064 kb
Host smart-9ca53290-357a-4ddd-a9fb-06640bb38049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366689207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3366689207
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3430945304
Short name T634
Test name
Test status
Simulation time 3498291908 ps
CPU time 7.22 seconds
Started Feb 29 01:37:41 PM PST 24
Finished Feb 29 01:37:48 PM PST 24
Peak memory 222184 kb
Host smart-f73f81af-a3d6-4e48-bc18-abd2f93724c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3430945304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3430945304
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2461011644
Short name T64
Test name
Test status
Simulation time 15451923926 ps
CPU time 157.13 seconds
Started Feb 29 01:37:50 PM PST 24
Finished Feb 29 01:40:27 PM PST 24
Peak memory 249160 kb
Host smart-f7f61529-03a3-4bae-aec5-a23a82b9bd40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461011644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2461011644
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3130917398
Short name T365
Test name
Test status
Simulation time 1893449144 ps
CPU time 5.32 seconds
Started Feb 29 01:37:42 PM PST 24
Finished Feb 29 01:37:49 PM PST 24
Peak memory 207940 kb
Host smart-c62aff38-53c9-4c84-b807-95d96b844219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130917398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3130917398
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3219947424
Short name T404
Test name
Test status
Simulation time 68396036 ps
CPU time 0.92 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:37:42 PM PST 24
Peak memory 205812 kb
Host smart-f6ed2f75-84be-42f6-b5b7-84fe7820deae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219947424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3219947424
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.594677537
Short name T872
Test name
Test status
Simulation time 379478693 ps
CPU time 0.99 seconds
Started Feb 29 01:37:40 PM PST 24
Finished Feb 29 01:37:42 PM PST 24
Peak memory 205420 kb
Host smart-8ca10fef-8dbf-4d2b-a622-fe9e4500632e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594677537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.594677537
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3605350278
Short name T356
Test name
Test status
Simulation time 12337946031 ps
CPU time 40.01 seconds
Started Feb 29 01:37:43 PM PST 24
Finished Feb 29 01:38:24 PM PST 24
Peak memory 220136 kb
Host smart-b7a669cc-81ed-4a1d-bfc9-4cc774b72cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605350278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3605350278
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2580446406
Short name T732
Test name
Test status
Simulation time 21289057 ps
CPU time 0.69 seconds
Started Feb 29 01:37:54 PM PST 24
Finished Feb 29 01:37:54 PM PST 24
Peak memory 205172 kb
Host smart-8e9483a5-db27-4574-8af8-8951f6f10a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580446406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2580446406
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.362356072
Short name T377
Test name
Test status
Simulation time 344802230 ps
CPU time 3.24 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:37:59 PM PST 24
Peak memory 233268 kb
Host smart-57fe3aaf-aea1-4a08-83a4-58b70eac823b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362356072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.362356072
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2722715696
Short name T921
Test name
Test status
Simulation time 34819259 ps
CPU time 0.75 seconds
Started Feb 29 01:37:53 PM PST 24
Finished Feb 29 01:37:54 PM PST 24
Peak memory 206312 kb
Host smart-efc0d15f-282e-48b4-b302-a01fd9a4d1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722715696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2722715696
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2855429653
Short name T770
Test name
Test status
Simulation time 7789198597 ps
CPU time 25.22 seconds
Started Feb 29 01:37:54 PM PST 24
Finished Feb 29 01:38:19 PM PST 24
Peak memory 240144 kb
Host smart-cbe53523-7ca1-4f45-8773-0038c15c4aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855429653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2855429653
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.728824705
Short name T206
Test name
Test status
Simulation time 92224108702 ps
CPU time 153.46 seconds
Started Feb 29 01:37:53 PM PST 24
Finished Feb 29 01:40:27 PM PST 24
Peak memory 235560 kb
Host smart-36580c66-65db-48d9-be26-7ee8fd46d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728824705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.728824705
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3127364809
Short name T573
Test name
Test status
Simulation time 6610590311 ps
CPU time 27.33 seconds
Started Feb 29 01:37:57 PM PST 24
Finished Feb 29 01:38:24 PM PST 24
Peak memory 237656 kb
Host smart-1fba0994-e47e-47da-b2d2-c451491d9d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127364809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3127364809
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3295868322
Short name T955
Test name
Test status
Simulation time 194657324 ps
CPU time 3.88 seconds
Started Feb 29 01:37:55 PM PST 24
Finished Feb 29 01:38:00 PM PST 24
Peak memory 234076 kb
Host smart-69d80a83-e66c-4d62-8b66-8cbfe0841ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295868322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3295868322
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1515087689
Short name T896
Test name
Test status
Simulation time 47105028418 ps
CPU time 41.29 seconds
Started Feb 29 01:37:53 PM PST 24
Finished Feb 29 01:38:35 PM PST 24
Peak memory 248864 kb
Host smart-32fc009d-3d1b-449b-9517-23e8f396e989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515087689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1515087689
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1935416469
Short name T11
Test name
Test status
Simulation time 2104916529 ps
CPU time 5.21 seconds
Started Feb 29 01:37:54 PM PST 24
Finished Feb 29 01:37:59 PM PST 24
Peak memory 224296 kb
Host smart-de56dd1e-590a-40e1-b17d-0c69a875b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935416469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1935416469
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1804823493
Short name T920
Test name
Test status
Simulation time 695937860 ps
CPU time 6.54 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:38:03 PM PST 24
Peak memory 227804 kb
Host smart-9fb803bc-1e6d-4ae5-b758-af14b8803775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804823493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1804823493
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.949127366
Short name T563
Test name
Test status
Simulation time 9209312441 ps
CPU time 7.07 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:38:03 PM PST 24
Peak memory 222172 kb
Host smart-75fb0f63-b4eb-48e9-8b9f-da7ca3337a59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=949127366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.949127366
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1053147832
Short name T141
Test name
Test status
Simulation time 9090394076 ps
CPU time 121.62 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:39:58 PM PST 24
Peak memory 257268 kb
Host smart-23c67e59-5292-4be3-9578-43a734d612e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053147832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1053147832
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3999941560
Short name T887
Test name
Test status
Simulation time 7302727095 ps
CPU time 18.91 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:38:15 PM PST 24
Peak memory 216044 kb
Host smart-a38c99f2-0466-44aa-b506-b3d2dbed8d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999941560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3999941560
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.9496569
Short name T712
Test name
Test status
Simulation time 1599885914 ps
CPU time 4.87 seconds
Started Feb 29 01:37:54 PM PST 24
Finished Feb 29 01:38:01 PM PST 24
Peak memory 215972 kb
Host smart-4066248d-7a76-49e6-937d-b1681409c57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9496569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.9496569
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3756657366
Short name T381
Test name
Test status
Simulation time 405076164 ps
CPU time 3.78 seconds
Started Feb 29 01:37:52 PM PST 24
Finished Feb 29 01:37:56 PM PST 24
Peak memory 216104 kb
Host smart-b24b2a49-c2a4-4d70-9336-e7e3263811d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756657366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3756657366
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2834958219
Short name T967
Test name
Test status
Simulation time 125863439 ps
CPU time 1.07 seconds
Started Feb 29 01:37:53 PM PST 24
Finished Feb 29 01:37:54 PM PST 24
Peak memory 206188 kb
Host smart-5a45c3b0-73a8-4e7c-8250-22d14b753b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834958219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2834958219
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.117564022
Short name T616
Test name
Test status
Simulation time 462695230 ps
CPU time 5.59 seconds
Started Feb 29 01:37:53 PM PST 24
Finished Feb 29 01:37:59 PM PST 24
Peak memory 235100 kb
Host smart-4cd255d6-1f9d-4c27-a395-3ba48131499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117564022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.117564022
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3284291454
Short name T534
Test name
Test status
Simulation time 12493081 ps
CPU time 0.73 seconds
Started Feb 29 01:37:59 PM PST 24
Finished Feb 29 01:38:00 PM PST 24
Peak memory 204848 kb
Host smart-9f3d1454-b499-40d4-8c9d-fdb5d08552d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284291454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3284291454
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1956746917
Short name T519
Test name
Test status
Simulation time 1688515974 ps
CPU time 2.46 seconds
Started Feb 29 01:37:52 PM PST 24
Finished Feb 29 01:37:54 PM PST 24
Peak memory 224264 kb
Host smart-84fc4f3e-062f-4c42-bf55-baef3f3bbe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956746917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1956746917
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1488286617
Short name T479
Test name
Test status
Simulation time 12959253 ps
CPU time 0.75 seconds
Started Feb 29 01:37:55 PM PST 24
Finished Feb 29 01:37:57 PM PST 24
Peak memory 206240 kb
Host smart-dfe77f02-f684-468e-a688-70ebeb139d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488286617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1488286617
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.4156290361
Short name T847
Test name
Test status
Simulation time 2458927985 ps
CPU time 12.18 seconds
Started Feb 29 01:37:54 PM PST 24
Finished Feb 29 01:38:06 PM PST 24
Peak memory 240760 kb
Host smart-b8d401a2-a807-4793-ad65-386536e253b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156290361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.4156290361
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3044158586
Short name T600
Test name
Test status
Simulation time 40906251336 ps
CPU time 285.1 seconds
Started Feb 29 01:37:57 PM PST 24
Finished Feb 29 01:42:42 PM PST 24
Peak memory 249632 kb
Host smart-0f2da804-3613-4bea-b213-93ecda08a407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044158586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3044158586
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4203526652
Short name T490
Test name
Test status
Simulation time 82569856798 ps
CPU time 123.67 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:40:00 PM PST 24
Peak memory 233760 kb
Host smart-ea0f08a2-0dc8-4b21-a970-993feb067b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203526652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4203526652
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4075893385
Short name T894
Test name
Test status
Simulation time 8207019423 ps
CPU time 19.51 seconds
Started Feb 29 01:37:54 PM PST 24
Finished Feb 29 01:38:16 PM PST 24
Peak memory 240456 kb
Host smart-ac29a704-812b-496b-a564-d2f37cc5a7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075893385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4075893385
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1719720730
Short name T51
Test name
Test status
Simulation time 108899297 ps
CPU time 3.38 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:38:00 PM PST 24
Peak memory 233664 kb
Host smart-549aa7dd-eaf4-4acd-846b-fbc775777b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719720730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1719720730
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3266957372
Short name T767
Test name
Test status
Simulation time 50884156801 ps
CPU time 28.25 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:38:24 PM PST 24
Peak memory 235100 kb
Host smart-7b6c2bec-da53-447c-bc3c-f506aa20effe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266957372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3266957372
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.673513879
Short name T651
Test name
Test status
Simulation time 407003965 ps
CPU time 2.44 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:37:59 PM PST 24
Peak memory 223280 kb
Host smart-49c15aad-872c-4e87-ac16-bc60eab15e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673513879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.673513879
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3727270041
Short name T950
Test name
Test status
Simulation time 443132993 ps
CPU time 2.46 seconds
Started Feb 29 01:37:58 PM PST 24
Finished Feb 29 01:38:00 PM PST 24
Peak memory 217924 kb
Host smart-aaa80938-4f8c-4cdc-ab5a-a008ba32abe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727270041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3727270041
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2922979185
Short name T353
Test name
Test status
Simulation time 1025547487 ps
CPU time 4.71 seconds
Started Feb 29 01:37:59 PM PST 24
Finished Feb 29 01:38:03 PM PST 24
Peak memory 219672 kb
Host smart-5f6707b1-8d2d-4f28-8279-20ac847bd9b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2922979185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2922979185
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.147922996
Short name T354
Test name
Test status
Simulation time 68928841801 ps
CPU time 228.16 seconds
Started Feb 29 01:37:59 PM PST 24
Finished Feb 29 01:41:47 PM PST 24
Peak memory 253160 kb
Host smart-bfd4d5ad-aa56-4f37-92f8-04d6bc8428b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147922996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.147922996
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2534914999
Short name T294
Test name
Test status
Simulation time 1596529845 ps
CPU time 28 seconds
Started Feb 29 01:37:57 PM PST 24
Finished Feb 29 01:38:25 PM PST 24
Peak memory 216100 kb
Host smart-9bfda5b5-7924-4b37-a39b-36fe6e9a65c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534914999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2534914999
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1414564132
Short name T798
Test name
Test status
Simulation time 3301254917 ps
CPU time 9.19 seconds
Started Feb 29 01:37:53 PM PST 24
Finished Feb 29 01:38:03 PM PST 24
Peak memory 216604 kb
Host smart-99527396-e967-4796-862e-7de761369dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414564132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1414564132
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3078244965
Short name T903
Test name
Test status
Simulation time 162586713 ps
CPU time 6.42 seconds
Started Feb 29 01:37:57 PM PST 24
Finished Feb 29 01:38:04 PM PST 24
Peak memory 216116 kb
Host smart-ad0f8e8e-fece-428a-9ebb-eca4fbb5275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078244965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3078244965
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3928184350
Short name T690
Test name
Test status
Simulation time 20253625 ps
CPU time 0.75 seconds
Started Feb 29 01:37:54 PM PST 24
Finished Feb 29 01:37:55 PM PST 24
Peak memory 205220 kb
Host smart-10c1dfcb-4a51-42ea-a360-644c53d0236e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928184350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3928184350
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3805738608
Short name T784
Test name
Test status
Simulation time 17689303421 ps
CPU time 21.39 seconds
Started Feb 29 01:37:53 PM PST 24
Finished Feb 29 01:38:15 PM PST 24
Peak memory 247460 kb
Host smart-fb81036c-bd21-489b-8cc6-67375035440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805738608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3805738608
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.220124424
Short name T869
Test name
Test status
Simulation time 34397508 ps
CPU time 0.72 seconds
Started Feb 29 01:37:59 PM PST 24
Finished Feb 29 01:38:00 PM PST 24
Peak memory 204840 kb
Host smart-41e83300-7656-4e95-af27-9b320b4c37ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220124424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.220124424
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3159153548
Short name T935
Test name
Test status
Simulation time 832568790 ps
CPU time 3.56 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:38:00 PM PST 24
Peak memory 224216 kb
Host smart-966e0bc4-c203-4e43-bf59-6530044d03c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159153548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3159153548
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1530016587
Short name T362
Test name
Test status
Simulation time 40162479 ps
CPU time 0.8 seconds
Started Feb 29 01:37:57 PM PST 24
Finished Feb 29 01:37:57 PM PST 24
Peak memory 205952 kb
Host smart-faaf4c95-29fb-485f-bf98-439f2f6bcf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530016587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1530016587
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2512215918
Short name T923
Test name
Test status
Simulation time 133710533142 ps
CPU time 102.59 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:39:39 PM PST 24
Peak memory 248912 kb
Host smart-eec49b2d-91ad-43e9-9d27-696ace04b0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512215918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2512215918
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3162834581
Short name T598
Test name
Test status
Simulation time 27326432098 ps
CPU time 126.89 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:40:03 PM PST 24
Peak memory 248072 kb
Host smart-cfeb8f71-2215-4bc7-a784-6dfd3623ff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162834581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3162834581
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.303848432
Short name T41
Test name
Test status
Simulation time 514456592 ps
CPU time 12.28 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:38:08 PM PST 24
Peak memory 238008 kb
Host smart-8de434c7-d047-46f4-a533-58abe6569b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303848432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.303848432
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.107111105
Short name T542
Test name
Test status
Simulation time 11153668550 ps
CPU time 9.98 seconds
Started Feb 29 01:37:58 PM PST 24
Finished Feb 29 01:38:09 PM PST 24
Peak memory 233604 kb
Host smart-df7ae580-d5f3-4c0c-add9-2d35cf540767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107111105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.107111105
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3545414022
Short name T963
Test name
Test status
Simulation time 8937192242 ps
CPU time 9.53 seconds
Started Feb 29 01:37:57 PM PST 24
Finished Feb 29 01:38:07 PM PST 24
Peak memory 225544 kb
Host smart-273c6c2e-1fe6-46e1-8434-30a11ddd01e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545414022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3545414022
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.517038091
Short name T852
Test name
Test status
Simulation time 15347014967 ps
CPU time 44.88 seconds
Started Feb 29 01:37:57 PM PST 24
Finished Feb 29 01:38:43 PM PST 24
Peak memory 249012 kb
Host smart-a6c5882f-fc36-494c-983e-7e77b924efd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517038091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.517038091
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2534617493
Short name T221
Test name
Test status
Simulation time 2339180780 ps
CPU time 10.47 seconds
Started Feb 29 01:37:59 PM PST 24
Finished Feb 29 01:38:09 PM PST 24
Peak memory 217360 kb
Host smart-bd076874-108c-45ad-bb9d-200fc9ee5a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534617493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2534617493
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.123243222
Short name T647
Test name
Test status
Simulation time 3367211388 ps
CPU time 4.66 seconds
Started Feb 29 01:37:57 PM PST 24
Finished Feb 29 01:38:02 PM PST 24
Peak memory 219648 kb
Host smart-4316d489-e529-4c59-8019-18050fa98223
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=123243222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.123243222
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.587764771
Short name T289
Test name
Test status
Simulation time 22030221867 ps
CPU time 146.46 seconds
Started Feb 29 01:37:58 PM PST 24
Finished Feb 29 01:40:25 PM PST 24
Peak memory 249076 kb
Host smart-7bfd98c6-030e-40f4-9671-b80cb39ffcb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587764771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.587764771
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4212444281
Short name T618
Test name
Test status
Simulation time 6791965837 ps
CPU time 7.91 seconds
Started Feb 29 01:37:57 PM PST 24
Finished Feb 29 01:38:05 PM PST 24
Peak memory 216244 kb
Host smart-9fa8671f-4d6e-4257-8679-52eece994e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212444281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4212444281
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3946343746
Short name T982
Test name
Test status
Simulation time 19232915296 ps
CPU time 24.71 seconds
Started Feb 29 01:37:53 PM PST 24
Finished Feb 29 01:38:18 PM PST 24
Peak memory 216240 kb
Host smart-ae1e412b-b4e7-48c8-a948-779064a01634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946343746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3946343746
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.817551511
Short name T587
Test name
Test status
Simulation time 18221308 ps
CPU time 0.87 seconds
Started Feb 29 01:37:55 PM PST 24
Finished Feb 29 01:37:57 PM PST 24
Peak memory 205188 kb
Host smart-4ba79ccd-501c-497e-9648-4e9731f248e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817551511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.817551511
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1458633347
Short name T880
Test name
Test status
Simulation time 209730414 ps
CPU time 1.02 seconds
Started Feb 29 01:37:58 PM PST 24
Finished Feb 29 01:37:59 PM PST 24
Peak memory 206244 kb
Host smart-cccf35ce-4739-4e41-9106-3b29343a33a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458633347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1458633347
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1328085858
Short name T648
Test name
Test status
Simulation time 600448280 ps
CPU time 2.72 seconds
Started Feb 29 01:37:56 PM PST 24
Finished Feb 29 01:37:59 PM PST 24
Peak memory 215988 kb
Host smart-17dd6477-e067-4e76-a495-0a6dcef86a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328085858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1328085858
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3191593173
Short name T987
Test name
Test status
Simulation time 22069982 ps
CPU time 0.75 seconds
Started Feb 29 01:38:03 PM PST 24
Finished Feb 29 01:38:05 PM PST 24
Peak memory 204996 kb
Host smart-26d6327b-83f3-4c05-888c-f88ce03fc0ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191593173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3191593173
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.282513131
Short name T932
Test name
Test status
Simulation time 6291874116 ps
CPU time 6.73 seconds
Started Feb 29 01:38:08 PM PST 24
Finished Feb 29 01:38:15 PM PST 24
Peak memory 233664 kb
Host smart-4507a867-bbb5-4a52-b1aa-61716d937edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282513131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.282513131
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3920090841
Short name T511
Test name
Test status
Simulation time 19658482 ps
CPU time 0.8 seconds
Started Feb 29 01:38:01 PM PST 24
Finished Feb 29 01:38:03 PM PST 24
Peak memory 206300 kb
Host smart-2b68fc4d-a5cf-4e90-97cf-7fa3ce79ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920090841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3920090841
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1465305208
Short name T506
Test name
Test status
Simulation time 6223266087 ps
CPU time 34.16 seconds
Started Feb 29 01:38:01 PM PST 24
Finished Feb 29 01:38:36 PM PST 24
Peak memory 235916 kb
Host smart-fd443b76-4669-4eb2-84b8-2887d726f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465305208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1465305208
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.173704474
Short name T150
Test name
Test status
Simulation time 50089514181 ps
CPU time 353.6 seconds
Started Feb 29 01:38:11 PM PST 24
Finished Feb 29 01:44:06 PM PST 24
Peak memory 265472 kb
Host smart-57a4dd7a-58ce-4976-a9a7-ceb33f6caa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173704474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.173704474
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3978699716
Short name T257
Test name
Test status
Simulation time 66123619646 ps
CPU time 242.49 seconds
Started Feb 29 01:38:04 PM PST 24
Finished Feb 29 01:42:07 PM PST 24
Peak memory 252676 kb
Host smart-1383e1d1-9e90-4e11-950c-fbd27d830fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978699716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3978699716
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.823467379
Short name T848
Test name
Test status
Simulation time 5252515906 ps
CPU time 17.5 seconds
Started Feb 29 01:38:01 PM PST 24
Finished Feb 29 01:38:19 PM PST 24
Peak memory 236644 kb
Host smart-75a293e3-37a0-4a50-b65a-372ecf7403c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823467379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.823467379
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.310170933
Short name T811
Test name
Test status
Simulation time 132234429 ps
CPU time 2.51 seconds
Started Feb 29 01:38:02 PM PST 24
Finished Feb 29 01:38:04 PM PST 24
Peak memory 216288 kb
Host smart-f2a13cea-3bc7-48bc-aa1b-c26f49b99988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310170933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.310170933
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2639928607
Short name T3
Test name
Test status
Simulation time 26806102547 ps
CPU time 28.39 seconds
Started Feb 29 01:38:02 PM PST 24
Finished Feb 29 01:38:31 PM PST 24
Peak memory 239220 kb
Host smart-2a91cd4d-d3d6-4828-b37f-60667241fdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639928607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2639928607
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1526503583
Short name T234
Test name
Test status
Simulation time 15898025999 ps
CPU time 6.09 seconds
Started Feb 29 01:38:04 PM PST 24
Finished Feb 29 01:38:10 PM PST 24
Peak memory 234048 kb
Host smart-492b445e-89f8-4208-85e5-c12fc4d6210a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526503583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1526503583
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.359907981
Short name T315
Test name
Test status
Simulation time 532571107 ps
CPU time 4.06 seconds
Started Feb 29 01:38:02 PM PST 24
Finished Feb 29 01:38:07 PM PST 24
Peak memory 222380 kb
Host smart-89d950d2-64db-4a19-8d2b-a57929d8c156
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=359907981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.359907981
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3725128916
Short name T737
Test name
Test status
Simulation time 8598545686 ps
CPU time 21.67 seconds
Started Feb 29 01:38:03 PM PST 24
Finished Feb 29 01:38:25 PM PST 24
Peak memory 216188 kb
Host smart-c6f09188-794a-460a-8010-4c7a21c97a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725128916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3725128916
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2496989005
Short name T369
Test name
Test status
Simulation time 5715557471 ps
CPU time 14.36 seconds
Started Feb 29 01:38:04 PM PST 24
Finished Feb 29 01:38:19 PM PST 24
Peak memory 216228 kb
Host smart-1b80deb5-869c-4e68-89a9-e69c8e545a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496989005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2496989005
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2636678114
Short name T305
Test name
Test status
Simulation time 760464912 ps
CPU time 7.41 seconds
Started Feb 29 01:38:11 PM PST 24
Finished Feb 29 01:38:20 PM PST 24
Peak memory 216248 kb
Host smart-79dc75a1-eb6d-49fe-a187-f2b71bc1c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636678114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2636678114
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2077336105
Short name T619
Test name
Test status
Simulation time 210691355 ps
CPU time 1.29 seconds
Started Feb 29 01:38:11 PM PST 24
Finished Feb 29 01:38:14 PM PST 24
Peak memory 206240 kb
Host smart-395642a4-d4a0-4172-bccd-9655dfd263d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077336105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2077336105
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.442748534
Short name T168
Test name
Test status
Simulation time 3422677834 ps
CPU time 14.39 seconds
Started Feb 29 01:38:03 PM PST 24
Finished Feb 29 01:38:18 PM PST 24
Peak memory 218688 kb
Host smart-6e528629-70d4-485e-93dc-8a6b6e84767b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442748534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.442748534
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.82423296
Short name T668
Test name
Test status
Simulation time 118384966 ps
CPU time 0.7 seconds
Started Feb 29 01:38:02 PM PST 24
Finished Feb 29 01:38:03 PM PST 24
Peak memory 205164 kb
Host smart-432dba5c-4658-4929-8ec2-ae38850c7553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82423296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.82423296
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.556456848
Short name T695
Test name
Test status
Simulation time 249036508 ps
CPU time 3.6 seconds
Started Feb 29 01:38:08 PM PST 24
Finished Feb 29 01:38:12 PM PST 24
Peak memory 224268 kb
Host smart-a3d49228-0502-4e31-9840-5f5962b9fdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556456848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.556456848
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2988146039
Short name T791
Test name
Test status
Simulation time 34633167 ps
CPU time 0.79 seconds
Started Feb 29 01:38:04 PM PST 24
Finished Feb 29 01:38:05 PM PST 24
Peak memory 205924 kb
Host smart-188afc4e-1db2-478d-828d-f9faac8ce814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988146039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2988146039
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3859041271
Short name T705
Test name
Test status
Simulation time 25389748974 ps
CPU time 55.23 seconds
Started Feb 29 01:38:08 PM PST 24
Finished Feb 29 01:39:03 PM PST 24
Peak memory 263972 kb
Host smart-9d194fdb-6f02-4039-944a-31f0b9b0346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859041271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3859041271
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1541972620
Short name T925
Test name
Test status
Simulation time 74346521374 ps
CPU time 131.4 seconds
Started Feb 29 01:38:11 PM PST 24
Finished Feb 29 01:40:24 PM PST 24
Peak memory 249040 kb
Host smart-61c478b9-82cf-4d66-a743-26e770a2468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541972620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1541972620
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2215570132
Short name T50
Test name
Test status
Simulation time 130724626653 ps
CPU time 165.9 seconds
Started Feb 29 01:38:02 PM PST 24
Finished Feb 29 01:40:48 PM PST 24
Peak memory 272552 kb
Host smart-e4c90ad8-4755-44bb-bc83-2b2e4ddfbd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215570132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2215570132
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1945820508
Short name T292
Test name
Test status
Simulation time 5965781592 ps
CPU time 7.45 seconds
Started Feb 29 01:38:09 PM PST 24
Finished Feb 29 01:38:20 PM PST 24
Peak memory 232396 kb
Host smart-43326e4f-6406-4863-bded-9457571f64bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945820508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1945820508
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.874238358
Short name T213
Test name
Test status
Simulation time 176050109 ps
CPU time 4.9 seconds
Started Feb 29 01:38:04 PM PST 24
Finished Feb 29 01:38:09 PM PST 24
Peak memory 233472 kb
Host smart-63f560bb-425b-4ed0-a5bb-431d38df9d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874238358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.874238358
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3654105760
Short name T46
Test name
Test status
Simulation time 933993387 ps
CPU time 7.28 seconds
Started Feb 29 01:38:09 PM PST 24
Finished Feb 29 01:38:19 PM PST 24
Peak memory 233444 kb
Host smart-629d970c-79b2-419d-ab77-1061e08e8b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654105760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3654105760
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.901270337
Short name T820
Test name
Test status
Simulation time 162907053 ps
CPU time 2.66 seconds
Started Feb 29 01:38:05 PM PST 24
Finished Feb 29 01:38:08 PM PST 24
Peak memory 216764 kb
Host smart-227d2898-17dc-447a-98bd-73005678edfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901270337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.901270337
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2227988362
Short name T687
Test name
Test status
Simulation time 8046395935 ps
CPU time 17.82 seconds
Started Feb 29 01:38:00 PM PST 24
Finished Feb 29 01:38:18 PM PST 24
Peak memory 218684 kb
Host smart-f269afed-4ffd-4047-9793-1939ea8bfbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227988362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2227988362
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3668498281
Short name T45
Test name
Test status
Simulation time 3072896699 ps
CPU time 4.99 seconds
Started Feb 29 01:38:06 PM PST 24
Finished Feb 29 01:38:11 PM PST 24
Peak memory 221272 kb
Host smart-42b5d44f-7f70-4038-9ded-8ab61c0d5171
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3668498281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3668498281
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.841151747
Short name T281
Test name
Test status
Simulation time 40076122685 ps
CPU time 71.98 seconds
Started Feb 29 01:38:09 PM PST 24
Finished Feb 29 01:39:24 PM PST 24
Peak memory 249084 kb
Host smart-0b9ed56c-adf2-4c23-ad70-134b4b08023b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841151747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.841151747
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1597429956
Short name T843
Test name
Test status
Simulation time 19994234241 ps
CPU time 25.9 seconds
Started Feb 29 01:38:11 PM PST 24
Finished Feb 29 01:38:38 PM PST 24
Peak memory 216204 kb
Host smart-c645a9fd-7f77-4a17-8b7e-c06509b5ef81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597429956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1597429956
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.960456828
Short name T696
Test name
Test status
Simulation time 4010716378 ps
CPU time 13.48 seconds
Started Feb 29 01:38:02 PM PST 24
Finished Feb 29 01:38:15 PM PST 24
Peak memory 216224 kb
Host smart-3dc7a96e-d9e3-4f01-ab2e-36221d8454db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960456828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.960456828
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2149152607
Short name T378
Test name
Test status
Simulation time 46138822 ps
CPU time 1.62 seconds
Started Feb 29 01:38:03 PM PST 24
Finished Feb 29 01:38:05 PM PST 24
Peak memory 216052 kb
Host smart-795fd837-b369-42c9-9727-da63147a05f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149152607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2149152607
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2945975239
Short name T701
Test name
Test status
Simulation time 54317643 ps
CPU time 0.68 seconds
Started Feb 29 01:38:08 PM PST 24
Finished Feb 29 01:38:09 PM PST 24
Peak memory 205220 kb
Host smart-8d73ae85-8421-46c9-b34c-90e94bcecfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945975239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2945975239
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.462557800
Short name T603
Test name
Test status
Simulation time 10376386771 ps
CPU time 17.72 seconds
Started Feb 29 01:38:03 PM PST 24
Finished Feb 29 01:38:21 PM PST 24
Peak memory 228980 kb
Host smart-ae96f47c-4995-43f3-9e73-c229b4f67de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462557800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.462557800
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.828341339
Short name T400
Test name
Test status
Simulation time 21978445 ps
CPU time 0.75 seconds
Started Feb 29 01:38:19 PM PST 24
Finished Feb 29 01:38:20 PM PST 24
Peak memory 204208 kb
Host smart-cb5d8ed2-3e17-40c2-9db8-dc36e417bcb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828341339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.828341339
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2986424363
Short name T785
Test name
Test status
Simulation time 51521366 ps
CPU time 2.61 seconds
Started Feb 29 01:38:14 PM PST 24
Finished Feb 29 01:38:17 PM PST 24
Peak memory 233344 kb
Host smart-146d966c-329a-4d05-b725-78d2e6e9860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986424363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2986424363
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3870846579
Short name T727
Test name
Test status
Simulation time 20562053 ps
CPU time 0.78 seconds
Started Feb 29 01:38:03 PM PST 24
Finished Feb 29 01:38:04 PM PST 24
Peak memory 205272 kb
Host smart-8263f5af-d163-457c-90c5-dcef0a0f1f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870846579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3870846579
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.538573287
Short name T72
Test name
Test status
Simulation time 48943215075 ps
CPU time 218.71 seconds
Started Feb 29 01:38:18 PM PST 24
Finished Feb 29 01:41:57 PM PST 24
Peak memory 250112 kb
Host smart-b8bab70f-342c-4186-b34e-bbe2882f2b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538573287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.538573287
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3015731571
Short name T860
Test name
Test status
Simulation time 8503514229 ps
CPU time 62.04 seconds
Started Feb 29 01:38:18 PM PST 24
Finished Feb 29 01:39:20 PM PST 24
Peak memory 255948 kb
Host smart-9f45e616-6ff4-4112-af1d-68c7504b909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015731571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3015731571
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2673334413
Short name T718
Test name
Test status
Simulation time 3145887176 ps
CPU time 14.77 seconds
Started Feb 29 01:38:15 PM PST 24
Finished Feb 29 01:38:30 PM PST 24
Peak memory 233588 kb
Host smart-d018e82a-82ac-4d7c-b764-e84ac0d0bf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673334413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2673334413
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1529630611
Short name T468
Test name
Test status
Simulation time 1024265952 ps
CPU time 3.28 seconds
Started Feb 29 01:38:17 PM PST 24
Finished Feb 29 01:38:21 PM PST 24
Peak memory 233336 kb
Host smart-d8fea234-fd9f-4fc3-a844-2516f12ecaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529630611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1529630611
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3441428960
Short name T780
Test name
Test status
Simulation time 45422668844 ps
CPU time 36.73 seconds
Started Feb 29 01:38:17 PM PST 24
Finished Feb 29 01:38:54 PM PST 24
Peak memory 232616 kb
Host smart-27807cd8-902b-4af0-b743-ebe27bd36010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441428960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3441428960
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3108029346
Short name T981
Test name
Test status
Simulation time 697597079 ps
CPU time 8.47 seconds
Started Feb 29 01:38:24 PM PST 24
Finished Feb 29 01:38:33 PM PST 24
Peak memory 233244 kb
Host smart-0ff6e3e7-93f4-4788-a786-d37d7f6c0ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108029346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3108029346
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.283767944
Short name T578
Test name
Test status
Simulation time 235365484 ps
CPU time 5.08 seconds
Started Feb 29 01:38:06 PM PST 24
Finished Feb 29 01:38:11 PM PST 24
Peak memory 234940 kb
Host smart-bc98e8ea-9e71-487f-b9a2-5898a2eb82d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283767944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.283767944
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3866326847
Short name T57
Test name
Test status
Simulation time 933496929 ps
CPU time 4.55 seconds
Started Feb 29 01:38:15 PM PST 24
Finished Feb 29 01:38:20 PM PST 24
Peak memory 222456 kb
Host smart-9a5ac17d-2c4b-4a8f-9292-e4cb3d5c7324
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3866326847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3866326847
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3641362873
Short name T420
Test name
Test status
Simulation time 289890528 ps
CPU time 1.01 seconds
Started Feb 29 01:38:16 PM PST 24
Finished Feb 29 01:38:17 PM PST 24
Peak memory 206264 kb
Host smart-984cb293-586c-4cb8-8e03-4959f799c808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641362873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3641362873
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2605341512
Short name T951
Test name
Test status
Simulation time 4755999377 ps
CPU time 33.49 seconds
Started Feb 29 01:38:09 PM PST 24
Finished Feb 29 01:38:46 PM PST 24
Peak memory 216060 kb
Host smart-8f1d01a4-0362-4a1f-8df7-11a971509958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605341512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2605341512
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2045521307
Short name T396
Test name
Test status
Simulation time 4227030865 ps
CPU time 13.47 seconds
Started Feb 29 01:38:10 PM PST 24
Finished Feb 29 01:38:26 PM PST 24
Peak memory 216248 kb
Host smart-4f6389fb-2ff9-4a87-b6f6-a5d686699862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045521307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2045521307
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1774509274
Short name T454
Test name
Test status
Simulation time 370555341 ps
CPU time 5.24 seconds
Started Feb 29 01:38:09 PM PST 24
Finished Feb 29 01:38:17 PM PST 24
Peak memory 216168 kb
Host smart-41c9b28a-67b2-4be9-9246-9e0f84450626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774509274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1774509274
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.267811565
Short name T688
Test name
Test status
Simulation time 102310165 ps
CPU time 0.8 seconds
Started Feb 29 01:38:09 PM PST 24
Finished Feb 29 01:38:13 PM PST 24
Peak memory 205152 kb
Host smart-2dcd9c6a-78c7-4910-ba75-9e4310cdd377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267811565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.267811565
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1939896316
Short name T245
Test name
Test status
Simulation time 2441859152 ps
CPU time 5.68 seconds
Started Feb 29 01:38:18 PM PST 24
Finished Feb 29 01:38:24 PM PST 24
Peak memory 217704 kb
Host smart-daa337ea-6ee2-4d49-be09-362127f2c792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939896316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1939896316
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1542264531
Short name T908
Test name
Test status
Simulation time 34311241 ps
CPU time 0.69 seconds
Started Feb 29 01:38:13 PM PST 24
Finished Feb 29 01:38:14 PM PST 24
Peak memory 204844 kb
Host smart-14255b4b-fe9a-44db-b29d-7cf4838b06cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542264531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1542264531
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3610553120
Short name T892
Test name
Test status
Simulation time 497049051 ps
CPU time 4.69 seconds
Started Feb 29 01:38:19 PM PST 24
Finished Feb 29 01:38:24 PM PST 24
Peak memory 220628 kb
Host smart-f85bd2e9-55c0-4789-a356-b5507a7ef9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610553120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3610553120
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3322903635
Short name T402
Test name
Test status
Simulation time 54529454 ps
CPU time 0.76 seconds
Started Feb 29 01:38:15 PM PST 24
Finished Feb 29 01:38:17 PM PST 24
Peak memory 204952 kb
Host smart-f86d2c8f-d7f1-4e3a-8663-091cade2410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322903635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3322903635
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2503669834
Short name T721
Test name
Test status
Simulation time 4356249333 ps
CPU time 46.36 seconds
Started Feb 29 01:38:15 PM PST 24
Finished Feb 29 01:39:02 PM PST 24
Peak memory 249028 kb
Host smart-8fc59b51-afd5-456e-b172-23829e88893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503669834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2503669834
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2232961953
Short name T725
Test name
Test status
Simulation time 66798760422 ps
CPU time 244.16 seconds
Started Feb 29 01:38:16 PM PST 24
Finished Feb 29 01:42:20 PM PST 24
Peak memory 249020 kb
Host smart-e078fbf1-aa1a-4117-9ded-b8a12565d848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232961953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2232961953
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3760445480
Short name T226
Test name
Test status
Simulation time 19131689700 ps
CPU time 74.58 seconds
Started Feb 29 01:38:15 PM PST 24
Finished Feb 29 01:39:30 PM PST 24
Peak memory 238936 kb
Host smart-aec92fdf-7791-4653-b923-389cfcb3d267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760445480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3760445480
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1885484990
Short name T876
Test name
Test status
Simulation time 41351517032 ps
CPU time 32.95 seconds
Started Feb 29 01:38:15 PM PST 24
Finished Feb 29 01:38:48 PM PST 24
Peak memory 237932 kb
Host smart-f54e9c37-5bdc-4a5b-a863-65a1defd9998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885484990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1885484990
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1704023083
Short name T209
Test name
Test status
Simulation time 1708988843 ps
CPU time 5.21 seconds
Started Feb 29 01:38:18 PM PST 24
Finished Feb 29 01:38:24 PM PST 24
Peak memory 217184 kb
Host smart-8de02ac7-5050-4ed4-8bf6-596cb93d66e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704023083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1704023083
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3808235623
Short name T929
Test name
Test status
Simulation time 5043883337 ps
CPU time 7.43 seconds
Started Feb 29 01:38:17 PM PST 24
Finished Feb 29 01:38:25 PM PST 24
Peak memory 224420 kb
Host smart-ad4b72fc-dd44-4ea7-90a5-64fd38965c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808235623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3808235623
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3333602781
Short name T652
Test name
Test status
Simulation time 3751291404 ps
CPU time 8.07 seconds
Started Feb 29 01:38:15 PM PST 24
Finished Feb 29 01:38:24 PM PST 24
Peak memory 234500 kb
Host smart-fe23de18-192b-4b40-970b-f3d9cc02134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333602781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3333602781
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.506451959
Short name T413
Test name
Test status
Simulation time 369327576 ps
CPU time 4.58 seconds
Started Feb 29 01:38:14 PM PST 24
Finished Feb 29 01:38:19 PM PST 24
Peak memory 224224 kb
Host smart-475436a9-baf4-48a6-a0b0-0854ec870921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506451959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.506451959
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3527662322
Short name T783
Test name
Test status
Simulation time 1121415041 ps
CPU time 3.94 seconds
Started Feb 29 01:38:16 PM PST 24
Finished Feb 29 01:38:20 PM PST 24
Peak memory 221800 kb
Host smart-a92ab713-6f2a-447f-bf5f-b8c68504e159
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3527662322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3527662322
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1641736395
Short name T639
Test name
Test status
Simulation time 4485750518 ps
CPU time 35.04 seconds
Started Feb 29 01:38:20 PM PST 24
Finished Feb 29 01:38:55 PM PST 24
Peak memory 251572 kb
Host smart-d6f5f9e5-1ab4-432c-ad2a-fc9429377f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641736395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1641736395
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.42108859
Short name T517
Test name
Test status
Simulation time 765253002 ps
CPU time 6.09 seconds
Started Feb 29 01:38:25 PM PST 24
Finished Feb 29 01:38:32 PM PST 24
Peak memory 216080 kb
Host smart-3e5d1de9-4eb4-4321-92ab-b4b8102ea7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42108859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.42108859
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.364462827
Short name T722
Test name
Test status
Simulation time 2084496096 ps
CPU time 7.85 seconds
Started Feb 29 01:38:18 PM PST 24
Finished Feb 29 01:38:26 PM PST 24
Peak memory 216180 kb
Host smart-8dd67947-a698-40e3-99f2-4832a447690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364462827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.364462827
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3628057737
Short name T557
Test name
Test status
Simulation time 254322205 ps
CPU time 1.86 seconds
Started Feb 29 01:38:17 PM PST 24
Finished Feb 29 01:38:19 PM PST 24
Peak memory 216104 kb
Host smart-eb71032f-43a1-4d5e-9824-5ccbf41fc508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628057737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3628057737
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2324047047
Short name T334
Test name
Test status
Simulation time 240453695 ps
CPU time 1.06 seconds
Started Feb 29 01:38:16 PM PST 24
Finished Feb 29 01:38:17 PM PST 24
Peak memory 205700 kb
Host smart-d3fce042-0b20-4909-804c-973d9a205bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324047047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2324047047
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.906684128
Short name T983
Test name
Test status
Simulation time 9856280689 ps
CPU time 29.43 seconds
Started Feb 29 01:38:20 PM PST 24
Finished Feb 29 01:38:50 PM PST 24
Peak memory 228920 kb
Host smart-b223531f-e511-46bc-98e0-2c7be4fc236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906684128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.906684128
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1373659799
Short name T683
Test name
Test status
Simulation time 22670746 ps
CPU time 0.72 seconds
Started Feb 29 01:38:15 PM PST 24
Finished Feb 29 01:38:17 PM PST 24
Peak memory 204280 kb
Host smart-52d535a0-2211-406a-8e21-2bf51cee1f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373659799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1373659799
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2150372562
Short name T630
Test name
Test status
Simulation time 16530633617 ps
CPU time 5.42 seconds
Started Feb 29 01:38:18 PM PST 24
Finished Feb 29 01:38:24 PM PST 24
Peak memory 224404 kb
Host smart-e4431d7a-f586-4783-bed8-f137d063d973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150372562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2150372562
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3270296949
Short name T946
Test name
Test status
Simulation time 30566679 ps
CPU time 0.75 seconds
Started Feb 29 01:38:16 PM PST 24
Finished Feb 29 01:38:17 PM PST 24
Peak memory 205972 kb
Host smart-34456e39-78c7-40ad-8b92-a5f33fe37e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270296949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3270296949
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1346611464
Short name T194
Test name
Test status
Simulation time 81532665943 ps
CPU time 207.49 seconds
Started Feb 29 01:38:16 PM PST 24
Finished Feb 29 01:41:44 PM PST 24
Peak memory 255016 kb
Host smart-f8eb7007-db05-4937-be0f-500b8b087616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346611464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1346611464
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.393391299
Short name T32
Test name
Test status
Simulation time 49500695320 ps
CPU time 166.68 seconds
Started Feb 29 01:38:14 PM PST 24
Finished Feb 29 01:41:01 PM PST 24
Peak memory 273432 kb
Host smart-fdacb640-9e12-416d-be9f-2650606a2321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393391299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.393391299
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2163389180
Short name T513
Test name
Test status
Simulation time 48554329043 ps
CPU time 124.64 seconds
Started Feb 29 01:38:14 PM PST 24
Finished Feb 29 01:40:19 PM PST 24
Peak memory 249072 kb
Host smart-19be007d-46eb-4165-b393-90ac2209be0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163389180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2163389180
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1245180542
Short name T730
Test name
Test status
Simulation time 589954521 ps
CPU time 8.54 seconds
Started Feb 29 01:38:14 PM PST 24
Finished Feb 29 01:38:23 PM PST 24
Peak memory 232452 kb
Host smart-30a4f27e-89ef-45be-af45-87858ab74790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245180542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1245180542
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.801506212
Short name T445
Test name
Test status
Simulation time 762969147 ps
CPU time 4.03 seconds
Started Feb 29 01:38:17 PM PST 24
Finished Feb 29 01:38:21 PM PST 24
Peak memory 235044 kb
Host smart-00291a78-ad04-46d5-b9e3-e8bf8b284a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801506212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.801506212
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1215629199
Short name T250
Test name
Test status
Simulation time 28679002515 ps
CPU time 22.83 seconds
Started Feb 29 01:38:17 PM PST 24
Finished Feb 29 01:38:40 PM PST 24
Peak memory 240820 kb
Host smart-36b25986-c1b7-42b4-b085-71b3d7ff163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215629199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1215629199
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2619352867
Short name T976
Test name
Test status
Simulation time 21174754782 ps
CPU time 11.52 seconds
Started Feb 29 01:38:24 PM PST 24
Finished Feb 29 01:38:36 PM PST 24
Peak memory 216752 kb
Host smart-a992db31-075b-4288-b188-4d3bd349ab0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619352867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2619352867
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4211880772
Short name T902
Test name
Test status
Simulation time 3381840456 ps
CPU time 12.91 seconds
Started Feb 29 01:38:17 PM PST 24
Finished Feb 29 01:38:30 PM PST 24
Peak memory 219888 kb
Host smart-e5fa6e51-128a-476b-83bb-5b1b201ed279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211880772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4211880772
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.874366541
Short name T471
Test name
Test status
Simulation time 844399464 ps
CPU time 3.62 seconds
Started Feb 29 01:38:16 PM PST 24
Finished Feb 29 01:38:20 PM PST 24
Peak memory 216392 kb
Host smart-49a464e2-4325-4ed3-bbef-25c3ef262e7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=874366541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.874366541
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2571004222
Short name T912
Test name
Test status
Simulation time 9323485385 ps
CPU time 11.46 seconds
Started Feb 29 01:38:24 PM PST 24
Finished Feb 29 01:38:36 PM PST 24
Peak memory 216156 kb
Host smart-9cb4a717-46d1-496d-999e-2f82b1946c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571004222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2571004222
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1385724041
Short name T380
Test name
Test status
Simulation time 714653491 ps
CPU time 3.18 seconds
Started Feb 29 01:38:13 PM PST 24
Finished Feb 29 01:38:17 PM PST 24
Peak memory 207884 kb
Host smart-3853ec4f-1c74-4a40-9d0a-6205ebec72f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385724041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1385724041
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.59766210
Short name T397
Test name
Test status
Simulation time 51379892 ps
CPU time 1.3 seconds
Started Feb 29 01:38:14 PM PST 24
Finished Feb 29 01:38:16 PM PST 24
Peak memory 207840 kb
Host smart-cda49f21-7f42-4a92-b4ef-edf720e4b09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59766210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.59766210
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3759335080
Short name T915
Test name
Test status
Simulation time 112271463 ps
CPU time 0.93 seconds
Started Feb 29 01:38:17 PM PST 24
Finished Feb 29 01:38:18 PM PST 24
Peak memory 205196 kb
Host smart-176601a7-b74a-4126-bbd5-6da64dde2c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759335080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3759335080
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2116383693
Short name T430
Test name
Test status
Simulation time 1957021493 ps
CPU time 8.03 seconds
Started Feb 29 01:38:18 PM PST 24
Finished Feb 29 01:38:26 PM PST 24
Peak memory 228496 kb
Host smart-215adc94-da63-49cb-8ae6-c76d322df7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116383693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2116383693
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4242119184
Short name T609
Test name
Test status
Simulation time 13415450 ps
CPU time 0.69 seconds
Started Feb 29 01:36:11 PM PST 24
Finished Feb 29 01:36:11 PM PST 24
Peak memory 204840 kb
Host smart-7b66d674-b9ea-4e63-be92-7b2e99d5c43f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242119184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
242119184
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3799664735
Short name T953
Test name
Test status
Simulation time 14103413055 ps
CPU time 12.07 seconds
Started Feb 29 01:36:12 PM PST 24
Finished Feb 29 01:36:24 PM PST 24
Peak memory 224364 kb
Host smart-0fcffeee-3403-43dc-b41f-91b76ea74028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799664735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3799664735
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1006109475
Short name T836
Test name
Test status
Simulation time 60630006 ps
CPU time 0.74 seconds
Started Feb 29 01:35:56 PM PST 24
Finished Feb 29 01:35:57 PM PST 24
Peak memory 205960 kb
Host smart-70c025c0-605a-4970-a047-9710317de6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006109475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1006109475
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1582859120
Short name T830
Test name
Test status
Simulation time 8565142582 ps
CPU time 52.86 seconds
Started Feb 29 01:36:12 PM PST 24
Finished Feb 29 01:37:05 PM PST 24
Peak memory 238468 kb
Host smart-d6a88bd0-a508-4c04-8e6d-92afc801b851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582859120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1582859120
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3207721792
Short name T279
Test name
Test status
Simulation time 31300271411 ps
CPU time 243.78 seconds
Started Feb 29 01:36:10 PM PST 24
Finished Feb 29 01:40:14 PM PST 24
Peak memory 252648 kb
Host smart-c3917eb9-4941-4801-aa26-11b553890c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207721792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3207721792
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3624076655
Short name T267
Test name
Test status
Simulation time 362122710957 ps
CPU time 232.57 seconds
Started Feb 29 01:36:15 PM PST 24
Finished Feb 29 01:40:08 PM PST 24
Peak memory 271368 kb
Host smart-dfbcd665-fb0a-4056-96f0-07c695c63433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624076655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3624076655
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2003312902
Short name T547
Test name
Test status
Simulation time 7573134653 ps
CPU time 38.17 seconds
Started Feb 29 01:36:10 PM PST 24
Finished Feb 29 01:36:48 PM PST 24
Peak memory 251028 kb
Host smart-ecd967c3-664e-4fc4-9c13-4bfeaff864de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003312902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2003312902
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1809563797
Short name T219
Test name
Test status
Simulation time 665063567 ps
CPU time 6.56 seconds
Started Feb 29 01:36:11 PM PST 24
Finished Feb 29 01:36:18 PM PST 24
Peak memory 233396 kb
Host smart-14d70843-19cb-4303-808b-a3bb7528d85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809563797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1809563797
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1447590699
Short name T228
Test name
Test status
Simulation time 412093676 ps
CPU time 2.59 seconds
Started Feb 29 01:36:13 PM PST 24
Finished Feb 29 01:36:15 PM PST 24
Peak memory 216116 kb
Host smart-4820f53a-49e0-47b5-86c9-97e2ec429eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447590699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1447590699
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1389851633
Short name T861
Test name
Test status
Simulation time 14811476 ps
CPU time 1.12 seconds
Started Feb 29 01:36:01 PM PST 24
Finished Feb 29 01:36:03 PM PST 24
Peak memory 216560 kb
Host smart-512c5e1e-61ae-43a5-8f4e-c79a08facbd3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389851633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1389851633
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3356598391
Short name T717
Test name
Test status
Simulation time 726887478 ps
CPU time 6.02 seconds
Started Feb 29 01:36:10 PM PST 24
Finished Feb 29 01:36:16 PM PST 24
Peak memory 232716 kb
Host smart-7a14c576-0fa4-495b-9308-c8dde750fd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356598391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3356598391
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2188299722
Short name T570
Test name
Test status
Simulation time 35280275571 ps
CPU time 53.95 seconds
Started Feb 29 01:36:11 PM PST 24
Finished Feb 29 01:37:05 PM PST 24
Peak memory 245944 kb
Host smart-d3df7afe-c042-4816-a643-428405d707cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188299722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2188299722
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.1721702021
Short name T544
Test name
Test status
Simulation time 28116663 ps
CPU time 0.78 seconds
Started Feb 29 01:36:00 PM PST 24
Finished Feb 29 01:36:01 PM PST 24
Peak memory 216008 kb
Host smart-cb41bf1a-6f54-43d6-b497-7c4e8b62b022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721702021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.1721702021
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4193159141
Short name T347
Test name
Test status
Simulation time 566269754 ps
CPU time 3.94 seconds
Started Feb 29 01:36:12 PM PST 24
Finished Feb 29 01:36:16 PM PST 24
Peak memory 221848 kb
Host smart-33f85af9-d4ad-41c8-9bac-fa5a95aeedeb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4193159141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4193159141
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1711679697
Short name T55
Test name
Test status
Simulation time 75806002 ps
CPU time 1.01 seconds
Started Feb 29 01:36:14 PM PST 24
Finished Feb 29 01:36:15 PM PST 24
Peak memory 234768 kb
Host smart-f09fe2de-cda8-410c-95e7-1cefb08282b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711679697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1711679697
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2850872108
Short name T351
Test name
Test status
Simulation time 7207023141 ps
CPU time 33.34 seconds
Started Feb 29 01:36:12 PM PST 24
Finished Feb 29 01:36:45 PM PST 24
Peak memory 249228 kb
Host smart-de509932-9bd7-4839-bcdc-6e12c1ae9717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850872108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2850872108
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3093018797
Short name T913
Test name
Test status
Simulation time 28625027830 ps
CPU time 34.23 seconds
Started Feb 29 01:35:56 PM PST 24
Finished Feb 29 01:36:31 PM PST 24
Peak memory 216188 kb
Host smart-31aa1029-b48d-4e42-a782-e9087218a846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093018797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3093018797
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2306666979
Short name T753
Test name
Test status
Simulation time 1191223992 ps
CPU time 4.08 seconds
Started Feb 29 01:36:01 PM PST 24
Finished Feb 29 01:36:06 PM PST 24
Peak memory 216072 kb
Host smart-45c16fa6-204e-4403-9da1-06650f74d280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306666979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2306666979
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3361971344
Short name T702
Test name
Test status
Simulation time 132504342 ps
CPU time 1.1 seconds
Started Feb 29 01:35:59 PM PST 24
Finished Feb 29 01:36:01 PM PST 24
Peak memory 206608 kb
Host smart-3634b9ee-9516-457e-bfba-dcf1cec84e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361971344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3361971344
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2679769273
Short name T579
Test name
Test status
Simulation time 153083062 ps
CPU time 0.99 seconds
Started Feb 29 01:36:00 PM PST 24
Finished Feb 29 01:36:02 PM PST 24
Peak memory 206248 kb
Host smart-b0875473-7e0c-41e4-8b73-bab89595e574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679769273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2679769273
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2054951444
Short name T555
Test name
Test status
Simulation time 26817764287 ps
CPU time 28.36 seconds
Started Feb 29 01:36:11 PM PST 24
Finished Feb 29 01:36:39 PM PST 24
Peak memory 247580 kb
Host smart-3a3d45bb-7a7b-4dde-b5e9-846dfa7cb11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054951444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2054951444
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1111470392
Short name T990
Test name
Test status
Simulation time 23287512 ps
CPU time 0.77 seconds
Started Feb 29 01:38:29 PM PST 24
Finished Feb 29 01:38:30 PM PST 24
Peak memory 204800 kb
Host smart-7d8c7d82-9968-48a0-bc20-afa7fa02111b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111470392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1111470392
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1199746997
Short name T839
Test name
Test status
Simulation time 1347357635 ps
CPU time 3.82 seconds
Started Feb 29 01:38:30 PM PST 24
Finished Feb 29 01:38:34 PM PST 24
Peak memory 233404 kb
Host smart-39b328f2-6079-4540-9556-f00a66b64ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199746997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1199746997
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.741200237
Short name T522
Test name
Test status
Simulation time 23112390 ps
CPU time 0.83 seconds
Started Feb 29 01:38:20 PM PST 24
Finished Feb 29 01:38:21 PM PST 24
Peak memory 206108 kb
Host smart-a1ba0b24-9cd6-40c4-ad04-e678461abe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741200237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.741200237
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1871973593
Short name T886
Test name
Test status
Simulation time 17093319005 ps
CPU time 58.24 seconds
Started Feb 29 01:38:33 PM PST 24
Finished Feb 29 01:39:32 PM PST 24
Peak memory 256876 kb
Host smart-1650305f-0233-4862-aa6a-be0f78b52c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871973593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1871973593
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3655991748
Short name T752
Test name
Test status
Simulation time 3239722346 ps
CPU time 58.09 seconds
Started Feb 29 01:38:30 PM PST 24
Finished Feb 29 01:39:28 PM PST 24
Peak memory 253544 kb
Host smart-f84fd186-8174-4944-8f2c-8351fe30c532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655991748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3655991748
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3355991037
Short name T288
Test name
Test status
Simulation time 44213800824 ps
CPU time 191.34 seconds
Started Feb 29 01:38:31 PM PST 24
Finished Feb 29 01:41:42 PM PST 24
Peak memory 265096 kb
Host smart-48033ba4-f286-444f-8e95-dff83bc62769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355991037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3355991037
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.916012678
Short name T590
Test name
Test status
Simulation time 4222702428 ps
CPU time 24.55 seconds
Started Feb 29 01:38:32 PM PST 24
Finished Feb 29 01:38:57 PM PST 24
Peak memory 235676 kb
Host smart-e925f98e-2da2-4f26-bf2a-390982ccaf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916012678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.916012678
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3434809291
Short name T477
Test name
Test status
Simulation time 37378594 ps
CPU time 2.68 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:38:31 PM PST 24
Peak memory 232508 kb
Host smart-8dc0b31a-2169-45ed-aced-81bad14cbcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434809291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3434809291
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1016122989
Short name T220
Test name
Test status
Simulation time 715965331 ps
CPU time 9.84 seconds
Started Feb 29 01:38:30 PM PST 24
Finished Feb 29 01:38:40 PM PST 24
Peak memory 232496 kb
Host smart-43dcade8-ad77-48cc-93aa-4051fc1d86df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016122989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1016122989
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1991757526
Short name T821
Test name
Test status
Simulation time 5841663731 ps
CPU time 16.9 seconds
Started Feb 29 01:38:29 PM PST 24
Finished Feb 29 01:38:46 PM PST 24
Peak memory 233668 kb
Host smart-0e8e783c-bcce-42b4-bb4b-fd66979f57ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991757526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1991757526
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.489951826
Short name T526
Test name
Test status
Simulation time 10969207240 ps
CPU time 13.5 seconds
Started Feb 29 01:38:31 PM PST 24
Finished Feb 29 01:38:45 PM PST 24
Peak memory 233312 kb
Host smart-e834116e-c323-4df8-8e34-d31284c429ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489951826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.489951826
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1315226507
Short name T670
Test name
Test status
Simulation time 405426888 ps
CPU time 3.62 seconds
Started Feb 29 01:38:30 PM PST 24
Finished Feb 29 01:38:34 PM PST 24
Peak memory 222036 kb
Host smart-889dfc10-1ea5-43a7-adda-d9d3a381ce62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1315226507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1315226507
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2236885638
Short name T301
Test name
Test status
Simulation time 45394269 ps
CPU time 1 seconds
Started Feb 29 01:38:27 PM PST 24
Finished Feb 29 01:38:29 PM PST 24
Peak memory 204900 kb
Host smart-94449936-c078-4a81-8c35-ee0b7e102ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236885638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2236885638
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3134492285
Short name T349
Test name
Test status
Simulation time 17868699211 ps
CPU time 21.55 seconds
Started Feb 29 01:38:17 PM PST 24
Finished Feb 29 01:38:38 PM PST 24
Peak memory 216192 kb
Host smart-6e540fa9-1543-451b-86da-4d63588345f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134492285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3134492285
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.66837637
Short name T303
Test name
Test status
Simulation time 5238740354 ps
CPU time 20.65 seconds
Started Feb 29 01:38:15 PM PST 24
Finished Feb 29 01:38:36 PM PST 24
Peak memory 216104 kb
Host smart-c79386e9-fb37-4400-9c4e-7acd8ada1740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66837637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.66837637
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2669412415
Short name T964
Test name
Test status
Simulation time 767590040 ps
CPU time 2.3 seconds
Started Feb 29 01:38:29 PM PST 24
Finished Feb 29 01:38:32 PM PST 24
Peak memory 216052 kb
Host smart-0bbb2c32-abb0-4b9a-b676-a92eebeb93ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669412415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2669412415
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3731272090
Short name T664
Test name
Test status
Simulation time 68482664 ps
CPU time 0.94 seconds
Started Feb 29 01:38:30 PM PST 24
Finished Feb 29 01:38:31 PM PST 24
Peak memory 205696 kb
Host smart-e5f98ea4-e53b-4bc4-95be-289f1f271fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731272090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3731272090
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4018538322
Short name T166
Test name
Test status
Simulation time 24580396987 ps
CPU time 35.22 seconds
Started Feb 29 01:38:29 PM PST 24
Finished Feb 29 01:39:04 PM PST 24
Peak memory 227988 kb
Host smart-ede637a2-9d81-4d17-b375-9ac6fbab2f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018538322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4018538322
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.815487835
Short name T572
Test name
Test status
Simulation time 24972710 ps
CPU time 0.7 seconds
Started Feb 29 01:38:30 PM PST 24
Finished Feb 29 01:38:31 PM PST 24
Peak memory 205308 kb
Host smart-4103f44e-0bdc-4995-ab29-594cdad5506d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815487835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.815487835
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2867522219
Short name T638
Test name
Test status
Simulation time 488509943 ps
CPU time 4.23 seconds
Started Feb 29 01:38:31 PM PST 24
Finished Feb 29 01:38:36 PM PST 24
Peak memory 234148 kb
Host smart-dae08bda-250b-42a9-98a9-133fdbfe25cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867522219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2867522219
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3995123557
Short name T148
Test name
Test status
Simulation time 17256779 ps
CPU time 0.75 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:38:29 PM PST 24
Peak memory 205256 kb
Host smart-645a3c07-42fe-47e5-86ae-29c0f22f0740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995123557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3995123557
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.651118837
Short name T842
Test name
Test status
Simulation time 15423555146 ps
CPU time 77.1 seconds
Started Feb 29 01:38:33 PM PST 24
Finished Feb 29 01:39:50 PM PST 24
Peak memory 250152 kb
Host smart-9c2fb5d1-5844-42dd-a6fa-3cfe30093bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651118837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.651118837
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.869727062
Short name T191
Test name
Test status
Simulation time 131067088599 ps
CPU time 294.68 seconds
Started Feb 29 01:38:33 PM PST 24
Finished Feb 29 01:43:28 PM PST 24
Peak memory 265416 kb
Host smart-c6bdae7f-2baa-4458-9da2-e5ab9a8555ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869727062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.869727062
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4090674787
Short name T797
Test name
Test status
Simulation time 5300161124 ps
CPU time 34.22 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:39:03 PM PST 24
Peak memory 240524 kb
Host smart-226e82ef-dd0e-470a-b769-ce1d880e67e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090674787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4090674787
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.541844875
Short name T748
Test name
Test status
Simulation time 1147079511 ps
CPU time 3.49 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:38:31 PM PST 24
Peak memory 216176 kb
Host smart-7f4cc8cb-a50a-48a4-a2fb-c9050d98d28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541844875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.541844875
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2121480918
Short name T169
Test name
Test status
Simulation time 3307319409 ps
CPU time 10.3 seconds
Started Feb 29 01:38:29 PM PST 24
Finished Feb 29 01:38:40 PM PST 24
Peak memory 233400 kb
Host smart-4c65638a-4188-4afd-a6c8-7388043296cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121480918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2121480918
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.755156723
Short name T711
Test name
Test status
Simulation time 5497930463 ps
CPU time 5.34 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:38:34 PM PST 24
Peak memory 216188 kb
Host smart-9cd085bc-0a22-41a1-bb09-959ad5b27f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755156723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.755156723
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.803449457
Short name T224
Test name
Test status
Simulation time 9331005994 ps
CPU time 8.4 seconds
Started Feb 29 01:38:31 PM PST 24
Finished Feb 29 01:38:39 PM PST 24
Peak memory 224316 kb
Host smart-30417f26-4874-4687-8120-57090657b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803449457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.803449457
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2234220163
Short name T309
Test name
Test status
Simulation time 3065054373 ps
CPU time 4.38 seconds
Started Feb 29 01:38:33 PM PST 24
Finished Feb 29 01:38:38 PM PST 24
Peak memory 216312 kb
Host smart-e555c505-c0ea-49ad-9682-8e76753dde7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2234220163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2234220163
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.39463018
Short name T943
Test name
Test status
Simulation time 52328899 ps
CPU time 1 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:38:29 PM PST 24
Peak memory 206316 kb
Host smart-90864ac7-35d6-4bee-a4cf-9ac7fbdc9437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39463018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress
_all.39463018
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1361256103
Short name T427
Test name
Test status
Simulation time 12379735588 ps
CPU time 56.57 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:39:24 PM PST 24
Peak memory 220432 kb
Host smart-fdcfc8d7-1154-4126-b21b-d2621d019b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361256103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1361256103
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3144949748
Short name T319
Test name
Test status
Simulation time 1814045416 ps
CPU time 8.09 seconds
Started Feb 29 01:38:31 PM PST 24
Finished Feb 29 01:38:40 PM PST 24
Peak memory 207960 kb
Host smart-a2288d33-40d0-402e-99db-7265b87e29fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144949748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3144949748
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2791868492
Short name T818
Test name
Test status
Simulation time 316973084 ps
CPU time 4.71 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:38:33 PM PST 24
Peak memory 216104 kb
Host smart-e36086c1-4b15-41df-8114-4279eb64d87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791868492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2791868492
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3780697544
Short name T550
Test name
Test status
Simulation time 22880273 ps
CPU time 0.75 seconds
Started Feb 29 01:38:30 PM PST 24
Finished Feb 29 01:38:31 PM PST 24
Peak memory 205224 kb
Host smart-9b5f1efc-58ce-436f-8adb-5ab48af3ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780697544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3780697544
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2997700571
Short name T183
Test name
Test status
Simulation time 26051546140 ps
CPU time 23.42 seconds
Started Feb 29 01:38:33 PM PST 24
Finished Feb 29 01:38:58 PM PST 24
Peak memory 230504 kb
Host smart-e04669c5-8ee4-4c23-85b4-c31732e172e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997700571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2997700571
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2813484373
Short name T775
Test name
Test status
Simulation time 18197900 ps
CPU time 0.69 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:38:43 PM PST 24
Peak memory 204260 kb
Host smart-b3d1e985-a218-44ea-a7b1-059775544316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813484373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2813484373
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.456067903
Short name T227
Test name
Test status
Simulation time 32031121781 ps
CPU time 7.01 seconds
Started Feb 29 01:38:29 PM PST 24
Finished Feb 29 01:38:36 PM PST 24
Peak memory 233616 kb
Host smart-09d90c01-e562-4965-a549-4b83799bcb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456067903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.456067903
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.275032778
Short name T440
Test name
Test status
Simulation time 26961962 ps
CPU time 0.8 seconds
Started Feb 29 01:38:31 PM PST 24
Finished Feb 29 01:38:33 PM PST 24
Peak memory 205980 kb
Host smart-c35a839d-493b-42ae-ae94-5ab95043c8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275032778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.275032778
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.576838019
Short name T641
Test name
Test status
Simulation time 4108190968 ps
CPU time 28.5 seconds
Started Feb 29 01:38:34 PM PST 24
Finished Feb 29 01:39:03 PM PST 24
Peak memory 240752 kb
Host smart-66b3ebc4-f9bc-483f-8c98-81819c1a3eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576838019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.576838019
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3883567985
Short name T893
Test name
Test status
Simulation time 42165307646 ps
CPU time 252.73 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:42:41 PM PST 24
Peak memory 249092 kb
Host smart-4b451760-47c5-4227-878f-28d1225e346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883567985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3883567985
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1885191479
Short name T438
Test name
Test status
Simulation time 58499805546 ps
CPU time 79.54 seconds
Started Feb 29 01:38:38 PM PST 24
Finished Feb 29 01:39:58 PM PST 24
Peak memory 236532 kb
Host smart-890b26b4-cca6-4f17-9488-c25d497c3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885191479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1885191479
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4170601665
Short name T972
Test name
Test status
Simulation time 1904630437 ps
CPU time 10.57 seconds
Started Feb 29 01:38:31 PM PST 24
Finished Feb 29 01:38:42 PM PST 24
Peak memory 240552 kb
Host smart-422bafd1-4fbd-486e-8f43-273026fa67a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170601665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4170601665
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4138320262
Short name T529
Test name
Test status
Simulation time 90878421 ps
CPU time 2.3 seconds
Started Feb 29 01:38:32 PM PST 24
Finished Feb 29 01:38:35 PM PST 24
Peak memory 224236 kb
Host smart-eac930d3-9e53-4ffd-990b-a6df52d5680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138320262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4138320262
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3112215941
Short name T875
Test name
Test status
Simulation time 8051946847 ps
CPU time 18.42 seconds
Started Feb 29 01:38:33 PM PST 24
Finished Feb 29 01:38:51 PM PST 24
Peak memory 216844 kb
Host smart-bda45294-9c9f-424f-b9fd-659fac0850d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112215941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3112215941
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1220329413
Short name T482
Test name
Test status
Simulation time 46009696 ps
CPU time 2.84 seconds
Started Feb 29 01:38:31 PM PST 24
Finished Feb 29 01:38:34 PM PST 24
Peak memory 232516 kb
Host smart-6f2d8975-4b08-4436-919f-ecf94b28f82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220329413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1220329413
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2215454138
Short name T973
Test name
Test status
Simulation time 1241279662 ps
CPU time 11.11 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:38:39 PM PST 24
Peak memory 232340 kb
Host smart-b9f43acd-37c1-48eb-9b68-bbe42c9de6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215454138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2215454138
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1098445423
Short name T481
Test name
Test status
Simulation time 179581477 ps
CPU time 3.91 seconds
Started Feb 29 01:38:30 PM PST 24
Finished Feb 29 01:38:35 PM PST 24
Peak memory 221896 kb
Host smart-5cdaff4c-2acd-443d-8e9d-674485879a66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1098445423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1098445423
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1112711429
Short name T552
Test name
Test status
Simulation time 4997261256 ps
CPU time 21.67 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:39:03 PM PST 24
Peak memory 232616 kb
Host smart-7b094e65-16db-4c57-b99d-dfcabb5c86a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112711429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1112711429
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3655365119
Short name T373
Test name
Test status
Simulation time 5448586989 ps
CPU time 17.77 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:38:46 PM PST 24
Peak memory 216216 kb
Host smart-d34332d9-19e9-4eed-a341-9a156c5903ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655365119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3655365119
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3375574112
Short name T394
Test name
Test status
Simulation time 17693887306 ps
CPU time 9.32 seconds
Started Feb 29 01:38:32 PM PST 24
Finished Feb 29 01:38:42 PM PST 24
Peak memory 216112 kb
Host smart-55c94a69-5018-4426-b581-dfdb7fcc61eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375574112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3375574112
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1441044029
Short name T945
Test name
Test status
Simulation time 90386258 ps
CPU time 1.05 seconds
Started Feb 29 01:38:31 PM PST 24
Finished Feb 29 01:38:33 PM PST 24
Peak memory 206452 kb
Host smart-735795f5-ecd4-47db-b27f-dbdddd39a8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441044029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1441044029
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3511682427
Short name T760
Test name
Test status
Simulation time 227574184 ps
CPU time 0.92 seconds
Started Feb 29 01:38:29 PM PST 24
Finished Feb 29 01:38:30 PM PST 24
Peak memory 205228 kb
Host smart-599bcc21-6b81-4b2b-bbd3-e8ddec9f4dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511682427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3511682427
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2386107516
Short name T585
Test name
Test status
Simulation time 509769727 ps
CPU time 5.52 seconds
Started Feb 29 01:38:28 PM PST 24
Finished Feb 29 01:38:34 PM PST 24
Peak memory 222332 kb
Host smart-a177d236-6229-45f7-ad5d-49aef13a3fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386107516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2386107516
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.325659745
Short name T62
Test name
Test status
Simulation time 14247607 ps
CPU time 0.71 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:38:43 PM PST 24
Peak memory 204960 kb
Host smart-b8b87d37-a455-4429-a321-9878049a5f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325659745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.325659745
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1366655421
Short name T43
Test name
Test status
Simulation time 299755056 ps
CPU time 2.73 seconds
Started Feb 29 01:38:40 PM PST 24
Finished Feb 29 01:38:43 PM PST 24
Peak memory 224220 kb
Host smart-354112d5-3871-438e-aa51-9f7f21bcf396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366655421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1366655421
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3267597622
Short name T991
Test name
Test status
Simulation time 119643068 ps
CPU time 0.76 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:38:44 PM PST 24
Peak memory 205960 kb
Host smart-198e78e8-f936-4c1d-8fec-cc56af0bbc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267597622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3267597622
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3734246527
Short name T713
Test name
Test status
Simulation time 4285190779 ps
CPU time 20.11 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:39:02 PM PST 24
Peak memory 234460 kb
Host smart-f1e6d0b3-906c-4b85-9645-13152468bdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734246527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3734246527
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.325233582
Short name T186
Test name
Test status
Simulation time 33526879052 ps
CPU time 81.59 seconds
Started Feb 29 01:38:39 PM PST 24
Finished Feb 29 01:40:01 PM PST 24
Peak memory 265728 kb
Host smart-a3c8f0f4-a44a-4579-adfc-bed9d0a42bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325233582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.325233582
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3228306729
Short name T723
Test name
Test status
Simulation time 7793867085 ps
CPU time 62.67 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:39:45 PM PST 24
Peak memory 249000 kb
Host smart-bff95c0d-8c9f-4961-97d8-8af900f8c7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228306729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3228306729
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.112537511
Short name T605
Test name
Test status
Simulation time 20261372059 ps
CPU time 26.88 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:39:08 PM PST 24
Peak memory 237648 kb
Host smart-77df6fab-9e8d-4e2f-aa77-562492808e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112537511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.112537511
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3662922056
Short name T222
Test name
Test status
Simulation time 2068097950 ps
CPU time 5.25 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:38:50 PM PST 24
Peak memory 233320 kb
Host smart-b7999900-73f5-4014-8c4d-e1a0e209aa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662922056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3662922056
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4219627142
Short name T189
Test name
Test status
Simulation time 5200981897 ps
CPU time 20.34 seconds
Started Feb 29 01:38:40 PM PST 24
Finished Feb 29 01:39:01 PM PST 24
Peak memory 234588 kb
Host smart-4980a714-7a7a-451b-a7b5-2a2d80d89935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219627142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4219627142
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3475458823
Short name T901
Test name
Test status
Simulation time 11532790288 ps
CPU time 32.07 seconds
Started Feb 29 01:38:43 PM PST 24
Finished Feb 29 01:39:16 PM PST 24
Peak memory 234412 kb
Host smart-a01af09e-9839-4d99-b138-df9e9f15d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475458823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3475458823
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.566718502
Short name T523
Test name
Test status
Simulation time 1545044567 ps
CPU time 8.23 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:38:50 PM PST 24
Peak memory 235752 kb
Host smart-b27277cb-fce7-4f9a-97c0-f8478967648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566718502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.566718502
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2698932851
Short name T53
Test name
Test status
Simulation time 3968309817 ps
CPU time 5.17 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:38:49 PM PST 24
Peak memory 216516 kb
Host smart-3d4a4422-01e9-4a3b-be92-99443450c8fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2698932851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2698932851
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3827560896
Short name T142
Test name
Test status
Simulation time 9468960805 ps
CPU time 66.86 seconds
Started Feb 29 01:38:46 PM PST 24
Finished Feb 29 01:39:53 PM PST 24
Peak memory 254196 kb
Host smart-693539eb-da41-4546-803c-e8e19164227e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827560896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3827560896
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1067970643
Short name T716
Test name
Test status
Simulation time 19600287519 ps
CPU time 53.46 seconds
Started Feb 29 01:38:43 PM PST 24
Finished Feb 29 01:39:37 PM PST 24
Peak memory 216156 kb
Host smart-b0a10b5c-e4a6-4203-a326-600226267b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067970643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1067970643
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1428280900
Short name T994
Test name
Test status
Simulation time 2847962151 ps
CPU time 13.42 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:38:58 PM PST 24
Peak memory 216232 kb
Host smart-7bb13b1f-7449-4ca8-a4d6-edea581bf776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428280900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1428280900
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2441025783
Short name T472
Test name
Test status
Simulation time 16589502 ps
CPU time 0.84 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:38:42 PM PST 24
Peak memory 205208 kb
Host smart-cbe283d1-c630-4f80-9229-d5a1e799b370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441025783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2441025783
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.448110116
Short name T307
Test name
Test status
Simulation time 127088794 ps
CPU time 1.18 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:38:43 PM PST 24
Peak memory 206228 kb
Host smart-b1dc509a-afcb-4d9c-8fab-9dd13d6a3033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448110116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.448110116
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.526869614
Short name T736
Test name
Test status
Simulation time 19000277753 ps
CPU time 49.06 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:39:34 PM PST 24
Peak memory 231172 kb
Host smart-437e6964-ccfe-422d-8e0c-d7ea87f235f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526869614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.526869614
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3154684695
Short name T63
Test name
Test status
Simulation time 24956204 ps
CPU time 0.75 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:38:42 PM PST 24
Peak memory 205124 kb
Host smart-47daa66c-360b-462b-b4a8-555a1ae5af44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154684695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3154684695
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3475939040
Short name T667
Test name
Test status
Simulation time 158710528 ps
CPU time 3.3 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:38:45 PM PST 24
Peak memory 233464 kb
Host smart-3af1593b-0b3b-4cae-bfd5-b515a2d0418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475939040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3475939040
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1600686931
Short name T514
Test name
Test status
Simulation time 40145895 ps
CPU time 0.83 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:38:43 PM PST 24
Peak memory 206004 kb
Host smart-907fffdc-ab25-48a3-8570-521a7734552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600686931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1600686931
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3024846917
Short name T13
Test name
Test status
Simulation time 4961763316 ps
CPU time 40.98 seconds
Started Feb 29 01:38:46 PM PST 24
Finished Feb 29 01:39:27 PM PST 24
Peak memory 257148 kb
Host smart-a9fbffe2-4620-4631-9b38-4ebe55a76a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024846917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3024846917
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3938807596
Short name T207
Test name
Test status
Simulation time 53415220603 ps
CPU time 139.71 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:41:02 PM PST 24
Peak memory 252808 kb
Host smart-15d1c57d-078c-48a5-95d5-ec712bee6bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938807596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3938807596
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.700196026
Short name T28
Test name
Test status
Simulation time 16630846331 ps
CPU time 59.24 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:39:41 PM PST 24
Peak memory 232684 kb
Host smart-31267e05-798b-4a7d-a99c-932e9b98062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700196026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.700196026
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.72002102
Short name T459
Test name
Test status
Simulation time 1558240263 ps
CPU time 15.13 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:39:00 PM PST 24
Peak memory 245948 kb
Host smart-ebb35d63-90c6-4a03-b99d-600d02011d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72002102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.72002102
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2784901405
Short name T569
Test name
Test status
Simulation time 1858512177 ps
CPU time 7.3 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:38:49 PM PST 24
Peak memory 233224 kb
Host smart-bef486d0-b8ba-4f95-9e3f-83e27f079d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784901405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2784901405
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2713465051
Short name T179
Test name
Test status
Simulation time 320129942 ps
CPU time 5.37 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:38:47 PM PST 24
Peak memory 234644 kb
Host smart-c03f980a-eb45-4559-86e6-4307accc021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713465051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2713465051
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1317380499
Short name T583
Test name
Test status
Simulation time 3529074030 ps
CPU time 7.47 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:38:50 PM PST 24
Peak memory 216268 kb
Host smart-af50ecf6-22c4-43a8-8e8a-acd566186f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317380499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1317380499
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2775198092
Short name T15
Test name
Test status
Simulation time 102362098 ps
CPU time 3.14 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:38:45 PM PST 24
Peak memory 233104 kb
Host smart-15261fa5-e9a9-41a3-aac5-56bd652eca3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775198092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2775198092
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1179593455
Short name T628
Test name
Test status
Simulation time 6223406771 ps
CPU time 4.34 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:38:49 PM PST 24
Peak memory 218680 kb
Host smart-0464f2c4-c6da-44d4-9945-0d1010a6bf8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1179593455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1179593455
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2834322490
Short name T654
Test name
Test status
Simulation time 295682702069 ps
CPU time 536.12 seconds
Started Feb 29 01:38:43 PM PST 24
Finished Feb 29 01:47:39 PM PST 24
Peak memory 281644 kb
Host smart-c425aa72-689d-4905-a239-cae097581929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834322490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2834322490
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.224739350
Short name T337
Test name
Test status
Simulation time 25541897798 ps
CPU time 31.67 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:39:13 PM PST 24
Peak memory 216152 kb
Host smart-30a8103e-35c8-4dcc-9222-3e88bab1f686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224739350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.224739350
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2312651043
Short name T321
Test name
Test status
Simulation time 1793479178 ps
CPU time 12.16 seconds
Started Feb 29 01:38:45 PM PST 24
Finished Feb 29 01:38:58 PM PST 24
Peak memory 215876 kb
Host smart-e411b988-ec27-4a72-a64f-647f42718426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312651043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2312651043
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3754903658
Short name T631
Test name
Test status
Simulation time 711548583 ps
CPU time 11.85 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:38:56 PM PST 24
Peak memory 215932 kb
Host smart-cd9ab8f9-d58f-47da-85cc-6995a8f65442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754903658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3754903658
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1955897482
Short name T308
Test name
Test status
Simulation time 33031198 ps
CPU time 0.87 seconds
Started Feb 29 01:38:45 PM PST 24
Finished Feb 29 01:38:46 PM PST 24
Peak memory 205212 kb
Host smart-0dad9ee7-35e9-456b-be95-2a38ef3b1c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955897482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1955897482
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4284276852
Short name T225
Test name
Test status
Simulation time 3182691135 ps
CPU time 15.87 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:39:00 PM PST 24
Peak memory 233276 kb
Host smart-1955f7d2-7d01-4cdd-ad85-c3ffa6bcb57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284276852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4284276852
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1307238123
Short name T299
Test name
Test status
Simulation time 27414533 ps
CPU time 0.75 seconds
Started Feb 29 01:38:56 PM PST 24
Finished Feb 29 01:38:57 PM PST 24
Peak memory 205124 kb
Host smart-66f6ab9e-bfd6-4c46-abb4-f7be0679b8d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307238123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1307238123
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3058975707
Short name T387
Test name
Test status
Simulation time 5689453272 ps
CPU time 5.89 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:38:48 PM PST 24
Peak memory 234032 kb
Host smart-827ae34b-345b-4e31-a40a-41a975cc6e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058975707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3058975707
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2645613646
Short name T789
Test name
Test status
Simulation time 56193267 ps
CPU time 0.76 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:38:46 PM PST 24
Peak memory 205964 kb
Host smart-e72631df-e2cd-4eb7-9ace-840885e47732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645613646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2645613646
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3371078021
Short name T270
Test name
Test status
Simulation time 1334995402356 ps
CPU time 351.46 seconds
Started Feb 29 01:38:56 PM PST 24
Finished Feb 29 01:44:48 PM PST 24
Peak memory 267296 kb
Host smart-b894508f-4796-4738-8447-85b5580ff02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371078021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3371078021
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2523302443
Short name T464
Test name
Test status
Simulation time 50020000216 ps
CPU time 99 seconds
Started Feb 29 01:38:53 PM PST 24
Finished Feb 29 01:40:32 PM PST 24
Peak memory 249020 kb
Host smart-a202e049-6c67-447d-93f8-af0f20aa18a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523302443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2523302443
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3406155643
Short name T709
Test name
Test status
Simulation time 652133441 ps
CPU time 9.91 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:39:04 PM PST 24
Peak memory 224220 kb
Host smart-f4110667-7142-4e04-ba48-1c7ce647b1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406155643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3406155643
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1288869961
Short name T258
Test name
Test status
Simulation time 3240937534 ps
CPU time 6.96 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:38:52 PM PST 24
Peak memory 224276 kb
Host smart-309540df-4f38-42fd-9b9d-954a1862d7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288869961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1288869961
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.24897785
Short name T165
Test name
Test status
Simulation time 5685611064 ps
CPU time 9.54 seconds
Started Feb 29 01:38:45 PM PST 24
Finished Feb 29 01:38:55 PM PST 24
Peak memory 230892 kb
Host smart-76885d52-19ea-4980-9368-752e1741da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24897785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.24897785
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3778133196
Short name T761
Test name
Test status
Simulation time 68124829735 ps
CPU time 18.53 seconds
Started Feb 29 01:38:43 PM PST 24
Finished Feb 29 01:39:02 PM PST 24
Peak memory 248616 kb
Host smart-f3fd5dec-0154-4bc1-aabf-a4ebf2fe9139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778133196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3778133196
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2898770105
Short name T660
Test name
Test status
Simulation time 619819556 ps
CPU time 4.29 seconds
Started Feb 29 01:38:42 PM PST 24
Finished Feb 29 01:38:47 PM PST 24
Peak memory 217672 kb
Host smart-bd67971a-b60d-410e-812d-54af98d05965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898770105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2898770105
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2831580445
Short name T129
Test name
Test status
Simulation time 508076638 ps
CPU time 4.79 seconds
Started Feb 29 01:38:53 PM PST 24
Finished Feb 29 01:38:58 PM PST 24
Peak memory 221888 kb
Host smart-875bf42d-1bf7-4ac7-a648-286f3c72f71c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2831580445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2831580445
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2839761435
Short name T610
Test name
Test status
Simulation time 89758756733 ps
CPU time 338.26 seconds
Started Feb 29 01:38:52 PM PST 24
Finished Feb 29 01:44:30 PM PST 24
Peak memory 267596 kb
Host smart-af0285ec-9d63-44d4-b513-0bb85709218d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839761435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2839761435
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.725264830
Short name T7
Test name
Test status
Simulation time 48749871357 ps
CPU time 35.49 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:39:17 PM PST 24
Peak memory 216376 kb
Host smart-56450648-b152-4ea7-b9c2-2be53dd54511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725264830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.725264830
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.615297162
Short name T361
Test name
Test status
Simulation time 2772991350 ps
CPU time 2.75 seconds
Started Feb 29 01:38:46 PM PST 24
Finished Feb 29 01:38:49 PM PST 24
Peak memory 207740 kb
Host smart-7785f6e2-9c40-4563-b827-d41983fee646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615297162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.615297162
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2262462631
Short name T478
Test name
Test status
Simulation time 29954600 ps
CPU time 1.07 seconds
Started Feb 29 01:38:46 PM PST 24
Finished Feb 29 01:38:48 PM PST 24
Peak memory 206204 kb
Host smart-b41af2e7-e21a-4e88-9706-dfc44d29231a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262462631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2262462631
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3266603514
Short name T304
Test name
Test status
Simulation time 181240861 ps
CPU time 0.86 seconds
Started Feb 29 01:38:41 PM PST 24
Finished Feb 29 01:38:42 PM PST 24
Peak memory 205112 kb
Host smart-d9a7de64-fa8b-49af-9314-89f2b62e021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266603514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3266603514
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4171147915
Short name T734
Test name
Test status
Simulation time 208724180 ps
CPU time 2.25 seconds
Started Feb 29 01:38:44 PM PST 24
Finished Feb 29 01:38:47 PM PST 24
Peak memory 216060 kb
Host smart-08b30a4d-b1d4-42cc-be45-18692494dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171147915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4171147915
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.704944669
Short name T588
Test name
Test status
Simulation time 37739074 ps
CPU time 0.75 seconds
Started Feb 29 01:38:51 PM PST 24
Finished Feb 29 01:38:52 PM PST 24
Peak memory 204732 kb
Host smart-05f49b8d-d271-44c0-8d83-ad23cb53097f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704944669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.704944669
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2770736818
Short name T229
Test name
Test status
Simulation time 2404541398 ps
CPU time 5.55 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:38:59 PM PST 24
Peak memory 217712 kb
Host smart-e41101a8-e271-459f-bdec-2e2f894d5956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770736818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2770736818
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.93134473
Short name T591
Test name
Test status
Simulation time 53044524 ps
CPU time 0.89 seconds
Started Feb 29 01:38:52 PM PST 24
Finished Feb 29 01:38:53 PM PST 24
Peak memory 205988 kb
Host smart-949dd719-9b4e-411d-a22b-e86c74584e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93134473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.93134473
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3905164647
Short name T239
Test name
Test status
Simulation time 14192390650 ps
CPU time 64.31 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:39:59 PM PST 24
Peak memory 254776 kb
Host smart-7643aa17-3496-48ac-a2aa-abb825305ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905164647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3905164647
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3041958119
Short name T800
Test name
Test status
Simulation time 5959045156 ps
CPU time 78.16 seconds
Started Feb 29 01:38:52 PM PST 24
Finished Feb 29 01:40:10 PM PST 24
Peak memory 250104 kb
Host smart-c25f1a14-a29c-4b68-a399-c8a92d2e7205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041958119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3041958119
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1235449791
Short name T640
Test name
Test status
Simulation time 25920678528 ps
CPU time 111.51 seconds
Started Feb 29 01:38:52 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 260564 kb
Host smart-ed444707-4335-4c0b-aa45-fdc7d4b4032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235449791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1235449791
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1700559712
Short name T325
Test name
Test status
Simulation time 541178540 ps
CPU time 9.98 seconds
Started Feb 29 01:38:52 PM PST 24
Finished Feb 29 01:39:02 PM PST 24
Peak memory 232488 kb
Host smart-26aa208c-71e4-47f1-a117-c2c58b86574d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700559712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1700559712
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2937797820
Short name T253
Test name
Test status
Simulation time 316460388 ps
CPU time 2.3 seconds
Started Feb 29 01:38:56 PM PST 24
Finished Feb 29 01:38:58 PM PST 24
Peak memory 216604 kb
Host smart-a309a268-dc12-4a60-84ee-83bdef47ae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937797820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2937797820
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1254516912
Short name T810
Test name
Test status
Simulation time 6001373549 ps
CPU time 24.91 seconds
Started Feb 29 01:38:51 PM PST 24
Finished Feb 29 01:39:16 PM PST 24
Peak memory 240504 kb
Host smart-eec5ef90-b874-43a5-8eee-eff959feb948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254516912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1254516912
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1691811223
Short name T237
Test name
Test status
Simulation time 7745761227 ps
CPU time 4.13 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:38:58 PM PST 24
Peak memory 216540 kb
Host smart-c93a2718-be42-45dc-9a92-5b081bf7fe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691811223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1691811223
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2046344320
Short name T214
Test name
Test status
Simulation time 1492289329 ps
CPU time 3.67 seconds
Started Feb 29 01:38:51 PM PST 24
Finished Feb 29 01:38:55 PM PST 24
Peak memory 216140 kb
Host smart-c586fdac-02c2-4fb3-a07e-cce7303a1b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046344320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2046344320
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1263270270
Short name T314
Test name
Test status
Simulation time 545706957 ps
CPU time 4.55 seconds
Started Feb 29 01:38:55 PM PST 24
Finished Feb 29 01:39:00 PM PST 24
Peak memory 221688 kb
Host smart-8dfe1258-0576-461b-9317-33941af6cefb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1263270270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1263270270
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3731302999
Short name T22
Test name
Test status
Simulation time 41198149514 ps
CPU time 265.39 seconds
Started Feb 29 01:38:55 PM PST 24
Finished Feb 29 01:43:20 PM PST 24
Peak memory 249072 kb
Host smart-322189fe-de2d-4ecb-8261-9b3587ee575a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731302999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3731302999
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2054079348
Short name T330
Test name
Test status
Simulation time 1092883059 ps
CPU time 17.62 seconds
Started Feb 29 01:38:57 PM PST 24
Finished Feb 29 01:39:14 PM PST 24
Peak memory 216120 kb
Host smart-d4d9c63b-da31-4f48-a255-76aa40695757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054079348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2054079348
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3411502536
Short name T706
Test name
Test status
Simulation time 7790087763 ps
CPU time 9.47 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:39:03 PM PST 24
Peak memory 216172 kb
Host smart-ee746080-d9fe-4c4e-99ee-17408078f99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411502536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3411502536
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2942485590
Short name T312
Test name
Test status
Simulation time 201457466 ps
CPU time 1.16 seconds
Started Feb 29 01:38:53 PM PST 24
Finished Feb 29 01:38:55 PM PST 24
Peak memory 207484 kb
Host smart-d01819cd-47fa-4a7a-b42a-8750a4fef576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942485590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2942485590
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1969562399
Short name T755
Test name
Test status
Simulation time 42773580 ps
CPU time 0.93 seconds
Started Feb 29 01:38:51 PM PST 24
Finished Feb 29 01:38:53 PM PST 24
Peak memory 205596 kb
Host smart-a441e114-939b-4d3d-a064-dc875724805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969562399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1969562399
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3450613656
Short name T803
Test name
Test status
Simulation time 32331536624 ps
CPU time 21.66 seconds
Started Feb 29 01:38:52 PM PST 24
Finished Feb 29 01:39:13 PM PST 24
Peak memory 223580 kb
Host smart-edc5a8cb-608e-4e07-b0a4-f3dbdb5de26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450613656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3450613656
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.983014597
Short name T922
Test name
Test status
Simulation time 20420763 ps
CPU time 0.69 seconds
Started Feb 29 01:38:50 PM PST 24
Finished Feb 29 01:38:51 PM PST 24
Peak memory 204260 kb
Host smart-b5b04dbf-7dd5-45aa-b948-8db9d385522e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983014597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.983014597
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3673782954
Short name T302
Test name
Test status
Simulation time 61777633 ps
CPU time 2.4 seconds
Started Feb 29 01:38:51 PM PST 24
Finished Feb 29 01:38:53 PM PST 24
Peak memory 216300 kb
Host smart-7a3ad4c7-03ad-436c-a37e-d046a6e62064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673782954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3673782954
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.261182221
Short name T1
Test name
Test status
Simulation time 20696237 ps
CPU time 0.74 seconds
Started Feb 29 01:38:51 PM PST 24
Finished Feb 29 01:38:52 PM PST 24
Peak memory 204972 kb
Host smart-595de4da-27e4-4ba2-b9fc-9d1259ff8974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261182221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.261182221
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2847233892
Short name T750
Test name
Test status
Simulation time 17683598112 ps
CPU time 70.82 seconds
Started Feb 29 01:39:06 PM PST 24
Finished Feb 29 01:40:17 PM PST 24
Peak memory 256800 kb
Host smart-4e4446fd-0487-4f8d-b8c0-44e6f0779dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847233892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2847233892
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1461218775
Short name T77
Test name
Test status
Simulation time 7850315727 ps
CPU time 48.18 seconds
Started Feb 29 01:39:06 PM PST 24
Finished Feb 29 01:39:55 PM PST 24
Peak memory 233640 kb
Host smart-698b63cf-dd34-4304-987b-b87ad4449ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461218775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1461218775
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.45410541
Short name T124
Test name
Test status
Simulation time 3366160737 ps
CPU time 36.64 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:39:31 PM PST 24
Peak memory 240900 kb
Host smart-3cdccd1c-1e6b-482d-840f-10e514c9b378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45410541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.45410541
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4167670914
Short name T556
Test name
Test status
Simulation time 2322286985 ps
CPU time 21.42 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:39:15 PM PST 24
Peak memory 248772 kb
Host smart-caf47211-b6c5-4f21-8fed-8e531cc75523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167670914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4167670914
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2217269232
Short name T879
Test name
Test status
Simulation time 553592321 ps
CPU time 5.62 seconds
Started Feb 29 01:39:06 PM PST 24
Finished Feb 29 01:39:12 PM PST 24
Peak memory 218276 kb
Host smart-8a6f1c52-e459-4d30-9345-fcf8b882e2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217269232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2217269232
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3452310973
Short name T914
Test name
Test status
Simulation time 39086770478 ps
CPU time 20.69 seconds
Started Feb 29 01:38:53 PM PST 24
Finished Feb 29 01:39:14 PM PST 24
Peak memory 236920 kb
Host smart-2a9dd7af-ff7a-4b59-96de-a9ffdad40bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452310973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3452310973
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3199464652
Short name T14
Test name
Test status
Simulation time 18553159108 ps
CPU time 14.9 seconds
Started Feb 29 01:39:06 PM PST 24
Finished Feb 29 01:39:21 PM PST 24
Peak memory 232212 kb
Host smart-83becb33-122c-430a-a618-31caad00ba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199464652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3199464652
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2798407017
Short name T498
Test name
Test status
Simulation time 902056616 ps
CPU time 2.96 seconds
Started Feb 29 01:38:53 PM PST 24
Finished Feb 29 01:38:56 PM PST 24
Peak memory 224208 kb
Host smart-a7a04b4f-2a16-4342-9c2e-4fe87fd7398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798407017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2798407017
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.742937359
Short name T520
Test name
Test status
Simulation time 1881142620 ps
CPU time 3.2 seconds
Started Feb 29 01:39:06 PM PST 24
Finished Feb 29 01:39:10 PM PST 24
Peak memory 219428 kb
Host smart-86273eb6-ccb2-45fd-8c97-720d68221761
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=742937359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.742937359
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1492614229
Short name T934
Test name
Test status
Simulation time 27821211039 ps
CPU time 53.36 seconds
Started Feb 29 01:38:55 PM PST 24
Finished Feb 29 01:39:49 PM PST 24
Peak memory 250020 kb
Host smart-6e3b7643-5146-495a-a2c5-56da186ceb91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492614229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1492614229
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1837551397
Short name T974
Test name
Test status
Simulation time 2815703846 ps
CPU time 21.11 seconds
Started Feb 29 01:38:52 PM PST 24
Finished Feb 29 01:39:13 PM PST 24
Peak memory 216108 kb
Host smart-6c68122b-ee96-41c4-bf15-5c217454ab55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837551397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1837551397
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2552738516
Short name T491
Test name
Test status
Simulation time 414431404 ps
CPU time 1.7 seconds
Started Feb 29 01:38:57 PM PST 24
Finished Feb 29 01:38:59 PM PST 24
Peak memory 207660 kb
Host smart-cd47c355-c6c0-415f-a264-48cdd447bc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552738516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2552738516
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2045212724
Short name T819
Test name
Test status
Simulation time 30506142 ps
CPU time 1.06 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:38:55 PM PST 24
Peak memory 207348 kb
Host smart-2f364247-29cb-4da7-89d7-c0ac0f295af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045212724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2045212724
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3643838423
Short name T558
Test name
Test status
Simulation time 177694013 ps
CPU time 0.83 seconds
Started Feb 29 01:38:51 PM PST 24
Finished Feb 29 01:38:52 PM PST 24
Peak memory 205236 kb
Host smart-a3d67f12-fbbf-4799-b67f-b2accd176a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643838423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3643838423
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.832727198
Short name T527
Test name
Test status
Simulation time 195685812 ps
CPU time 3.43 seconds
Started Feb 29 01:38:52 PM PST 24
Finished Feb 29 01:38:56 PM PST 24
Peak memory 233616 kb
Host smart-6b31b8e4-d779-410c-a345-9ac6329a325b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832727198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.832727198
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3839829194
Short name T930
Test name
Test status
Simulation time 17767994 ps
CPU time 0.71 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:39:03 PM PST 24
Peak memory 205284 kb
Host smart-39b057d3-caab-46d2-8221-cac360d97a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839829194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3839829194
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.854802143
Short name T758
Test name
Test status
Simulation time 2448351210 ps
CPU time 4.79 seconds
Started Feb 29 01:38:55 PM PST 24
Finished Feb 29 01:39:00 PM PST 24
Peak memory 233468 kb
Host smart-41dd0417-9b5f-4343-88dc-fac74d7aa386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854802143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.854802143
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.698819745
Short name T384
Test name
Test status
Simulation time 97336165 ps
CPU time 0.77 seconds
Started Feb 29 01:38:56 PM PST 24
Finished Feb 29 01:38:57 PM PST 24
Peak memory 205876 kb
Host smart-e8c1b5f0-af29-4f94-8296-e67f10a2f0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698819745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.698819745
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3318831961
Short name T911
Test name
Test status
Simulation time 43516581778 ps
CPU time 81.9 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:40:24 PM PST 24
Peak memory 250400 kb
Host smart-2e7eafc4-fd99-4424-8a74-082ad897dfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318831961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3318831961
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3706153546
Short name T236
Test name
Test status
Simulation time 35423675257 ps
CPU time 125.49 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 251960 kb
Host smart-a971f0f0-8478-47cf-bfd1-3db81d35f4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706153546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3706153546
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.914332039
Short name T125
Test name
Test status
Simulation time 81705904249 ps
CPU time 154.57 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 240820 kb
Host smart-c27a52e4-8a53-407f-8c4a-0429faa011bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914332039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.914332039
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1859041563
Short name T671
Test name
Test status
Simulation time 23901161270 ps
CPU time 30.83 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:39:33 PM PST 24
Peak memory 232484 kb
Host smart-61fbb603-65ac-4917-8446-18c996bd227f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859041563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1859041563
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1296769193
Short name T177
Test name
Test status
Simulation time 6478834087 ps
CPU time 9.94 seconds
Started Feb 29 01:38:57 PM PST 24
Finished Feb 29 01:39:07 PM PST 24
Peak memory 234380 kb
Host smart-2c030029-8695-4565-9615-812195d52707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296769193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1296769193
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3640819030
Short name T796
Test name
Test status
Simulation time 1258936290 ps
CPU time 14.26 seconds
Started Feb 29 01:38:56 PM PST 24
Finished Feb 29 01:39:10 PM PST 24
Peak memory 247864 kb
Host smart-9b68aefa-ce65-437c-bc31-4d1a88e27815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640819030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3640819030
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3899219569
Short name T864
Test name
Test status
Simulation time 1778037381 ps
CPU time 10.58 seconds
Started Feb 29 01:38:53 PM PST 24
Finished Feb 29 01:39:03 PM PST 24
Peak memory 232500 kb
Host smart-2fe433e4-797d-4f98-90eb-bc62f586061b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899219569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3899219569
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1342492649
Short name T176
Test name
Test status
Simulation time 451826921 ps
CPU time 7.47 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:39:01 PM PST 24
Peak memory 244208 kb
Host smart-439ef62e-f735-4532-a67f-9b719dd4d6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342492649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1342492649
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.561560728
Short name T857
Test name
Test status
Simulation time 1471050719 ps
CPU time 4.47 seconds
Started Feb 29 01:39:02 PM PST 24
Finished Feb 29 01:39:07 PM PST 24
Peak memory 218688 kb
Host smart-3d074920-44de-42d9-b968-24436aaf9a08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=561560728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.561560728
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.390779073
Short name T174
Test name
Test status
Simulation time 4455699933 ps
CPU time 58.8 seconds
Started Feb 29 01:39:09 PM PST 24
Finished Feb 29 01:40:08 PM PST 24
Peak memory 249056 kb
Host smart-bf42f209-5ffb-493e-9d25-12d5faca90be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390779073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.390779073
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3201382771
Short name T714
Test name
Test status
Simulation time 1373717023 ps
CPU time 7.8 seconds
Started Feb 29 01:39:06 PM PST 24
Finished Feb 29 01:39:14 PM PST 24
Peak memory 216104 kb
Host smart-9b935f55-372a-4bc3-84b1-ae0713995889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201382771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3201382771
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3430373259
Short name T575
Test name
Test status
Simulation time 5530049493 ps
CPU time 18.88 seconds
Started Feb 29 01:38:56 PM PST 24
Finished Feb 29 01:39:15 PM PST 24
Peak memory 216152 kb
Host smart-2a48cfcd-6e80-463e-af96-9b52108f924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430373259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3430373259
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2717211032
Short name T52
Test name
Test status
Simulation time 827163813 ps
CPU time 8.08 seconds
Started Feb 29 01:38:57 PM PST 24
Finished Feb 29 01:39:05 PM PST 24
Peak memory 217324 kb
Host smart-e353916a-49c4-4eba-998c-ed348eba403b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717211032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2717211032
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3413422116
Short name T825
Test name
Test status
Simulation time 155444812 ps
CPU time 0.9 seconds
Started Feb 29 01:38:54 PM PST 24
Finished Feb 29 01:38:55 PM PST 24
Peak memory 206272 kb
Host smart-9fab5d2a-e478-4b51-9f54-cc1d3556e4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413422116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3413422116
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.490718960
Short name T774
Test name
Test status
Simulation time 2151976070 ps
CPU time 6.16 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:39:08 PM PST 24
Peak memory 236104 kb
Host smart-317d8d02-bd97-4cb9-ba2d-2d1bae86c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490718960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.490718960
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4145978611
Short name T956
Test name
Test status
Simulation time 49877096 ps
CPU time 0.76 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:39:04 PM PST 24
Peak memory 204272 kb
Host smart-f5ed995a-b569-409b-b318-6ba7c7cc3f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145978611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4145978611
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1930662176
Short name T781
Test name
Test status
Simulation time 114821875 ps
CPU time 3.01 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:39:04 PM PST 24
Peak memory 234404 kb
Host smart-74bb7220-df2a-44cd-9c72-7e72e01a94a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930662176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1930662176
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3692213701
Short name T313
Test name
Test status
Simulation time 20998439 ps
CPU time 0.81 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:39:03 PM PST 24
Peak memory 205912 kb
Host smart-7be97711-1930-48f3-942b-d54317bc28df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692213701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3692213701
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4110516356
Short name T537
Test name
Test status
Simulation time 15702656716 ps
CPU time 45 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:39:48 PM PST 24
Peak memory 241040 kb
Host smart-a3d23f9a-5a18-4735-aa85-a81a53ad16d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110516356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4110516356
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.114615176
Short name T282
Test name
Test status
Simulation time 12849239415 ps
CPU time 45.79 seconds
Started Feb 29 01:39:02 PM PST 24
Finished Feb 29 01:39:48 PM PST 24
Peak memory 240784 kb
Host smart-3c1f37b3-2105-48b1-b4ed-525f9ee5a3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114615176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.114615176
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2539011109
Short name T817
Test name
Test status
Simulation time 5449573953 ps
CPU time 109.76 seconds
Started Feb 29 01:39:05 PM PST 24
Finished Feb 29 01:40:54 PM PST 24
Peak memory 253536 kb
Host smart-15abaf67-2d0f-446e-8cef-e4b5b75e72f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539011109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2539011109
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_intercept.383701556
Short name T367
Test name
Test status
Simulation time 207938870 ps
CPU time 3.46 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:39:06 PM PST 24
Peak memory 218356 kb
Host smart-8ed17d84-c172-4d79-ac05-7d9c8bdf0442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383701556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.383701556
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.210904086
Short name T586
Test name
Test status
Simulation time 42251449440 ps
CPU time 30.02 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:39:34 PM PST 24
Peak memory 233632 kb
Host smart-54b76cf7-25af-40bc-a784-e0d31c38aa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210904086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.210904086
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1466084620
Short name T338
Test name
Test status
Simulation time 5914817561 ps
CPU time 15.18 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:39:19 PM PST 24
Peak memory 233012 kb
Host smart-a1e2b077-43da-44f7-9bfe-cfd001e64563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466084620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1466084620
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3961710175
Short name T411
Test name
Test status
Simulation time 1463459214 ps
CPU time 7.8 seconds
Started Feb 29 01:39:06 PM PST 24
Finished Feb 29 01:39:14 PM PST 24
Peak memory 237512 kb
Host smart-d50250c3-23e3-4925-b063-f20812da735d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961710175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3961710175
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.959255104
Short name T866
Test name
Test status
Simulation time 1763678079 ps
CPU time 7.31 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:39:11 PM PST 24
Peak memory 216264 kb
Host smart-3c45510e-3aa4-4806-8cbc-cdc24224ba0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=959255104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.959255104
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.179224917
Short name T589
Test name
Test status
Simulation time 149616330 ps
CPU time 0.89 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:39:04 PM PST 24
Peak memory 205016 kb
Host smart-0673f031-0cac-4fe2-acd2-495d652904d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179224917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.179224917
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4255798231
Short name T515
Test name
Test status
Simulation time 906764875 ps
CPU time 12.16 seconds
Started Feb 29 01:39:02 PM PST 24
Finished Feb 29 01:39:15 PM PST 24
Peak memory 216020 kb
Host smart-4c2a1ff1-7cc5-4f49-b90c-a9e341691757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255798231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4255798231
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3729837603
Short name T685
Test name
Test status
Simulation time 110600914114 ps
CPU time 32.76 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:39:35 PM PST 24
Peak memory 216260 kb
Host smart-8f758a2d-bc7b-433b-b804-a676c1158d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729837603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3729837603
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1375651964
Short name T568
Test name
Test status
Simulation time 290051567 ps
CPU time 1.85 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:39:04 PM PST 24
Peak memory 216408 kb
Host smart-7ab28ded-c2cd-4ee1-84a1-36739a75d62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375651964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1375651964
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3933177650
Short name T441
Test name
Test status
Simulation time 199758371 ps
CPU time 1.02 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:05 PM PST 24
Peak memory 206200 kb
Host smart-f902e8f9-c6c7-400c-b4d1-74cc8b7fe0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933177650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3933177650
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2458153133
Short name T499
Test name
Test status
Simulation time 10192578252 ps
CPU time 35.34 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:39:38 PM PST 24
Peak memory 234852 kb
Host smart-67960c07-b0c8-4bd0-9b6e-fe730538033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458153133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2458153133
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1112925893
Short name T423
Test name
Test status
Simulation time 12618178 ps
CPU time 0.73 seconds
Started Feb 29 01:36:30 PM PST 24
Finished Feb 29 01:36:31 PM PST 24
Peak memory 204836 kb
Host smart-35f65600-6981-4f88-8d61-04d38b68fc18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112925893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
112925893
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2801490677
Short name T707
Test name
Test status
Simulation time 21515954093 ps
CPU time 10.81 seconds
Started Feb 29 01:36:12 PM PST 24
Finished Feb 29 01:36:23 PM PST 24
Peak memory 221592 kb
Host smart-5d7944f5-62da-47d3-b177-294a1de3e3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801490677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2801490677
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.405407884
Short name T576
Test name
Test status
Simulation time 23230675 ps
CPU time 0.77 seconds
Started Feb 29 01:36:10 PM PST 24
Finished Feb 29 01:36:11 PM PST 24
Peak memory 205968 kb
Host smart-57164039-0919-4a1a-9e7c-27e55308b51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405407884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.405407884
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4102595411
Short name T815
Test name
Test status
Simulation time 5838426288 ps
CPU time 53.06 seconds
Started Feb 29 01:36:10 PM PST 24
Finished Feb 29 01:37:03 PM PST 24
Peak memory 249996 kb
Host smart-cf994a5d-9ea7-4615-af53-b829366baaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102595411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4102595411
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1239682688
Short name T595
Test name
Test status
Simulation time 34074203167 ps
CPU time 219.86 seconds
Started Feb 29 01:36:15 PM PST 24
Finished Feb 29 01:39:55 PM PST 24
Peak memory 249068 kb
Host smart-777b5514-8b2c-4d0a-a6f2-e12666019211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239682688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1239682688
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.709641022
Short name T607
Test name
Test status
Simulation time 44564572049 ps
CPU time 76.12 seconds
Started Feb 29 01:36:11 PM PST 24
Finished Feb 29 01:37:28 PM PST 24
Peak memory 232644 kb
Host smart-723807a6-e1eb-46c5-a907-58177a404458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709641022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
709641022
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2219044887
Short name T678
Test name
Test status
Simulation time 1784978772 ps
CPU time 11.74 seconds
Started Feb 29 01:36:10 PM PST 24
Finished Feb 29 01:36:22 PM PST 24
Peak memory 236356 kb
Host smart-f843bdb7-1cb4-4251-b328-4a0531aff384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219044887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2219044887
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3214863532
Short name T863
Test name
Test status
Simulation time 3382023878 ps
CPU time 13.11 seconds
Started Feb 29 01:36:11 PM PST 24
Finished Feb 29 01:36:24 PM PST 24
Peak memory 224408 kb
Host smart-0a437567-2ae8-46a5-9e11-6199d330a278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214863532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3214863532
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3418644921
Short name T574
Test name
Test status
Simulation time 371147265 ps
CPU time 6.03 seconds
Started Feb 29 01:36:09 PM PST 24
Finished Feb 29 01:36:15 PM PST 24
Peak memory 230768 kb
Host smart-7dc02e61-33ab-4839-8a57-d59b55552867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418644921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3418644921
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3562154346
Short name T342
Test name
Test status
Simulation time 18317276 ps
CPU time 1.04 seconds
Started Feb 29 01:36:15 PM PST 24
Finished Feb 29 01:36:16 PM PST 24
Peak memory 216564 kb
Host smart-065a897c-dd00-4f28-85df-3a6bcd75f8b7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562154346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3562154346
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4184163876
Short name T849
Test name
Test status
Simulation time 12774104437 ps
CPU time 8.58 seconds
Started Feb 29 01:36:10 PM PST 24
Finished Feb 29 01:36:19 PM PST 24
Peak memory 217548 kb
Host smart-81146d41-847c-4703-b36b-aaa6d74a0c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184163876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4184163876
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.707400006
Short name T199
Test name
Test status
Simulation time 157554661 ps
CPU time 2.67 seconds
Started Feb 29 01:36:11 PM PST 24
Finished Feb 29 01:36:14 PM PST 24
Peak memory 217456 kb
Host smart-07dab998-310e-46c2-9e5b-e74f29fba964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707400006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.707400006
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2435703955
Short name T745
Test name
Test status
Simulation time 43985578 ps
CPU time 0.73 seconds
Started Feb 29 01:36:11 PM PST 24
Finished Feb 29 01:36:12 PM PST 24
Peak memory 215936 kb
Host smart-f2a69c3b-84d7-4e5c-a3c7-b786499d2d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435703955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2435703955
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2117249543
Short name T335
Test name
Test status
Simulation time 177178309 ps
CPU time 3.41 seconds
Started Feb 29 01:36:10 PM PST 24
Finished Feb 29 01:36:14 PM PST 24
Peak memory 221996 kb
Host smart-31d592e5-b2f2-4607-8fe1-b10b1e0c78fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2117249543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2117249543
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1988906225
Short name T70
Test name
Test status
Simulation time 96380290 ps
CPU time 1.2 seconds
Started Feb 29 01:36:11 PM PST 24
Finished Feb 29 01:36:13 PM PST 24
Peak memory 235288 kb
Host smart-96114592-47e0-47bb-a5b5-562a2551df38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988906225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1988906225
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1997479752
Short name T432
Test name
Test status
Simulation time 65115897918 ps
CPU time 119.78 seconds
Started Feb 29 01:36:10 PM PST 24
Finished Feb 29 01:38:10 PM PST 24
Peak memory 265448 kb
Host smart-806041f7-d953-4b5e-a509-fb1f973b74db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997479752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1997479752
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3034901244
Short name T483
Test name
Test status
Simulation time 3349135528 ps
CPU time 30.69 seconds
Started Feb 29 01:36:09 PM PST 24
Finished Feb 29 01:36:40 PM PST 24
Peak memory 216128 kb
Host smart-b0efc7a4-11ac-4750-b4a9-0788420bed33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034901244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3034901244
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2534200770
Short name T853
Test name
Test status
Simulation time 7148393712 ps
CPU time 19.69 seconds
Started Feb 29 01:36:12 PM PST 24
Finished Feb 29 01:36:32 PM PST 24
Peak memory 216268 kb
Host smart-c4730bfd-a4fe-4d5c-b544-4289bd73fee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534200770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2534200770
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.690530107
Short name T594
Test name
Test status
Simulation time 111199565 ps
CPU time 0.87 seconds
Started Feb 29 01:36:09 PM PST 24
Finished Feb 29 01:36:10 PM PST 24
Peak memory 206212 kb
Host smart-3a87d8aa-d6c1-4f1c-b2ff-095d16d00b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690530107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.690530107
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1856930117
Short name T406
Test name
Test status
Simulation time 157398931 ps
CPU time 0.9 seconds
Started Feb 29 01:36:09 PM PST 24
Finished Feb 29 01:36:10 PM PST 24
Peak memory 205216 kb
Host smart-5b54e7c9-07ed-4c02-a10f-34687739e10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856930117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1856930117
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1554988804
Short name T657
Test name
Test status
Simulation time 442996022 ps
CPU time 5.09 seconds
Started Feb 29 01:36:11 PM PST 24
Finished Feb 29 01:36:16 PM PST 24
Peak memory 217036 kb
Host smart-9aacfd45-be23-4a61-98ce-7fc3be362e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554988804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1554988804
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4006619382
Short name T944
Test name
Test status
Simulation time 41654331 ps
CPU time 0.72 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:39:04 PM PST 24
Peak memory 204224 kb
Host smart-4fd2c1e5-e493-4f4a-a244-efb803b1bf1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006619382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4006619382
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2634985459
Short name T549
Test name
Test status
Simulation time 1265784054 ps
CPU time 6.3 seconds
Started Feb 29 01:39:09 PM PST 24
Finished Feb 29 01:39:16 PM PST 24
Peak memory 234088 kb
Host smart-9f25b6ef-a4dc-4824-b45c-1f77779cca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634985459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2634985459
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1111149790
Short name T352
Test name
Test status
Simulation time 67690266 ps
CPU time 0.84 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:05 PM PST 24
Peak memory 206440 kb
Host smart-25ace52d-6f02-4e54-af69-af67b39e52ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111149790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1111149790
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2862150911
Short name T756
Test name
Test status
Simulation time 91431436215 ps
CPU time 207.53 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:42:32 PM PST 24
Peak memory 256348 kb
Host smart-fdbd2f67-85e8-4c6f-a18d-31cfea375df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862150911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2862150911
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.499330355
Short name T909
Test name
Test status
Simulation time 141347677260 ps
CPU time 449.16 seconds
Started Feb 29 01:39:05 PM PST 24
Finished Feb 29 01:46:35 PM PST 24
Peak memory 257412 kb
Host smart-5995ea7a-d0a7-44f8-8dde-ea2a70863cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499330355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.499330355
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2624830496
Short name T211
Test name
Test status
Simulation time 561386038 ps
CPU time 5.24 seconds
Started Feb 29 01:39:00 PM PST 24
Finished Feb 29 01:39:06 PM PST 24
Peak memory 217764 kb
Host smart-72566190-6117-483d-a5e8-0a92edb5aa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624830496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2624830496
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3151394802
Short name T622
Test name
Test status
Simulation time 21009347749 ps
CPU time 21.26 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:26 PM PST 24
Peak memory 233264 kb
Host smart-a6f428eb-9f0d-4a9f-8f15-a015852a5458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151394802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3151394802
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1254993926
Short name T233
Test name
Test status
Simulation time 573885801 ps
CPU time 3.61 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:39:07 PM PST 24
Peak memory 232892 kb
Host smart-b873eaaa-4aa9-455d-a950-46491212d6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254993926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1254993926
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1909194994
Short name T692
Test name
Test status
Simulation time 41591895022 ps
CPU time 21.37 seconds
Started Feb 29 01:39:01 PM PST 24
Finished Feb 29 01:39:24 PM PST 24
Peak memory 224416 kb
Host smart-6a41b890-5eed-4a7f-93fd-f597af28ca6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909194994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1909194994
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3145389687
Short name T919
Test name
Test status
Simulation time 4652913207 ps
CPU time 6.02 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:11 PM PST 24
Peak memory 222040 kb
Host smart-7e4df431-d63e-4dfc-be1b-856ec6d0187b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3145389687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3145389687
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3453921330
Short name T273
Test name
Test status
Simulation time 872137338430 ps
CPU time 1249 seconds
Started Feb 29 01:39:03 PM PST 24
Finished Feb 29 01:59:53 PM PST 24
Peak memory 288780 kb
Host smart-032f6b25-f4ce-4b55-ba56-01315170ff4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453921330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3453921330
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2612712578
Short name T672
Test name
Test status
Simulation time 2974545793 ps
CPU time 12.5 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:17 PM PST 24
Peak memory 216240 kb
Host smart-5599a2ef-c85b-45e2-90c2-7812d2ef1971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612712578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2612712578
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3545070251
Short name T684
Test name
Test status
Simulation time 13111051935 ps
CPU time 18.13 seconds
Started Feb 29 01:39:00 PM PST 24
Finished Feb 29 01:39:18 PM PST 24
Peak memory 216192 kb
Host smart-29999c16-b77d-4a28-a59b-a0f20f276735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545070251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3545070251
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1681844013
Short name T497
Test name
Test status
Simulation time 45343314 ps
CPU time 0.85 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:05 PM PST 24
Peak memory 205964 kb
Host smart-5bf7ac74-3962-4403-9468-033498cbad08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681844013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1681844013
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2569571581
Short name T8
Test name
Test status
Simulation time 95237216 ps
CPU time 0.81 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:05 PM PST 24
Peak memory 205164 kb
Host smart-0c6c7e5c-e3db-4b82-8ef0-13debfa2458e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569571581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2569571581
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1666499435
Short name T480
Test name
Test status
Simulation time 18094946508 ps
CPU time 13.8 seconds
Started Feb 29 01:39:02 PM PST 24
Finished Feb 29 01:39:16 PM PST 24
Peak memory 217288 kb
Host smart-d6b57c41-dc46-4765-b752-422ad735e97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666499435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1666499435
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3313525788
Short name T346
Test name
Test status
Simulation time 13231897 ps
CPU time 0.75 seconds
Started Feb 29 01:39:17 PM PST 24
Finished Feb 29 01:39:18 PM PST 24
Peak memory 204808 kb
Host smart-1da7ea61-5c90-4e73-84a9-672c224e61ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313525788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3313525788
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.955857292
Short name T395
Test name
Test status
Simulation time 398605125 ps
CPU time 2.53 seconds
Started Feb 29 01:39:13 PM PST 24
Finished Feb 29 01:39:15 PM PST 24
Peak memory 224268 kb
Host smart-2df725f7-f7e7-4a54-9055-152aef78e561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955857292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.955857292
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3448235210
Short name T56
Test name
Test status
Simulation time 70684768 ps
CPU time 0.85 seconds
Started Feb 29 01:39:09 PM PST 24
Finished Feb 29 01:39:10 PM PST 24
Peak memory 206296 kb
Host smart-cffe5d61-c9d1-4ef0-a167-3f81f6f6859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448235210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3448235210
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3355039546
Short name T74
Test name
Test status
Simulation time 4250582690 ps
CPU time 41.39 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:58 PM PST 24
Peak memory 240164 kb
Host smart-07d96649-1917-4c24-b97f-14146a17ce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355039546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3355039546
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4019727806
Short name T834
Test name
Test status
Simulation time 7103795764 ps
CPU time 72.25 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:40:28 PM PST 24
Peak memory 253160 kb
Host smart-e1f9b1c1-747e-4541-acdc-fd2c62e031bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019727806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4019727806
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1073090934
Short name T164
Test name
Test status
Simulation time 15556589960 ps
CPU time 142.48 seconds
Started Feb 29 01:39:19 PM PST 24
Finished Feb 29 01:41:41 PM PST 24
Peak memory 254768 kb
Host smart-45e9e26a-dd81-425c-b151-f4e197d348ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073090934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1073090934
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2204364529
Short name T488
Test name
Test status
Simulation time 3044270323 ps
CPU time 10.06 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:26 PM PST 24
Peak memory 233660 kb
Host smart-ba4d6d7f-e8b3-49f0-93f5-3bd0be8c4d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204364529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2204364529
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.900822117
Short name T728
Test name
Test status
Simulation time 3368684195 ps
CPU time 12.52 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:29 PM PST 24
Peak memory 234260 kb
Host smart-9e0da547-f6fe-41c0-971f-80305fe3b332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900822117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.900822117
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4100223395
Short name T489
Test name
Test status
Simulation time 34294293849 ps
CPU time 34.24 seconds
Started Feb 29 01:39:20 PM PST 24
Finished Feb 29 01:39:54 PM PST 24
Peak memory 237148 kb
Host smart-408c09b7-1b6e-40e0-b6a4-4aac585e3ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100223395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4100223395
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.228203015
Short name T269
Test name
Test status
Simulation time 79304845 ps
CPU time 2.56 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:39:17 PM PST 24
Peak memory 232712 kb
Host smart-d5c4596c-bde8-43ba-afc0-2278837a0756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228203015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.228203015
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1303148112
Short name T883
Test name
Test status
Simulation time 114184286 ps
CPU time 2.87 seconds
Started Feb 29 01:39:06 PM PST 24
Finished Feb 29 01:39:09 PM PST 24
Peak memory 233360 kb
Host smart-ce34fd76-7a84-47b4-860f-817a2de4316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303148112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1303148112
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4247019219
Short name T419
Test name
Test status
Simulation time 4642767728 ps
CPU time 5.72 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:39:21 PM PST 24
Peak memory 220040 kb
Host smart-dbaa1a68-0cbe-4a0d-b189-51e7ccdf84f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4247019219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4247019219
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1793154724
Short name T584
Test name
Test status
Simulation time 10590844506 ps
CPU time 75.95 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 250128 kb
Host smart-b63908c8-5b99-406e-86f1-00899fb52a78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793154724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1793154724
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3104007421
Short name T855
Test name
Test status
Simulation time 29757005453 ps
CPU time 32.78 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:37 PM PST 24
Peak memory 216076 kb
Host smart-fae2070a-f180-4f1a-8428-c155242bf990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104007421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3104007421
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.381862076
Short name T952
Test name
Test status
Simulation time 5711816025 ps
CPU time 9.07 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:14 PM PST 24
Peak memory 216184 kb
Host smart-881e0fa8-5b36-43cc-a14c-8f908a73ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381862076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.381862076
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.597430864
Short name T582
Test name
Test status
Simulation time 119662880 ps
CPU time 1 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:05 PM PST 24
Peak memory 206280 kb
Host smart-55c31b95-46db-4be6-91c2-1282a1079703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597430864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.597430864
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3840799118
Short name T686
Test name
Test status
Simulation time 525528576 ps
CPU time 1.15 seconds
Started Feb 29 01:39:04 PM PST 24
Finished Feb 29 01:39:05 PM PST 24
Peak memory 206200 kb
Host smart-cd275830-b37e-4609-9961-b14ec7522358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840799118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3840799118
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3408918422
Short name T450
Test name
Test status
Simulation time 3241533525 ps
CPU time 12.64 seconds
Started Feb 29 01:39:17 PM PST 24
Finished Feb 29 01:39:30 PM PST 24
Peak memory 233108 kb
Host smart-cc7637dc-5b1d-4892-933d-ef66e5c1d277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408918422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3408918422
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4151050680
Short name T677
Test name
Test status
Simulation time 15254617 ps
CPU time 0.77 seconds
Started Feb 29 01:39:20 PM PST 24
Finished Feb 29 01:39:21 PM PST 24
Peak memory 204780 kb
Host smart-6747f89f-84df-49e3-9efd-777b109620ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151050680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4151050680
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1396090719
Short name T495
Test name
Test status
Simulation time 6209704157 ps
CPU time 10.27 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:39:25 PM PST 24
Peak memory 220160 kb
Host smart-247ad35a-c1d1-4540-a87c-6923ebf2920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396090719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1396090719
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1455530909
Short name T662
Test name
Test status
Simulation time 60218748 ps
CPU time 0.75 seconds
Started Feb 29 01:39:13 PM PST 24
Finished Feb 29 01:39:14 PM PST 24
Peak memory 206312 kb
Host smart-6ca82e2b-263b-4ec3-ac88-34072433a500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455530909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1455530909
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3387843325
Short name T151
Test name
Test status
Simulation time 246903999460 ps
CPU time 291.66 seconds
Started Feb 29 01:39:14 PM PST 24
Finished Feb 29 01:44:06 PM PST 24
Peak memory 253420 kb
Host smart-743bc2e2-d44a-4a21-82d3-3471c398f20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387843325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3387843325
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1871143522
Short name T285
Test name
Test status
Simulation time 111140312941 ps
CPU time 789.06 seconds
Started Feb 29 01:39:13 PM PST 24
Finished Feb 29 01:52:23 PM PST 24
Peak memory 264356 kb
Host smart-b0b5f3ff-e71a-45bd-8b13-6aa736319f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871143522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1871143522
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2510187903
Short name T768
Test name
Test status
Simulation time 3722866689 ps
CPU time 53.62 seconds
Started Feb 29 01:39:14 PM PST 24
Finished Feb 29 01:40:08 PM PST 24
Peak memory 251108 kb
Host smart-206e46f6-33f7-42c1-a8a9-22365d4e3d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510187903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2510187903
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3798424201
Short name T509
Test name
Test status
Simulation time 41603134875 ps
CPU time 37.7 seconds
Started Feb 29 01:39:17 PM PST 24
Finished Feb 29 01:39:54 PM PST 24
Peak memory 248860 kb
Host smart-a866f779-6012-4d2b-94e1-2e146e83f9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798424201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3798424201
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4159530445
Short name T854
Test name
Test status
Simulation time 4085978992 ps
CPU time 11.77 seconds
Started Feb 29 01:39:13 PM PST 24
Finished Feb 29 01:39:25 PM PST 24
Peak memory 224380 kb
Host smart-fa779430-a16e-4654-9340-48dbbab54012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159530445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4159530445
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.724541490
Short name T741
Test name
Test status
Simulation time 1391721714 ps
CPU time 3.94 seconds
Started Feb 29 01:39:22 PM PST 24
Finished Feb 29 01:39:26 PM PST 24
Peak memory 223600 kb
Host smart-198b6630-7a11-4bfc-878a-65ea513279e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724541490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.724541490
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1364253705
Short name T180
Test name
Test status
Simulation time 1901342356 ps
CPU time 8.94 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:25 PM PST 24
Peak memory 224300 kb
Host smart-4334576c-d77f-4a45-9aa4-e3fc907a5333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364253705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1364253705
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.368255959
Short name T804
Test name
Test status
Simulation time 266830757 ps
CPU time 5.6 seconds
Started Feb 29 01:39:12 PM PST 24
Finished Feb 29 01:39:18 PM PST 24
Peak memory 236588 kb
Host smart-48bfd2ac-f755-4cc0-95ca-ed666b21af46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368255959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.368255959
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.534679437
Short name T989
Test name
Test status
Simulation time 755489479 ps
CPU time 3.74 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:19 PM PST 24
Peak memory 221380 kb
Host smart-75f90e45-ae76-4d11-9e78-394c67fa9117
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=534679437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.534679437
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4270026895
Short name T83
Test name
Test status
Simulation time 6824065550 ps
CPU time 42.22 seconds
Started Feb 29 01:39:17 PM PST 24
Finished Feb 29 01:39:59 PM PST 24
Peak memory 216224 kb
Host smart-aabbe5e8-8b09-49d6-99b8-891c45064b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270026895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4270026895
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1325454672
Short name T949
Test name
Test status
Simulation time 20249220408 ps
CPU time 16.98 seconds
Started Feb 29 01:39:19 PM PST 24
Finished Feb 29 01:39:36 PM PST 24
Peak memory 216184 kb
Host smart-b412b1dd-3a78-4776-83c4-63e1e6dc2b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325454672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1325454672
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.588420062
Short name T724
Test name
Test status
Simulation time 224587138 ps
CPU time 1.19 seconds
Started Feb 29 01:39:14 PM PST 24
Finished Feb 29 01:39:15 PM PST 24
Peak memory 215992 kb
Host smart-37f6f047-736b-422c-951a-d6a554724406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588420062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.588420062
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2545321129
Short name T795
Test name
Test status
Simulation time 72152606 ps
CPU time 1.02 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:18 PM PST 24
Peak memory 206212 kb
Host smart-59c37175-d280-4827-b65e-ccc5253c320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545321129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2545321129
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1554585688
Short name T809
Test name
Test status
Simulation time 9066689103 ps
CPU time 25.75 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:39:41 PM PST 24
Peak memory 229512 kb
Host smart-0e1b6620-f22c-4fd9-af3f-db8a6fedb89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554585688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1554585688
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1887327923
Short name T980
Test name
Test status
Simulation time 18602067 ps
CPU time 0.7 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:39:16 PM PST 24
Peak memory 205168 kb
Host smart-32222f29-8f3a-48aa-81b8-7dc30f3b1608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887327923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1887327923
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.577806424
Short name T528
Test name
Test status
Simulation time 215338541 ps
CPU time 2.91 seconds
Started Feb 29 01:39:21 PM PST 24
Finished Feb 29 01:39:24 PM PST 24
Peak memory 234492 kb
Host smart-3f067692-f98d-43f9-95fb-d05fc149a9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577806424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.577806424
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1210746059
Short name T431
Test name
Test status
Simulation time 15392089 ps
CPU time 0.74 seconds
Started Feb 29 01:39:18 PM PST 24
Finished Feb 29 01:39:18 PM PST 24
Peak memory 204908 kb
Host smart-c9c379e3-d6c1-4203-a4ee-679887fe3c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210746059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1210746059
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1821551637
Short name T262
Test name
Test status
Simulation time 10481779012 ps
CPU time 81.26 seconds
Started Feb 29 01:39:21 PM PST 24
Finished Feb 29 01:40:42 PM PST 24
Peak memory 265368 kb
Host smart-0448c6ad-afd2-4616-b69a-8d499f81e8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821551637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1821551637
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.748342378
Short name T958
Test name
Test status
Simulation time 56512301926 ps
CPU time 428.76 seconds
Started Feb 29 01:39:14 PM PST 24
Finished Feb 29 01:46:23 PM PST 24
Peak memory 256148 kb
Host smart-6b8d9950-aacb-4fbc-b6cb-71bba378359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748342378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.748342378
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.268705642
Short name T48
Test name
Test status
Simulation time 125501017487 ps
CPU time 129.32 seconds
Started Feb 29 01:39:17 PM PST 24
Finished Feb 29 01:41:26 PM PST 24
Peak memory 240884 kb
Host smart-6359b4d6-651d-442a-bd52-87a510ca3e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268705642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.268705642
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4152598271
Short name T425
Test name
Test status
Simulation time 33551983311 ps
CPU time 20.73 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:39:36 PM PST 24
Peak memory 236668 kb
Host smart-7e28cf7f-6252-4191-ad0e-e4c002a00175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152598271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4152598271
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3305601243
Short name T110
Test name
Test status
Simulation time 22397664829 ps
CPU time 7.34 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:23 PM PST 24
Peak memory 233152 kb
Host smart-7adcbac0-b8b6-4d4f-b69f-c387e399ec1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305601243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3305601243
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4173889414
Short name T681
Test name
Test status
Simulation time 27085729072 ps
CPU time 24.16 seconds
Started Feb 29 01:39:12 PM PST 24
Finished Feb 29 01:39:37 PM PST 24
Peak memory 238092 kb
Host smart-03c70fb9-d591-41f9-9d7b-dd23f8490bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173889414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4173889414
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.388559078
Short name T792
Test name
Test status
Simulation time 707064730 ps
CPU time 4.79 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:39:20 PM PST 24
Peak memory 232840 kb
Host smart-261f6459-50c4-41eb-a6f9-f79d137128f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388559078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.388559078
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1176607497
Short name T682
Test name
Test status
Simulation time 24665340516 ps
CPU time 13.18 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:39:28 PM PST 24
Peak memory 232808 kb
Host smart-22ee13d7-9967-426f-9531-b38f64078d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176607497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1176607497
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.888153428
Short name T933
Test name
Test status
Simulation time 1263897653 ps
CPU time 3.25 seconds
Started Feb 29 01:39:14 PM PST 24
Finished Feb 29 01:39:17 PM PST 24
Peak memory 218316 kb
Host smart-c2a2beba-5bd5-4708-a5c5-540db3627abd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=888153428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.888153428
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3706875841
Short name T139
Test name
Test status
Simulation time 67565671 ps
CPU time 1.14 seconds
Started Feb 29 01:39:17 PM PST 24
Finished Feb 29 01:39:18 PM PST 24
Peak memory 206540 kb
Host smart-8b308545-d3fd-4300-ab5c-ee0c803a80c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706875841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3706875841
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2685217861
Short name T370
Test name
Test status
Simulation time 2431455001 ps
CPU time 32.79 seconds
Started Feb 29 01:39:15 PM PST 24
Finished Feb 29 01:39:48 PM PST 24
Peak memory 216176 kb
Host smart-ed5ac3a9-d5d6-4566-918a-a1566649cb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685217861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2685217861
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4080623579
Short name T650
Test name
Test status
Simulation time 277206634 ps
CPU time 2.61 seconds
Started Feb 29 01:39:21 PM PST 24
Finished Feb 29 01:39:24 PM PST 24
Peak memory 207908 kb
Host smart-8b9db54c-b401-4851-8a45-32903c48627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080623579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4080623579
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2077412441
Short name T910
Test name
Test status
Simulation time 73253007 ps
CPU time 1.49 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:17 PM PST 24
Peak memory 216336 kb
Host smart-66f3471e-0de9-4325-8a2a-01efe0ebafda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077412441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2077412441
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3903747935
Short name T828
Test name
Test status
Simulation time 36175057 ps
CPU time 0.86 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:17 PM PST 24
Peak memory 205200 kb
Host smart-06e87703-8b4b-49f9-9c8c-bb7ce8cc7104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903747935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3903747935
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3726710514
Short name T666
Test name
Test status
Simulation time 1001517304 ps
CPU time 8.26 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:24 PM PST 24
Peak memory 226888 kb
Host smart-484b763f-9ad9-4f22-aebc-bd62c156c78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726710514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3726710514
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2040554450
Short name T554
Test name
Test status
Simulation time 28751051 ps
CPU time 0.72 seconds
Started Feb 29 01:39:30 PM PST 24
Finished Feb 29 01:39:30 PM PST 24
Peak memory 204384 kb
Host smart-f05e4590-a67a-42d2-a88a-39efdc787902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040554450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2040554450
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2628010146
Short name T597
Test name
Test status
Simulation time 321824527 ps
CPU time 4.15 seconds
Started Feb 29 01:39:26 PM PST 24
Finished Feb 29 01:39:30 PM PST 24
Peak memory 235004 kb
Host smart-72069a45-9ff0-4ebd-b44c-36bc3a64a449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628010146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2628010146
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.897218073
Short name T856
Test name
Test status
Simulation time 39950314 ps
CPU time 0.92 seconds
Started Feb 29 01:39:16 PM PST 24
Finished Feb 29 01:39:17 PM PST 24
Peak memory 205912 kb
Host smart-ad6427da-bfbc-4214-87aa-a3cd48d3da2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897218073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.897218073
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1539544873
Short name T859
Test name
Test status
Simulation time 19587453958 ps
CPU time 46.36 seconds
Started Feb 29 01:39:29 PM PST 24
Finished Feb 29 01:40:16 PM PST 24
Peak memory 235560 kb
Host smart-6f983b8b-cdf4-4510-b031-d76d32dc72d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539544873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1539544873
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.36525440
Short name T484
Test name
Test status
Simulation time 4597364873 ps
CPU time 63.65 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:40:32 PM PST 24
Peak memory 237404 kb
Host smart-2b92c974-0556-4cf0-bca4-2b7a0e78a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36525440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.36525440
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2169960056
Short name T296
Test name
Test status
Simulation time 2950080161 ps
CPU time 49.8 seconds
Started Feb 29 01:39:26 PM PST 24
Finished Feb 29 01:40:16 PM PST 24
Peak memory 255772 kb
Host smart-af7173dc-3bc7-41f2-86ba-472cd5b522e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169960056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2169960056
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2998032345
Short name T823
Test name
Test status
Simulation time 72100675146 ps
CPU time 25.21 seconds
Started Feb 29 01:39:30 PM PST 24
Finished Feb 29 01:39:56 PM PST 24
Peak memory 240016 kb
Host smart-1407d3dc-ae5d-4ad3-806f-0e86921ae014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998032345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2998032345
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3648104745
Short name T333
Test name
Test status
Simulation time 414799243 ps
CPU time 3.62 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:39:32 PM PST 24
Peak memory 234016 kb
Host smart-6dbcccea-505d-417d-af21-55a3b34b0d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648104745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3648104745
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2552505139
Short name T567
Test name
Test status
Simulation time 10001443447 ps
CPU time 13.72 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:39:42 PM PST 24
Peak memory 235616 kb
Host smart-109d7783-0c97-4af1-924a-393ec7278ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552505139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2552505139
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.903866341
Short name T888
Test name
Test status
Simulation time 396634899 ps
CPU time 4.24 seconds
Started Feb 29 01:39:27 PM PST 24
Finished Feb 29 01:39:31 PM PST 24
Peak memory 217596 kb
Host smart-7e9c453d-dfa9-4677-90a1-11adabd2a01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903866341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.903866341
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1287811893
Short name T771
Test name
Test status
Simulation time 9134894830 ps
CPU time 14.1 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:39:42 PM PST 24
Peak memory 240016 kb
Host smart-5b2d4edd-b7c6-49be-b9c7-539e73704187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287811893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1287811893
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.894384358
Short name T840
Test name
Test status
Simulation time 604591652 ps
CPU time 3.46 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:39:32 PM PST 24
Peak memory 218812 kb
Host smart-1ba89eb1-4102-49a5-85b9-171ef465d119
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=894384358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.894384358
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2385219504
Short name T218
Test name
Test status
Simulation time 102456596562 ps
CPU time 317.3 seconds
Started Feb 29 01:39:26 PM PST 24
Finished Feb 29 01:44:44 PM PST 24
Peak memory 272688 kb
Host smart-d0d65b41-a6a7-4913-8525-fed4ff0ee269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385219504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2385219504
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.834441483
Short name T29
Test name
Test status
Simulation time 57675635578 ps
CPU time 71.84 seconds
Started Feb 29 01:39:25 PM PST 24
Finished Feb 29 01:40:37 PM PST 24
Peak memory 220468 kb
Host smart-17c546ec-9ebb-4db9-a3a9-f78f16ed3e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834441483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.834441483
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1867157070
Short name T6
Test name
Test status
Simulation time 6419739426 ps
CPU time 19.62 seconds
Started Feb 29 01:39:27 PM PST 24
Finished Feb 29 01:39:47 PM PST 24
Peak memory 216180 kb
Host smart-c60db3b2-0886-43cc-af19-259f814916da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867157070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1867157070
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3993127890
Short name T323
Test name
Test status
Simulation time 357783706 ps
CPU time 14.47 seconds
Started Feb 29 01:39:29 PM PST 24
Finished Feb 29 01:39:43 PM PST 24
Peak memory 216076 kb
Host smart-d09d7b92-828a-4fa4-b878-8b8b4d8fe7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993127890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3993127890
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1623150802
Short name T624
Test name
Test status
Simulation time 88011129 ps
CPU time 1.01 seconds
Started Feb 29 01:39:26 PM PST 24
Finished Feb 29 01:39:27 PM PST 24
Peak memory 206372 kb
Host smart-cc5cd1f8-d529-4528-864f-26668ff16dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623150802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1623150802
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2298835612
Short name T463
Test name
Test status
Simulation time 12323292492 ps
CPU time 26.59 seconds
Started Feb 29 01:39:29 PM PST 24
Finished Feb 29 01:39:56 PM PST 24
Peak memory 229528 kb
Host smart-80fae76d-a51f-46f5-b3de-46c636eee247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298835612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2298835612
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4202052991
Short name T637
Test name
Test status
Simulation time 58755351 ps
CPU time 0.7 seconds
Started Feb 29 01:39:32 PM PST 24
Finished Feb 29 01:39:33 PM PST 24
Peak memory 204856 kb
Host smart-e0a07b35-03ed-4d37-8498-916b701ae31a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202052991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4202052991
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3556789322
Short name T658
Test name
Test status
Simulation time 255711671 ps
CPU time 3.96 seconds
Started Feb 29 01:39:26 PM PST 24
Finished Feb 29 01:39:30 PM PST 24
Peak memory 224236 kb
Host smart-c43de0ca-865c-43b3-b480-40b221585c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556789322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3556789322
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1982641602
Short name T60
Test name
Test status
Simulation time 13907050 ps
CPU time 0.77 seconds
Started Feb 29 01:39:27 PM PST 24
Finished Feb 29 01:39:29 PM PST 24
Peak memory 204936 kb
Host smart-ffad99f4-d612-4287-9f5a-7076c144c9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982641602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1982641602
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2853016806
Short name T807
Test name
Test status
Simulation time 6329478467 ps
CPU time 82.26 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:40:50 PM PST 24
Peak memory 257132 kb
Host smart-5de86cc0-52e4-4ec0-b875-6cd8348d0e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853016806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2853016806
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.463290933
Short name T49
Test name
Test status
Simulation time 11658926551 ps
CPU time 63.34 seconds
Started Feb 29 01:39:27 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 252152 kb
Host smart-058be95d-0ec1-4460-a7f0-1820ac607162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463290933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.463290933
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2977386096
Short name T360
Test name
Test status
Simulation time 4558749220 ps
CPU time 76.27 seconds
Started Feb 29 01:39:31 PM PST 24
Finished Feb 29 01:40:48 PM PST 24
Peak memory 257264 kb
Host smart-7559c8f4-dbb1-4849-a159-dc758b8da264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977386096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2977386096
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1234988672
Short name T566
Test name
Test status
Simulation time 537586378 ps
CPU time 10.87 seconds
Started Feb 29 01:39:26 PM PST 24
Finished Feb 29 01:39:37 PM PST 24
Peak memory 233520 kb
Host smart-18b6bb02-9913-4d69-812e-9fd45bb0c0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234988672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1234988672
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3359091136
Short name T192
Test name
Test status
Simulation time 7553581950 ps
CPU time 12.69 seconds
Started Feb 29 01:39:26 PM PST 24
Finished Feb 29 01:39:39 PM PST 24
Peak memory 233124 kb
Host smart-2e46132f-9481-4e76-8bae-95495d2fd43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359091136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3359091136
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1688818517
Short name T599
Test name
Test status
Simulation time 31720999096 ps
CPU time 28.16 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:39:56 PM PST 24
Peak memory 232624 kb
Host smart-382c09bb-18cd-4740-8ca6-f44c47007a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688818517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1688818517
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.357254937
Short name T536
Test name
Test status
Simulation time 1081302174 ps
CPU time 7.66 seconds
Started Feb 29 01:39:25 PM PST 24
Finished Feb 29 01:39:32 PM PST 24
Peak memory 232880 kb
Host smart-71240426-5646-4e25-a46e-4f4b70775a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357254937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.357254937
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1590772562
Short name T461
Test name
Test status
Simulation time 1382618430 ps
CPU time 5.87 seconds
Started Feb 29 01:39:31 PM PST 24
Finished Feb 29 01:39:37 PM PST 24
Peak memory 218704 kb
Host smart-672bddb3-ae11-4cfe-9911-9e629ce15dc0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1590772562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1590772562
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.20129342
Short name T693
Test name
Test status
Simulation time 233034420825 ps
CPU time 509.87 seconds
Started Feb 29 01:39:29 PM PST 24
Finished Feb 29 01:47:59 PM PST 24
Peak memory 283720 kb
Host smart-cf32a63e-15fb-4f7a-9b8a-431957522f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20129342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress
_all.20129342
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2290311329
Short name T293
Test name
Test status
Simulation time 5478552352 ps
CPU time 37.3 seconds
Started Feb 29 01:39:29 PM PST 24
Finished Feb 29 01:40:07 PM PST 24
Peak memory 216056 kb
Host smart-bd8ab806-72e5-4f33-9056-a45228c06b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290311329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2290311329
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1503027054
Short name T376
Test name
Test status
Simulation time 3508783421 ps
CPU time 3.12 seconds
Started Feb 29 01:39:25 PM PST 24
Finished Feb 29 01:39:28 PM PST 24
Peak memory 215908 kb
Host smart-c30ff01d-be29-42d6-80a5-f1e78f9c9d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503027054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1503027054
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4211061260
Short name T297
Test name
Test status
Simulation time 22586881 ps
CPU time 0.93 seconds
Started Feb 29 01:39:29 PM PST 24
Finished Feb 29 01:39:30 PM PST 24
Peak memory 206172 kb
Host smart-783384ab-0e3d-4077-bf4d-ff84590b9a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211061260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4211061260
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.4251701684
Short name T918
Test name
Test status
Simulation time 308094096 ps
CPU time 0.91 seconds
Started Feb 29 01:39:26 PM PST 24
Finished Feb 29 01:39:27 PM PST 24
Peak memory 205196 kb
Host smart-70b97d33-3879-4201-9393-d3811ed207c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251701684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4251701684
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3078548847
Short name T510
Test name
Test status
Simulation time 1249910842 ps
CPU time 6.51 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:39:35 PM PST 24
Peak memory 217416 kb
Host smart-a8190b88-10e0-47a0-8ea8-202efe0f8cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078548847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3078548847
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1656973371
Short name T669
Test name
Test status
Simulation time 12096432 ps
CPU time 0.72 seconds
Started Feb 29 01:39:38 PM PST 24
Finished Feb 29 01:39:39 PM PST 24
Peak memory 204864 kb
Host smart-b5f7f548-d162-4c7c-b7d2-6e838cba0ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656973371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1656973371
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2815791308
Short name T613
Test name
Test status
Simulation time 154461730 ps
CPU time 2.67 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:39:31 PM PST 24
Peak memory 233480 kb
Host smart-fe7e351c-3783-468d-abc8-2e6b07080ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815791308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2815791308
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1975650147
Short name T328
Test name
Test status
Simulation time 37343371 ps
CPU time 0.78 seconds
Started Feb 29 01:39:30 PM PST 24
Finished Feb 29 01:39:31 PM PST 24
Peak memory 205280 kb
Host smart-eb712686-9ed0-4ca5-a6d8-8bf483b55053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975650147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1975650147
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3235265097
Short name T200
Test name
Test status
Simulation time 14168276930 ps
CPU time 81.61 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:41:03 PM PST 24
Peak memory 250224 kb
Host smart-d5066dd9-2115-4300-9d65-7ca197a9b0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235265097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3235265097
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.836971140
Short name T84
Test name
Test status
Simulation time 12976841358 ps
CPU time 63.32 seconds
Started Feb 29 01:39:38 PM PST 24
Finished Feb 29 01:40:41 PM PST 24
Peak memory 239928 kb
Host smart-a9abede1-9036-45fd-91b6-fa998fb6ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836971140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.836971140
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2965483436
Short name T310
Test name
Test status
Simulation time 306206585 ps
CPU time 7.36 seconds
Started Feb 29 01:39:29 PM PST 24
Finished Feb 29 01:39:36 PM PST 24
Peak memory 248552 kb
Host smart-220c73d7-323f-4b39-8ca4-dceaa5d3fb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965483436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2965483436
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2082375512
Short name T663
Test name
Test status
Simulation time 1971635378 ps
CPU time 3.71 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:39:32 PM PST 24
Peak memory 234568 kb
Host smart-6d738995-c8c6-4838-a192-f6f379e0e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082375512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2082375512
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2216743190
Short name T500
Test name
Test status
Simulation time 32092225078 ps
CPU time 27.08 seconds
Started Feb 29 01:39:26 PM PST 24
Finished Feb 29 01:39:54 PM PST 24
Peak memory 239860 kb
Host smart-a3547f52-bb33-4d3b-98eb-11b3ec292d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216743190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2216743190
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3315374915
Short name T844
Test name
Test status
Simulation time 2551696570 ps
CPU time 4.93 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:39:33 PM PST 24
Peak memory 224360 kb
Host smart-2d9e89b5-9ae0-43c4-b98f-134f466d3c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315374915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3315374915
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.130667767
Short name T251
Test name
Test status
Simulation time 34545668340 ps
CPU time 11.93 seconds
Started Feb 29 01:39:29 PM PST 24
Finished Feb 29 01:39:41 PM PST 24
Peak memory 216760 kb
Host smart-e38b99d1-efce-405b-bc2a-8e222124be2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130667767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.130667767
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2552520128
Short name T127
Test name
Test status
Simulation time 294861593 ps
CPU time 3.11 seconds
Started Feb 29 01:39:27 PM PST 24
Finished Feb 29 01:39:30 PM PST 24
Peak memory 220036 kb
Host smart-cb4437dd-7313-4bba-8f71-b3f98a764ba9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2552520128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2552520128
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.747822363
Short name T265
Test name
Test status
Simulation time 15776306444 ps
CPU time 64.91 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 251208 kb
Host smart-5e0c7c40-2ed0-4b08-b68d-ea7aef0a627e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747822363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.747822363
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1188114595
Short name T390
Test name
Test status
Simulation time 960613984 ps
CPU time 6.62 seconds
Started Feb 29 01:39:27 PM PST 24
Finished Feb 29 01:39:34 PM PST 24
Peak memory 216020 kb
Host smart-f20a0ca8-f630-4884-8074-60a6a9d6a78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188114595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1188114595
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4068703242
Short name T320
Test name
Test status
Simulation time 21333717926 ps
CPU time 30.82 seconds
Started Feb 29 01:39:27 PM PST 24
Finished Feb 29 01:39:58 PM PST 24
Peak memory 216124 kb
Host smart-d6bb63fd-4701-4a20-b4ea-a98e522ef19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068703242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4068703242
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2602265818
Short name T382
Test name
Test status
Simulation time 19904173 ps
CPU time 0.88 seconds
Started Feb 29 01:39:28 PM PST 24
Finished Feb 29 01:39:29 PM PST 24
Peak memory 205908 kb
Host smart-ded17de5-d86d-4957-be6e-d1b4380feba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602265818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2602265818
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.956812222
Short name T968
Test name
Test status
Simulation time 304947760 ps
CPU time 0.84 seconds
Started Feb 29 01:39:30 PM PST 24
Finished Feb 29 01:39:31 PM PST 24
Peak memory 205104 kb
Host smart-bbc726c0-e6df-45c9-8f5c-82d450658ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956812222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.956812222
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3962708013
Short name T366
Test name
Test status
Simulation time 10596385457 ps
CPU time 15.33 seconds
Started Feb 29 01:39:29 PM PST 24
Finished Feb 29 01:39:45 PM PST 24
Peak memory 233212 kb
Host smart-0b015d7a-1c4c-4774-b628-029c9686edc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962708013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3962708013
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2605114553
Short name T458
Test name
Test status
Simulation time 13790379 ps
CPU time 0.72 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:42 PM PST 24
Peak memory 204828 kb
Host smart-de31d55a-efa6-4725-a9e3-62256333ee84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605114553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2605114553
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3918343727
Short name T345
Test name
Test status
Simulation time 462861790 ps
CPU time 3.34 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:45 PM PST 24
Peak memory 233932 kb
Host smart-93eb4c1f-27a8-495c-8034-956e0ac3b0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918343727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3918343727
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.663571601
Short name T837
Test name
Test status
Simulation time 36543149 ps
CPU time 0.77 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:39:40 PM PST 24
Peak memory 204960 kb
Host smart-0f4a0b56-bad5-4bcc-8246-421356109ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663571601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.663571601
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2748199000
Short name T474
Test name
Test status
Simulation time 22278438313 ps
CPU time 120.56 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:41:42 PM PST 24
Peak memory 257188 kb
Host smart-5dc48b32-9974-477c-89c2-f1ad3b0a6856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748199000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2748199000
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2959372284
Short name T961
Test name
Test status
Simulation time 92235461261 ps
CPU time 281.75 seconds
Started Feb 29 01:39:40 PM PST 24
Finished Feb 29 01:44:22 PM PST 24
Peak memory 254836 kb
Host smart-8142a6af-807b-4313-923c-4c7d1b9ef296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959372284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2959372284
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.858823198
Short name T277
Test name
Test status
Simulation time 19376990816 ps
CPU time 108.89 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:41:28 PM PST 24
Peak memory 255892 kb
Host smart-31107770-43e5-4b88-9add-2f28132b1ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858823198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.858823198
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3702351126
Short name T247
Test name
Test status
Simulation time 855803518 ps
CPU time 3.99 seconds
Started Feb 29 01:39:38 PM PST 24
Finished Feb 29 01:39:42 PM PST 24
Peak memory 217656 kb
Host smart-50c7cb2f-431d-465f-bdfe-083bd09b254a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702351126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3702351126
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1928220354
Short name T249
Test name
Test status
Simulation time 6540609828 ps
CPU time 19.31 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:40:01 PM PST 24
Peak memory 234172 kb
Host smart-dc5ab26f-195d-4305-8851-ee80dc981250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928220354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1928220354
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.967038161
Short name T170
Test name
Test status
Simulation time 5511424469 ps
CPU time 8.1 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:50 PM PST 24
Peak memory 237676 kb
Host smart-181347d2-2f8b-41cb-a8ee-8b67ea94aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967038161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.967038161
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.849120659
Short name T776
Test name
Test status
Simulation time 2394911332 ps
CPU time 11.92 seconds
Started Feb 29 01:39:36 PM PST 24
Finished Feb 29 01:39:48 PM PST 24
Peak memory 233300 kb
Host smart-3f7c0d1c-70f8-498d-8b34-9f74beb635e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849120659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.849120659
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2313767816
Short name T379
Test name
Test status
Simulation time 1782632290 ps
CPU time 5.75 seconds
Started Feb 29 01:39:38 PM PST 24
Finished Feb 29 01:39:44 PM PST 24
Peak memory 222396 kb
Host smart-bd51235a-b252-4576-b673-d3a40eaea121
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2313767816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2313767816
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2433786131
Short name T21
Test name
Test status
Simulation time 77491358158 ps
CPU time 244.45 seconds
Started Feb 29 01:39:37 PM PST 24
Finished Feb 29 01:43:42 PM PST 24
Peak memory 255720 kb
Host smart-1f22649d-d0c3-4e26-9843-20d318fb4fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433786131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2433786131
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2500788142
Short name T16
Test name
Test status
Simulation time 3655259353 ps
CPU time 39.39 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:40:18 PM PST 24
Peak memory 216244 kb
Host smart-d074244f-0a55-4309-be91-dd4f542a82d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500788142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2500788142
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2700835211
Short name T649
Test name
Test status
Simulation time 193629977 ps
CPU time 1.52 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:44 PM PST 24
Peak memory 207660 kb
Host smart-3df3573a-81e5-4567-846d-fdffd18c8530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700835211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2700835211
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.699530016
Short name T602
Test name
Test status
Simulation time 116001440 ps
CPU time 4.25 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:39:44 PM PST 24
Peak memory 216184 kb
Host smart-943d3a75-f47a-429f-bc2c-08a700a6fd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699530016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.699530016
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.273038343
Short name T518
Test name
Test status
Simulation time 81936157 ps
CPU time 0.78 seconds
Started Feb 29 01:39:38 PM PST 24
Finished Feb 29 01:39:39 PM PST 24
Peak memory 205212 kb
Host smart-db2e5b49-81a4-4fcd-99ce-5d8755961792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273038343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.273038343
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3142427636
Short name T926
Test name
Test status
Simulation time 12775504007 ps
CPU time 15.66 seconds
Started Feb 29 01:39:38 PM PST 24
Finished Feb 29 01:39:54 PM PST 24
Peak memory 239948 kb
Host smart-02bb3078-c516-4b0a-9604-8128b88cba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142427636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3142427636
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1423533554
Short name T444
Test name
Test status
Simulation time 200119296 ps
CPU time 0.71 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:42 PM PST 24
Peak memory 204220 kb
Host smart-3e49ee56-7dc8-40a4-877f-c8592768fa24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423533554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1423533554
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3312988525
Short name T216
Test name
Test status
Simulation time 192751632 ps
CPU time 2.52 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:45 PM PST 24
Peak memory 233464 kb
Host smart-ccc41356-a527-40f5-acb5-0d5da4808283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312988525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3312988525
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3314369145
Short name T548
Test name
Test status
Simulation time 39558137 ps
CPU time 0.76 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:39:40 PM PST 24
Peak memory 205964 kb
Host smart-909e0e23-7952-46f9-a952-fd812b44648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314369145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3314369145
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1435871252
Short name T264
Test name
Test status
Simulation time 24572235082 ps
CPU time 132.53 seconds
Started Feb 29 01:39:40 PM PST 24
Finished Feb 29 01:41:53 PM PST 24
Peak memory 248716 kb
Host smart-8fde8c9c-0f00-4bb7-930b-f4faebb581ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435871252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1435871252
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.988318062
Short name T184
Test name
Test status
Simulation time 10473293467 ps
CPU time 54.38 seconds
Started Feb 29 01:39:43 PM PST 24
Finished Feb 29 01:40:38 PM PST 24
Peak memory 254880 kb
Host smart-bca7eece-8a9c-4df0-9b4b-fb9b426275e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988318062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.988318062
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2209748209
Short name T759
Test name
Test status
Simulation time 54840246921 ps
CPU time 113.7 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:41:35 PM PST 24
Peak memory 250052 kb
Host smart-cb9133bc-5818-47d5-ae90-35268801c99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209748209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2209748209
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.743362060
Short name T208
Test name
Test status
Simulation time 526281037 ps
CPU time 9.62 seconds
Started Feb 29 01:39:38 PM PST 24
Finished Feb 29 01:39:47 PM PST 24
Peak memory 234904 kb
Host smart-dace00f8-5565-4458-acae-8a00983bb759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743362060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.743362060
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3304588084
Short name T739
Test name
Test status
Simulation time 1836902335 ps
CPU time 5.75 seconds
Started Feb 29 01:39:38 PM PST 24
Finished Feb 29 01:39:44 PM PST 24
Peak memory 237624 kb
Host smart-75310fab-27f4-49ef-9336-337b3d5d71d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304588084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3304588084
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.382674546
Short name T898
Test name
Test status
Simulation time 12791185845 ps
CPU time 16.62 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:58 PM PST 24
Peak memory 240804 kb
Host smart-51579221-cc6f-4010-a4b9-a445d38a7570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382674546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.382674546
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3229976174
Short name T699
Test name
Test status
Simulation time 862948341 ps
CPU time 9.98 seconds
Started Feb 29 01:39:38 PM PST 24
Finished Feb 29 01:39:48 PM PST 24
Peak memory 232384 kb
Host smart-832211d3-8a03-4a70-bf6d-15a3b2646317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229976174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3229976174
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2439855748
Short name T172
Test name
Test status
Simulation time 772508232 ps
CPU time 8.84 seconds
Started Feb 29 01:39:43 PM PST 24
Finished Feb 29 01:39:53 PM PST 24
Peak memory 232884 kb
Host smart-eb69c56e-5ea2-4ff0-83f8-10cc2e7e6fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439855748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2439855748
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1852659647
Short name T720
Test name
Test status
Simulation time 5423960783 ps
CPU time 6.02 seconds
Started Feb 29 01:39:40 PM PST 24
Finished Feb 29 01:39:47 PM PST 24
Peak memory 222608 kb
Host smart-dac80ac7-9a04-40f0-8dc6-a4342d5f37e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1852659647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1852659647
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2367267334
Short name T144
Test name
Test status
Simulation time 33646762310 ps
CPU time 106.59 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:41:26 PM PST 24
Peak memory 272584 kb
Host smart-20629e7e-f9c8-44f9-b110-4efa7c3bafef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367267334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2367267334
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3048455512
Short name T363
Test name
Test status
Simulation time 9208722406 ps
CPU time 43.01 seconds
Started Feb 29 01:39:38 PM PST 24
Finished Feb 29 01:40:21 PM PST 24
Peak memory 216232 kb
Host smart-71fae63d-3060-49df-b651-5241d24c1571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048455512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3048455512
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2889161654
Short name T801
Test name
Test status
Simulation time 26074769144 ps
CPU time 33.85 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:40:13 PM PST 24
Peak memory 216168 kb
Host smart-9ec1cc8b-1e3e-4cae-a1d0-4906805f7b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889161654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2889161654
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3188191067
Short name T47
Test name
Test status
Simulation time 605804011 ps
CPU time 3.68 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:39:43 PM PST 24
Peak memory 216056 kb
Host smart-80d8b5c5-b3e5-4c2e-a81a-921dbf623014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188191067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3188191067
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2138870087
Short name T850
Test name
Test status
Simulation time 65402109 ps
CPU time 0.78 seconds
Started Feb 29 01:39:40 PM PST 24
Finished Feb 29 01:39:41 PM PST 24
Peak memory 205240 kb
Host smart-98d8f9aa-8558-4db5-8516-aa23c414ca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138870087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2138870087
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.4037348625
Short name T845
Test name
Test status
Simulation time 56210613 ps
CPU time 2.65 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:39:42 PM PST 24
Peak memory 224300 kb
Host smart-090f6101-342f-4dc9-befe-a839ba29ef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037348625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4037348625
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.397311773
Short name T435
Test name
Test status
Simulation time 12670646 ps
CPU time 0.71 seconds
Started Feb 29 01:39:50 PM PST 24
Finished Feb 29 01:39:51 PM PST 24
Peak memory 205152 kb
Host smart-9bca63e1-149b-49fd-8979-94caa432e01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397311773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.397311773
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3048814321
Short name T846
Test name
Test status
Simulation time 2465235749 ps
CPU time 4.3 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:46 PM PST 24
Peak memory 224352 kb
Host smart-6d3fa807-e475-4f73-a335-b871a537441b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048814321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3048814321
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.335161735
Short name T17
Test name
Test status
Simulation time 29243101 ps
CPU time 0.78 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:42 PM PST 24
Peak memory 206308 kb
Host smart-ac65232f-6917-4ccb-a40d-8e6a0144e423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335161735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.335161735
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2123861094
Short name T167
Test name
Test status
Simulation time 56064825470 ps
CPU time 62.81 seconds
Started Feb 29 01:39:50 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 247620 kb
Host smart-00bc58d1-3823-4300-94c1-9d35ccf5483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123861094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2123861094
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3735796407
Short name T284
Test name
Test status
Simulation time 10386163483 ps
CPU time 131.36 seconds
Started Feb 29 01:39:52 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 255728 kb
Host smart-43db3eb0-d8bf-42f5-aae8-879c10e180df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735796407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3735796407
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1016187262
Short name T59
Test name
Test status
Simulation time 63532893087 ps
CPU time 213.86 seconds
Started Feb 29 01:39:53 PM PST 24
Finished Feb 29 01:43:27 PM PST 24
Peak memory 252312 kb
Host smart-2a3ff94d-ae38-419f-92b2-55eff4f2cb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016187262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1016187262
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2214500813
Short name T128
Test name
Test status
Simulation time 12043666529 ps
CPU time 24.2 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:40:06 PM PST 24
Peak memory 232696 kb
Host smart-0e50171e-ede4-4806-870b-d99d954be845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214500813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2214500813
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2806169414
Short name T553
Test name
Test status
Simulation time 744108701 ps
CPU time 3.65 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:46 PM PST 24
Peak memory 233336 kb
Host smart-be7b454d-c920-47e6-b487-6cda8a8a8f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806169414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2806169414
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2845775994
Short name T871
Test name
Test status
Simulation time 22695710033 ps
CPU time 17.34 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:39:57 PM PST 24
Peak memory 235940 kb
Host smart-9e6b26f2-24d0-47d9-8272-2032708b4e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845775994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2845775994
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2393624840
Short name T874
Test name
Test status
Simulation time 2033413637 ps
CPU time 10.88 seconds
Started Feb 29 01:39:42 PM PST 24
Finished Feb 29 01:39:54 PM PST 24
Peak memory 224296 kb
Host smart-d0184d46-e9cf-4627-a01a-36d78e99f067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393624840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2393624840
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1931042426
Short name T743
Test name
Test status
Simulation time 7290491632 ps
CPU time 8.45 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:50 PM PST 24
Peak memory 233528 kb
Host smart-930477ce-eecc-442a-a1ce-84f024616050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931042426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1931042426
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1077801509
Short name T612
Test name
Test status
Simulation time 253483665 ps
CPU time 4 seconds
Started Feb 29 01:39:52 PM PST 24
Finished Feb 29 01:39:56 PM PST 24
Peak memory 222032 kb
Host smart-a48bf771-1814-45ca-8aff-c5e5b48bafe4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1077801509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1077801509
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.900889782
Short name T140
Test name
Test status
Simulation time 134294475 ps
CPU time 1.04 seconds
Started Feb 29 01:39:50 PM PST 24
Finished Feb 29 01:39:51 PM PST 24
Peak memory 205920 kb
Host smart-9365adf7-38e3-4357-af01-ef101ac95efe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900889782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.900889782
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2038509931
Short name T426
Test name
Test status
Simulation time 9771322136 ps
CPU time 60.38 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:40:43 PM PST 24
Peak memory 216188 kb
Host smart-c8606432-8dc7-4248-990a-b2ca79eb2a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038509931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2038509931
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2532268296
Short name T453
Test name
Test status
Simulation time 4902250591 ps
CPU time 8.19 seconds
Started Feb 29 01:39:40 PM PST 24
Finished Feb 29 01:39:49 PM PST 24
Peak memory 216176 kb
Host smart-29ea0e84-21b2-4817-89e7-6c3129cf5555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532268296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2532268296
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3327179145
Short name T507
Test name
Test status
Simulation time 868052717 ps
CPU time 3.78 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:45 PM PST 24
Peak memory 217860 kb
Host smart-152029a4-b626-4c20-a8b6-7499019aa772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327179145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3327179145
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3862714869
Short name T625
Test name
Test status
Simulation time 423095457 ps
CPU time 1.05 seconds
Started Feb 29 01:39:39 PM PST 24
Finished Feb 29 01:39:40 PM PST 24
Peak memory 206244 kb
Host smart-3f13c051-8cf5-4098-bb18-7f4bbeec709e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862714869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3862714869
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4191804255
Short name T561
Test name
Test status
Simulation time 2128768661 ps
CPU time 10.58 seconds
Started Feb 29 01:39:41 PM PST 24
Finished Feb 29 01:39:52 PM PST 24
Peak memory 238640 kb
Host smart-8d398cc0-3613-46f9-af35-053a1808f9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191804255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4191804255
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1532159722
Short name T754
Test name
Test status
Simulation time 20851773 ps
CPU time 0.73 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:29 PM PST 24
Peak memory 204272 kb
Host smart-67e9ee1a-74ac-4e17-866d-742129c825d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532159722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
532159722
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.445163600
Short name T398
Test name
Test status
Simulation time 2294085636 ps
CPU time 4.92 seconds
Started Feb 29 01:36:27 PM PST 24
Finished Feb 29 01:36:32 PM PST 24
Peak memory 234728 kb
Host smart-95ea947f-a724-4234-952b-8c27b7dfe8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445163600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.445163600
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.856104489
Short name T332
Test name
Test status
Simulation time 17014256 ps
CPU time 0.78 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:29 PM PST 24
Peak memory 206344 kb
Host smart-074987ae-1f38-4f5e-8cc2-96c95458a2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856104489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.856104489
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3638814979
Short name T726
Test name
Test status
Simulation time 9392248512 ps
CPU time 58.09 seconds
Started Feb 29 01:36:31 PM PST 24
Finished Feb 29 01:37:30 PM PST 24
Peak memory 239264 kb
Host smart-e65d3d74-7b60-44a4-8b43-0ac557865163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638814979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3638814979
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3861352449
Short name T984
Test name
Test status
Simulation time 189272882681 ps
CPU time 159.82 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:39:09 PM PST 24
Peak memory 255264 kb
Host smart-961c696d-907f-47d1-9a8a-f734ffaec218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861352449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3861352449
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.901171738
Short name T359
Test name
Test status
Simulation time 40232282846 ps
CPU time 173.04 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:39:21 PM PST 24
Peak memory 255188 kb
Host smart-15cbbc38-9506-4262-be4c-39d13fd250f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901171738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
901171738
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3075243027
Short name T291
Test name
Test status
Simulation time 11052815581 ps
CPU time 49.14 seconds
Started Feb 29 01:36:32 PM PST 24
Finished Feb 29 01:37:21 PM PST 24
Peak memory 239900 kb
Host smart-7d324fa9-759c-4466-a540-eb1958f74ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075243027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3075243027
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.582742355
Short name T223
Test name
Test status
Simulation time 4160154257 ps
CPU time 14.44 seconds
Started Feb 29 01:36:25 PM PST 24
Finished Feb 29 01:36:40 PM PST 24
Peak memory 219132 kb
Host smart-fc3a8f07-97ec-41d6-b6d1-3765545b0565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582742355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.582742355
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2875130857
Short name T777
Test name
Test status
Simulation time 26082684821 ps
CPU time 14.07 seconds
Started Feb 29 01:36:27 PM PST 24
Finished Feb 29 01:36:41 PM PST 24
Peak memory 224352 kb
Host smart-89d739f3-daf2-4266-8604-f0c8e6a3e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875130857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2875130857
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3295793183
Short name T769
Test name
Test status
Simulation time 48819128 ps
CPU time 1.04 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:29 PM PST 24
Peak memory 217748 kb
Host smart-2a0449bc-8231-42c8-a795-1fd0496cf4ed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295793183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3295793183
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1739638968
Short name T868
Test name
Test status
Simulation time 2606853239 ps
CPU time 13.65 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:42 PM PST 24
Peak memory 239156 kb
Host smart-db4a67cc-fbbb-470e-b8f5-b65051d57a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739638968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1739638968
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3718981046
Short name T428
Test name
Test status
Simulation time 18507369999 ps
CPU time 31 seconds
Started Feb 29 01:36:27 PM PST 24
Finished Feb 29 01:36:58 PM PST 24
Peak memory 232456 kb
Host smart-e00ffc80-e815-4dd3-aa52-698f87607044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718981046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3718981046
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.242038411
Short name T414
Test name
Test status
Simulation time 18997901 ps
CPU time 0.77 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:30 PM PST 24
Peak memory 215968 kb
Host smart-e50bd704-35a8-46fa-9527-18860bb776ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242038411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.242038411
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3119909937
Short name T318
Test name
Test status
Simulation time 240918433 ps
CPU time 3.43 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:32 PM PST 24
Peak memory 219976 kb
Host smart-75132b8c-d443-47ed-8eee-73845fab4140
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3119909937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3119909937
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4129231869
Short name T143
Test name
Test status
Simulation time 50555502514 ps
CPU time 200.3 seconds
Started Feb 29 01:36:30 PM PST 24
Finished Feb 29 01:39:50 PM PST 24
Peak memory 240848 kb
Host smart-75d1f4a5-e1c6-44ec-ae24-1f677cc7a2a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129231869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4129231869
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3281809783
Short name T355
Test name
Test status
Simulation time 2497375576 ps
CPU time 23.19 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:51 PM PST 24
Peak memory 217924 kb
Host smart-42d409fb-636d-47cf-8924-eb67a6d760d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281809783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3281809783
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2902326126
Short name T733
Test name
Test status
Simulation time 1597108755 ps
CPU time 5.01 seconds
Started Feb 29 01:36:27 PM PST 24
Finished Feb 29 01:36:32 PM PST 24
Peak memory 207856 kb
Host smart-c604d610-6272-4b1b-8f33-3f3a582667cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902326126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2902326126
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2637161996
Short name T374
Test name
Test status
Simulation time 28857274 ps
CPU time 1.15 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:30 PM PST 24
Peak memory 206916 kb
Host smart-bad82e5e-c6b8-4eae-8c3e-866205f8f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637161996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2637161996
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.56151776
Short name T986
Test name
Test status
Simulation time 56925611 ps
CPU time 0.73 seconds
Started Feb 29 01:36:32 PM PST 24
Finished Feb 29 01:36:33 PM PST 24
Peak memory 205196 kb
Host smart-0a5e2b21-13f4-44f4-944b-554839310278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56151776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.56151776
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2215417964
Short name T424
Test name
Test status
Simulation time 1183247146 ps
CPU time 4.74 seconds
Started Feb 29 01:36:26 PM PST 24
Finished Feb 29 01:36:31 PM PST 24
Peak memory 233976 kb
Host smart-d4c147e4-586f-483b-85bc-d89033561e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215417964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2215417964
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.4138168893
Short name T298
Test name
Test status
Simulation time 54060264 ps
CPU time 0.72 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:30 PM PST 24
Peak memory 205160 kb
Host smart-65fcb68c-3e76-4f5b-b805-7e8710073d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138168893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.4
138168893
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3868531516
Short name T904
Test name
Test status
Simulation time 1380615724 ps
CPU time 4.88 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:34 PM PST 24
Peak memory 233628 kb
Host smart-073ca96d-ab4f-47fc-b163-109cbd817bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868531516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3868531516
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.548431259
Short name T878
Test name
Test status
Simulation time 16131984 ps
CPU time 0.72 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:28 PM PST 24
Peak memory 204900 kb
Host smart-a6405406-e5a6-4fbf-8242-7b328470a131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548431259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.548431259
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3591270524
Short name T948
Test name
Test status
Simulation time 20758958233 ps
CPU time 25.07 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:53 PM PST 24
Peak memory 236748 kb
Host smart-1c610d8c-4f01-48e0-a412-170bf3445376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591270524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3591270524
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3180051445
Short name T486
Test name
Test status
Simulation time 2350380753 ps
CPU time 38.63 seconds
Started Feb 29 01:36:32 PM PST 24
Finished Feb 29 01:37:11 PM PST 24
Peak memory 255216 kb
Host smart-7f95d0c1-d205-496a-a4a1-78cbd752228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180051445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3180051445
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3872467790
Short name T181
Test name
Test status
Simulation time 90460445779 ps
CPU time 331.87 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:42:01 PM PST 24
Peak memory 256340 kb
Host smart-6ca96b99-c650-40c9-9a28-b4f2e06e5538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872467790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3872467790
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3132275375
Short name T601
Test name
Test status
Simulation time 207499410 ps
CPU time 2.7 seconds
Started Feb 29 01:36:32 PM PST 24
Finished Feb 29 01:36:35 PM PST 24
Peak memory 232932 kb
Host smart-c00ac91d-e93d-4107-bf6e-ed3f6a4d90a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132275375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3132275375
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2320756762
Short name T858
Test name
Test status
Simulation time 1260800163 ps
CPU time 9.8 seconds
Started Feb 29 01:36:30 PM PST 24
Finished Feb 29 01:36:40 PM PST 24
Peak memory 240628 kb
Host smart-dba20ca9-f1d5-4746-989d-930b3b3108bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320756762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2320756762
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.4060620829
Short name T772
Test name
Test status
Simulation time 61734582 ps
CPU time 1.04 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:29 PM PST 24
Peak memory 217788 kb
Host smart-e2af5757-279f-4bd2-87df-5a59a0b66b0e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060620829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.4060620829
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1175555384
Short name T873
Test name
Test status
Simulation time 570411270 ps
CPU time 7.26 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:36 PM PST 24
Peak memory 233188 kb
Host smart-7a6824e3-73b2-459d-aef4-0f9b711d269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175555384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1175555384
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2604183085
Short name T44
Test name
Test status
Simulation time 42729731952 ps
CPU time 14.91 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:43 PM PST 24
Peak memory 248744 kb
Host smart-e24d17f4-ce0b-474d-8465-ebd751b6fe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604183085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2604183085
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.1892651269
Short name T540
Test name
Test status
Simulation time 25287742 ps
CPU time 0.8 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:30 PM PST 24
Peak memory 216020 kb
Host smart-8bbf73a5-5a70-4ed1-92d8-5d5de13ca09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892651269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.1892651269
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2748287298
Short name T978
Test name
Test status
Simulation time 9858565155 ps
CPU time 5.22 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:34 PM PST 24
Peak memory 218752 kb
Host smart-458ca789-8138-4ce3-b810-b903fa49ab5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2748287298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2748287298
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2881021827
Short name T442
Test name
Test status
Simulation time 42531108 ps
CPU time 1.09 seconds
Started Feb 29 01:36:32 PM PST 24
Finished Feb 29 01:36:33 PM PST 24
Peak memory 206416 kb
Host smart-60ea5dd5-3abb-40e9-8f90-add18d141d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881021827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2881021827
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3890220240
Short name T897
Test name
Test status
Simulation time 44780967869 ps
CPU time 65.03 seconds
Started Feb 29 01:36:30 PM PST 24
Finished Feb 29 01:37:35 PM PST 24
Peak memory 220460 kb
Host smart-0d168bd5-1a2c-41ba-9ebf-4955c74f5dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890220240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3890220240
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3359628563
Short name T516
Test name
Test status
Simulation time 1560291462 ps
CPU time 6.53 seconds
Started Feb 29 01:36:32 PM PST 24
Finished Feb 29 01:36:38 PM PST 24
Peak memory 208048 kb
Host smart-fabe51fe-d26f-44cc-b26f-817adb56c92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359628563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3359628563
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.825989101
Short name T417
Test name
Test status
Simulation time 262144996 ps
CPU time 1.53 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:30 PM PST 24
Peak memory 216036 kb
Host smart-476627e1-a864-410f-9860-1ca3b52257ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825989101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.825989101
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3418961078
Short name T322
Test name
Test status
Simulation time 22128201 ps
CPU time 0.75 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:30 PM PST 24
Peak memory 205224 kb
Host smart-954a5fd6-21d5-4293-9f80-5fde9c78281e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418961078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3418961078
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.157445678
Short name T358
Test name
Test status
Simulation time 1215521261 ps
CPU time 4.67 seconds
Started Feb 29 01:36:26 PM PST 24
Finished Feb 29 01:36:31 PM PST 24
Peak memory 218332 kb
Host smart-50fce290-3801-42c5-a2cc-89a8350e7d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157445678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.157445678
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1259197750
Short name T61
Test name
Test status
Simulation time 11823513 ps
CPU time 0.74 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:30 PM PST 24
Peak memory 204852 kb
Host smart-11f80c4b-754a-491a-9a76-20dd896fba7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259197750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
259197750
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1295059976
Short name T212
Test name
Test status
Simulation time 5840645674 ps
CPU time 3.51 seconds
Started Feb 29 01:36:31 PM PST 24
Finished Feb 29 01:36:34 PM PST 24
Peak memory 218648 kb
Host smart-6c81547b-0c46-41d3-8d1b-632e1065cd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295059976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1295059976
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3417338814
Short name T812
Test name
Test status
Simulation time 41421685 ps
CPU time 0.8 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:29 PM PST 24
Peak memory 206216 kb
Host smart-e2342f5d-fde2-44ca-b0b9-219847cb8dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417338814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3417338814
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.999856748
Short name T246
Test name
Test status
Simulation time 6590572434 ps
CPU time 17.97 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:47 PM PST 24
Peak memory 238092 kb
Host smart-e09974fe-ea12-41ef-ba64-4307ae34a0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999856748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.999856748
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.802498677
Short name T203
Test name
Test status
Simulation time 57899392437 ps
CPU time 190.34 seconds
Started Feb 29 01:36:32 PM PST 24
Finished Feb 29 01:39:42 PM PST 24
Peak memory 254164 kb
Host smart-130d2c64-e341-4bce-8d8f-7ace3f2b792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802498677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.802498677
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3931226503
Short name T193
Test name
Test status
Simulation time 8433752832 ps
CPU time 91.88 seconds
Started Feb 29 01:36:32 PM PST 24
Finished Feb 29 01:38:04 PM PST 24
Peak memory 267740 kb
Host smart-ac11d083-929f-464e-a7b4-8ffb2e5df37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931226503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3931226503
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2318855649
Short name T565
Test name
Test status
Simulation time 368720506 ps
CPU time 9.84 seconds
Started Feb 29 01:36:30 PM PST 24
Finished Feb 29 01:36:40 PM PST 24
Peak memory 240116 kb
Host smart-44ce0295-8b16-4b5c-8bac-e6845655014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318855649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2318855649
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.312308055
Short name T492
Test name
Test status
Simulation time 110172757 ps
CPU time 3.37 seconds
Started Feb 29 01:36:31 PM PST 24
Finished Feb 29 01:36:34 PM PST 24
Peak memory 233504 kb
Host smart-16c3fc06-2dca-48a3-9c6a-191055746356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312308055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.312308055
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1038616886
Short name T655
Test name
Test status
Simulation time 4427508804 ps
CPU time 19.75 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:49 PM PST 24
Peak memory 239304 kb
Host smart-0745dca4-3ee5-4238-94f8-33d9f45ade6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038616886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1038616886
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.888975846
Short name T744
Test name
Test status
Simulation time 71445740 ps
CPU time 1.11 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:30 PM PST 24
Peak memory 216484 kb
Host smart-fcd44e01-3015-45c0-89cc-1ff9218ccdc9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888975846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.888975846
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.762448013
Short name T348
Test name
Test status
Simulation time 3872343545 ps
CPU time 9.79 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:38 PM PST 24
Peak memory 232960 kb
Host smart-7ab7b4ec-d643-4bd0-935b-907f238b2d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762448013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
762448013
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.338599825
Short name T501
Test name
Test status
Simulation time 510672547 ps
CPU time 4.52 seconds
Started Feb 29 01:36:30 PM PST 24
Finished Feb 29 01:36:35 PM PST 24
Peak memory 224104 kb
Host smart-7164bbfb-396e-4f36-8c5b-6070901a0ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338599825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.338599825
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.607786010
Short name T626
Test name
Test status
Simulation time 16834599 ps
CPU time 0.76 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:29 PM PST 24
Peak memory 216164 kb
Host smart-c227c2b8-be4a-46d7-ba08-af1c798ba01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607786010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.607786010
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2634187920
Short name T675
Test name
Test status
Simulation time 393509825 ps
CPU time 3.74 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:32 PM PST 24
Peak memory 222452 kb
Host smart-24f9fcea-e08d-4404-acaa-7fad6522a348
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2634187920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2634187920
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.364416810
Short name T278
Test name
Test status
Simulation time 185158458756 ps
CPU time 416.56 seconds
Started Feb 29 01:36:30 PM PST 24
Finished Feb 29 01:43:27 PM PST 24
Peak memory 265476 kb
Host smart-e41f9f37-3416-4606-a55a-56dc60fe3c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364416810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.364416810
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1075865958
Short name T615
Test name
Test status
Simulation time 3469000977 ps
CPU time 2.93 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:31 PM PST 24
Peak memory 216172 kb
Host smart-57c4a6a4-4196-4fc9-94a3-341f63052ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075865958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1075865958
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1384637679
Short name T76
Test name
Test status
Simulation time 1468368679 ps
CPU time 9.61 seconds
Started Feb 29 01:36:32 PM PST 24
Finished Feb 29 01:36:42 PM PST 24
Peak memory 216048 kb
Host smart-22fd3eb5-595d-4932-a9aa-6b125ac56910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384637679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1384637679
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.659903364
Short name T421
Test name
Test status
Simulation time 30858220 ps
CPU time 1.37 seconds
Started Feb 29 01:36:29 PM PST 24
Finished Feb 29 01:36:30 PM PST 24
Peak memory 207784 kb
Host smart-8646294d-6d67-48e7-983e-32fe82a75c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659903364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.659903364
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2245118108
Short name T447
Test name
Test status
Simulation time 67953425 ps
CPU time 0.9 seconds
Started Feb 29 01:36:31 PM PST 24
Finished Feb 29 01:36:32 PM PST 24
Peak memory 205204 kb
Host smart-7e65a5b4-584d-4398-8da6-172f17d128e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245118108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2245118108
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3928771975
Short name T782
Test name
Test status
Simulation time 375237979 ps
CPU time 3.19 seconds
Started Feb 29 01:36:28 PM PST 24
Finished Feb 29 01:36:31 PM PST 24
Peak memory 235096 kb
Host smart-23c8c06a-7610-406c-9a7e-d85097515c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928771975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3928771975
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1717012966
Short name T975
Test name
Test status
Simulation time 23600640 ps
CPU time 0.67 seconds
Started Feb 29 01:36:43 PM PST 24
Finished Feb 29 01:36:44 PM PST 24
Peak memory 204228 kb
Host smart-a9122169-83b6-439f-9d41-48b20c2697b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717012966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
717012966
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.298023840
Short name T700
Test name
Test status
Simulation time 1749833296 ps
CPU time 5.94 seconds
Started Feb 29 01:36:46 PM PST 24
Finished Feb 29 01:36:52 PM PST 24
Peak memory 224256 kb
Host smart-735790f6-07d2-446e-934e-7d0fe1fdf8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298023840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.298023840
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3712659584
Short name T581
Test name
Test status
Simulation time 15744192 ps
CPU time 0.76 seconds
Started Feb 29 01:36:33 PM PST 24
Finished Feb 29 01:36:34 PM PST 24
Peak memory 204924 kb
Host smart-8dafab35-c1f2-4d6c-93d6-206f8c69cc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712659584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3712659584
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.751524269
Short name T439
Test name
Test status
Simulation time 10201418132 ps
CPU time 58.12 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:37:44 PM PST 24
Peak memory 238772 kb
Host smart-9cc3c1fe-9f02-4254-a9e4-434d573cb968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751524269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.751524269
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2763886720
Short name T644
Test name
Test status
Simulation time 21958604299 ps
CPU time 122.7 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:38:47 PM PST 24
Peak memory 232704 kb
Host smart-6c2eaaa6-216a-418d-bd3f-bad8f8b7e22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763886720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2763886720
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1242103159
Short name T241
Test name
Test status
Simulation time 160210969721 ps
CPU time 227.57 seconds
Started Feb 29 01:36:48 PM PST 24
Finished Feb 29 01:40:36 PM PST 24
Peak memory 265600 kb
Host smart-94a68c55-f50f-4111-b9f1-993d79314dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242103159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1242103159
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3439650155
Short name T93
Test name
Test status
Simulation time 6705910453 ps
CPU time 9.89 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:54 PM PST 24
Peak memory 222968 kb
Host smart-803ce400-0522-4288-92af-c3a5f5d45ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439650155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3439650155
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2680027640
Short name T906
Test name
Test status
Simulation time 1141880956 ps
CPU time 5.8 seconds
Started Feb 29 01:36:47 PM PST 24
Finished Feb 29 01:36:53 PM PST 24
Peak memory 233168 kb
Host smart-3eee1547-f6c5-4514-9e97-2067d6bdbb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680027640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2680027640
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2438544767
Short name T659
Test name
Test status
Simulation time 418839919 ps
CPU time 3.75 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:48 PM PST 24
Peak memory 224224 kb
Host smart-8b916f90-ab24-4ecd-abea-ab809da542cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438544767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2438544767
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.7032652
Short name T937
Test name
Test status
Simulation time 49821459 ps
CPU time 1.12 seconds
Started Feb 29 01:36:34 PM PST 24
Finished Feb 29 01:36:35 PM PST 24
Peak memory 217188 kb
Host smart-5161996b-0b25-4726-9816-d873f0f93cbd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7032652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST
_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.spi_device_mem_parity.7032652
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.792270173
Short name T202
Test name
Test status
Simulation time 2153347602 ps
CPU time 6.34 seconds
Started Feb 29 01:36:43 PM PST 24
Finished Feb 29 01:36:50 PM PST 24
Peak memory 233520 kb
Host smart-397a1229-db42-462f-8af9-b6d37df8aee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792270173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
792270173
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2697497142
Short name T408
Test name
Test status
Simulation time 2436964589 ps
CPU time 14.92 seconds
Started Feb 29 01:36:43 PM PST 24
Finished Feb 29 01:36:58 PM PST 24
Peak memory 231564 kb
Host smart-68d147cf-ead8-4148-b05e-94b3ed78e706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697497142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2697497142
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.4181488773
Short name T731
Test name
Test status
Simulation time 15574438 ps
CPU time 0.78 seconds
Started Feb 29 01:36:30 PM PST 24
Finished Feb 29 01:36:31 PM PST 24
Peak memory 215976 kb
Host smart-c8497f4f-8e64-4181-99da-257de5326c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181488773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.4181488773
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.247888766
Short name T27
Test name
Test status
Simulation time 86911003671 ps
CPU time 284.21 seconds
Started Feb 29 01:36:41 PM PST 24
Finished Feb 29 01:41:26 PM PST 24
Peak memory 252840 kb
Host smart-a85795d8-1f11-49f1-bb47-7666681adc8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247888766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.247888766
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3721782112
Short name T437
Test name
Test status
Simulation time 2469911229 ps
CPU time 35.09 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:37:21 PM PST 24
Peak memory 216180 kb
Host smart-31581487-ab36-46ac-9e33-e408886188f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721782112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3721782112
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1649904513
Short name T822
Test name
Test status
Simulation time 108494562459 ps
CPU time 17.63 seconds
Started Feb 29 01:36:34 PM PST 24
Finished Feb 29 01:36:52 PM PST 24
Peak memory 215604 kb
Host smart-5fad955d-0504-4c72-b125-4c8a5d48b4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649904513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1649904513
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2543268774
Short name T816
Test name
Test status
Simulation time 110465334 ps
CPU time 2.2 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:36:48 PM PST 24
Peak memory 216104 kb
Host smart-79678de9-854f-4ecb-9385-c75fd6502762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543268774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2543268774
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2728415526
Short name T643
Test name
Test status
Simulation time 16671248 ps
CPU time 0.73 seconds
Started Feb 29 01:36:42 PM PST 24
Finished Feb 29 01:36:43 PM PST 24
Peak memory 205196 kb
Host smart-e499ea20-28bd-433f-8820-5cec1355e4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728415526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2728415526
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3427906078
Short name T152
Test name
Test status
Simulation time 181383344 ps
CPU time 4.55 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:49 PM PST 24
Peak memory 237796 kb
Host smart-077912db-5325-4e60-ac5f-4e941fe4cf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427906078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3427906078
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2215705921
Short name T521
Test name
Test status
Simulation time 39873494 ps
CPU time 0.71 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:45 PM PST 24
Peak memory 204756 kb
Host smart-6c739215-2c45-45d4-814c-7c11c338b126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215705921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
215705921
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1004890208
Short name T635
Test name
Test status
Simulation time 420824583 ps
CPU time 6.04 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:51 PM PST 24
Peak memory 220232 kb
Host smart-5869236f-67bb-4024-8499-de727db0f69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004890208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1004890208
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1725146490
Short name T606
Test name
Test status
Simulation time 55202693 ps
CPU time 0.79 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:36:46 PM PST 24
Peak memory 204972 kb
Host smart-3ad73757-b436-4c79-8ced-b5ff8a67fb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725146490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1725146490
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2537082156
Short name T838
Test name
Test status
Simulation time 16674871186 ps
CPU time 67.45 seconds
Started Feb 29 01:36:43 PM PST 24
Finished Feb 29 01:37:51 PM PST 24
Peak memory 240804 kb
Host smart-8952f4ee-034a-4c8e-b70f-9cdca5febe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537082156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2537082156
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.553542251
Short name T163
Test name
Test status
Simulation time 101841957796 ps
CPU time 512.66 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:45:18 PM PST 24
Peak memory 250132 kb
Host smart-10299bed-a703-4f3d-bcf1-c67aea5f65dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553542251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.553542251
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2575397275
Short name T393
Test name
Test status
Simulation time 11903765037 ps
CPU time 16.9 seconds
Started Feb 29 01:36:47 PM PST 24
Finished Feb 29 01:37:04 PM PST 24
Peak memory 233196 kb
Host smart-b200db85-7a7d-476f-99c2-0dc9e89ae1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575397275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2575397275
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2028063025
Short name T42
Test name
Test status
Simulation time 4703797109 ps
CPU time 6.72 seconds
Started Feb 29 01:36:49 PM PST 24
Finished Feb 29 01:36:56 PM PST 24
Peak memory 234184 kb
Host smart-eb756b16-cc97-4651-9ba5-d02fcea96bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028063025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2028063025
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.71487299
Short name T171
Test name
Test status
Simulation time 122326553313 ps
CPU time 38.45 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:37:22 PM PST 24
Peak memory 216856 kb
Host smart-866c6bb3-f1de-43bd-81b5-2fb10f764100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71487299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.71487299
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2228277771
Short name T689
Test name
Test status
Simulation time 121436132 ps
CPU time 1.03 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:46 PM PST 24
Peak memory 216568 kb
Host smart-cf2aa1e8-44c1-4e03-91da-7aed1f0eb7d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228277771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2228277771
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1368319760
Short name T673
Test name
Test status
Simulation time 6159291376 ps
CPU time 8.94 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:53 PM PST 24
Peak memory 240644 kb
Host smart-ada6cc3d-9163-4580-9a46-3d87d67a886a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368319760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1368319760
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.667840797
Short name T429
Test name
Test status
Simulation time 288071447 ps
CPU time 2.88 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:47 PM PST 24
Peak memory 232448 kb
Host smart-209ffb02-9bd6-49d7-ba3c-4d490d35426a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667840797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.667840797
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.1069828535
Short name T327
Test name
Test status
Simulation time 16979165 ps
CPU time 0.73 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:36:46 PM PST 24
Peak memory 216036 kb
Host smart-9cbd0e2c-17c3-4b2f-b574-ce429af434db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069828535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1069828535
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3545077164
Short name T835
Test name
Test status
Simulation time 415631091 ps
CPU time 3.65 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:36:48 PM PST 24
Peak memory 218388 kb
Host smart-aa1848c4-9529-41a4-8607-6b157f89890f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3545077164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3545077164
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3217265510
Short name T694
Test name
Test status
Simulation time 1981423552 ps
CPU time 14.79 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:37:00 PM PST 24
Peak memory 216024 kb
Host smart-01f94d68-e1be-4a4a-a6f8-0c302794436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217265510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3217265510
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3424079784
Short name T368
Test name
Test status
Simulation time 110807732198 ps
CPU time 29.45 seconds
Started Feb 29 01:36:44 PM PST 24
Finished Feb 29 01:37:14 PM PST 24
Peak memory 216196 kb
Host smart-d825cf95-aef4-434f-8872-43191fa831a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424079784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3424079784
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3475574028
Short name T865
Test name
Test status
Simulation time 232203461 ps
CPU time 1.63 seconds
Started Feb 29 01:36:46 PM PST 24
Finished Feb 29 01:36:48 PM PST 24
Peak memory 216080 kb
Host smart-48f85a25-99c0-429e-bbc0-7d7b70e00e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475574028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3475574028
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.805654418
Short name T560
Test name
Test status
Simulation time 116860436 ps
CPU time 1.09 seconds
Started Feb 29 01:36:47 PM PST 24
Finished Feb 29 01:36:48 PM PST 24
Peak memory 206360 kb
Host smart-b3e82c1c-1ad4-44f5-bda8-3f436361a0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805654418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.805654418
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3338646096
Short name T190
Test name
Test status
Simulation time 1962025519 ps
CPU time 7.19 seconds
Started Feb 29 01:36:45 PM PST 24
Finished Feb 29 01:36:53 PM PST 24
Peak memory 233840 kb
Host smart-84415008-b41c-4f0c-bec9-1f4a93906cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338646096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3338646096
Directory /workspace/9.spi_device_upload/latest
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