Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	8718497	1			T1	1		T2	1		T3	1
all_values[1]	8718497	1			T1	1		T2	1		T3	1
all_values[2]	8718497	1			T1	1		T2	1		T3	1
all_values[3]	8718497	1			T1	1		T2	1		T3	1
all_values[4]	8718497	1			T1	1		T2	1		T3	1
all_values[5]	8718497	1			T1	1		T2	1		T3	1
all_values[6]	8718497	1			T1	1		T2	1		T3	1
all_values[7]	8718497	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68371257

1

T1

8

T2

8

T3

8

auto[1]

1376719

1

T53

40

T72

347957

T73

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69658539

1

T1

8

T2

8

T3

8

auto[1]

89437

1

T11

33

T14

1

T21

452

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	8635943	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	51139	1			T11	11		T21	275		T23	206
all_values[0]	auto[1]	auto[0]	30516	1			T53	2		T75	3		T153	7
all_values[0]	auto[1]	auto[1]	899	1			T53	5		T73	2		T74	1
all_values[1]	auto[0]	auto[0]	8555473	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	24900	1			T11	11		T21	128		T23	67
all_values[1]	auto[1]	auto[0]	137428	1			T53	1		T72	86968		T73	4
all_values[1]	auto[1]	auto[1]	696	1			T53	1		T72	20		T73	4
all_values[2]	auto[0]	auto[0]	8671609	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	9451	1			T11	11		T21	49		T23	35
all_values[2]	auto[1]	auto[0]	37120	1			T53	7		T72	1		T75	4
all_values[2]	auto[1]	auto[1]	317	1			T53	1		T72	1		T73	5
all_values[3]	auto[0]	auto[0]	8367299	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	166	1			T53	2		T73	4		T153	1
all_values[3]	auto[1]	auto[0]	350841	1			T72	86985		T73	3		T74	46208
all_values[3]	auto[1]	auto[1]	191	1			T53	4		T72	3		T73	2
all_values[4]	auto[0]	auto[0]	8450207	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	200	1			T14	1		T53	3		T72	1
all_values[4]	auto[1]	auto[0]	267895	1			T53	1		T73	1		T74	46205
all_values[4]	auto[1]	auto[1]	195	1			T73	3		T74	3		T153	3
all_values[5]	auto[0]	auto[0]	8533927	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	373	1			T31	1		T33	3		T53	2
all_values[5]	auto[1]	auto[0]	184022	1			T53	6		T72	86987		T73	1
all_values[5]	auto[1]	auto[1]	175	1			T53	2		T72	2		T73	3
all_values[6]	auto[0]	auto[0]	8593415	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	172	1			T53	3		T73	2		T74	3
all_values[6]	auto[1]	auto[0]	124708	1			T53	3		T72	86985		T75	3
all_values[6]	auto[1]	auto[1]	202	1			T53	3		T72	4		T74	1
all_values[7]	auto[0]	auto[0]	8476815	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	168	1			T53	1		T73	3		T74	2
all_values[7]	auto[1]	auto[0]	241321	1			T53	4		T72	1		T73	1
all_values[7]	auto[1]	auto[1]	193	1			T73	4		T75	1		T153	2