Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	45296	1			T1	30		T10	20		T13	14
auto[SpiFlashAddrCfg]	10175	1			T9	8		T13	8		T11	21
auto[SpiFlashAddr3b]	12400	1			T5	2		T9	8		T15	2
auto[SpiFlashAddr4b]	10271	1			T5	6		T9	2		T13	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44222

1

T1

30

T9

18

T10

20

auto[1]

33920

1

T5

8

T11

30

T17

28

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42189

1

T1

30

T5

2

T9

8

auto[1]

35953

1

T5

6

T9

10

T15

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	51539	1			T1	30		T10	20		T13	10
values[1]	1563	1			T11	1		T21	5		T23	14
values[2]	1902	1			T9	6		T11	1		T17	2
values[3]	1941	1			T5	2		T9	8		T13	4
values[4]	1933	1			T17	6		T14	1		T21	6
values[5]	2040	1			T11	3		T17	8		T21	7
values[6]	1841	1			T11	5		T17	4		T21	9
values[7]	1951	1			T21	11		T23	14		T36	4
values[8]	13432	1			T5	6		T9	4		T15	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38253

1

T1

30

T5

8

T9

18

auto[1]

39889

1

T14

15

T23

711

T42

16

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

75120

1

T1

30

T5

8

T9

18

write

3022

1

T11

1

T21

17

T23

26

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

26687

1

T1

30

T5

8

T9

4

valids[0x1]

51455

1

T9

14

T15

2

T13

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	2175	1			T13	2		T17	2		T21	8
internal_process_ops[0x5a]	2096	1			T15	2		T11	2		T17	4
internal_process_ops[0x05]	26404	1			T13	2		T11	4		T21	45
internal_process_ops[0x35]	2205	1			T13	2		T21	9		T23	12
internal_process_ops[0x15]	2119	1			T13	2		T11	3		T21	12
internal_process_ops[0x03]	1447	1			T9	8		T11	3		T14	6
internal_process_ops[0x0b]	1383	1			T9	6		T11	1		T17	2
internal_process_ops[0x3b]	1476	1			T11	2		T16	6		T21	3
internal_process_ops[0x6b]	1502	1			T11	4		T14	1		T21	7
internal_process_ops[0xbb]	1354	1			T9	2		T13	2		T16	2
internal_process_ops[0xeb]	1441	1			T9	2		T11	2		T14	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76635

1

T1

30

T5

8

T9

18

auto[1]

1507

1

T11

1

T21

11

T23

12

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75364

1

T1

30

T5

8

T9

18

auto[1]

2778

1

T11

1

T21

11

T23

21

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12777

1

T1

30

T10

20

T13

14

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8143

1

T11

10

T17

2

T21

40

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2667

1

T9

8

T13

8

T11

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2287

1

T11

11

T17

10

T21

18

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3337

1

T9

8

T15

2

T13

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2732

1

T5

2

T11

7

T17

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2655

1

T9

2

T13

2

T11

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2262

1

T5

6

T11

2

T17

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T21

2

T35

2

T38

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

73

1

T21

3

T25

2

T26

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

70

1

T21

2

T40

2

T41

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

102

1

T21

1

T32

1

T37

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

137

1

T32

2

T34

2

T38

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

82

1

T21

3

T32

1

T35

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

82

1

T21

1

T38

3

T25

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

88

1

T39

1

T41

1

T166

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

90

1

T75

1

T167

2

T142

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

64

1

T11

1

T39

4

T41

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

59

1

T38

1

T39

1

T75

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

111

1

T21

2

T32

2

T39

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

93

1

T35

1

T39

3

T26

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

83

1

T32

2

T39

2

T40

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

63

1

T21

1

T35

1

T38

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

87

1

T21

2

T32

1

T38

5

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13608

1

T23

284

T32

163

T30

35

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

10003

1

T23

211

T32

124

T30

58

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2338

1

T14

7

T23

38

T42

11

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2093

1

T23

21

T32

23

T30

18

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2885

1

T14

2

T23

36

T45

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2698

1

T23

29

T32

37

T30

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2425

1

T14

6

T23

37

T42

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2210

1

T23

29

T32

27

T30

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

89

1

T23

2

T32

2

T30

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

104

1

T23

2

T32

4

T52

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

111

1

T23

3

T32

2

T52

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

107

1

T32

4

T53

1

T26

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

102

1

T23

5

T32

1

T55

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

109

1

T23

3

T32

1

T55

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

106

1

T23

1

T32

1

T55

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

84

1

T32

2

T30

1

T53

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

104

1

T32

3

T30

1

T53

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

102

1

T32

2

T55

1

T26

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

119

1

T23

1

T52

1

T55

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

99

1

T23

2

T26

1

T168

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

87

1

T23

1

T169

2

T26

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

102

1

T23

1

T55

2

T169

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

94

1

T23

1

T32

3

T53

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T23

4

T32

2

T53

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	5143	1			T1	30		T10	20		T13	2
auto[0]	values[0]	valids[0x1]	19180	1			T13	8		T11	14		T17	2
auto[0]	values[1]	valids[0x1]	755	1			T11	1		T21	5		T32	4
auto[0]	values[2]	valids[0x0]	645	1			T21	2		T32	13		T35	4
auto[0]	values[2]	valids[0x1]	328	1			T9	6		T11	1		T17	2
auto[0]	values[3]	valids[0x0]	667	1			T5	2		T11	3		T16	6
auto[0]	values[3]	valids[0x1]	384	1			T9	8		T13	4		T21	2
auto[0]	values[4]	valids[0x0]	669	1			T17	6		T21	5		T32	5
auto[0]	values[4]	valids[0x1]	381	1			T21	1		T32	1		T69	2
auto[0]	values[5]	valids[0x0]	716	1			T17	8		T21	5		T44	8
auto[0]	values[5]	valids[0x1]	335	1			T11	3		T21	2		T32	6
auto[0]	values[6]	valids[0x0]	611	1			T11	4		T17	4		T21	5
auto[0]	values[6]	valids[0x1]	369	1			T11	1		T21	4		T32	2
auto[0]	values[7]	valids[0x0]	644	1			T21	9		T36	4		T32	4
auto[0]	values[7]	valids[0x1]	374	1			T21	2		T32	1		T35	2
auto[0]	values[8]	valids[0x0]	4437	1			T5	6		T9	4		T13	2
auto[0]	values[8]	valids[0x1]	2615	1			T15	2		T13	10		T11	12
auto[1]	values[0]	valids[0x0]	6001	1			T23	98		T32	100		T30	28
auto[1]	values[0]	valids[0x1]	21215	1			T14	7		T23	457		T32	240
auto[1]	values[1]	valids[0x1]	808	1			T23	14		T32	15		T30	4
auto[1]	values[2]	valids[0x0]	553	1			T23	6		T32	5		T30	7
auto[1]	values[2]	valids[0x1]	376	1			T23	2		T32	2		T30	7
auto[1]	values[3]	valids[0x0]	526	1			T23	5		T32	8		T52	4
auto[1]	values[3]	valids[0x1]	364	1			T23	6		T32	6		T30	4
auto[1]	values[4]	valids[0x0]	539	1			T14	1		T23	7		T32	5
auto[1]	values[4]	valids[0x1]	344	1			T23	2		T32	4		T30	3
auto[1]	values[5]	valids[0x0]	611	1			T23	6		T32	13		T30	4
auto[1]	values[5]	valids[0x1]	378	1			T23	4		T32	11		T52	3
auto[1]	values[6]	valids[0x0]	517	1			T23	10		T32	6		T30	7
auto[1]	values[6]	valids[0x1]	344	1			T23	2		T32	8		T30	2
auto[1]	values[7]	valids[0x0]	594	1			T23	8		T32	4		T52	10
auto[1]	values[7]	valids[0x1]	339	1			T23	6		T32	3		T30	6
auto[1]	values[8]	valids[0x0]	3814	1			T14	1		T23	51		T42	10
auto[1]	values[8]	valids[0x1]	2566	1			T14	6		T23	27		T42	6