Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21883

1

T1

14

T3

4

T5

1

auto[1]

26660

1

T11

3

T21

49

T23

352

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18271

1

T1

14

T3

4

T5

1

auto[1]

30272

1

T11

7

T21

66

T23

377

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7836	1			T1	1		T3	1		T5	1
auto[524288:1048575]	5709	1			T11	5		T14	2		T21	17
auto[1048576:1572863]	5934	1			T1	2		T9	7		T10	1
auto[1572864:2097151]	5550	1			T9	3		T10	3		T11	2
auto[2097152:2621439]	6219	1			T1	2		T9	3		T10	1
auto[2621440:3145727]	5705	1			T3	1		T16	2		T14	2
auto[3145728:3670015]	5426	1			T1	7		T15	1		T16	1
auto[3670016:4194303]	6164	1			T1	2		T3	2		T9	6

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47567

1

T1

14

T3

4

T5

1

auto[1]

976

1

T23

13

T32

5

T52

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39232

1

T1

14

T3

4

T5

1

auto[1]

9311

1

T10

8

T11

1

T21

21

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	2028	1			T1	1		T3	1		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	854	1			T21	3		T23	4		T43	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1478	1			T11	3		T14	2		T21	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	631	1			T11	2		T21	2		T23	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1545	1			T1	2		T9	7		T10	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	609	1			T21	1		T23	5		T32	10
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1551	1			T9	3		T10	2		T11	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	582	1			T21	2		T23	4		T32	6
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1488	1			T1	2		T9	3		T11	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	602	1			T21	1		T23	2		T32	10
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1591	1			T3	1		T16	2		T14	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	594	1			T21	6		T23	2		T32	9
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1427	1			T1	7		T15	1		T16	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	630	1			T21	5		T23	6		T32	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1544	1			T1	2		T3	2		T9	6
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	552	1			T11	3		T21	6		T23	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	437	1			T11	1		T23	1		T32	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	223	1			T32	1		T53	2		T55	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	334	1			T21	4		T23	4		T32	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	144	1			T21	1		T23	2		T32	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	366	1			T21	1		T55	8		T38	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	144	1			T30	1		T52	2		T53	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	359	1			T10	1		T21	2		T32	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	157	1			T23	2		T32	3		T52	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	328	1			T10	1		T23	4		T32	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	174	1			T23	3		T32	4		T52	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	343	1			T23	4		T32	2		T53	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	167	1			T23	5		T32	1		T35	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	298	1			T21	2		T23	9		T32	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	168	1			T21	1		T23	6		T32	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	376	1			T10	6		T21	2		T23	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	159	1			T23	1		T26	2		T40	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	357	1			T21	1		T23	4		T32	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3298	1			T21	8		T23	72		T32	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	275	1			T21	1		T23	2		T32	5
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2222	1			T21	1		T23	18		T32	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	284	1			T21	1		T23	3		T32	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2439	1			T21	7		T23	41		T32	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	244	1			T23	3		T32	3		T53	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2005	1			T23	69		T32	7		T53	80
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	264	1			T23	2		T32	5		T53	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2592	1			T23	33		T32	19		T53	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	276	1			T21	2		T32	5		T35	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2208	1			T21	7		T32	8		T35	89
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	258	1			T23	2		T32	3		T53	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2133	1			T23	27		T32	9		T53	81
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	274	1			T11	1		T21	3		T23	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2397	1			T11	2		T21	10		T23	8
auto[1]	auto[1]	auto[0:524287]	auto[0]	78	1			T55	1		T73	1		T141	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	561	1			T55	1		T73	1		T141	5
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	62	1			T21	2		T23	1		T53	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	563	1			T21	2		T23	22		T53	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	63	1			T55	1		T168	1		T47	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	484	1			T55	1		T168	16		T47	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	78	1			T21	1		T32	1		T30	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	574	1			T21	3		T32	1		T30	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	62	1			T23	1		T32	2		T39	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	709	1			T23	12		T32	6		T39	9
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	59	1			T23	2		T32	1		T35	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	467	1			T23	29		T32	4		T35	121
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	66	1			T32	1		T52	2		T26	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	446	1			T32	2		T52	47		T26	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	78	1			T40	3		T73	1		T141	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	784	1			T40	31		T73	1		T141	8

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	17320	1			T1	14		T3	4		T5	1
auto[0]	auto[0]	auto[1]	386	1			T23	8		T53	6		T34	1
auto[0]	auto[1]	auto[0]	4089	1			T10	8		T11	1		T21	13
auto[0]	auto[1]	auto[1]	88	1			T23	2		T168	1		T92	2
auto[1]	auto[0]	auto[0]	21121	1			T11	3		T21	41		T23	282
auto[1]	auto[0]	auto[1]	405	1			T23	3		T32	4		T53	3
auto[1]	auto[1]	auto[0]	5037	1			T21	8		T23	67		T32	17
auto[1]	auto[1]	auto[1]	97	1			T32	1		T52	2		T40	2