Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22167

1

T1

30

T9

18

T10

20

auto[1]

16086

1

T5

8

T11

30

T17

28

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4540	1			T11	20		T21	24		T138	4
values[1]	4799	1			T1	30		T15	2		T16	8
values[2]	4950	1			T21	28		T43	4		T44	14
values[3]	4268	1			T5	8		T17	28		T32	46
values[4]	4690	1			T11	20		T21	51		T32	64
values[5]	4455	1			T13	26		T11	22		T36	16
values[6]	4990	1			T9	18		T21	26		T32	52
values[7]	5561	1			T10	20		T21	63		T32	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4903	1			T10	20		T16	8		T32	63
values[1]	4524	1			T11	22		T21	30		T32	20
values[2]	4837	1			T21	86		T36	16		T32	40
values[3]	5205	1			T32	26		T162	2		T69	65
values[4]	4356	1			T1	30		T9	18		T11	40
values[5]	4507	1			T5	8		T17	28		T21	23
values[6]	4232	1			T21	72		T32	43		T160	20
values[7]	5689	1			T15	2		T13	26		T21	26

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	509	1			T138	4		T183	20		T178	14
auto[0]	values[0]	values[1]	313	1			T38	10		T39	13		T40	44
auto[0]	values[0]	values[2]	240	1			T180	7		T181	35		T212	10
auto[0]	values[0]	values[3]	408	1			T162	2		T166	12		T213	20
auto[0]	values[0]	values[4]	337	1			T11	12		T39	11		T166	16
auto[0]	values[0]	values[5]	330	1			T38	15		T40	13		T75	8
auto[0]	values[0]	values[6]	304	1			T21	8		T38	12		T26	9
auto[0]	values[0]	values[7]	242	1			T139	2		T38	19		T72	18
auto[0]	values[1]	values[0]	247	1			T16	8		T32	13		T26	25
auto[0]	values[1]	values[1]	353	1			T191	22		T188	11		T183	24
auto[0]	values[1]	values[2]	344	1			T21	32		T140	10		T38	9
auto[0]	values[1]	values[3]	356	1			T35	15		T214	96		T212	60
auto[0]	values[1]	values[4]	402	1			T1	30		T40	6		T142	9
auto[0]	values[1]	values[5]	340	1			T166	8		T89	56		T154	10
auto[0]	values[1]	values[6]	333	1			T21	15		T188	14		T142	36
auto[0]	values[1]	values[7]	373	1			T15	2		T142	39		T83	28
auto[0]	values[2]	values[0]	379	1			T35	19		T38	11		T25	9
auto[0]	values[2]	values[1]	313	1			T39	6		T182	26		T26	10
auto[0]	values[2]	values[2]	618	1			T32	16		T215	12		T188	28
auto[0]	values[2]	values[3]	339	1			T39	33		T178	9		T87	15
auto[0]	values[2]	values[4]	279	1			T43	4		T44	14		T124	24
auto[0]	values[2]	values[5]	306	1			T39	8		T166	14		T179	13
auto[0]	values[2]	values[6]	303	1			T21	13		T142	25		T97	9
auto[0]	values[2]	values[7]	419	1			T39	12		T142	44		T216	14
auto[0]	values[3]	values[0]	327	1			T183	52		T193	12		T154	25
auto[0]	values[3]	values[1]	309	1			T38	20		T41	27		T166	26
auto[0]	values[3]	values[2]	239	1			T39	11		T72	14		T166	12
auto[0]	values[3]	values[3]	340	1			T32	12		T166	14		T180	20
auto[0]	values[3]	values[4]	251	1			T26	17		T142	8		T178	12
auto[0]	values[3]	values[5]	347	1			T40	12		T41	9		T217	12
auto[0]	values[3]	values[6]	219	1			T39	12		T26	16		T166	7
auto[0]	values[3]	values[7]	316	1			T32	11		T35	10		T25	7
auto[0]	values[4]	values[0]	481	1			T32	16		T101	22		T34	106
auto[0]	values[4]	values[1]	356	1			T21	25		T32	10		T26	9
auto[0]	values[4]	values[2]	275	1			T188	14		T87	13		T218	10
auto[0]	values[4]	values[3]	315	1			T40	12		T219	2		T75	13
auto[0]	values[4]	values[4]	236	1			T11	6		T21	12		T40	43
auto[0]	values[4]	values[5]	269	1			T32	9		T35	17		T41	6
auto[0]	values[4]	values[6]	257	1			T160	20		T35	10		T67	2
auto[0]	values[4]	values[7]	396	1			T35	14		T39	24		T142	11
auto[0]	values[5]	values[0]	317	1			T38	9		T75	13		T220	2
auto[0]	values[5]	values[1]	368	1			T11	14		T166	9		T142	30
auto[0]	values[5]	values[2]	274	1			T36	16		T41	10		T75	39
auto[0]	values[5]	values[3]	281	1			T69	65		T38	8		T178	11
auto[0]	values[5]	values[4]	288	1			T221	10		T39	5		T25	15
auto[0]	values[5]	values[5]	353	1			T125	14		T38	16		T142	97
auto[0]	values[5]	values[6]	403	1			T32	22		T26	11		T41	47
auto[0]	values[5]	values[7]	373	1			T13	26		T38	15		T66	28
auto[0]	values[6]	values[0]	457	1			T40	14		T41	19		T179	9
auto[0]	values[6]	values[1]	230	1			T222	14		T166	15		T223	12
auto[0]	values[6]	values[2]	281	1			T32	8		T100	26		T35	14
auto[0]	values[6]	values[3]	353	1			T41	9		T167	16		T189	20
auto[0]	values[6]	values[4]	389	1			T9	18		T224	28		T225	16
auto[0]	values[6]	values[5]	209	1			T32	24		T183	34		T226	10
auto[0]	values[6]	values[6]	497	1			T227	2		T166	103		T75	7
auto[0]	values[6]	values[7]	413	1			T21	16		T40	12		T41	6
auto[0]	values[7]	values[0]	349	1			T10	20		T32	9		T196	14
auto[0]	values[7]	values[1]	398	1			T40	13		T41	14		T75	14
auto[0]	values[7]	values[2]	456	1			T21	12		T40	14		T41	19
auto[0]	values[7]	values[3]	698	1			T40	8		T228	14		T75	11
auto[0]	values[7]	values[4]	250	1			T21	11		T40	11		T41	25
auto[0]	values[7]	values[5]	375	1			T21	17		T41	12		T166	79
auto[0]	values[7]	values[6]	282	1			T26	10		T229	4		T178	13
auto[0]	values[7]	values[7]	553	1			T35	75		T230	6		T166	75
auto[1]	values[0]	values[0]	230	1			T183	8		T178	6		T154	6
auto[1]	values[0]	values[1]	154	1			T38	26		T39	7		T40	6
auto[1]	values[0]	values[2]	192	1			T180	13		T181	37		T212	10
auto[1]	values[0]	values[3]	324	1			T166	48		T142	126		T193	9
auto[1]	values[0]	values[4]	212	1			T11	8		T39	12		T166	4
auto[1]	values[0]	values[5]	221	1			T38	5		T40	7		T75	12
auto[1]	values[0]	values[6]	251	1			T21	16		T38	8		T26	12
auto[1]	values[0]	values[7]	273	1			T38	9		T72	3		T228	14
auto[1]	values[1]	values[0]	150	1			T32	7		T26	15		T179	8
auto[1]	values[1]	values[1]	258	1			T188	38		T183	20		T87	16
auto[1]	values[1]	values[2]	278	1			T21	34		T38	11		T231	11
auto[1]	values[1]	values[3]	371	1			T35	126		T212	25		T187	9
auto[1]	values[1]	values[4]	280	1			T40	16		T142	11		T181	12
auto[1]	values[1]	values[5]	206	1			T46	2		T166	71		T232	24
auto[1]	values[1]	values[6]	132	1			T21	5		T188	6		T142	17
auto[1]	values[1]	values[7]	376	1			T142	55		T193	8		T233	17
auto[1]	values[2]	values[0]	237	1			T35	11		T38	9		T25	19
auto[1]	values[2]	values[1]	221	1			T39	14		T26	10		T166	10
auto[1]	values[2]	values[2]	207	1			T32	4		T188	7		T180	9
auto[1]	values[2]	values[3]	165	1			T39	8		T178	27		T87	8
auto[1]	values[2]	values[4]	242	1			T75	6		T142	10		T212	10
auto[1]	values[2]	values[5]	329	1			T39	12		T199	12		T166	42
auto[1]	values[2]	values[6]	157	1			T21	15		T142	10		T97	34
auto[1]	values[2]	values[7]	436	1			T39	19		T142	31		T180	25
auto[1]	values[3]	values[0]	263	1			T183	9		T193	93		T154	19
auto[1]	values[3]	values[1]	246	1			T38	43		T41	33		T166	14
auto[1]	values[3]	values[2]	254	1			T39	11		T72	6		T166	8
auto[1]	values[3]	values[3]	168	1			T32	14		T166	6		T180	12
auto[1]	values[3]	values[4]	239	1			T26	3		T142	12		T178	8
auto[1]	values[3]	values[5]	214	1			T5	8		T17	28		T40	8
auto[1]	values[3]	values[6]	196	1			T39	8		T26	4		T166	80
auto[1]	values[3]	values[7]	340	1			T32	9		T35	10		T25	15
auto[1]	values[4]	values[0]	201	1			T32	4		T35	16		T39	11
auto[1]	values[4]	values[1]	232	1			T21	5		T32	10		T26	13
auto[1]	values[4]	values[2]	264	1			T188	6		T87	7		T234	10
auto[1]	values[4]	values[3]	410	1			T37	20		T40	8		T75	21
auto[1]	values[4]	values[4]	265	1			T11	14		T21	9		T40	8
auto[1]	values[4]	values[5]	298	1			T32	15		T35	64		T41	16
auto[1]	values[4]	values[6]	234	1			T35	10		T40	54		T87	6
auto[1]	values[4]	values[7]	201	1			T35	6		T39	2		T142	26
auto[1]	values[5]	values[0]	181	1			T38	11		T75	7		T187	15
auto[1]	values[5]	values[1]	231	1			T11	8		T166	59		T142	14
auto[1]	values[5]	values[2]	285	1			T41	10		T75	9		T183	6
auto[1]	values[5]	values[3]	186	1			T38	12		T235	32		T178	17
auto[1]	values[5]	values[4]	238	1			T39	25		T25	14		T183	12
auto[1]	values[5]	values[5]	245	1			T38	19		T142	12		T178	8
auto[1]	values[5]	values[6]	215	1			T32	21		T26	9		T41	12
auto[1]	values[5]	values[7]	217	1			T38	5		T142	71		T178	26
auto[1]	values[6]	values[0]	283	1			T40	6		T41	12		T179	11
auto[1]	values[6]	values[1]	287	1			T166	42		T223	9		T233	12
auto[1]	values[6]	values[2]	287	1			T32	12		T35	39		T25	8
auto[1]	values[6]	values[3]	186	1			T41	11		T87	8		T187	7
auto[1]	values[6]	values[4]	218	1			T183	6		T180	41		T193	10
auto[1]	values[6]	values[5]	121	1			T32	8		T183	9		T233	10
auto[1]	values[6]	values[6]	266	1			T236	18		T166	14		T75	25
auto[1]	values[6]	values[7]	513	1			T21	10		T40	8		T41	55
auto[1]	values[7]	values[0]	292	1			T32	14		T196	6		T155	23
auto[1]	values[7]	values[1]	255	1			T40	19		T41	6		T75	6
auto[1]	values[7]	values[2]	343	1			T21	8		T40	6		T41	10
auto[1]	values[7]	values[3]	305	1			T40	13		T228	8		T75	10
auto[1]	values[7]	values[4]	230	1			T21	9		T40	10		T41	15
auto[1]	values[7]	values[5]	344	1			T21	6		T41	20		T166	52
auto[1]	values[7]	values[6]	183	1			T26	12		T178	7		T154	11
auto[1]	values[7]	values[7]	248	1			T35	12		T166	6		T142	12