Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	497	1			T9	4		T21	5		T36	10
auto[ReadAddrCrossIntoMailbox]	357	1			T9	2		T11	1		T16	2
auto[ReadAddrCrossOutOfMailbox]	436	1			T11	1		T16	4		T21	11
auto[ReadAddrCrossAllMailbox]	304	1			T11	2		T21	6		T44	2
auto[ReadAddrOutsideMailbox]	4329	1			T9	12		T13	2		T11	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2930

1

T9

9

T13

1

T11

10

auto[1]

2993

1

T9

9

T13

1

T11

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	1006	1			T9	8		T11	3		T21	12
read_ops[0x0b]	962	1			T9	6		T11	1		T17	2
read_ops[0x3b]	1017	1			T11	2		T16	6		T21	3
read_ops[0x6b]	1025	1			T11	4		T21	7		T44	2
read_ops[0xbb]	922	1			T9	2		T13	2		T16	2
read_ops[0xeb]	991	1			T9	2		T11	2		T21	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T9	2		T21	1		T36	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	50	1			T9	2		T21	1		T36	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T9	1		T11	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T9	1		T35	1		T166	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T25	1		T188	1		T142	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T21	2		T38	1		T39	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T21	2		T39	1		T26	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T38	1		T26	1		T142	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	385	1			T9	1		T11	2		T21	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	356	1			T9	1		T21	2		T160	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T36	1		T138	2		T222	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T36	1		T32	1		T138	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T35	2		T26	2		T40	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T32	1		T38	1		T39	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	46	1			T21	1		T35	3		T40	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T21	1		T32	1		T35	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T21	1		T40	1		T237	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T38	1		T26	1		T237	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	337	1			T9	3		T11	1		T17	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	364	1			T9	3		T17	1		T21	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T21	1		T124	1		T35	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T32	2		T124	1		T35	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T16	1		T35	1		T38	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T16	1		T26	1		T188	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T16	2		T139	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	42	1			T16	2		T32	1		T139	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T228	1		T142	1		T203	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T35	1		T40	1		T166	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	367	1			T11	2		T21	1		T44	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	384	1			T21	1		T44	4		T32	6
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	49	1			T36	2		T38	1		T39	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T36	2		T35	1		T38	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T21	1		T40	1		T166	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	38	1			T32	1		T142	2		T178	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	40	1			T11	1		T21	1		T38	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	45	1			T21	2		T25	1		T26	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	34	1			T11	2		T21	1		T44	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T44	1		T166	1		T142	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	336	1			T11	1		T21	2		T32	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	382	1			T32	7		T35	6		T38	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T21	1		T41	1		T166	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T21	1		T35	1		T39	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T32	1		T41	1		T75	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T21	1		T35	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T21	1		T41	1		T166	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T21	1		T41	2		T166	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T223	1		T238	1		T154	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T21	1		T41	1		T188	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	356	1			T9	1		T13	1		T16	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	327	1			T9	1		T13	1		T16	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T124	2		T35	1		T26	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T124	2		T38	1		T40	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T166	1		T75	2		T239	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T35	2		T40	1		T166	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T21	1		T41	1		T166	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	42	1			T21	1		T32	1		T39	4
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T21	1		T166	1		T188	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	32	1			T35	1		T40	1		T166	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	369	1			T9	1		T21	2		T32	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	366	1			T9	1		T11	2		T21	1