Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	8718497	1			T1	1		T2	1		T3	1
all_pins[1]	8718497	1			T1	1		T2	1		T3	1
all_pins[2]	8718497	1			T1	1		T2	1		T3	1
all_pins[3]	8718497	1			T1	1		T2	1		T3	1
all_pins[4]	8718497	1			T1	1		T2	1		T3	1
all_pins[5]	8718497	1			T1	1		T2	1		T3	1
all_pins[6]	8718497	1			T1	1		T2	1		T3	1
all_pins[7]	8718497	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	69613422	1			T1	8		T2	8		T3	8
values[0x1]	134554	1			T53	16		T72	88224		T73	23
transitions[0x0=>0x1]	128763	1			T53	14		T72	86996		T73	19
transitions[0x1=>0x0]	128775	1			T53	14		T72	86996		T73	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	8717552	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	945	1			T53	5		T73	2		T74	1
all_pins[0]	transitions[0x0=>0x1]	756	1			T53	4		T73	1		T74	1
all_pins[0]	transitions[0x1=>0x0]	537	1			T72	23		T73	3		T75	4
all_pins[1]	values[0x0]	8717771	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	726	1			T53	1		T72	23		T73	4
all_pins[1]	transitions[0x0=>0x1]	543	1			T53	1		T72	22		T73	2
all_pins[1]	transitions[0x1=>0x0]	142	1			T53	1		T73	3		T74	1
all_pins[2]	values[0x0]	8718172	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	325	1			T53	1		T72	1		T73	5
all_pins[2]	transitions[0x0=>0x1]	285	1			T53	1		T73	5		T74	1
all_pins[2]	transitions[0x1=>0x0]	151	1			T53	4		T72	2		T73	2
all_pins[3]	values[0x0]	8718306	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	191	1			T53	4		T72	3		T73	2
all_pins[3]	transitions[0x0=>0x1]	148	1			T53	4		T72	3		T73	2
all_pins[3]	transitions[0x1=>0x0]	152	1			T73	3		T74	3		T153	2
all_pins[4]	values[0x0]	8718302	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	195	1			T73	3		T74	3		T153	3
all_pins[4]	transitions[0x0=>0x1]	154	1			T73	2		T74	3		T153	2
all_pins[4]	transitions[0x1=>0x0]	7425	1			T53	2		T72	1236		T73	2
all_pins[5]	values[0x0]	8711031	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	7466	1			T53	2		T72	1236		T73	3
all_pins[5]	transitions[0x0=>0x1]	2273	1			T53	1		T72	10		T73	3
all_pins[5]	transitions[0x1=>0x0]	119320	1			T53	2		T72	85735		T74	1
all_pins[6]	values[0x0]	8593984	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	124513	1			T53	3		T72	86961		T74	1
all_pins[6]	transitions[0x0=>0x1]	124469	1			T53	3		T72	86961		T74	1
all_pins[6]	transitions[0x1=>0x0]	149	1			T73	4		T75	1		T153	2
all_pins[7]	values[0x0]	8718304	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	193	1			T73	4		T75	1		T153	2
all_pins[7]	transitions[0x0=>0x1]	135	1			T73	4		T75	1		T153	2
all_pins[7]	transitions[0x1=>0x0]	899	1			T53	5		T73	2		T74	1