Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4267	1			T15	2		T21	20		T44	14
values[1]	5172	1			T21	46		T46	2		T100	26
values[2]	4971	1			T9	18		T13	26		T11	20
values[3]	4467	1			T43	4		T32	75		T138	4
values[4]	5171	1			T1	30		T16	8		T21	72
values[5]	4488	1			T11	22		T21	48		T32	20
values[6]	4670	1			T10	20		T11	20		T17	28
values[7]	5047	1			T5	8		T21	44		T32	90

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4396	1			T15	2		T16	8		T44	14
values[1]	4202	1			T32	46		T140	10		T35	88
values[2]	5067	1			T1	30		T21	104		T36	16
values[3]	5806	1			T13	26		T11	20		T21	65
values[4]	4547	1			T11	20		T21	20		T46	2
values[5]	4740	1			T11	22		T21	41		T101	22
values[6]	4991	1			T5	8		T9	18		T32	64
values[7]	4504	1			T10	20		T17	28		T21	48

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37563

1

T1

30

T5

8

T9

18

auto[1]

690

1

T11

1

T21

11

T32

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	424	1			T15	2		T44	14		T32	22
auto[0]	values[0]	values[1]	347	1			T41	20		T75	20		T180	20
auto[0]	values[0]	values[2]	950	1			T36	16		T227	2		T35	20
auto[0]	values[0]	values[3]	541	1			T188	20		T223	21		T84	18
auto[0]	values[0]	values[4]	473	1			T66	28		T26	20		T40	70
auto[0]	values[0]	values[5]	536	1			T224	28		T199	8		T166	77
auto[0]	values[0]	values[6]	262	1			T178	20		T181	28		T154	42
auto[0]	values[0]	values[7]	661	1			T21	19		T38	20		T41	30
auto[0]	values[1]	values[0]	690	1			T182	26		T26	20		T166	50
auto[0]	values[1]	values[1]	737	1			T39	40		T166	40		T188	20
auto[0]	values[1]	values[2]	601	1			T21	26		T100	26		T35	61
auto[0]	values[1]	values[3]	757	1			T34	106		T183	36		T240	26
auto[0]	values[1]	values[4]	483	1			T46	2		T221	10		T38	33
auto[0]	values[1]	values[5]	619	1			T21	19		T41	32		T213	20
auto[0]	values[1]	values[6]	729	1			T180	46		T193	88		T181	25
auto[0]	values[1]	values[7]	478	1			T38	20		T191	22		T178	23
auto[0]	values[2]	values[0]	652	1			T25	27		T26	20		T40	22
auto[0]	values[2]	values[1]	628	1			T39	24		T241	20		T188	46
auto[0]	values[2]	values[2]	497	1			T125	14		T40	20		T75	20
auto[0]	values[2]	values[3]	742	1			T13	26		T166	80		T188	18
auto[0]	values[2]	values[4]	674	1			T11	20		T41	39		T235	32
auto[0]	values[2]	values[5]	500	1			T162	2		T38	27		T222	14
auto[0]	values[2]	values[6]	715	1			T9	18		T41	19		T142	74
auto[0]	values[2]	values[7]	478	1			T21	28		T26	21		T41	20
auto[0]	values[3]	values[0]	420	1			T38	36		T40	20		T142	43
auto[0]	values[3]	values[1]	301	1			T140	10		T35	68		T25	19
auto[0]	values[3]	values[2]	474	1			T32	42		T242	14		T180	51
auto[0]	values[3]	values[3]	760	1			T138	4		T219	2		T75	47
auto[0]	values[3]	values[4]	467	1			T32	31		T166	84		T167	16
auto[0]	values[3]	values[5]	614	1			T101	22		T40	68		T243	12
auto[0]	values[3]	values[6]	809	1			T124	24		T35	30		T38	20
auto[0]	values[3]	values[7]	555	1			T43	4		T40	41		T188	34
auto[0]	values[4]	values[0]	350	1			T16	8		T26	22		T87	20
auto[0]	values[4]	values[1]	387	1			T32	20		T35	20		T39	18
auto[0]	values[4]	values[2]	731	1			T1	30		T21	25		T39	28
auto[0]	values[4]	values[3]	859	1			T21	21		T139	2		T38	20
auto[0]	values[4]	values[4]	687	1			T35	20		T142	21		T183	43
auto[0]	values[4]	values[5]	691	1			T21	20		T75	20		T142	37
auto[0]	values[4]	values[6]	726	1			T39	31		T40	29		T142	124
auto[0]	values[4]	values[7]	645	1			T69	65		T183	24		T244	43
auto[0]	values[5]	values[0]	402	1			T75	25		T188	20		T142	18
auto[0]	values[5]	values[1]	477	1			T26	21		T217	12		T142	19
auto[0]	values[5]	values[2]	477	1			T21	47		T67	2		T183	21
auto[0]	values[5]	values[3]	751	1			T35	140		T39	40		T142	19
auto[0]	values[5]	values[4]	596	1			T245	14		T142	61		T183	52
auto[0]	values[5]	values[5]	601	1			T11	21		T35	52		T38	20
auto[0]	values[5]	values[6]	684	1			T32	19		T35	107		T25	29
auto[0]	values[5]	values[7]	403	1			T41	18		T87	20		T196	21
auto[0]	values[6]	values[0]	735	1			T32	20		T228	21		T166	97
auto[0]	values[6]	values[1]	699	1			T166	20		T188	30		T87	20
auto[0]	values[6]	values[2]	600	1			T32	20		T160	20		T38	20
auto[0]	values[6]	values[3]	542	1			T11	20		T35	20		T41	58
auto[0]	values[6]	values[4]	654	1			T21	20		T166	20		T142	20
auto[0]	values[6]	values[5]	628	1			T87	25		T246	8		T187	27
auto[0]	values[6]	values[6]	403	1			T38	20		T39	21		T215	12
auto[0]	values[6]	values[7]	308	1			T10	20		T17	28		T25	23
auto[0]	values[7]	values[0]	653	1			T26	20		T166	87		T75	31
auto[0]	values[7]	values[1]	560	1			T32	25		T142	38		T178	19
auto[0]	values[7]	values[2]	642	1			T38	61		T230	6		T41	20
auto[0]	values[7]	values[3]	740	1			T21	42		T26	19		T41	20
auto[0]	values[7]	values[4]	416	1			T32	20		T37	16		T26	20
auto[0]	values[7]	values[5]	449	1			T41	38		T247	30		T180	50
auto[0]	values[7]	values[6]	582	1			T5	8		T32	42		T40	20
auto[0]	values[7]	values[7]	911	1			T40	63		T166	81		T75	20
auto[1]	values[0]	values[0]	5	1			T32	1		T197	1		T248	2
auto[1]	values[0]	values[1]	3	1			T154	1		T249	1		T250	1
auto[1]	values[0]	values[2]	14	1			T142	3		T181	1		T251	2
auto[1]	values[0]	values[3]	10	1			T233	1		T197	2		T252	5
auto[1]	values[0]	values[4]	6	1			T26	2		T40	1		T231	2
auto[1]	values[0]	values[5]	13	1			T199	4		T187	5		T253	1
auto[1]	values[0]	values[6]	11	1			T181	1		T154	2		T254	1
auto[1]	values[0]	values[7]	11	1			T21	1		T41	1		T233	2
auto[1]	values[1]	values[0]	17	1			T183	2		T255	1		T248	1
auto[1]	values[1]	values[1]	5	1			T87	1		T208	1		T256	1
auto[1]	values[1]	values[2]	7	1			T57	3		T257	1		T258	1
auto[1]	values[1]	values[3]	10	1			T183	4		T197	2		T57	1
auto[1]	values[1]	values[4]	10	1			T38	2		T166	3		T259	2
auto[1]	values[1]	values[5]	14	1			T21	1		T142	1		T181	1
auto[1]	values[1]	values[6]	9	1			T180	1		T253	1		T208	2
auto[1]	values[1]	values[7]	6	1			T193	2		T260	2		T254	1
auto[1]	values[2]	values[0]	6	1			T25	1		T196	2		T59	1
auto[1]	values[2]	values[1]	10	1			T39	2		T188	3		T197	2
auto[1]	values[2]	values[2]	12	1			T261	8		T262	3		T263	1
auto[1]	values[2]	values[3]	17	1			T166	1		T188	2		T154	2
auto[1]	values[2]	values[4]	14	1			T41	1		T183	3		T178	2
auto[1]	values[2]	values[5]	10	1			T38	1		T260	3		T258	2
auto[1]	values[2]	values[6]	12	1			T41	1		T197	2		T260	4
auto[1]	values[2]	values[7]	4	1			T180	2		T257	1		T264	1
auto[1]	values[3]	values[0]	1	1			T265	1		-	-		-	-
auto[1]	values[3]	values[1]	8	1			T25	3		T205	2		T59	1
auto[1]	values[3]	values[2]	7	1			T32	1		T180	1		T238	1
auto[1]	values[3]	values[3]	8	1			T75	1		T179	1		T155	2
auto[1]	values[3]	values[4]	8	1			T32	1		T166	3		T266	3
auto[1]	values[3]	values[5]	15	1			T40	2		T255	2		T195	3
auto[1]	values[3]	values[6]	10	1			T154	1		T212	1		T196	2
auto[1]	values[3]	values[7]	10	1			T188	1		T154	3		T187	2
auto[1]	values[4]	values[0]	5	1			T267	4		T268	1		-	-
auto[1]	values[4]	values[1]	6	1			T39	2		T269	1		T270	3
auto[1]	values[4]	values[2]	17	1			T21	5		T39	2		T142	2
auto[1]	values[4]	values[3]	21	1			T183	1		T87	1		T181	1
auto[1]	values[4]	values[4]	18	1			T142	1		T183	3		T181	1
auto[1]	values[4]	values[5]	8	1			T21	1		T178	2		T212	1
auto[1]	values[4]	values[6]	16	1			T40	3		T142	5		T187	3
auto[1]	values[4]	values[7]	4	1			T183	1		T196	1		T271	2
auto[1]	values[5]	values[0]	21	1			T75	2		T142	2		T193	2
auto[1]	values[5]	values[1]	4	1			T26	1		T142	1		T268	2
auto[1]	values[5]	values[2]	9	1			T21	1		T183	2		T154	2
auto[1]	values[5]	values[3]	16	1			T35	1		T39	1		T142	1
auto[1]	values[5]	values[4]	5	1			T142	1		T183	1		T210	2
auto[1]	values[5]	values[5]	20	1			T11	1		T35	1		T41	1
auto[1]	values[5]	values[6]	9	1			T32	1		T166	2		T197	1
auto[1]	values[5]	values[7]	13	1			T41	2		T248	2		T272	3
auto[1]	values[6]	values[0]	5	1			T228	1		T179	1		T251	1
auto[1]	values[6]	values[1]	14	1			T188	2		T258	1		T198	3
auto[1]	values[6]	values[2]	20	1			T75	6		T57	2		T253	1
auto[1]	values[6]	values[3]	13	1			T41	3		T75	1		T183	1
auto[1]	values[6]	values[4]	19	1			T181	2		T233	2		T234	1
auto[1]	values[6]	values[5]	14	1			T246	2		T260	5		T57	1
auto[1]	values[6]	values[6]	9	1			T39	2		T87	2		T192	2
auto[1]	values[6]	values[7]	7	1			T233	2		T255	3		T273	2
auto[1]	values[7]	values[0]	10	1			T166	1		T75	1		T183	1
auto[1]	values[7]	values[1]	16	1			T32	1		T142	7		T178	1
auto[1]	values[7]	values[2]	9	1			T38	2		T166	2		T259	1
auto[1]	values[7]	values[3]	19	1			T21	2		T26	1		T190	8
auto[1]	values[7]	values[4]	17	1			T37	4		T142	2		T57	2
auto[1]	values[7]	values[5]	8	1			T41	1		T180	2		T154	2
auto[1]	values[7]	values[6]	5	1			T32	2		T40	1		T142	1
auto[1]	values[7]	values[7]	10	1			T40	1		T254	4		T257	4