Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2622

1

T4

8

T8

11

T18

11

auto[1]

2633

1

T4

4

T8

9

T18

18

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2916

1

T11

9

T21

10

T32

31

auto[1]

2339

1

T4

12

T8

20

T18

29

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4142

1

T4

12

T8

20

T18

29

auto[1]

1113

1

T11

1

T21

7

T32

14

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1037	1			T4	2		T8	3		T18	5
valid[1]	1050	1			T4	3		T8	4		T18	3
valid[2]	1076	1			T4	2		T8	3		T18	5
valid[3]	1009	1			T8	2		T18	10		T20	8
valid[4]	1083	1			T4	5		T8	8		T18	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	155	1			T29	1		T53	1		T38	4
auto[0]	auto[0]	valid[0]	auto[1]	238	1			T4	1		T8	1		T20	2
auto[0]	auto[0]	valid[1]	auto[0]	185	1			T21	1		T32	2		T29	1
auto[0]	auto[0]	valid[1]	auto[1]	230	1			T4	3		T8	3		T20	2
auto[0]	auto[0]	valid[2]	auto[0]	173	1			T11	1		T32	1		T29	1
auto[0]	auto[0]	valid[2]	auto[1]	242	1			T8	1		T18	3		T20	1
auto[0]	auto[0]	valid[3]	auto[0]	171	1			T21	1		T32	2		T33	1
auto[0]	auto[0]	valid[3]	auto[1]	226	1			T8	1		T18	3		T20	5
auto[0]	auto[0]	valid[4]	auto[0]	185	1			T11	1		T32	5		T29	3
auto[0]	auto[0]	valid[4]	auto[1]	245	1			T4	4		T8	5		T18	5
auto[0]	auto[1]	valid[0]	auto[0]	203	1			T11	1		T32	2		T29	1
auto[0]	auto[1]	valid[0]	auto[1]	229	1			T4	1		T8	2		T18	5
auto[0]	auto[1]	valid[1]	auto[0]	188	1			T11	1		T32	1		T29	2
auto[0]	auto[1]	valid[1]	auto[1]	214	1			T8	1		T18	3		T20	3
auto[0]	auto[1]	valid[2]	auto[0]	181	1			T11	2		T21	1		T32	1
auto[0]	auto[1]	valid[2]	auto[1]	246	1			T4	2		T8	2		T18	2
auto[0]	auto[1]	valid[3]	auto[0]	165	1			T11	1		T29	2		T55	1
auto[0]	auto[1]	valid[3]	auto[1]	229	1			T8	1		T18	7		T20	3
auto[0]	auto[1]	valid[4]	auto[0]	197	1			T11	1		T32	3		T30	2
auto[0]	auto[1]	valid[4]	auto[1]	240	1			T4	1		T8	3		T18	1
auto[1]	auto[0]	valid[0]	auto[0]	103	1			T11	1		T21	1		T32	1
auto[1]	auto[0]	valid[1]	auto[0]	118	1			T32	4		T29	1		T30	1
auto[1]	auto[0]	valid[2]	auto[0]	120	1			T29	1		T55	1		T39	1
auto[1]	auto[0]	valid[3]	auto[0]	113	1			T21	1		T32	1		T30	1
auto[1]	auto[0]	valid[4]	auto[0]	118	1			T30	1		T55	2		T39	3
auto[1]	auto[1]	valid[0]	auto[0]	109	1			T30	1		T39	3		T169	2
auto[1]	auto[1]	valid[1]	auto[0]	115	1			T21	2		T32	1		T38	1
auto[1]	auto[1]	valid[2]	auto[0]	114	1			T32	4		T29	2		T30	2
auto[1]	auto[1]	valid[3]	auto[0]	105	1			T21	1		T32	2		T55	3
auto[1]	auto[1]	valid[4]	auto[0]	98	1			T21	2		T32	1		T38	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal