Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74858

1

T11

335

T21

346

T31

11

auto[1]

24183

1

T4

12

T8

20

T18

449

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72021

1

T4

12

T8

20

T18

449

auto[1]

27020

1

T11

131

T21

148

T31

8

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	51076	1			T4	12		T8	20		T18	229
others[1]	8389	1			T18	35		T20	20		T11	35
others[2]	8208	1			T18	38		T20	25		T11	31
others[3]	9492	1			T18	38		T20	27		T11	36
interest[1]	5493	1			T18	25		T20	11		T11	26
interest[4]	33406	1			T4	12		T8	20		T18	145
interest[64]	16383	1			T18	84		T20	48		T11	61

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	24606	1			T11	113		T21	101		T32	258
auto[0]	auto[0]	others[1]	4074	1			T11	18		T21	15		T32	40
auto[0]	auto[0]	others[2]	3964	1			T11	10		T21	16		T32	43
auto[0]	auto[0]	others[3]	4533	1			T11	20		T21	18		T32	43
auto[0]	auto[0]	interest[1]	2665	1			T11	13		T21	8		T32	25
auto[0]	auto[0]	interest[4]	16031	1			T11	74		T21	67		T32	172
auto[0]	auto[0]	interest[64]	7996	1			T11	30		T21	40		T31	3
auto[0]	auto[1]	others[0]	12538	1			T4	12		T8	20		T18	229
auto[0]	auto[1]	others[1]	2080	1			T18	35		T20	20		T11	6
auto[0]	auto[1]	others[2]	1915	1			T18	38		T20	25		T11	7
auto[0]	auto[1]	others[3]	2351	1			T18	38		T20	27		T11	8
auto[0]	auto[1]	interest[1]	1358	1			T18	25		T20	11		T11	4
auto[0]	auto[1]	interest[4]	8300	1			T4	12		T8	20		T18	145
auto[0]	auto[1]	interest[64]	3941	1			T18	84		T20	48		T11	9
auto[1]	auto[0]	others[0]	13932	1			T11	67		T21	76		T31	5
auto[1]	auto[0]	others[1]	2235	1			T11	11		T21	17		T31	1
auto[1]	auto[0]	others[2]	2329	1			T11	14		T21	19		T32	29
auto[1]	auto[0]	others[3]	2608	1			T11	8		T21	13		T32	31
auto[1]	auto[0]	interest[1]	1470	1			T11	9		T21	7		T32	11
auto[1]	auto[0]	interest[4]	9075	1			T11	43		T21	52		T31	4
auto[1]	auto[0]	interest[64]	4446	1			T11	22		T21	16		T31	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal