Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	764	1			T53	10		T72	4		T73	10
all_values[1]	764	1			T53	10		T72	4		T73	10
all_values[2]	764	1			T53	10		T72	4		T73	10
all_values[3]	764	1			T53	10		T72	4		T73	10
all_values[4]	764	1			T53	10		T72	4		T73	10
all_values[5]	764	1			T53	10		T72	4		T73	10
all_values[6]	764	1			T53	10		T72	4		T73	10
all_values[7]	764	1			T53	10		T72	4		T73	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3173

1

T53

53

T72

19

T73

52

auto[1]

2939

1

T53

27

T72

13

T73

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2452

1

T53

28

T72

13

T73

23

auto[1]

3660

1

T53

52

T72

19

T73

57

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3482

1

T53

40

T72

20

T73

36

auto[1]

2630

1

T53

40

T72

12

T73

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	167	1			T72	1		T73	4		T74	1
all_values[0]	auto[0]	auto[0]	auto[1]	71	1			T53	2		T72	2		T153	2
all_values[0]	auto[0]	auto[1]	auto[0]	125	1			T74	1		T75	1		T153	3
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T53	1		T163	1		T164	2
all_values[0]	auto[1]	auto[0]	auto[1]	177	1			T53	5		T72	1		T73	5
all_values[0]	auto[1]	auto[1]	auto[1]	146	1			T53	2		T73	1		T75	1
all_values[1]	auto[0]	auto[0]	auto[0]	146	1			T74	2		T75	2		T165	3
all_values[1]	auto[0]	auto[0]	auto[1]	70	1			T53	3		T165	1		T163	5
all_values[1]	auto[0]	auto[1]	auto[0]	143	1			T73	2		T74	1		T153	1
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T72	1		T73	1		T75	1
all_values[1]	auto[1]	auto[0]	auto[1]	179	1			T53	6		T72	2		T73	1
all_values[1]	auto[1]	auto[1]	auto[1]	150	1			T53	1		T72	1		T73	6
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T53	2		T72	2		T73	4
all_values[2]	auto[0]	auto[0]	auto[1]	59	1			T53	2		T153	2		T165	2
all_values[2]	auto[0]	auto[1]	auto[0]	126	1			T53	4		T72	1		T74	1
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T73	1		T75	1		T153	2
all_values[2]	auto[1]	auto[0]	auto[1]	165	1			T73	3		T75	1		T153	3
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T53	2		T72	1		T73	2
all_values[3]	auto[0]	auto[0]	auto[0]	134	1			T53	2		T74	2		T153	2
all_values[3]	auto[0]	auto[0]	auto[1]	61	1			T53	1		T153	1		T163	1
all_values[3]	auto[0]	auto[1]	auto[0]	165	1			T73	1		T74	2		T75	6
all_values[3]	auto[0]	auto[1]	auto[1]	78	1			T72	1		T73	1		T153	3
all_values[3]	auto[1]	auto[0]	auto[1]	166	1			T53	4		T72	2		T73	6
all_values[3]	auto[1]	auto[1]	auto[1]	160	1			T53	3		T72	1		T73	2
all_values[4]	auto[0]	auto[0]	auto[0]	142	1			T53	4		T72	3		T73	1
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T73	2		T75	1		T153	2
all_values[4]	auto[0]	auto[1]	auto[0]	125	1			T73	1		T75	3		T153	3
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T53	1		T74	2		T153	1
all_values[4]	auto[1]	auto[0]	auto[1]	185	1			T53	5		T72	1		T73	4
all_values[4]	auto[1]	auto[1]	auto[1]	152	1			T73	2		T74	1		T75	1
all_values[5]	auto[0]	auto[0]	auto[0]	229	1			T53	3		T73	3		T74	2
all_values[5]	auto[0]	auto[1]	auto[0]	193	1			T53	3		T72	2		T73	1
all_values[5]	auto[1]	auto[0]	auto[1]	172	1			T53	2		T72	1		T73	5
all_values[5]	auto[1]	auto[1]	auto[1]	170	1			T53	2		T72	1		T73	1
all_values[6]	auto[0]	auto[0]	auto[0]	121	1			T53	2		T73	5		T75	2
all_values[6]	auto[0]	auto[0]	auto[1]	67	1			T73	2		T74	2		T75	1
all_values[6]	auto[0]	auto[1]	auto[0]	151	1			T75	3		T153	4		T164	2
all_values[6]	auto[0]	auto[1]	auto[1]	88	1			T53	1		T72	3		T165	2
all_values[6]	auto[1]	auto[0]	auto[1]	183	1			T53	4		T72	1		T73	3
all_values[6]	auto[1]	auto[1]	auto[1]	154	1			T53	3		T74	2		T75	1
all_values[7]	auto[0]	auto[0]	auto[0]	171	1			T53	5		T72	3		T73	1
all_values[7]	auto[0]	auto[0]	auto[1]	69	1			T73	2		T74	1		T75	1
all_values[7]	auto[0]	auto[1]	auto[0]	131	1			T53	3		T72	1		T75	3
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T53	1		T73	4		T165	2
all_values[7]	auto[1]	auto[0]	auto[1]	172	1			T53	1		T73	1		T74	1
all_values[7]	auto[1]	auto[1]	auto[1]	149	1			T73	2		T75	1		T153	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal