Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5611571	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6251542

1

T1

109

T2

907

T3

157

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7486103	1			T1	101		T2	10		T3	10205
values[0x0]	2188254	1			T1	52		T2	457		T3	70
values[0x1]	2188756	1			T1	48		T2	449		T3	79

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4072554	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

7790559

1

T1

156

T2

911

T3

3540

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	46423	1			T3	35		T4	32		T5	1
valid_sources[0x01]	46969	1			T3	35		T4	27		T5	6
valid_sources[0x02]	47206	1			T3	15		T4	12		T5	5
valid_sources[0x03]	46419	1			T3	5		T4	26		T5	5
valid_sources[0x04]	44470	1			T1	1		T3	46		T4	26
valid_sources[0x05]	43326	1			T3	50		T4	23		T5	4
valid_sources[0x06]	49514	1			T3	82		T4	31		T5	4
valid_sources[0x07]	45762	1			T3	70		T4	33		T5	5
valid_sources[0x08]	44283	1			T3	99		T4	18		T8	27
valid_sources[0x09]	43386	1			T3	60		T4	29		T5	9
valid_sources[0x0a]	47995	1			T3	19		T4	15		T5	6
valid_sources[0x0b]	43521	1			T3	88		T4	16		T5	4
valid_sources[0x0c]	52158	1			T1	2		T3	6		T4	28
valid_sources[0x0d]	44808	1			T3	21		T4	13		T8	23
valid_sources[0x0e]	45881	1			T3	2		T4	12		T5	8
valid_sources[0x0f]	49224	1			T4	17		T5	2		T8	23
valid_sources[0x10]	45817	1			T3	64		T4	21		T8	17
valid_sources[0x11]	46922	1			T3	40		T4	38		T8	14
valid_sources[0x12]	48550	1			T3	51		T4	26		T5	9
valid_sources[0x13]	51314	1			T3	25		T4	14		T5	3
valid_sources[0x14]	44195	1			T3	57		T4	22		T5	4
valid_sources[0x15]	46727	1			T3	11		T4	18		T5	8
valid_sources[0x16]	46615	1			T3	22		T4	48		T8	20
valid_sources[0x17]	43035	1			T3	8		T4	29		T5	10
valid_sources[0x18]	48678	1			T3	68		T4	38		T5	4
valid_sources[0x19]	43386	1			T3	33		T4	53		T5	7
valid_sources[0x1a]	45083	1			T3	30		T4	48		T5	9
valid_sources[0x1b]	43776	1			T1	11		T3	28		T4	24
valid_sources[0x1c]	44198	1			T3	60		T4	26		T5	9
valid_sources[0x1d]	44687	1			T3	32		T4	29		T5	1
valid_sources[0x1e]	44723	1			T3	81		T4	29		T8	17
valid_sources[0x1f]	47342	1			T1	18		T3	75		T4	15
valid_sources[0x20]	42014	1			T3	34		T4	34		T5	5
valid_sources[0x21]	44389	1			T3	58		T4	24		T5	2
valid_sources[0x22]	46348	1			T3	45		T4	25		T8	18
valid_sources[0x23]	44793	1			T1	17		T3	32		T4	26
valid_sources[0x24]	49277	1			T3	110		T4	20		T5	11
valid_sources[0x25]	46283	1			T3	19		T4	15		T8	25
valid_sources[0x26]	45058	1			T3	101		T4	7		T5	14
valid_sources[0x27]	46969	1			T3	142		T4	36		T5	1
valid_sources[0x28]	45832	1			T3	23		T4	30		T5	10
valid_sources[0x29]	50514	1			T4	27		T5	1		T8	16
valid_sources[0x2a]	44832	1			T1	8		T3	75		T4	30
valid_sources[0x2b]	53644	1			T3	73		T4	22		T5	4
valid_sources[0x2c]	42784	1			T3	68		T4	27		T5	7
valid_sources[0x2d]	48356	1			T4	30		T5	4		T6	1
valid_sources[0x2e]	46911	1			T3	29		T4	27		T5	3
valid_sources[0x2f]	47211	1			T3	16		T4	10		T5	6
valid_sources[0x30]	49049	1			T3	26		T4	27		T5	17
valid_sources[0x31]	47058	1			T3	65		T4	14		T5	10
valid_sources[0x32]	49039	1			T3	26		T4	17		T5	1
valid_sources[0x33]	48029	1			T3	27		T4	36		T8	26
valid_sources[0x34]	47307	1			T3	55		T4	19		T5	2
valid_sources[0x35]	48999	1			T3	21		T4	39		T5	3
valid_sources[0x36]	46005	1			T4	17		T8	26		T13	3
valid_sources[0x37]	43802	1			T3	25		T4	35		T5	6
valid_sources[0x38]	45622	1			T3	79		T4	16		T5	12
valid_sources[0x39]	45209	1			T3	59		T4	53		T6	1
valid_sources[0x3a]	47475	1			T3	70		T4	36		T6	1
valid_sources[0x3b]	45319	1			T1	21		T3	95		T4	37
valid_sources[0x3c]	47262	1			T3	16		T4	10		T5	4
valid_sources[0x3d]	44543	1			T3	1		T4	21		T5	11
valid_sources[0x3e]	45458	1			T3	25		T4	27		T5	8
valid_sources[0x3f]	45516	1			T3	16		T4	24		T5	5
valid_sources[0x40]	48299	1			T3	106		T4	34		T5	2
valid_sources[0x41]	44628	1			T1	2		T3	46		T4	31
valid_sources[0x42]	48150	1			T3	5		T4	12		T5	1
valid_sources[0x43]	50135	1			T3	27		T4	23		T5	2
valid_sources[0x44]	46521	1			T3	24		T4	14		T5	3
valid_sources[0x45]	46981	1			T3	55		T4	18		T8	20
valid_sources[0x46]	47953	1			T3	2		T4	18		T8	17
valid_sources[0x47]	47220	1			T3	5		T4	24		T5	9
valid_sources[0x48]	49739	1			T3	32		T4	25		T5	1
valid_sources[0x49]	52792	1			T3	44		T4	23		T8	24
valid_sources[0x4a]	49060	1			T3	56		T4	26		T5	9
valid_sources[0x4b]	48301	1			T1	14		T3	75		T4	13
valid_sources[0x4c]	46079	1			T1	4		T3	7		T4	27
valid_sources[0x4d]	44998	1			T3	57		T4	31		T8	21
valid_sources[0x4e]	50510	1			T3	33		T4	33		T5	6
valid_sources[0x4f]	44163	1			T3	5		T4	22		T5	8
valid_sources[0x50]	51227	1			T3	44		T4	28		T5	7
valid_sources[0x51]	50089	1			T3	24		T4	26		T5	4
valid_sources[0x52]	45343	1			T3	23		T4	36		T5	10
valid_sources[0x53]	48739	1			T3	60		T4	35		T5	2
valid_sources[0x54]	48225	1			T3	23		T4	19		T5	1
valid_sources[0x55]	44692	1			T3	16		T4	45		T5	3
valid_sources[0x56]	42588	1			T3	18		T4	26		T5	2
valid_sources[0x57]	48002	1			T3	35		T4	39		T8	18
valid_sources[0x58]	44503	1			T3	46		T4	21		T5	7
valid_sources[0x59]	47021	1			T1	12		T3	13		T4	27
valid_sources[0x5a]	44849	1			T3	1		T4	22		T6	3
valid_sources[0x5b]	45218	1			T1	4		T3	35		T4	20
valid_sources[0x5c]	54235	1			T3	60		T4	24		T5	11
valid_sources[0x5d]	43538	1			T3	83		T4	16		T5	4
valid_sources[0x5e]	45801	1			T3	34		T4	26		T8	18
valid_sources[0x5f]	45953	1			T1	13		T3	40		T4	48
valid_sources[0x60]	48425	1			T3	89		T4	21		T5	4
valid_sources[0x61]	43893	1			T3	25		T4	22		T6	1
valid_sources[0x62]	44458	1			T3	11		T4	21		T5	3
valid_sources[0x63]	50275	1			T3	22		T4	32		T5	1
valid_sources[0x64]	49182	1			T3	20		T4	29		T5	2
valid_sources[0x65]	47874	1			T3	30		T4	16		T8	24
valid_sources[0x66]	46602	1			T1	4		T3	27		T4	28
valid_sources[0x67]	46089	1			T3	47		T4	12		T6	1
valid_sources[0x68]	50154	1			T3	51		T4	30		T5	1
valid_sources[0x69]	49522	1			T3	5		T4	22		T5	18
valid_sources[0x6a]	43741	1			T3	32		T4	14		T5	4
valid_sources[0x6b]	46327	1			T3	8		T4	11		T5	1
valid_sources[0x6c]	49860	1			T3	1		T4	20		T5	4
valid_sources[0x6d]	41767	1			T3	4		T4	16		T5	2
valid_sources[0x6e]	46122	1			T3	64		T4	21		T5	4
valid_sources[0x6f]	49545	1			T3	35		T4	36		T5	3
valid_sources[0x70]	43686	1			T3	35		T4	26		T5	2
valid_sources[0x71]	48518	1			T3	18		T4	27		T5	1
valid_sources[0x72]	45634	1			T3	14		T4	34		T5	7
valid_sources[0x73]	45845	1			T3	61		T4	9		T5	3
valid_sources[0x74]	43297	1			T3	12		T4	32		T7	4
valid_sources[0x75]	44046	1			T3	67		T4	24		T5	3
valid_sources[0x76]	48777	1			T1	14		T3	27		T4	21
valid_sources[0x77]	46064	1			T3	43		T4	20		T8	25
valid_sources[0x78]	44209	1			T3	11		T4	15		T6	1
valid_sources[0x79]	46769	1			T3	108		T4	15		T5	5
valid_sources[0x7a]	46533	1			T3	38		T4	14		T5	1
valid_sources[0x7b]	44123	1			T3	58		T4	18		T5	1
valid_sources[0x7c]	51918	1			T3	24		T4	25		T8	28
valid_sources[0x7d]	43454	1			T1	2		T3	41		T4	32
valid_sources[0x7e]	47514	1			T1	4		T3	45		T4	27
valid_sources[0x7f]	48752	1			T3	52		T4	26		T5	5
valid_sources[0x80]	43609	1			T3	129		T4	36		T5	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2315437

1

T1

9

T2

3

T3

69

values[0x0]

all_enables

biggest_size

1984487

1

T1

52

T2

457

T3

37

values[0x1]

all_enables

biggest_size

1951618

1

T1

48

T2

447

T3

51