Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5630517

1

T2

9

T3

10197

T4

1043

full_word

6250598

1

T2

907

T3

157

T4

5402

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	11880745	1			T2	916		T3	10354		T4	6445
auto[TlIntgErrCmd]	123	1			T86	8		T88	2		T91	7
auto[TlIntgErrData]	111	1			T86	9		T88	5		T91	5
auto[TlIntgErrBoth]	136	1			T86	13		T88	3		T91	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7487355

1

T2

10

T3

10205

T4

2037

auto[1]

4393760

1

T2

906

T3

149

T4

4408

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5171672	1			T2	7		T3	10136		T4	1024
auto[TlIntgErrNone]	partial	auto[1]	458503	1			T2	2		T3	61		T4	19
auto[TlIntgErrNone]	full_word	auto[0]	2315524	1			T2	3		T3	69		T4	1013
auto[TlIntgErrNone]	full_word	auto[1]	3935046	1			T2	904		T3	88		T4	4389
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T86	3		T91	1		T100	3
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T86	3		T88	2		T91	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T86	2		T91	1		T153	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T134	1		T154	1		T155	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T86	4		T88	3		T91	4
auto[TlIntgErrData]	partial	auto[1]	49	1			T86	4		T88	2		T91	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T156	1		T151	1		T157	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T86	1		T158	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T86	4		T88	1		T91	1
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T86	8		T88	1		T91	7
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T86	1		T131	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T88	1		T100	1		T134	2