Unified Coverage Report :: Module :: spi_tpm

Module : spi_tpm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.86	99.65	91.20		91.67	96.77	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm	95.86	99.65	91.20		91.67	96.77	100.00

---

Module Instance : tb.dut.u_spi_tpm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.86	99.65	91.20		91.67	96.77	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.79	99.46	84.99		91.67	95.68	92.16

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arbiter	86.14	100.00	70.73			92.86	80.95
u_cmdaddr_buffer	92.67	100.00	76.92			93.75	100.00
u_csb_sync_rst	100.00	100.00	100.00			100.00
u_hw_reg_slice	100.00	100.00					100.00
u_rdfifo_ready	100.00	100.00				100.00
u_sram_fifo	89.11	95.00	78.12			83.33	100.00
u_tpm_rd_buffer	89.74	100.00	69.23			100.00
u_tpm_wr_buffer	96.15	100.00	84.62			100.00	100.00
u_wrfifo_busy_sync	100.00	100.00				100.00
u_wrfifo_release_reqack	87.50	100.00	50.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_tpm

	Line No.	Total	Covered	Percent
TOTAL		282	281	99.65
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
ALWAYS	524	8	8	100.00
ALWAYS	541	3	3	100.00
ALWAYS	554	4	4	100.00
CONT_ASSIGN	563	1	1	100.00
CONT_ASSIGN	565	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
ALWAYS	593	3	3	100.00
ALWAYS	601	4	4	100.00
ALWAYS	609	3	3	100.00
ALWAYS	619	6	6	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
ALWAYS	647	4	4	100.00
CONT_ASSIGN	654	1	1	100.00
ALWAYS	657	4	4	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
ALWAYS	682	6	6	100.00
CONT_ASSIGN	705	1	1	100.00
ALWAYS	708	6	6	100.00
ALWAYS	720	4	4	100.00
ALWAYS	742	3	3	100.00
ALWAYS	750	3	3	100.00
ALWAYS	762	6	6	100.00
ALWAYS	779	6	6	100.00
ALWAYS	795	3	3	100.00
ALWAYS	801	6	6	100.00
ALWAYS	812	4	4	100.00
ALWAYS	822	4	4	100.00
ALWAYS	831	4	4	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
ALWAYS	851	6	6	100.00
ALWAYS	862	6	6	100.00
ALWAYS	872	3	3	100.00
ALWAYS	892	7	7	100.00
ALWAYS	934	15	15	100.00
ALWAYS	1011	3	3	100.00
CONT_ASSIGN	1020	1	1	100.00
ALWAYS	1023	3	3	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1044	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
ALWAYS	1051	3	3	100.00
ALWAYS	1063	4	4	100.00
CONT_ASSIGN	1072	1	1	100.00
ALWAYS	1094	3	3	100.00
ALWAYS	1122	72	72	100.00
CONT_ASSIGN	1372	1	1	100.00
CONT_ASSIGN	1374	1	1	100.00
ALWAYS	1381	6	6	100.00
ALWAYS	1393	8	8	100.00
ALWAYS	1408	6	6	100.00
CONT_ASSIGN	1424	1	1	100.00
CONT_ASSIGN	1427	1	0	0.00
CONT_ASSIGN	1458	1	1	100.00
CONT_ASSIGN	1464	1	1	100.00
ALWAYS	1469	6	6	100.00
ALWAYS	1479	4	4	100.00
CONT_ASSIGN	1488	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00
CONT_ASSIGN	1521	1	1	100.00
CONT_ASSIGN	1555	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
334	1	1
348	1	1
373	1	1
491	1	1
492	1	1
520	1	1
524	1	1
525	1	1
526	1	1
528	1	1
529	1	1
530	1	1
531	1	1
532	1	1
			MISSING_ELSE
541	1	1
542	1	1
544	1	1
554	1	1
555	1	1
556	1	1
557	1	1
			MISSING_ELSE
563	1	1
565	1	1
590	1	1
593	1	1
594	1	1
596	1	1
601	1	1
602	1	1
603	1	1
604	1	1
			MISSING_ELSE
609	1	1
610	1	1
612	1	1
619	1	1
620	1	1
621	1	1
623	1	1
624	1	1
625	1	1
			MISSING_ELSE
636	1	1
643	1	1
647	1	1
648	1	1
649	1	1
650	1	1
			MISSING_ELSE
654	1	1
657	1	1
658	1	1
659	1	1
660	1	1
			MISSING_ELSE
664	1	1
666	1	1
679	1	1
682	1	1
683	1	1
684	1	1
685	1	1
686	1	1
687	1	1
			MISSING_ELSE
705	1	1
708	1	1
709	1	1
710	1	1
711	1	1
712	1	1
713	1	1
			MISSING_ELSE
720	1	1
721	1	1
726	1	1
732	1	1
742	1	1
743	1	1
745	1	1
			MISSING_ELSE
750	1	1
751	1	1
753	1	1
762	1	1
763	1	1
764	1	1
765	1	1
773	1	1
774	1	1
			MISSING_ELSE
779	1	1
780	1	1
782	1	1
783	1	1
784	1	1
785	1	1
			MISSING_ELSE
795	2	2
796	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
806	1	1
			MISSING_ELSE
812	1	1
813	1	1
814	1	1
816	1	1
			MISSING_ELSE
822	1	1
823	1	1
824	1	1
825	1	1
			MISSING_ELSE
831	1	1
832	1	1
833	1	1
835	1	1
			MISSING_ELSE
838	1	1
839	1	1
851	1	1
852	1	1
853	1	1
854	1	1
855	1	1
856	1	1
			MISSING_ELSE
862	1	1
863	1	1
864	1	1
865	1	1
866	1	1
867	1	1
			MISSING_ELSE
872	1	1
873	1	1
875	1	1
892	1	1
894	1	1
896	1	1
900	1	1
904	1	1
908	1	1
912	1	1
934	1	1
936	1	1
938	1	1
939	1	1
940	1	1
			MISSING_ELSE
947	1	1
951	1	1
955	1	1
959	1	1
964	1	1
966	1	1
968	1	1
973	1	1
977	1	1
981	1	1
1011	1	1
1012	1	1
1014	1	1
1020	1	1
1023	2	2
1024	1	1
1043	1	1
1044	1	1
1048	1	1
1051	1	1
1052	1	1
1054	1	1
1063	1	1
1064	1	1
1065	1	1
1066	1	1
			MISSING_ELSE
1072	1	1
1094	1	1
1095	1	1
1097	1	1
1122	1	1
1125	1	1
1126	1	1
1128	1	1
1129	1	1
1130	1	1
1132	1	1
1133	1	1
1139	1	1
1141	1	1
1143	1	1
1145	1	1
1146	1	1
1147	1	1
1149	1	1
1157	1	1
			MISSING_ELSE
1164	1	1
1166	1	1
1168	1	1
1169	1	1
			MISSING_ELSE
1173	1	1
1174	1	1
			MISSING_ELSE
1178	1	1
1179	1	1
1182	1	1
1187	1	1
1188	1	1
			MISSING_ELSE
1190	1	1
1193	1	1
1194	1	1
1197	1	1
1200	1	1
1205	1	1
1206	1	1
			MISSING_ELSE
			MISSING_ELSE
1211	1	1
1212	1	1
1214	1	1
1218	1	1
			MISSING_ELSE
1224	1	1
1225	1	1
1228	1	1
1229	1	1
			MISSING_ELSE
1233	1	1
1236	1	1
			MISSING_ELSE
1241	1	1
1242	1	1
1244	1	1
1246	1	1
1247	1	1
1248	1	1
1249	1	1
1250	1	1
1251	1	1
			==> MISSING_ELSE
			MISSING_ELSE
1257	1	1
1259	1	1
1260	1	1
1262	1	1
1263	1	1
			MISSING_ELSE
1268	1	1
1269	1	1
1273	1	1
1274	1	1
			MISSING_ELSE
1279	1	1
1282	1	1
1284	1	1
1285	1	1
			MISSING_ELSE
1291	1	1
1292	1	1
1293	1	1
			==> MISSING_ELSE
1298	1	1
1299	1	1
1300	1	1
			MISSING_ELSE
1372	1	1
1374	1	1
1381	1	1
1382	1	1
1383	1	1
1384	1	1
1385	1	1
1386	1	1
			MISSING_ELSE
1393	1	1
1394	1	1
1395	1	1
1399	1	1
1400	1	1
1401	1	1
1402	1	1
1403	1	1
			MISSING_ELSE
1408	1	1
1409	1	1
1410	1	1
1416	1	1
1417	1	1
1418	1	1
			MISSING_ELSE
1424	1	1
1427	0	1
1458	1	1
1464	1	1
1469	1	1
1470	1	1
1471	1	1
1472	1	1
1473	1	1
1474	1	1
			MISSING_ELSE
1479	1	1
1480	1	1
1481	1	1
1482	1	1
			MISSING_ELSE
1488	1	1
1489	1	1
1521	1	1
1555	1	1

---

Cond Coverage for Module : spi_tpm

	Total	Covered	Percent
Conditions	216	197	91.20
Logical	216	197	91.20
Non-Logical	0	0
Event	0	0

 LINE       563
 EXPRESSION ((cmdaddr_bitcnt == 5'b0) && (sck_st_q == StIdle))
             ------------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T7,T11
1	1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'b0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (sck_st_q == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       565
 EXPRESSION (cmdaddr_bitcnt == 5'h1d)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T11

 LINE       590
 EXPRESSION (cmdaddr_bitcnt == 5'h1f)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T11

 LINE       643
 EXPRESSION (isck_p2s_sent && (isck_data_sel == SelHwReg))
             ------1------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T18
1	0	Covered	T3,T7,T11
1	1	Covered	T7,T17,T18

 LINE       643
 SUB-EXPRESSION (isck_data_sel == SelHwReg)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T17,T18

 LINE       654
 EXPRESSION (wrdata_bitcnt == 3'h7)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T12

 LINE       710
 EXPRESSION (sck_cmdaddr_wvalid && (cmd_type == Write))
             ---------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       710
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T11
1	Covered	T2,T3,T4

 LINE       743
 EXPRESSION (check_locality && (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr)))
             -------1------    ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T17
1	0	Covered	T3,T11,T12
1	1	Covered	T7,T11,T17

 LINE       743
 SUB-EXPRESSION (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr))
                 ---------------1---------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T17
1	0	Covered	T11,T12,T18

 LINE       743
 SUB-EXPRESSION (addr[23:16] == TpmAddr)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T11,T17

 LINE       765
 EXPRESSION (((!sys_clk_tpm_cfg.tpm_mode)) && check_hw_reg && (cmd_type == Read) && is_tpm_reg_q && ((!invalid_locality)) && ((!sys_clk_tpm_cfg.hw_reg_dis)))
             --------------1--------------    ------2-----    ---------3--------    ------4-----    ----------5----------    ---------------6---------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T11,T12,T27
1	0	1	1	1	1	Covered	T7,T17,T18
1	1	0	1	1	1	Covered	T18,T26,T31
1	1	1	0	1	1	Covered	T18,T26,T57
1	1	1	1	0	1	Covered	T17,T18,T19
1	1	1	1	1	0	Covered	T18,T26,T31
1	1	1	1	1	1	Covered	T7,T17,T18

 LINE       765
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T3,T7,T11

 LINE       783
 EXPRESSION (TpmReturnByHwAddr[i][11:2] == addr[11:2])
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       804
 EXPRESSION (check_locality && is_tpm_reg_d)
             -------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T17
1	0	Covered	T3,T11,T12
1	1	Covered	T7,T11,T17

 LINE       806
 EXPRESSION ((addr[15:12] < 4'(spi_device_reg_pkg::NumLocality)) ? 1'b0 : 1'b1)
             -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T11,T17,T12
1	Covered	T7,T11,T17

 LINE       833
 EXPRESSION ((isck_p2s_sent && sck_rddata_shift_en) || (sck_wrfifo_wvalid && wrdata_shift_en))
             -------------------1------------------    -------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T12

 LINE       833
 SUB-EXPRESSION (isck_p2s_sent && sck_rddata_shift_en)
                 ------1------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T7,T11
1	1	Covered	T3,T11,T12

 LINE       833
 SUB-EXPRESSION (sck_wrfifo_wvalid && wrdata_shift_en)
                 --------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Not Covered
1	1	Covered	T3,T11,T12

 LINE       839
 EXPRESSION (xfer_bytes_q == xfer_size)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       855
 EXPRESSION (sys_rdfifo_wvalid_i & sys_rdfifo_wready_o)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T11,T12

 LINE       866
 EXPRESSION (sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             ----------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       939
 EXPRESSION (((!invalid_locality)) && (4'(i) == locality))
             ----------1----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       939
 SUB-EXPRESSION (4'(i) == locality)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       964
 EXPRESSION (((!invalid_locality)) && sys_active_locality[locality[2:0]])
             ----------1----------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T17,T18
1	1	Covered	T7,T17,T18

 LINE       1020
 EXPRESSION (isck_p2s_valid && (isck_p2s_bitcnt == '0))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T7,T11
1	1	Covered	T3,T7,T11

 LINE       1020
 SUB-EXPRESSION (isck_p2s_bitcnt == '0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       1048
 EXPRESSION (isck_p2s_sent && (isck_data_sel == SelRdFifo))
             ------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T7,T11
1	1	Covered	T3,T11,T12

 LINE       1048
 SUB-EXPRESSION (isck_data_sel == SelRdFifo)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T12

 LINE       1072
 EXPRESSION (((&sck_rdfifo_idx)) && (isck_data_sel == SelRdFifo) && sck_p2s_valid && (isck_p2s_bitcnt == 3'b1))
             ---------1---------    --------------2-------------    ------3------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T3,T11,T12
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T3,T11,T12
1	1	1	1	Covered	T3,T11,T12

 LINE       1072
 SUB-EXPRESSION (isck_data_sel == SelRdFifo)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T12

 LINE       1072
 SUB-EXPRESSION (isck_p2s_bitcnt == 3'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       1145
 EXPRESSION (cmdaddr_bitcnt == 5'h07)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       1173
 EXPRESSION (cmdaddr_bitcnt == 5'h1b)
            ------------1------------

-1-	Status	Tests
0	Covered	T3,T7,T11
1	Covered	T3,T7,T11

 LINE       1178
 EXPRESSION ((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Read))
             ------------1------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T7,T11

 LINE       1178
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'h1f)
                ------------1------------

-1-	Status	Tests
0	Covered	T3,T7,T11
1	Covered	T3,T7,T11

 LINE       1178
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T7,T11

 LINE       1179
 EXPRESSION (((!is_tpm_reg_q)) || sys_clk_tpm_cfg.tpm_mode)
             --------1--------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T17,T18
0	1	Covered	T11,T12,T27
1	0	Covered	T18,T26,T57

 LINE       1187
 EXPRESSION (sck_cmdaddr_wdepth == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T11,T12,T18
1	Covered	T3,T11,T12

 LINE       1194
 EXPRESSION (invalid_locality && sys_clk_tpm_cfg.invalid_locality)
             --------1-------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T31
1	0	Covered	T18,T26,T31
1	1	Covered	T17,T18,T19

 LINE       1205
 EXPRESSION (sck_cmdaddr_wdepth == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T18,T26,T31
1	Covered	T18,T26,T31

 LINE       1211
 EXPRESSION ((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Write))
             ------------1------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T7,T11
1	1	Covered	T3,T11,T12

 LINE       1211
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'h1f)
                ------------1------------

-1-	Status	Tests
0	Covered	T3,T7,T11
1	Covered	T3,T7,T11

 LINE       1211
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T11
1	Covered	T3,T11,T12

 LINE       1212
 EXPRESSION (((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))
             ----------1---------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T28
1	0	Covered	T26,T27,T30
1	1	Covered	T3,T11,T12

 LINE       1228
 EXPRESSION ((cmd_type == Read) && ((!sck_rdfifo_cmd_pending)) && ((~|sck_cmdaddr_wdepth)))
             ---------1--------    -------------2-------------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T18
1	0	1	Covered	T3,T11,T12
1	1	0	Covered	T11,T12,T18
1	1	1	Covered	T11,T12,T18

 LINE       1228
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T11,T12,T18
1	Covered	T3,T11,T12

 LINE       1233
 EXPRESSION (isck_p2s_sent && (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))))
             ------1------    ---------------------------------------------------------------2---------------------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       1233
 SUB-EXPRESSION (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth))))
                 ------------------------1-----------------------    ------------------------------------2------------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T11,T12,T18
1	0	Covered	T3,T11,T12

 LINE       1233
 SUB-EXPRESSION ((cmd_type == Read) && enough_payload_in_rdfifo)
                 ---------1--------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       1233
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T11,T12,T18
1	Covered	T3,T11,T12

 LINE       1233
 SUB-EXPRESSION ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))
                 ---------1---------    ----------2---------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T11,T12
1	0	1	Covered	T11,T12,T18
1	1	0	Covered	T26,T27,T30
1	1	1	Covered	T11,T12,T18

 LINE       1233
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T11,T12,T18

 LINE       1246
 EXPRESSION ((cmd_type == Read) && is_hw_reg)
             ---------1--------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T11,T12
1	1	Covered	T7,T17,T18

 LINE       1246
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T7,T11

 LINE       1248
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T11,T12

 LINE       1250
 EXPRESSION (cmd_type == Write)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T11,T12

 LINE       1262
 EXPRESSION (isck_p2s_sent && xfer_size_met)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       1273
 EXPRESSION (isck_p2s_sent && xfer_size_met)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T7,T17,T18
1	1	Covered	T17,T18,T19

 LINE       1282
 EXPRESSION (sck_wrfifo_wvalid && xfer_size_met)
             --------1--------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       1291
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T17,T18,T19

 LINE       1298
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T11,T17

 LINE       1385
 EXPRESSION (sys_cmdaddr.rnw & sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             -------1-------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T11,T12
1	0	1	Not Covered
1	1	0	Covered	T3,T11,T12
1	1	1	Covered	T3,T11,T12

 LINE       1395
 EXPRESSION (cmdaddr_bitcnt == 5'h0f)
            ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T7,T11

 LINE       1400
 EXPRESSION (sck_cmdaddr_wvalid && (cmd_type == Read))
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       1400
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T7,T11

 LINE       1402
 EXPRESSION (isck_p2s_sent && xfer_size_met && (sck_st_q == StReadFifo))
             ------1------    ------2------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T11,T12
1	0	1	Covered	T3,T11,T12
1	1	0	Covered	T3,T11,T17
1	1	1	Covered	T3,T11,T12

 LINE       1402
 SUB-EXPRESSION (sck_st_q == StReadFifo)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T11,T12

 LINE       1410
 EXPRESSION (sys_csb_deasserted_pulse & ((!sys_rdfifo_sync_clr)))
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T11,T12

 LINE       1417
 EXPRESSION (sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             ----------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       1424
 EXPRESSION (sys_csb_deasserted_pulse & ((!sys_rdfifo_sync_clr)))
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T11,T12

 LINE       1458
 EXPRESSION (sys_rdfifo_wvalid_i & ((!sys_rdfifo_wready_o)))
             ---------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Not Covered

 LINE       1464
 EXPRESSION (enough_payload_in_rdfifo && ((sck_st_q == StReadFifo) || (sck_st_q == StStartByte)))
             ------------1-----------    ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T12

 LINE       1464
 SUB-EXPRESSION ((sck_st_q == StReadFifo) || (sck_st_q == StStartByte))
                 ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T11
1	0	Covered	T3,T11,T12

 LINE       1464
 SUB-EXPRESSION (sck_st_q == StReadFifo)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T12

 LINE       1464
 SUB-EXPRESSION (sck_st_q == StStartByte)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T11

 LINE       1471
 EXPRESSION (sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo])
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T11,T12

 LINE       1481
 EXPRESSION (sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo])
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T11,T12

 LINE       1488
 EXPRESSION (rdfifo_active && ((!sck_rdfifo_req_pending)) && ((!sck_rdfifo_full)))
             ------1------    -------------2-------------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T11,T12
1	1	0	Covered	T3,T11,T12
1	1	1	Covered	T3,T11,T12

---

FSM Coverage for Module : spi_tpm

Summary for FSM :: sck_st_q

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	12	11	91.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: sck_st_q

---

states	Line No.	Covered	Tests
StAddr	1147	Covered	T3,T7,T11
StEnd	1157	Covered	T3,T11,T17
StIdle	1142	Covered	T1,T2,T3
StInvalid	1197	Covered	T17,T18,T19
StReadFifo	1249	Covered	T3,T11,T12
StReadHwReg	1247	Covered	T7,T17,T18
StStartByte	1193	Covered	T3,T7,T11
StWait	1182	Covered	T3,T11,T12
StWrite	1251	Covered	T3,T11,T12

transitions	Line No.	Covered	Tests
StAddr->StInvalid	1197	Covered	T17,T18,T19
StAddr->StStartByte	1193	Covered	T3,T7,T11
StAddr->StWait	1182	Covered	T3,T11,T12
StIdle->StAddr	1147	Covered	T3,T7,T11
StIdle->StEnd	1157	Not Covered
StReadFifo->StEnd	1263	Covered	T3,T11,T12
StReadHwReg->StEnd	1274	Covered	T17,T18,T19
StStartByte->StReadFifo	1249	Covered	T3,T11,T12
StStartByte->StReadHwReg	1247	Covered	T7,T17,T18
StStartByte->StWrite	1251	Covered	T3,T11,T12
StWait->StStartByte	1236	Covered	T3,T11,T12
StWrite->StEnd	1285	Covered	T3,T11,T12

---

Branch Coverage for Module : spi_tpm

	Line No.	Total	Covered	Percent
Branches		155	150	96.77
IF	524	3	3	100.00
IF	541	2	2	100.00
IF	554	3	3	100.00
IF	593	2	2	100.00
IF	601	3	3	100.00
IF	609	2	2	100.00
IF	619	4	4	100.00
IF	647	3	3	100.00
IF	657	3	3	100.00
IF	682	4	4	100.00
IF	708	4	4	100.00
CASE	721	3	3	100.00
IF	743	2	2	100.00
IF	750	2	2	100.00
IF	762	3	3	100.00
IF	783	2	2	100.00
IF	795	2	2	100.00
IF	801	4	4	100.00
IF	812	3	3	100.00
IF	822	3	3	100.00
IF	831	3	3	100.00
IF	851	4	4	100.00
IF	862	4	4	100.00
IF	872	2	2	100.00
CASE	894	6	5	83.33
CASE	936	11	10	90.91
IF	1011	2	2	100.00
IF	1023	2	2	100.00
IF	1051	2	2	100.00
IF	1063	3	3	100.00
IF	1094	2	2	100.00
CASE	1141	37	34	91.89
IF	1381	4	4	100.00
IF	1393	5	5	100.00
IF	1408	4	4	100.00
IF	1469	4	4	100.00
IF	1479	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	524	if ((!sys_rst_ni))
-2-:	528	if (sys_csb_asserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	541	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	554	if ((!rst_ni))
-2-:	556	if (cmdaddr_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
0	0	Covered	T3,T7,T11

	LineNo.	Expression
-1-:	593	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	601	if ((!rst_ni))
-2-:	603	if (cmdaddr_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
0	0	Covered	T3,T7,T11

	LineNo.	Expression
-1-:	609	if (cmdaddr_shift_en)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T11

	LineNo.	Expression
-1-:	619	if ((!rst_ni))
-2-:	621	if (isck_fifoaddr_latch)
-3-:	624	if (isck_fifoaddr_inc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T7,T11
0	0	1	Covered	T7,T17,T18
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	647	if ((!rst_ni))
-2-:	649	if (wrdata_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T11,T12
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	657	if ((!rst_ni))
-2-:	659	if (wrdata_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T11,T12
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	682	if ((!sys_rst_ni))
-2-:	684	if (sys_wrfifo_release_i)
-3-:	686	if (sys_wrfifo_release_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T11,T12
0	0	1	Covered	T3,T11,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	708	if ((!sys_rst_ni))
-2-:	710	if ((sck_cmdaddr_wvalid && (cmd_type == Write)))
-3-:	712	if (sck_wrfifo_release_req)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T11,T12
0	0	1	Covered	T3,T11,T12
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	721	case (1'b1)

Branches:

-1-	Status	Tests
check_locality	Covered	T3,T7,T11
check_hw_reg	Covered	T3,T7,T11
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	743	if ((check_locality && (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr))))

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	762	if ((!rst_ni))
-2-:	765	if (((((((!sys_clk_tpm_cfg.tpm_mode) && check_hw_reg) && (cmd_type == Read)) && is_tpm_reg_q) && (!invalid_locality)) && (!sys_clk_tpm_cfg.hw_reg_dis)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T17,T18
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	783	if ((TpmReturnByHwAddr[i][11:2] == addr[11:2]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	795	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	801	if ((!rst_ni))
-2-:	804	if ((check_locality && is_tpm_reg_d))
-3-:	806	((addr[15:12] < 4'(spi_device_reg_pkg::NumLocality))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T7,T11,T17
0	1	0	Covered	T11,T17,T12
0	0	-	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	812	if ((!rst_ni))
-2-:	814	if (latch_cmd_type)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	822	if ((!rst_ni))
-2-:	824	if (latch_xfer_size)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T7,T11
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	831	if ((!rst_ni))
-2-:	833	if (((isck_p2s_sent && sck_rddata_shift_en) || (sck_wrfifo_wvalid && wrdata_shift_en)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T11,T12
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	851	if ((!sys_rst_ni))
-2-:	853	if (sys_csb_asserted_pulse)
-3-:	855	if ((sys_rdfifo_wvalid_i & sys_rdfifo_wready_o))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T6
0	0	1	Covered	T3,T11,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	862	if ((!sys_rst_ni))
-2-:	864	if (sys_csb_asserted_pulse)
-3-:	866	if ((sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T6
0	0	1	Covered	T3,T11,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	872	if ((!sys_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	894	case (isck_data_sel)

Branches:

-1-	Status	Tests
SelWait	Covered	T1,T2,T3
SelStart	Covered	T3,T7,T11
SelInvalid	Covered	T17,T18,T19
SelHwReg	Covered	T7,T17,T18
SelRdFifo	Covered	T3,T11,T12
default	Not Covered

	LineNo.	Expression
-1-:	936	case (isck_hw_reg_idx)
-2-:	964	if (((!invalid_locality) && sys_active_locality[locality[2:0]]))

Branches:

-1-	-2-	Status	Tests
RegAccess	-	Covered	T1,T2,T3
RegIntEn	-	Covered	T17,T18,T19
RegIntVect	-	Covered	T17,T18,T19
RegIntSts	-	Covered	T17,T18,T19
RegIntfCap	-	Covered	T81,T82
RegSts	1	Covered	T7,T17,T18
RegSts	0	Covered	T7,T17,T18
RegHashStart	-	Covered	T17,T18,T19
RegId	-	Covered	T17,T18,T19
RegRid	-	Covered	T17,T18,T19
default	-	Not Covered

	LineNo.	Expression
-1-:	1011	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	1023	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	1051	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	1063	if ((!rst_ni))
-2-:	1065	if (isck_rd_byte_sent)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T11,T12
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	1094	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	1141	case (sck_st_q)
-2-:	1145	if ((cmdaddr_bitcnt == 5'h07))
-3-:	1146	if (sys_clk_tpm_en)
-4-:	1166	if ((cmdaddr_bitcnt >= 5'h18))
-5-:	1173	if ((cmdaddr_bitcnt == 5'h1b))
-6-:	1178	if (((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Read)))
-7-:	1179	if (((!is_tpm_reg_q) || sys_clk_tpm_cfg.tpm_mode))
-8-:	1187	if ((sck_cmdaddr_wdepth == '0))
-9-:	1190	if (is_hw_reg)
-10-:	1194	if ((invalid_locality && sys_clk_tpm_cfg.invalid_locality))
-11-:	1205	if ((sck_cmdaddr_wdepth == '0))
-12-:	1211	if (((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Write)))
-13-:	1212	if (((!sck_wrfifo_busy) && (~|sck_cmdaddr_wdepth)))
-14-:	1228	if ((((cmd_type == Read) && (!sck_rdfifo_cmd_pending)) && (~|sck_cmdaddr_wdepth)))
-15-:	1233	if ((isck_p2s_sent && (((cmd_type == Read) && enough_payload_in_rdfifo) || (((cmd_type == Write) && (!sck_wrfifo_busy)) && (~|sck_cmdaddr_wdepth)))))
-16-:	1244	if (isck_p2s_sent)
-17-:	1246	if (((cmd_type == Read) && is_hw_reg))
-18-:	1248	if ((cmd_type == Read))
-19-:	1250	if ((cmd_type == Write))
-20-:	1262	if ((isck_p2s_sent && xfer_size_met))
-21-:	1273	if ((isck_p2s_sent && xfer_size_met))
-22-:	1282	if ((sck_wrfifo_wvalid && xfer_size_met))
-23-:	1291	if ((cmd_type == Read))
-24-:	1298	if ((cmd_type == Read))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	Status	Tests
StIdle	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
StIdle	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StAddr	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
StAddr	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
StAddr	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
StAddr	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
StAddr	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
StAddr	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T18
StAddr	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T17,T18
StAddr	-	-	-	-	1	0	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
StAddr	-	-	-	-	1	0	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T26,T31
StAddr	-	-	-	-	1	0	-	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T26,T31
StAddr	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
StAddr	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
StAddr	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T18
StAddr	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
StWait	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T18
StWait	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
StWait	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
StWait	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T7,T17,T18
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	Covered	T3,T11,T12
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	Covered	T3,T11,T12
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	Not Covered
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
StReadFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T11,T12
StReadFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T11,T12
StReadHwReg	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T17,T18,T19
StReadHwReg	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T7,T17,T18
StWrite	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T11,T12
StWrite	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T11,T12
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T17,T18,T19
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StEnd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T11,T17
StEnd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	1381	if ((!sys_rst_ni))
-2-:	1383	if (sys_csb_deasserted_pulse)
-3-:	1385	if (((sys_cmdaddr.rnw & sys_cmdaddr_rvalid_o) & sys_cmdaddr_rready_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T6
0	0	1	Covered	T3,T11,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1393	if ((!sys_rst_ni))
-2-:	1395	if ((cmdaddr_bitcnt == 5'h0f))
-3-:	1400	if ((sck_cmdaddr_wvalid && (cmd_type == Read)))
-4-:	1402	if (((isck_p2s_sent && xfer_size_met) && (sck_st_q == StReadFifo)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T3,T7,T11
0	0	1	-	Covered	T3,T11,T12
0	0	0	1	Covered	T3,T11,T12
0	0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	1408	if ((!sys_rst_ni))
-2-:	1410	if ((sys_csb_deasserted_pulse & (!sys_rdfifo_sync_clr)))
-3-:	1417	if ((sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T11,T12
0	0	1	Covered	T3,T11,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1469	if ((!rst_ni))
-2-:	1471	if ((sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo]))
-3-:	1473	if (sck_sram_rvalid[SramRdFifo])

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T11,T12
0	0	1	Covered	T3,T11,T12
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	1479	if ((!rst_ni))
-2-:	1481	if ((sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo]))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T11,T12
0	0	Covered	T3,T4,T7

---

Assert Coverage for Module : spi_tpm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CmdAddrAvailable_A	188963472	72346	0	0
CmdAddrBitCntInAddrSt_A	188963472	779808	0	0
CmdAddrInfo_A	188963472	77783	0	0
CmdPowerof2_A	942	942	0	0
DataFifoLessThan64_A	942	942	0	0
DataSelKnown_A	188964388	42345565	0	0
HwRegCondition2_a	188963472	15807	0	0
HwRegCondition_A	188963472	97476	0	0
HwRegIdxKnown_A	188964388	42345565	0	0
LocalityLatchCondition_A	188963472	97476	0	0
RdFifoDepthPoT_A	942	942	0	0
RdFifoNumBytesPoT_A	942	942	0	0
RdPowerof2_A	942	942	0	0
SckFifoAddrLatchCondition_A	188963472	97476	0	0
TpmRegSizeMatch_A	942	942	0	0
WrDepthSpec_A	942	942	0	0
WrFifoAvailable_A	188963472	617475	0	0

CmdAddrAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	72346	0	0
T3	5350	15	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	328	0	0
T12	721605	362	0	0
T13	30167	0	0	0
T17	44632	0	0	0
T18	0	474	0	0
T26	0	271	0	0
T27	0	317	0	0
T28	0	303	0	0
T30	0	368	0	0
T31	0	514	0	0
T38	0	4	0	0

CmdAddrBitCntInAddrSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	779808	0	0
T3	5350	120	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	152	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	2624	0	0
T12	721605	2896	0	0
T13	30167	0	0	0
T17	44632	1568	0	0
T18	0	4176	0	0
T19	0	3960	0	0
T26	0	2640	0	0
T27	0	2536	0	0
T37	0	2224	0	0

CmdAddrInfo_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	77783	0	0
T7	1775	19	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	209	0	0
T12	721605	247	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T15	73586	0	0	0
T17	44632	196	0	0
T18	0	327	0	0
T19	0	495	0	0
T25	308214	0	0	0
T26	0	277	0	0
T27	0	213	0	0
T28	0	236	0	0
T37	0	278	0	0

CmdPowerof2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

DataFifoLessThan64_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

DataSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188964388	42345565	0	0
T3	5351	4776	0	0
T4	160313	7	0	0
T5	55555	0	0	0
T6	1	0	0	0
T7	1775	1368	0	0
T8	75333	0	0	0
T9	16744	0	0	0
T10	1	0	0	0
T11	0	86496	0	0
T12	0	119800	0	0
T13	30167	0	0	0
T17	0	42032	0	0
T18	0	161656	0	0
T19	0	114736	0	0
T26	0	101088	0	0
T37	0	57616	0	0
T52	1	0	0	0

HwRegCondition2_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	15807	0	0
T7	1775	19	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	0	0	0
T12	721605	0	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T15	73586	0	0	0
T17	44632	137	0	0
T18	0	34	0	0
T19	0	319	0	0
T25	308214	0	0	0
T26	0	41	0	0
T31	0	7	0	0
T37	0	185	0	0
T57	0	3	0	0
T83	0	429	0	0
T84	0	15	0	0

HwRegCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	97476	0	0
T3	5350	15	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	19	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	328	0	0
T12	721605	362	0	0
T13	30167	0	0	0
T17	44632	196	0	0
T18	0	522	0	0
T19	0	495	0	0
T26	0	330	0	0
T27	0	317	0	0
T37	0	278	0	0

HwRegIdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188964388	42345565	0	0
T3	5351	4776	0	0
T4	160313	7	0	0
T5	55555	0	0	0
T6	1	0	0	0
T7	1775	1368	0	0
T8	75333	0	0	0
T9	16744	0	0	0
T10	1	0	0	0
T11	0	86496	0	0
T12	0	119800	0	0
T13	30167	0	0	0
T17	0	42032	0	0
T18	0	161656	0	0
T19	0	114736	0	0
T26	0	101088	0	0
T37	0	57616	0	0
T52	1	0	0	0

LocalityLatchCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	97476	0	0
T3	5350	15	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	19	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	328	0	0
T12	721605	362	0	0
T13	30167	0	0	0
T17	44632	196	0	0
T18	0	522	0	0
T19	0	495	0	0
T26	0	330	0	0
T27	0	317	0	0
T37	0	278	0	0

RdFifoDepthPoT_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

RdFifoNumBytesPoT_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

RdPowerof2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SckFifoAddrLatchCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	97476	0	0
T3	5350	15	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	19	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	328	0	0
T12	721605	362	0	0
T13	30167	0	0	0
T17	44632	196	0	0
T18	0	522	0	0
T19	0	495	0	0
T26	0	330	0	0
T27	0	317	0	0
T37	0	278	0	0

TpmRegSizeMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WrDepthSpec_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WrFifoAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	617475	0	0
T3	5350	249	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	3006	0	0
T12	721605	3924	0	0
T13	30167	0	0	0
T17	44632	0	0	0
T18	0	4633	0	0
T26	0	2536	0	0
T27	0	2561	0	0
T28	0	1635	0	0
T30	0	2843	0	0
T31	0	4767	0	0
T38	0	6	0	0